Display substrate and preparation method therefor, and display

Abstract

A display substrate and a preparation method therefor, and a display. The display substrate comprises a plurality of circuit units which form a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel driving circuit and at least one initial signal line, the pixel driving circuit comprising at least one initialization transistor, and the initial signal line being connected to a first electrode of the initialization transistor; and in at least one circuit unit and a circuit unit adjacent thereto in a pixel column direction, pixel driving circuits in the two circuit units are in mirror symmetry relative to a row boundary line, first electrodes of initialization transistors in the two pixel driving circuits are connected to the same initial signal line, and the row boundary line is a straight line located between adjacent unit rows and extending in the direction of the unit rows. The present disclosure effectively reduces the number of traces and the number of via holes, thereby effectively improving the yield and an aperture ratio.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 28, 2024, with application number 202410226283.5 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one initial signal line, the pixel driving circuit comprising at least one initialization transistor, the initial signal line being connected to a first electrode of the initialization transistor; in at least one circuit unit and a circuit unit adjacent in the direction of the pixel column, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to a row dividing line, the first electrodes of the initialization transistors in the two pixel driving circuits are connected to the same initial signal line, and the row dividing line is a straight line located between adjacent unit rows and extending along the unit row direction.

[0006] In an exemplary embodiment, the at least one initial signal line includes a first initial signal line extending along the unit row direction, the at least one initialization transistor includes a first initialization transistor, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first electrodes of the first initialization transistors in the two circuit units are connected to the same first initial signal line, and the first initial signal line is configured to provide a first initial signal to the pixel driving circuit.

[0007] In an exemplary embodiment, the first initialization transistor includes at least a first initialization active layer, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first regions of the first initialization active layer in the two circuit units are connected to the same first initial signal line through the same via hole.

[0008] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to each other in a pixel column direction, the first initialization active layers in the two circuit units are connected to each other in an integrated structure.

[0009] In an exemplary embodiment, at least one circuit unit further includes at least one first initial connection line extending along a unit column direction, wherein the first initial connection line is connected to the first initial signal line to form a mesh connection structure.

[0010] In an exemplary embodiment, the at least one initial signal line includes a second initial signal line extending along the unit row direction, the at least one initialization transistor includes a second initialization transistor, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first electrodes of the second initialization transistors in the two circuit units are connected to the same second initial signal line, and the second initial signal line is configured to provide a second initial signal to the pixel driving circuit.

[0011] In an exemplary embodiment, the second initialization transistor includes at least a second initialization active layer, and at least one circuit unit further includes a second initial connection block. The first region of the second initialization active layer is connected to the second initial connection block via a connection electrode. In at least one circuit unit and a circuit unit adjacent to each other in a pixel column direction, the second initial connection blocks in the two circuit units are connected to the same second initial signal line.

[0012] In an exemplary embodiment, at least one circuit unit further includes at least one second initial connection line extending along the unit column direction, and the second initial connection line is connected to the second initial signal line to form a mesh connection structure.

[0013] In an exemplary embodiment, at least one circuit unit further includes an auxiliary initial signal line extending along the unit row direction, wherein the orthographic projection of the auxiliary initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane, and the auxiliary initial signal line is connected to the second initial signal line to form a second initial signal line with a double-layer structure.

[0014] In an exemplary embodiment, the at least one initial signal line includes a first initial signal line and a second initial signal line extending along the unit row direction, and at least one circuit unit further includes at least one third initial connection line extending along the unit column direction, and the third initial connection line is respectively connected to the first initial signal line and the second initial signal line to form a meshed connection structure.

[0015] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on a base, and the first preliminary signal line, the second preliminary signal line, and the preliminary connection line are disposed in different conductive layers.

[0016] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence along a direction away from the substrate, the first initial signal line is arranged in the fourth conductive layer, the second initial signal line is arranged in the third conductive layer, and the initial connecting line is arranged in the fifth conductive layer, or the first initial signal line is arranged in the third conductive layer, the second initial signal line is arranged in the fourth conductive layer, and the initial connecting line is arranged in the fifth conductive layer.

[0017] In an exemplary embodiment, the at least one initialization transistor includes a first initialization transistor, and the pixel driving circuit further includes a compensation transistor and a driving transistor, the gate electrode of the compensation transistor is connected to the third scanning signal line, the first electrode of the compensation transistor is connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the first initialization transistor and the second electrode of the driving transistor; the first initialization transistor and the compensation transistor are oxide transistors, the driving transistor is a polysilicon transistor, the first initialization transistor is a top-gate single-gate structure, and the compensation transistor is a top-gate and bottom-gate double-gate structure.

[0018] In an exemplary embodiment, at least one circuit unit further includes an auxiliary scanning signal line, the orthographic projection of the auxiliary scanning signal line on the display substrate plane at least partially overlaps with the orthographic projection of the third scanning signal line on the display substrate plane, and the auxiliary scanning signal line is connected to the third scanning signal line to form a double-layer structure of the third scanning signal line.

[0019] In an exemplary embodiment, the display substrate includes a plurality of conductive layers arranged on a base, the plurality of conductive layers including at least a gate metal layer and a source / drain metal layer arranged on a side of the gate metal layer away from the base, the third scan signal line is arranged in the gate metal layer, and the auxiliary scan signal line is arranged in the source / drain metal layer.

[0020] In an exemplary embodiment, the at least one initial signal line includes a first initial signal line and a second initial signal line extending along the unit row direction, and at least one circuit unit further includes at least one scanning signal line or a light-emitting signal line extending along the unit row direction, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit, and the orthographic projections of the first initial signal line and the second initial signal line on the display substrate plane do not overlap with the orthographic projections of the scanning signal line on the display substrate plane, and the orthographic projections of the first initial signal line and the second initial signal line on the display substrate plane do not overlap with the orthographic projections of the light-emitting signal line on the display substrate plane.

[0021] In an exemplary embodiment, at least one circuit unit further includes a power connection line extending along the unit row direction and a first power line extending along the unit column direction, the first power line being configured to provide a first power signal to the pixel driving circuit, the first power line being connected to the power connection line to form a mesh connectivity structure.

[0022] In an exemplary embodiment, at least one circuit unit further includes at least one scanning signal line or a light-emitting signal line extending along the unit row direction, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit, and the orthographic projection of the power connection line on the display substrate plane does not overlap with the orthographic projection of the scanning signal line on the display substrate plane, and the orthographic projection of the power connection line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

[0023] In an exemplary embodiment, at least one circuit unit further includes a first plate, a second plate, and an auxiliary plate; the orthographic projection of the first plate on the display substrate plane at least partially overlaps with the orthographic projection of the second plate on the display substrate plane, and the first plate and the second plate constitute a storage capacitor; the orthographic projection of the auxiliary plate on the display substrate plane at least partially overlaps with the orthographic projection of the second plate on the display substrate plane, the auxiliary plate is connected to the first plate via a first connecting electrode, and the auxiliary plate and the second plate constitute an auxiliary capacitor.

[0024] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0025] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the method comprising:

[0026] A pixel driving circuit and at least one initial signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least one initialization transistor, and the initial signal line is connected to the first electrode of the initialization transistor; in at least one circuit unit and a circuit unit adjacent in the pixel column direction, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to a row dividing line, and the first electrodes of the initialization transistors in the two pixel driving circuits are connected to the same initial signal line, and the row dividing line is a straight line located between adjacent unit rows and extending along the unit row direction.

[0027] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0029] FIG1 is a schematic structural diagram of a display device;

[0030] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0031] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0032] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0033] FIG5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG6 is a schematic diagram of a display substrate after a shielding layer pattern is formed thereon according to the present disclosure;

[0035] 7A and 7B are schematic diagrams of a display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0036] 8A and 8B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0037] 9A and 9B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0038] 10A and 10B are schematic diagrams of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0039] 11A and 11B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0040] 12A and 12B are schematic diagrams of a display substrate after a sixth insulating layer pattern is formed according to the present disclosure;

[0041] 13A and 13B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0042] FIG14 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure;

[0043] 15A and 15B are schematic diagrams of a display substrate after a fifth conductive layer pattern is formed thereon according to the present disclosure;

[0044] FIG16 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] FIG17 is a schematic diagram of another display substrate after forming a sixth insulating layer pattern according to the present disclosure;

[0046] 18A and 18B are schematic diagrams of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0047] FIG19 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure;

[0048] 20A and 20B are schematic diagrams of another display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0049] FIG21 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0050] FIG. 22 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0051] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line; 25—light-emitting signal line; 26—first shielding line; 27—power connection line; 31—first electrode plate; 32—second electrode plate; 33—opening; 34—board-level connecting bar; 41—first initial signal line; 42—second initial signal line; 43—auxiliary initial signal line; 44—auxiliary scanning signal line; 45—auxiliary electrode plate; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode; 60—shielding electrode; 61—first shielding connecting strip; 62—second shielding connecting strip; 71—first power line; 72—data signal line; 73—anode connecting electrode; 74—first initial connecting line; 75—second initial connecting line; 76—third initial connecting line; 77—second power line; 101—substrate; 102—driving structure layer; 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0053] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0054] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0055] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0056] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0057] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0058] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0059] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0060] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0061] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0062] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0063] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0064] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0065] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a third sub-pixel P3 emitting a third color light, a second sub-pixel P2 emitting a second color light, and a fourth sub-pixel P4 emitting a second color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0066] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal, and the four subpixels may be arranged in an RGBG pixel arrangement. In other exemplary embodiments, the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0067] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0068] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0069] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material laminated structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0070] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to nine signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power line VDD).

[0071] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0072] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0073] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the third node N3 .

[0074] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the third scan signal line S3 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0075] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0076] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0077] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0078] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0079] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0080] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0081] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0082] In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0083] In example embodiments, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0084] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0085] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0086] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0087] In an exemplary embodiment, the exemplary embodiment of the present disclosure displays a substrate including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one initial signal line, the pixel driving circuit including at least one initialization transistor, the initial signal line being connected to a first electrode of the initialization transistor; in at least one circuit unit and a circuit unit adjacent in the direction of the pixel column, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to a row dividing line, the first electrodes of the initialization transistors in the two pixel driving circuits are connected to the same initial signal line, and the row dividing line is a straight line located between adjacent unit rows and extending along the unit row direction.

[0088] In an exemplary embodiment, in at least one circuit unit, the at least one initial signal line includes a first initial signal line extending along the unit row direction, the at least one initialization transistor includes a first initialization transistor, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first electrodes of the first initialization transistors in the two circuit units are connected to the same first initial signal line, and the first initial signal line is configured to provide a first initial signal to the pixel driving circuit.

[0089] In an exemplary embodiment, in at least one circuit unit, the at least one initial signal line includes a second initial signal line extending along the unit row direction, the at least one initialization transistor includes a second initialization transistor, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first electrodes of the second initialization transistors in the two circuit units are connected to the same second initial signal line, and the second initial signal line is configured to provide a second initial signal to the pixel driving circuit.

[0090] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the multiple circuit units can form multiple unit rows and multiple unit columns, with the multiple circuit units in each unit row arranged sequentially along a first direction X, and the multiple circuit units in each unit column arranged sequentially along a second direction Y, forming an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0091] In an exemplary embodiment, at least one circuit unit may include at least a pixel driving circuit. The pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The storage capacitor may include a first plate and a second plate, wherein the orthographic projection of the second plate on the display substrate plane at least partially overlaps with the orthographic projection of the first plate on the display substrate plane. The plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, and a seventh transistor T7 as a second initialization transistor.

[0092] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 24, and the first electrode of the first transistor T1 is connected to the first initial signal line 41. The gate electrode of the second transistor T2 is connected to the third scan signal line 23, and the first electrode of the second transistor T2 is connected to the first plate of the storage capacitor (which is also the gate electrode of the third transistor T3). The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line 72. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, the first electrode of the fifth transistor T5 is connected to the first power supply line 71, and the second electrode of the fifth transistor T5 is respectively connected to the first electrode of the third transistor T3 and the second electrode of the fourth transistor T4. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 25, and the first electrode of the sixth transistor T6 is respectively connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the third transistor T3. A gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22 , a first electrode of the seventh transistor T7 is connected to the second initial signal line 42 , and a second electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6 .

[0093] In example embodiments, the first and second transistors T1 and T2 may be oxide transistors, and the third to seventh transistors T3 to T7 may be low-temperature polysilicon transistors.

[0094] In an exemplary embodiment, the first transistor T1 has a top-gate single-gate structure, and the second transistor T2 has a top-gate and bottom-gate double-gate structure.

[0095] In an exemplary embodiment, the shapes of the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the fourth scanning signal line 24, the light-emitting signal line 25, the first initial signal line 41 and the second initial signal line 42 can be straight lines or broken lines with the main parts extending along the first direction X (pixel row direction), and the shapes of the first power line 71 and the data signal line 72 can be straight lines or broken lines with the main parts extending along the second direction Y (pixel column direction).

[0096] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0097] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the fourth scan signal line 24 are configured to provide the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal to the pixel driving circuit, respectively, the light-emitting signal line is configured to provide the light-emitting control signal to the pixel driving circuit, the first initial signal line 41 and the second initial signal line 42 are configured to provide the first initial signal and the second initial signal to the pixel driving circuit, respectively, the first power line 71 is configured to provide the first power signal to the pixel driving circuit, and the data signal line 72 is configured to provide the data signal to the pixel driving circuit.

[0098] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent in the second direction Y, the pixel driving circuits in the two circuit units are mirror-symmetric with respect to a row boundary O, and the row boundary O may be a straight line located between adjacent unit rows and extending along the unit row direction. For example, the pixel driving circuit in the Mth unit row and the pixel driving circuit in the M+1th unit row are mirror-symmetric with respect to the row boundary. For another example, the pixel driving circuit in the M-1th unit row and the pixel driving circuit in the Mth unit row are mirror-symmetric with respect to the row boundary. For another example, the pixel driving circuit in the M+1th unit row and the pixel driving circuit in the M+2th unit row are mirror-symmetric with respect to the row boundary.

[0099] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to each other in the first direction X, the pixel driving circuits in the two circuit units are mirror-symmetric with respect to a column boundary, where the column boundary is a straight line located between adjacent unit columns and extending along the unit column direction. For example, the pixel driving circuit in the Nth unit column and the pixel driving circuit in the N+1th unit column are mirror-symmetric with respect to the column boundary. For another example, the pixel driving circuit in the N+1th unit column and the pixel driving circuit in the N+2th unit column are mirror-symmetric with respect to the column boundary. For another example, the pixel driving circuit in the N+2th unit column and the pixel driving circuit in the N+3th unit column are mirror-symmetric with respect to the column boundary.

[0100] In an exemplary embodiment, in at least one circuit unit and circuit units adjacent to each other in the second direction Y, first electrodes of initialization transistors in two pixel driving circuits are connected to the same initialization signal line.

[0101] In an exemplary embodiment, in at least one circuit unit, the first electrode of the first transistor T1 (first initialization transistor) is connected to the first initialization signal line 41. In at least one circuit unit and circuit units adjacent in the second direction Y, the first electrodes of the first transistors T1 in two circuit units are connected to the same first initialization signal line 41, that is, the pixel driving circuits in two adjacent unit rows share the same first initialization signal line 41. For example, the pixel driving circuits in the M-1 unit row and the M-th unit row share the same first initialization signal line 41. For another example, the pixel driving circuits in the M+1 unit row and the M+2 unit row share the same first initialization signal line 41.

[0102] In an exemplary embodiment, the first transistor T1 may include at least a first active layer. In at least one circuit unit and a circuit unit adjacent in the second direction Y, the first active layers in the two circuit units may be interconnected as an integrated structure, and the first regions of the first active layers in the two circuit units may be connected to the same first initial signal line 41 through the same via hole. That is, the pixel driving circuits in two adjacent unit rows share the same first region of the first active layer and the same via hole.

[0103] In an exemplary embodiment, at least one circuit unit may further include at least one first initial connection line 74, and the shape of the first initial connection line 74 may be a straight line or a broken line extending along the second direction Y. The first initial connection line 74 may be connected to the first initial signal line 41, so that the first initial signal line 41 and the first initial connection line 74 form a meshed connection structure for transmitting the first initial signal.

[0104] In an exemplary embodiment, the orthographic projection of the first initial signal line 41 on the display substrate plane does not overlap with the orthographic projections of the first scan signal line 21 , the second scan signal line 22 , the third scan signal line 23 , the fourth scan signal line 24 and the light emitting signal line 25 on the display substrate plane.

[0105] In an exemplary embodiment, in at least one circuit unit, the first electrode of the seventh transistor T7 (the second initialization transistor) is connected to the second initialization signal line 42. In at least one circuit unit and circuit units adjacent to each other in the second direction Y, the first electrodes of the seventh transistors T7 in two circuit units are connected to the same second initialization signal line 42, that is, the pixel driving circuits in two adjacent unit rows share the same second initialization signal line 42. For example, the pixel driving circuits in the Mth unit row and the M+1th unit row share the same second initialization signal line 42.

[0106] In an exemplary embodiment, the seventh transistor T7 may include at least a seventh active layer, and at least one circuit unit may further include a second initial connection block, wherein the first region of the seventh active layer is connected to the second initial connection block via a connection electrode. In the at least one circuit unit and adjacent circuit units in the second direction Y, the second initial connection blocks in both circuit units are connected to the same second initial signal line 42.

[0107] In an exemplary embodiment, at least one circuit unit may further include at least one second initial connection line 75, and the shape of the second initial connection line 75 may be a straight line or a broken line extending along the second direction Y. The second initial connection line 75 may be connected to the second initial signal line 42, so that the second initial signal line 42 and the second initial connection line 75 form a meshed connection structure for transmitting the second initial signal.

[0108] In an exemplary embodiment, at least one circuit unit may further include at least one auxiliary initial signal line, and the shape of the auxiliary initial signal line may be a straight line or a broken line extending along the first direction X. The orthographic projection of the auxiliary initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line 42 on the display substrate plane. The auxiliary initial signal line is connected to the second initial signal line 42 through a via to form a second initial signal line with a double-layer structure.

[0109] In an exemplary embodiment, the second initial connection line 75 may be connected to the auxiliary initial signal line through a via, and the auxiliary initial signal line is connected to the second initial signal line 42 through a via, thereby achieving connection between the second initial connection line 75 and the second initial signal line 42 .

[0110] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the display substrate plane does not overlap with the orthographic projections of the first scan signal line 21 , the second scan signal line 22 , the third scan signal line 23 , the fourth scan signal line 24 and the light emitting signal line 25 on the display substrate plane.

[0111] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a plurality of conductive layers disposed on a base, and the first preliminary signal line 41 and the second preliminary signal line 42 are disposed in different conductive layers.

[0112] In an exemplary embodiment, the plurality of conductive layers may include at least a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially arranged in a direction away from the substrate. The first initial signal line 41 may be arranged in the fourth conductive layer, the second initial signal line 42 may be arranged in the third conductive layer, and the first initial connection line 74 and the second initial connection line 75 may be arranged in the fifth conductive layer. Alternatively, the first initial signal line 41 may be arranged in the third conductive layer, the second initial signal line 42 may be arranged in the fourth conductive layer, and the first initial connection line 74 and the second initial connection line 75 may be arranged in the fifth conductive layer.

[0113] In an exemplary embodiment, at least one circuit unit may further include at least one power connection line 27. The shape of the power connection line 27 may be a straight line or a broken line extending along the second direction Y. The power connection line 27 may be connected to the first power line 71, so that the power connection line 27 and the first power line 71 form a meshed connection structure for transmitting the first power signal.

[0114] In an exemplary embodiment, the orthographic projection of the power connection line 27 on the display substrate plane does not overlap with the orthographic projections of the first scan signal line 21 , the second scan signal line 22 , the third scan signal line 23 , the fourth scan signal line 24 and the light emitting signal line 25 on the display substrate plane.

[0115] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0116] In an exemplary embodiment, taking eight circuit units (the Mth unit row and the M+1th unit row, the Nth unit column, the N+1th unit column, the N+2th unit column and the N+3th unit column) as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0117] (11) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG6 . In an exemplary embodiment, the blocking layer may be referred to as a bottom metal (LS) layer.

[0118] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 60 , a first shielding connection bar 61 , and a second shielding connection bar 62 .

[0119] In an exemplary embodiment, the shielding electrode 60 may be rectangular in shape, with chamfers or grooves provided at the corners of the rectangle, and may be disposed in a central region of the circuit unit in the first direction X and the second direction Y.

[0120] In an exemplary embodiment, the shape of the first shielding connection strip 61 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding connection strip 61 can be arranged on one side of the shielding electrode 60 in the first direction X or on the side opposite to the first direction X of the shielding electrode 60. The first end of the first shielding connection strip 61 is connected to the shielding electrode 60 of the current circuit unit, and the second end of the first shielding connection strip 61 is connected to the shielding electrode 60 of the adjacent circuit unit in the first direction X, so that the first shielding connection strip 61 and the shielding electrode 60 in a unit row are connected into one, forming an interconnected structure.

[0121] In an exemplary embodiment, the shape of the second shielding connection strip 62 can be a straight line or a broken line with the main part extending along the second direction Y. The second shielding connection strip 62 can be arranged on one side of the shielding electrode 60 in the second direction Y or on the side opposite to the second direction Y of the shielding electrode 60. The first end of the second shielding connection strip 62 is connected to the shielding electrode 60 of the current circuit unit, and the second end of the second shielding connection strip 62 is connected to the shielding electrode 60 of the adjacent circuit unit in the second direction Y, so that the second shielding connection strip 62 and the shielding electrode 60 in a unit column are connected into one, forming an interconnected structure.

[0122] In an exemplary embodiment, in at least one unit column, the plurality of shielding electrodes 60 and the plurality of first shielding connection bars 61 may be an integrated structure connected to each other.

[0123] In an exemplary embodiment, in at least one unit column, the plurality of shielding electrodes 60 and the plurality of second shielding connection bars 62 may be an integrated structure connected to each other.

[0124] In an exemplary embodiment, the multiple blocking electrodes 60, the multiple first blocking connecting strips 61 and the multiple second blocking connecting strips 62 in the multiple unit rows and the multiple unit columns can be an integrated structure connected to each other, which can ensure that the blocking layers in the display substrate have the same electric potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0125] In an exemplary embodiment, the shielding layers of adjacent cell rows may be mirror-symmetrical with respect to the row boundary. For example, the shielding layer in the Mth cell row and the shielding layer in the M+1th cell row may be mirror-symmetrical with respect to the row boundary. For another example, the shielding layer in the M-1th cell row and the shielding layer in the Mth cell row may be mirror-symmetrical with respect to the row boundary. For another example, the shielding layer in the M+1th cell row and the shielding layer in the M+2th cell row may be mirror-symmetrical with respect to the row boundary.

[0126] In an exemplary embodiment, the shielding layers of adjacent unit columns may be mirror-symmetric with respect to the column boundary. For example, the shielding layer of the Nth unit column and the shielding layer of the N+1th unit column may be mirror-symmetric with respect to the column boundary, the shielding layer of the N+1th unit column and the shielding layer of the N+2th unit column may be mirror-symmetric with respect to the column boundary, and the shielding layer of the N+2th unit column and the shielding layer of the N+3th unit column may be mirror-symmetric with respect to the column boundary.

[0127] (12) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a plan view schematic diagram of the first semiconductor layer in FIG7A .

[0128] In an exemplary embodiment, the first semiconductor layer pattern of each circuit unit may include at least the third active layer 13 of the third transistor T3 to the seventh active layer 17 of the seventh transistor T7, the third active layer 13 and the fourth active layer 14 may be an integrated structure connected to each other, the sixth active layer 16 and the seventh active layer 17 may be an integrated structure connected to each other, and the fifth active layer 15 may be provided separately.

[0129] In an exemplary embodiment, in the first direction X, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on one side of the fourth active layer 14 in the first direction X or on a side opposite to the first direction X, that is, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on the same side of the fourth active layer 14. In the second direction Y, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on one side of the third active layer 13 in the second direction Y or on a side opposite to the second direction Y, that is, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on the same side of the third active layer 13.

[0130] In an exemplary embodiment, the third active layer 13 may have an L shape, and the fourth, fifth, sixth, and seventh active layers 14, 15, 16, and 17 may have an I shape.

[0131] In an exemplary embodiment, each of the third to seventh active layers 13 to 17 may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer and the second region 14-2 of the fourth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer. The second region 16-2 of the sixth active layer is connected to the second region 17-2 of the seventh active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The second region 13-2 of the third active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the second region 15-2 of the fifth active layer, the first region 16-1 of the sixth active layer, and the first region 17-1 of the seventh active layer may be provided separately.

[0132] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 60 on the substrate. The shielding electrode 60 can serve as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0133] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer 13 on the substrate is located within the range of the orthographic projection of the shielding electrode 60 on the substrate.

[0134] In example embodiments, the seventh active layer 17 may be referred to as a second initialization active layer.

[0135] In an exemplary embodiment, the first semiconductor layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the first semiconductor layer in the Mth cell row and the first semiconductor layer in the M+1th cell row may be mirror-symmetric with respect to the row boundary. For another example, the first semiconductor layer in the M-1th cell row and the first semiconductor layer in the Mth cell row may be mirror-symmetric with respect to the row boundary. For another example, the first semiconductor layer in the M+1th cell row and the first semiconductor layer in the M+2th cell row may be mirror-symmetric with respect to the row boundary.

[0136] In an exemplary embodiment, the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the first semiconductor layer of the Nth cell column and the first semiconductor layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary, the first semiconductor layer of the N+1th cell column and the first semiconductor layer of the N+2th cell column may be mirror-symmetrical with respect to the column boundary, and the first semiconductor layer of the N+2th cell column and the first semiconductor layer of the N+3th cell column may be mirror-symmetrical with respect to the column boundary.

[0137] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0138] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the first conductive layer in FIG8A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0139] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a light emitting signal line 25 , and a first plate 31 of a storage capacitor.

[0140] In an exemplary embodiment, the first electrode plate 31 may be rectangular, with chamfered or grooved corners. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 31 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0141] In an exemplary embodiment, an orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with an orthographic projection of the shielding electrode 60 on the substrate.

[0142] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line with the main portion extending along the first direction X. The first scanning signal line 21 can be located on one side of the first electrode plate 31 in the second direction Y or on the side opposite to the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.

[0143] In an exemplary embodiment, the shape of the second scan signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scan signal line 22 can be located on the side of the first scan signal line 21 away from the first electrode plate 31, and the area where the second scan signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.

[0144] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a broken line with the main portion extending along the first direction X. The light-emitting signal line 25 can be located between the first scanning signal line 21 and the second scanning signal line 22. The area where the light-emitting signal line 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 25 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0145] In an exemplary embodiment, the first conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the first conductive layer in the Mth cell row and the first conductive layer in the M+1th cell row may be mirror-symmetric with respect to the row boundary. For another example, the first conductive layer in the M-1th cell row and the first conductive layer in the Mth cell row may be mirror-symmetric with respect to the row boundary. For another example, the first conductive layer in the M+1th cell row and the first conductive layer in the M+2th cell row may be mirror-symmetric with respect to the row boundary.

[0146] In an exemplary embodiment, the first conductive layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the first conductive layer of the Nth cell column and the first conductive layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary, the first conductive layer of the N+1th cell column and the first conductive layer of the N+2th cell column may be mirror-symmetrical with respect to the column boundary, and the first conductive layer of the N+2th cell column and the first conductive layer of the N+3th cell column may be mirror-symmetrical with respect to the column boundary.

[0147] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the third transistor T3 to the seventh transistor T7 are both conductorized.

[0148] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the second conductive layer in FIG9A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0149] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a second plate 32 of the storage capacitor, a first shielding line 26 , and a power connection line 27 .

[0150] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as another electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0151] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. The opening 33 may be rectangular and located on a side of the second electrode plate 32 away from the first scan signal line 21. The opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a twelfth via hole to be formed later. The twelfth via hole is located within the opening 33 and exposes the first electrode plate 31, allowing a first connecting electrode to be formed later to be connected to the first electrode plate 31.

[0152] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate-level connecting bar 34. The plate-level connecting bar 34 may be in the shape of a straight line or a broken line extending along the first direction X. The plate-level connecting bar 34 may be provided on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the plate-level connecting bar 34 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the plate-level connecting bar 34 is connected to the second electrode plate 32 in the adjacent circuit unit in the first direction X.

[0153] In an exemplary embodiment, the second plates 32 in two adjacent circuit units in a unit row can be interconnected integral structures. For example, the second plate 32 of the Nth unit column and the second plate 32 of the N+1th unit column are interconnected by a plate-level connecting bar 34 to form an interconnected integral structure. For another example, the second plate 32 of the N+1th unit column and the second plate 32 of the N+2th unit column can be interconnected by a plate-level connecting bar 34 to form an interconnected integral structure. Since the second plate 32 in each circuit unit is connected to the first power line formed subsequently, by forming the second plates 32 of adjacent circuit units into an interconnected integral structure, the second plates of the integral structure can be reused as a power signal line, which can ensure that the multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0154] In an exemplary embodiment, since the first power lines in a cell column are respectively connected to the second plates 32 in multiple circuit cells in the cell column, the second plates 32 of the integrated structure in one cell row are connected to the second plates 32 of the integrated structure in other cell rows through the first power lines.

[0155] In an exemplary embodiment, the first shielding line 26 may be in the shape of a straight line or a line, with the main portion extending along the first direction X. The first shielding line 26 may be located on a side of the second plate 32 away from the first scan signal line 21. A first shielding block 26-1 may be provided on a side of the first shielding line 26 close to the second plate 32. The first shielding block 26-1 may be in the shape of a block (e.g., a rectangle). A first end of the first shielding block 26-1 is connected to the first shielding line 26, and a second end of the first shielding block 26-1 extends toward the second plate 32. The first shielding block 26-1 is configured as a shielding layer for the second transistor T2, shielding the channel region of the second transistor T2 to ensure the electrical performance of the oxide second transistor T2, and is also configured as the bottom gate electrode of the second transistor T2.

[0156] In an exemplary embodiment, the first shielding line 26 and the first shielding block 26 - 1 may be an integral structure connected to each other.

[0157] In an exemplary embodiment, the power connection line 27 may be in the shape of a straight line or a line, with a main portion extending along the first direction X. The power connection line 27 may be located on a side of the second scan signal line 22 away from the second electrode plate 32. A power connection block 27-1 may be provided on a side of the power connection line 27 close to the second electrode plate 32. The power connection block 27-1 may be in the shape of a block (e.g., a rectangle). A first end of the power connection block 27-1 is connected to the power connection line 27, and a second end of the power connection block 27-1 extends toward the second electrode plate 32. The power connection block 27-1 is configured to be connected to a ninth connection electrode to be formed subsequently.

[0158] In an exemplary embodiment, the power connection line 27 and the power connection block 27 - 1 may be an integral structure connected to each other.

[0159] In an exemplary embodiment, the orthographic projection of the power connection line 27 on the substrate does not overlap with the orthographic projections of the first scanning signal line 21, the second scanning signal line 22 and the light-emitting signal line 25 on the substrate, which can minimize the parasitic capacitance of the power connection line, effectively improve the horizontal stripes caused by excessive parasitic capacitance of the power connection line, and improve the display quality and display quality.

[0160] In an exemplary embodiment, the second conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the second conductive layer in the Mth cell row and the second conductive layer in the M+1th cell row may be mirror-symmetric with respect to the row boundary. For another example, the second conductive layer in the M-1th cell row and the second conductive layer in the Mth cell row may be mirror-symmetric with respect to the row boundary. For another example, the second conductive layer in the M+1th cell row and the second conductive layer in the M+2th cell row may be mirror-symmetric with respect to the row boundary.

[0161] In an exemplary embodiment, the second conductive layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary. For example, the second conductive layer of the Nth cell column and the second conductive layer of the N+1th cell column may be mirror-symmetrical with respect to the column boundary, the second conductive layer of the N+1th cell column and the second conductive layer of the N+2th cell column may be mirror-symmetrical with respect to the column boundary, and the second conductive layer of the N+2th cell column and the second conductive layer of the N+3th cell column may be mirror-symmetrical with respect to the column boundary.

[0162] (15) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second semiconductor layer in FIG10A .

[0163] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a first active layer 11 of a first transistor T1 and a second active layer 12 of a second transistor T2 , and the first active layer 11 and the second active layer 12 are connected to each other as an integral structure.

[0164] In an exemplary embodiment, the first active layer 11 may be in a strip shape extending along the second direction Y, and an orthographic projection of the first active layer 11 on the substrate at least partially overlaps an orthographic projection of the first shielding line 26 on the substrate.

[0165] In an exemplary embodiment, the second active layer 12 may be in the shape of a strip extending along the first direction X, and an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the first blocking block 26 - 1 of the first blocking line 26 on the substrate.

[0166] In an exemplary embodiment, the second region 11-2 of the first active layer and the second region 12-2 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the second region 12-2 of the second active layer. The first region 11-1 of the first active layer and the first region 12-1 of the second active layer may be provided separately. The first region 11-1 of the first active layer may be located on a side of the first shielding line 26 away from the second electrode plate 32, and the first region 12-1 of the second active layer may be located on a side of the first shielding line 26 close to the second electrode plate 32.

[0167] In an exemplary embodiment, the first active layers 11 of some adjacent cell rows may be interconnected as a single unit. For example, the first active layer 11 in the M-1th cell row and the first active layer 11 in the Mth cell row may be interconnected as a single unit, and the circuit units in the two adjacent cell rows may share the first region 11-1 of the same first active layer. For another example, the first active layer 11 in the M+1th cell row and the first active layer 11 in the M+2th cell row may be interconnected as a single unit, and the circuit units in the two adjacent cell rows may share the first region 11-1 of the same first active layer.

[0168] In an exemplary embodiment, the first active layer 11 may be referred to as a first initialization active layer. In at least one circuit unit and a circuit unit adjacent in the pixel column direction, the first active layers 11 in the two circuit units may be interconnected as a single unit, and the first active layers 11 in the two circuit units may share the same first region 11-1 of the first active layer. For example, the first active layer 11 in the M-1th cell row and the first active layer 11 in the Mth cell row may be interconnected as a single unit. For another example, the first active layer 11 in the M+1th cell row and the first active layer 11 in the M+2th cell row may be interconnected as a single unit.

[0169] In an exemplary embodiment, the second semiconductor layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the second semiconductor layer in the Mth cell row and the second semiconductor layer in the M+1th cell row may be mirror-symmetric with respect to the row boundary. For another example, the second semiconductor layer in the M-1th cell row and the second semiconductor layer in the Mth cell row may be mirror-symmetric with respect to the row boundary. For another example, the second semiconductor layer in the M+1th cell row and the second semiconductor layer in the M+2th cell row may be mirror-symmetric with respect to the row boundary.

[0170] In an exemplary embodiment, the second semiconductor layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the second semiconductor layer of the Nth cell column and the second semiconductor layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, the second semiconductor layer of the N+1th cell column and the second semiconductor layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary, and the second semiconductor layer of the N+2th cell column and the second semiconductor layer of the N+3th cell column may be mirror-symmetric with respect to the column boundary. In an exemplary embodiment, the shapes of the second semiconductor layers in multiple cell rows may be substantially the same.

[0171] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0172] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the third conductive layer in FIG11A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0173] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a third scan signal line 23 , a fourth scan signal line 24 , and a second preliminary signal line 42 .

[0174] In an exemplary embodiment, the third scan signal line 23 may be in the shape of a straight line or a line, with the main portion extending along the first direction X. The third scan signal line 23 may be located on a side of the second electrode plate 32 away from the first scan signal line 21. A third gate block 23-1 may be disposed on a side of the third scan signal line 23 close to the second electrode plate 32. The third gate block 23-1 may be in the shape of a block (e.g., a rectangle). A first end of the third gate block 23-1 is connected to the third scan signal line 23, and a second end of the third gate block 23-1 extends toward the second electrode plate 32. The region where the third gate block 23-1 overlaps with the second active layer may serve as the gate electrode of the second transistor T2.

[0175] In an exemplary embodiment, the third scan signal line 23 and the third gate block 23 - 1 may be an integral structure connected to each other.

[0176] In an exemplary embodiment, the orthographic projection of the third gate block 23-1 on the substrate at least partially overlaps with the orthographic projection of the first blocking block 26-1 on the substrate, and the third scanning signal line 23 and the first blocking line 26 can be connected to the same signal source, so that the first blocking block 26-1 can serve as the bottom gate electrode of the second transistor T2, and the third gate block 23-1 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-bottom double-gate structure.

[0177] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a line shape with the main portion extending along the first direction X. The fourth scan signal line 24 can be located on the side of the third scan signal line 23 away from the second electrode plate 32, and the area overlapping with the first active layer can serve as the top gate electrode of the first transistor T1.

[0178] In an exemplary embodiment, the first transistor T1 and the second transistor T2 of the oxide are single-gate and top-bottom dual-gate, respectively. By configuring the first transistor T1 of the oxide as a single-gate structure and the second transistor T2 of the oxide as a top-bottom dual-gate structure, the present disclosure can reduce mutual interference between the first transistor T1 and the second transistor T2, and can also reduce mutual interference between the third scan signal line 23 and the fourth scan signal line 24, thereby improving the driving performance of the pixel driving circuit.

[0179] In an exemplary embodiment, the second initial signal line 42 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The second initial signal line 42 may be located between the power connection lines 27 of two cell rows. A second initial connection block 42-1 may be provided on a side of the second initial signal line 42 near the second electrode plate 32. The second initial connection block 42-1 may be in the shape of a block (e.g., a rectangle). A first end of the second initial connection block 42-1 is connected to the second initial signal line 42, and a second end of the second initial connection block 42-1 extends toward the second electrode plate 32. The second initial connection block 42-1 is configured to connect to the first region of the seventh active layer via a subsequently formed eighth connection electrode.

[0180] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate does not overlap with the orthographic projections of the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the fourth scanning signal line 24 and the light-emitting signal line 25 on the substrate, which can minimize the parasitic capacitance of the second initial signal line, effectively improve the horizontal stripes caused by the excessive parasitic capacitance of the second initial signal line, and improve the display quality.

[0181] In an exemplary embodiment, in at least one circuit unit and circuit units adjacent in the second direction Y, the second initial connection blocks 42-1 in both circuit units are connected to the same second initial signal line 42, that is, adjacent unit rows can share the same second initial signal line 42. For example, the second initial signal line 42 of the Mth unit row is also the second initial signal line 42 of the M+1th unit row, and the second initial connection blocks 42-1 of each circuit unit in the Mth unit row and the second initial connection blocks 42-1 of each circuit unit in the M+1th unit row are connected to the same second initial signal line 42. By allowing adjacent unit rows to share the same second initial signal line, the present disclosure effectively reduces the number of wiring, reduces the space occupied by the pixel driver circuit, optimizes the layout space, effectively improves the yield, and effectively increases the aperture ratio, making it suitable for high-resolution products.

[0182] In an exemplary embodiment, the third conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the third conductive layer in the Mth cell row and the third conductive layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the third conductive layer in the M-1th cell row and the third conductive layer in the Mth cell row may be mirror-symmetric with respect to a row boundary. For another example, the third conductive layer in the M+1th cell row and the third conductive layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary.

[0183] In an exemplary embodiment, the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the third conductive layer of the Nth cell column and the third conductive layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, the third conductive layer of the N+1th cell column and the third conductive layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary, and the third conductive layer of the N+2th cell column and the third conductive layer of the N+3th cell column may be mirror-symmetric with respect to the column boundary.

[0184] (17) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of via holes, as shown in FIG. 12A .

[0185] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14 and a fifteenth via V15.

[0186] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via hole.

[0187] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the second region of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer (also the second region of the second active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer (also the second region of the second active layer) through the via hole.

[0188] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.

[0189] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer), and the fourth via hole V4 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer) through the via hole.

[0190] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second region of the third active layer. The fifth via hole V5 is configured to connect a subsequently formed second connecting electrode to the second region of the third active layer through the via hole.

[0191] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0192] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fifth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0193] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second region of the fifth active layer, and the eighth via V8 is configured to connect a subsequently formed fourth connecting electrode to the second region of the fifth active layer through the via hole.

[0194] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the sixth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first area of ​​the sixth active layer, and the ninth via hole V9 is configured to connect the subsequently formed second connecting electrode to the first area of ​​the sixth active layer through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the tenth via hole V10 is configured to connect the subsequently formed sixth connecting electrode to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole.

[0196] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eleventh via hole V11 are etched away to expose the surface of the first region of the seventh active layer, and the eleventh via hole V11 is configured to connect the subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0197] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the twelfth via hole V12 are etched away to expose the surface of the first electrode 31. The twelfth via hole V12 is configured to connect a subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0198] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the second electrode plate 32, and the thirteenth via hole V13 is configured to connect the subsequently formed seventh connecting electrode to the second electrode plate 32 through the via hole.

[0199] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the sixth insulating layer in the fourteenth via V14 is etched away, exposing the surface of the second initial connection block 42-1, and the fourteenth via V14 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 42-1 through the via.

[0200] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the power connection block 27-1 of the power connection line 27 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the power connection block 27-1, and the fifteenth via hole V15 is configured to connect the subsequently formed ninth connection electrode to the power connection block 27-1 through the via hole.

[0201] In an exemplary embodiment, at least one circuit unit may further be provided with a sixteenth via V16. The orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second initial signal line 42 on the substrate. The sixth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the second initial signal line 42. The sixteenth via V16 is configured to connect a subsequently formed auxiliary initial signal line to the second initial signal line 42 through the via.

[0202] In exemplary embodiments, the sixteenth via V16 may be disposed between the Nth cell column and the N+1th cell column, or may be disposed between the N+2th cell column and the N+3th cell column.

[0203] Figure 12B is a schematic diagram of adjacent circuit units of the present disclosure sharing the same first via. As shown in Figure 12B, since the first active layers of some adjacent cell rows are interconnected as a single unit, the two circuit units share the first region of the first active layer. Therefore, the two circuit units in some adjacent cell rows can share the same first via V1. Since the first via V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer, the first regions of the first active layers in the two circuit units are connected to the same first initial signal line through the same via. For example, in at least one cell column, the first active layer in the M+1th cell row and the first active layer in the M+2th cell row are interconnected as a single unit. The first active layers of the two circuit units share the same first region of the first active layer. Therefore, the two circuit units share the same first via V1. The first regions of the first active layers of the two circuit units are connected to the same first initial signal line through the shared first via V1. The first initial signal line simultaneously writes the first initial signal into the first electrode of the first transistor T1 of the two circuit units.

[0204] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 13A and FIG. 13B , where FIG. 13B is a plan view schematic diagram of the fourth conductive layer in FIG. 13A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0205] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first initial signal line 41, an auxiliary initial signal line 43, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.

[0206] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main portion extending along the first direction X. The first initial signal line 41 can be located on the side of the fourth scanning signal line 24 away from the second electrode plate 32. The first initial signal line 41 is connected to the first area of ​​the first active layer in each circuit unit through the first via V1 in each circuit unit, so that the first initial signal line 41 writes the first initial signal into the first electrode of the first transistor T1.

[0207] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent in the second direction Y, the first regions of the first active layers in the two circuit units are connected to the same first initial signal line 41, that is, adjacent unit rows can share the same first initial signal line 41. For example, the first initial signal line 41 of the M-1th unit row is also the first initial signal line 41 of the Mth unit row, and the first regions of the first active layers in the two circuit units are connected to the same first initial signal line 41 through the same first via. For another example, the first initial signal line 41 of the M+1th unit row is also the first initial signal line 41 of the M+2th unit row, and the first regions of the first active layers in the two circuit units are connected to the same first initial signal line 41 through the same first via. By setting up adjacent unit rows to share the same first initial signal line and the same first via, the present disclosure effectively reduces the number of wiring and the number of vias, reduces the space occupied by the pixel driving circuit, optimizes the layout space, effectively improves the yield, effectively improves the aperture ratio, and is adaptable to high-resolution products.

[0208] In an exemplary embodiment, the orthographic projection of the first initial signal line 41 on the substrate does not overlap with the orthographic projections of the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the fourth scanning signal line 24 and the light-emitting signal line 25 on the substrate, which can minimize the parasitic capacitance of the first initial signal line, effectively improve the horizontal stripes caused by the excessive parasitic capacitance of the first initial signal line, and improve the display quality.

[0209] In an exemplary embodiment, the shape of the auxiliary initial signal line 43 can be a straight line or a broken line with the main part extending along the first direction X. The auxiliary initial signal line 43 can be located between the power connection lines 27 of two adjacent unit rows and connected to the second initial signal line 42 through the sixteenth via V16.

[0210] In an exemplary embodiment, the orthographic projection of auxiliary initial signal line 43 on the substrate at least partially overlaps the orthographic projection of second initial signal line 42 on the substrate, forming a double-layer structure of initial signal lines. By forming a double-layer structure of initial signal lines, the present disclosure can effectively reduce the resistance of second initial signal line 42, reduce the voltage drop of the second initial signal, and effectively improve the uniformity of the second initial signal across the display substrate, effectively improving display uniformity and enhancing display quality.

[0211] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the first region of the second active layer through a third via hole V3. The second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 31 through a twelfth via hole V12. In an exemplary embodiment, because the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0212] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 52 is connected to the second region of the first active layer (also the second region of the second active layer) via a second via hole V2. A second end of the second connection electrode 52 is connected to the first region of the sixth active layer via a ninth via hole V9. A portion between the first and second ends of the second connection electrode 52 is connected to the second region of the third active layer via a fifth via hole V5. In an exemplary embodiment, the second connection electrode 52 causes the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0213] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fourth active layer through a sixth via hole V6. In an exemplary embodiment, the third connection electrode 53 may serve as a first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0214] In an exemplary embodiment, the fourth connection electrode 54 may be in an "L" shape. A first end of the fourth connection electrode 54 is connected to the first region of the third active layer (also the second region of the fourth active layer) via a fourth via hole V4, and a second end of the fourth connection electrode 54 is connected to the second region of the fifth active layer via an eighth via hole V8. In an exemplary embodiment, the fourth connection electrode causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0215] In an exemplary embodiment, the fifth connection electrode 55 may be in a block shape (e.g., a rectangular shape) and is connected to the first region of the fifth active layer through a seventh via hole V7. In an exemplary embodiment, the fifth connection electrode 55 may serve as a first electrode of the fifth transistor T5 and is configured to be connected to a first power line formed subsequently.

[0216] In an exemplary embodiment, the sixth connection electrode 56 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a tenth via hole V10. In an exemplary embodiment, the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, forming a fourth node N4 of the pixel driving circuit. The sixth connection electrode 56 is configured to be connected to an anode connection electrode formed subsequently.

[0217] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a bar with a main portion extending along the first direction X. The seventh connection electrode 57 is connected to the second electrode plate 32 through the thirteenth via hole V13 and is configured to be connected to a first power line formed subsequently.

[0218] In an exemplary embodiment, the seventh connecting electrodes 57 of some adjacent circuit cells in a unit row may be interconnected as an integral structure, ensuring that the second electrode plates 32 of adjacent circuit cells have the same potential, thereby improving the uniformity of the panel, preventing display defects on the display substrate, and ensuring the display quality of the display substrate. For example, the seventh connecting electrode 57 of the N-1th column and the seventh connecting electrode 57 of the Nth unit column are interconnected as an integral structure, the seventh connecting electrode 57 of the N+1th unit column and the seventh connecting electrode 57 of the N+2th unit column are interconnected as an integral structure, and the seventh connecting electrode 57 of the N+3th unit column and the seventh connecting electrode 57 of the N+4th column are interconnected as an integral structure.

[0219] In the exemplary embodiment, since the first plate 31 has the potential of the first node N1 and the second plate 32 has the potential of the first power line, the first plate 31 and the second plate 32 form a storage capacitor.

[0220] In an exemplary embodiment, the eighth connection electrode 58 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer via an eleventh via hole V11, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 via a fourteenth via hole V14. Because the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 enables the second initial signal line 42 to write the second initial signal to the first electrode of the seventh transistor T7.

[0221] In an exemplary embodiment, the ninth connection electrode 59 may be block-shaped (eg, rectangular) and connected to the power connection block 27 - 1 through the fifteenth via hole V15 . The ninth connection electrode 59 is configured to be connected to a first power line formed subsequently.

[0222] In an exemplary embodiment, the fourth conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the fourth conductive layer in the Mth cell row and the fourth conductive layer in the M+1th cell row may be mirror-symmetric with respect to the row boundary. For another example, the fourth conductive layer in the M-1th cell row and the fourth conductive layer in the Mth cell row may be mirror-symmetric with respect to the row boundary. For another example, the fourth conductive layer in the M+1th cell row and the fourth conductive layer in the M+2th cell row may be mirror-symmetric with respect to the row boundary.

[0223] In an exemplary embodiment, the fourth conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the fourth conductive layer of the Nth cell column and the fourth conductive layer of the N+1th cell column may be mirror-symmetric with respect to a column boundary, the fourth conductive layer of the N+1th cell column and the fourth conductive layer of the N+2th cell column may be mirror-symmetric with respect to a column boundary, and the fourth conductive layer of the N+2th cell column and the fourth conductive layer of the N+3th cell column may be mirror-symmetric with respect to a column boundary. In an exemplary embodiment, the shapes of the fourth conductive layers in multiple cell rows may be substantially the same.

[0224] (19) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 14 .

[0225] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , a twenty-third via V23 , a twenty-fourth via V24 , and a twenty-fifth via V25 .

[0226] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer within the twenty-first via hole V21 is etched away to expose the surface of the fifth connecting electrode 55, and the twenty-first via hole V21 is configured to connect a subsequently formed first power line to the fifth connecting electrode 55 through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the seventh connecting electrode 57 on the substrate, the first flat layer within the twenty-second via hole V22 is etched away to expose the surface of the seventh connecting electrode 57, and the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the seventh connecting electrode 57 through the via hole.

[0228] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the ninth connecting electrode 59 on the substrate, the first flat layer within the twenty-third via V23 is etched away to expose the surface of the ninth connecting electrode 59, and the twenty-third via V23 is configured to connect the subsequently formed first power line to the ninth connecting electrode 59 through the via.

[0229] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-fourth via hole V24 is etched away to expose the surface of the third connecting electrode 53, and the twenty-fourth via hole V24 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0230] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer within the twenty-fifth via hole V25 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-fifth via hole V25 is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.

[0231] In an exemplary embodiment, at least one circuit unit may further be provided with a twenty-sixth via V26. The orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first initial signal line 41 on the substrate. The first flat layer within the twenty-sixth via V26 is etched away, exposing the surface of the first initial signal line 41. The twenty-sixth via V26 is configured to connect a subsequently formed first initial connection line to the first initial signal line 41 through the via.

[0232] In an exemplary embodiment, the twenty-sixth via hole V26 may be disposed between the (N+2)th cell column and the (N+3)th cell column.

[0233] In an exemplary embodiment, at least one circuit unit may further be provided with a twenty-seventh via V27. The orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the auxiliary initial signal line 43 on the substrate. The first flat layer within the twenty-seventh via V27 is etched away, exposing the surface of the auxiliary initial signal line 43. The twenty-seventh via V27 is configured to connect a subsequently formed second initial connection line to the auxiliary initial signal line 43 through the via.

[0234] In exemplary embodiments, the twenty-seventh via hole V27 may be disposed between the Nth cell column and the (N+1)th cell column.

[0235] (20) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG15A and FIG15B , where FIG15B is a planar schematic diagram of the fifth conductive layer in FIG15A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0236] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .

[0237] In an exemplary embodiment, the first power line 71 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 71 is connected to the fifth connection electrode 55 via the twenty-first via hole V21, and is connected to the seventh connection electrode 57 via the twenty-second via hole V22. Because the fifth connection electrode 55 is connected to the first region of the fifth active layer and the seventh connection electrode 57 is connected to the second electrode plate 32, the first power line 71 writes the first power signal to the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor.

[0238] In the exemplary embodiment, the first power line 71 is further connected to the ninth connection electrode 59 through the twenty-third via V23. Since the ninth connection electrode 59 is connected to the power connection block 27-1, and the power connection block 27-1 is connected to the power connection line 27, a connection is established between the power connection line 27 extending in the first direction X of the main body and the first power line 71 extending in the second direction Y of the main body. This allows the first power line 71 and the power connection line 27 to form a mesh-like interconnected structure in the display area for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0239] In an exemplary embodiment, at least one groove may be provided on the first power line 71 , and the groove is configured to accommodate the anode connection electrode 73 .

[0240] In an exemplary embodiment, the data signal line 72 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 72 is connected to the third connection electrode 53 through the twenty-fourth via hole V24. Since the third connection electrode 53 is connected to the first region of the fourth active layer, the data signal line 72 writes the data signal to the first electrode of the fourth transistor T4.

[0241] In an exemplary embodiment, first power lines 71 are disposed between some adjacent data signal lines 72 . The first power lines 71 transmitting DC signals can reduce mutual influence between adjacent data signal lines 72 .

[0242] In an exemplary embodiment, the anode connection electrode 73 may be in a block shape (e.g., a rectangular shape), and the anode connection electrode 73 is connected to the sixth connection electrode 56 through the twenty-fifth via hole V25. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0243] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a first initial connection line 74. The first initial connection line 74 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first initial connection line 74 may be disposed between adjacent portions of the first power lines 71. The first initial connection line 74 may be connected to the first initial signal line 41 through the twenty-sixth via V26, thereby achieving a connection between the first initial signal line 41 extending along the first direction X and the first initial connection line 74 extending along the second direction Y. This allows the first initial signal line 41 and the first initial connection line 74 to form a mesh-like interconnected structure in the display area for transmitting the first initial signal. This effectively reduces the resistance of the first initial signal line and the voltage drop of the first initial signal, and also effectively improves the uniformity of the first initial signal in the display substrate, thereby effectively improving display uniformity and enhancing display quality.

[0244] In an exemplary embodiment, the first preliminary connection line 74 may be disposed between the (N+2)th cell column and the (N+3)th cell column.

[0245] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second initial connection line 75. The second initial connection line 75 may be in the form of a straight line or a zigzag line, with the main portion extending along the second direction Y. The second initial connection line 75 may be disposed between adjacent first power lines 71. The second initial connection line 75 may be connected to the auxiliary initial signal line 43 via the twenty-seventh via hole V27. Since the auxiliary initial signal line 43 is connected to the second initial signal line 42, a connection is established between the second initial signal line 42, which extends along the first direction X, and the second initial connection line 75, which extends along the second direction Y. This allows the second initial signal lines 42 and the second initial connection lines 75 to form a mesh-like interconnected structure in the display area for transmitting the second initial signal. This effectively reduces the resistance of the second initial signal lines and the voltage drop of the second initial signal, and also effectively improves the uniformity of the second initial signal across the display substrate, thereby enhancing display uniformity and improving display quality.

[0246] In an exemplary embodiment, the second preliminary connection line 75 may be disposed between the Nth cell column and the N+1th cell column.

[0247] In an exemplary embodiment, the first initial connection line 74 and the second initial connection line 75 can be periodically arranged in multiple unit columns, with the second initial connection line 75 arranged between two adjacent first initial connection lines 74, and the first initial connection line 74 arranged between two adjacent second initial connection lines 75, thereby forming a meshed interconnected structure for transmitting the first initial signal and a meshed interconnected structure for transmitting the second initial signal in the display area.

[0248] In some possible embodiments, the fifth conductive layer of at least one circuit unit may also be provided with a data connection line whose main body extends along the second direction Y, forming a data connection line located in the display area (Fanout in Panel or Fanout in AA, abbreviated as FIP or FIAA) structure to effectively reduce the width of the lower border.

[0249] In some possible embodiments, the fifth conductive layer of at least one circuit unit may also be provided with a second power line to form a second power line located in the display area (VSS in pixel) structure. This can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, reduce the current density, improve the heat generation phenomenon, effectively improve the uniformity of the second power signal in the display substrate, and effectively improve the display uniformity, but also can significantly reduce the width of the frame power lead, greatly reduce the width of the left and right frames, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0250] In an exemplary embodiment, the first initial connection line, the second initial connection line, and the second power supply line can be periodically arranged in multiple unit columns, or the first initial connection line, the second initial connection line, and the data connection line can be periodically arranged in multiple unit columns, or the first initial connection line, the second initial connection line, the data connection line, and the second power supply line can be periodically arranged in multiple unit columns, and the present disclosure is not limited hereto.

[0251] In an exemplary embodiment, the fifth conductive layers of adjacent cell rows may be mirror-symmetric with respect to a row boundary. For example, the fifth conductive layer in the Mth cell row and the fifth conductive layer in the M+1th cell row may be mirror-symmetric with respect to a row boundary. For another example, the fifth conductive layer in the M-1th cell row and the fifth conductive layer in the Mth cell row may be mirror-symmetric with respect to a row boundary. For another example, the fifth conductive layer in the M+1th cell row and the fifth conductive layer in the M+2th cell row may be mirror-symmetric with respect to a row boundary.

[0252] In an exemplary embodiment, the fifth conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary. For example, the fifth conductive layer of the Nth cell column and the fifth conductive layer of the N+1th cell column may be mirror-symmetric with respect to the column boundary, the fifth conductive layer of the N+1th cell column and the fifth conductive layer of the N+2th cell column may be mirror-symmetric with respect to the column boundary, and the fifth conductive layer of the N+2th cell column and the fifth conductive layer of the N+3th cell column may be mirror-symmetric with respect to the column boundary.

[0253] In an exemplary embodiment, the subsequent process may include forming a second planar layer having at least an anode via disposed thereon, the anode via exposing the anode connection electrode, the anode via being configured to connect a subsequently formed anode to the anode connection electrode through the via.

[0254] At this point, the driving structure layer of this embodiment is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting control line, a first initial signal line, a second initial signal line, a data signal line and a first power line connected to the pixel driving circuit. In a direction perpendicular to the display substrate, the driving structure layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer and a second flat layer arranged in sequence on the substrate. The blocking layer may include at least a blocking electrode and a blocking connecting strip, the first semiconductor layer may include at least the active layer of the third transistor to the seventh transistor, the first conductive layer may include at least the first scanning signal line, the second scanning signal line and the first plate of the storage capacitor, the second conductive layer may include at least the power connection line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the first transistor and the second transistor, the third conductive layer may include at least the third scanning signal line, the fourth scanning signal line and the second initial signal line, the fourth conductive layer may include at least the first initial signal line, the auxiliary initial signal line and a plurality of connecting electrodes, and the fifth conductive layer may include at least the first power line, the data signal line and the anode connecting electrode.

[0255] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0256] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of organic materials, such as resin.

[0257] In an exemplary embodiment, the pixel driving circuits of adjacent unit rows may be mirror-symmetric with respect to a row boundary. For example, the pixel driving circuit of the Mth unit row and the pixel driving circuit of the M+1th unit row may be mirror-symmetric with respect to a row boundary. For another example, the pixel driving circuit of the M-1th unit row and the pixel driving circuit of the Mth unit row may be mirror-symmetric with respect to a row boundary. For another example, the pixel driving circuit of the M+1th unit row and the pixel driving circuit of the M+2th unit row may be mirror-symmetric with respect to a row boundary.

[0258] In an exemplary embodiment, the pixel driving circuits of adjacent unit columns may be mirror-symmetric with respect to a column boundary. For example, the pixel driving circuit of the Nth unit column and the pixel driving circuit of the N+1th unit column may be mirror-symmetric with respect to the column boundary, the pixel driving circuit of the N+1th unit column and the pixel driving circuit of the N+2th unit column may be mirror-symmetric with respect to the column boundary, and the pixel driving circuit of the N+2th unit column and the pixel driving circuit of the N+3th unit column may be mirror-symmetric with respect to the column boundary.

[0259] In an exemplary embodiment, after the driving structure layer is prepared, the process may further include first preparing a light emitting structure layer on the driving structure layer, and then preparing an encapsulation structure layer on the light emitting structure layer, which will not be described in detail here.

[0260] An exemplary embodiment of the present disclosure provides a display substrate. By arranging the pixel driving circuits in two adjacent unit rows to be mirror-symmetrical with respect to the row dividing line, the pixel driving circuits in some adjacent unit rows share the same first initial signal line, and the pixel driving circuits in some adjacent unit rows share the same second initial signal line. This effectively reduces the number of wiring and the number of vias, reduces the space occupied by the pixel driving circuits, optimizes the layout space, effectively improves the yield, effectively improves the aperture ratio, and is adaptable to high-resolution products.

[0261] The present disclosure effectively reduces the overlapping capacitance between the first power line and the first initial signal line and the overlapping capacitance between the first power line and the second initial signal line by setting the pixel driving circuits in two adjacent unit rows to share the initial signal line, and reduces the resistance and capacitance load (RC Loading) of the first power line, the first initial signal line and the second initial signal line to a limited extent, effectively improving the uniformity of the DC signal in the display substrate, effectively improving the display uniformity, and improving the display quality and display quality. Simulation tests show that the present disclosure can reduce the overlapping capacitance between the first power line and the first initial signal line from 3.3176 in the existing structure to 2.7913, and the overlapping capacitance is reduced by about 15%. The present disclosure can reduce the overlapping capacitance between the first power line and the second initial signal line from 4.5444 in the existing structure to 3.6739, and the overlapping capacitance is reduced by about 20%.

[0262] The present disclosure provides a connection between a power connection line extending along a first direction X of the main body and a first power line extending along a second direction Y of the main body, so that the first power line and the power connection form a meshed connection structure. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and improves display quality.

[0263] The present disclosure provides a first initial signal line extending in a first direction in the main body and a first initial connection line extending in a second direction in the main body, and provides a second initial signal line extending in the first direction in the main body and a second initial connection line extending in the second direction in the main body, so that the first initial signal line and the second initial signal line respectively form a mesh connection structure, which not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0264] The present disclosure arranges the first scanning signal line and the second scanning signal line in the first conductive layer, and arranges the third scanning signal line and the fourth scanning signal line in the third conductive layer, and the plurality of scanning signal lines do not overlap with the first initial signal line, the second initial signal line and the power connection line, thereby minimizing the parasitic capacitance of the DC signal line, effectively improving the horizontal stripes caused by the excessive parasitic capacitance of the DC signal line, and improving the display quality.

[0265] By setting a double-layer structure of the second initial signal line, the present disclosure can further reduce the resistance of the second initial signal line, further reduce the voltage drop of the second initial signal, further improve the uniformity of the second initial signal in the display substrate, further improve the display uniformity, and further improve the display quality.

[0266] The present disclosure sets the oxide first transistor T1 as a single-gate structure and the oxide second transistor T2 as a top-bottom double-gate structure, which can reduce mutual interference between the first transistor T1 and the second transistor T2, reduce mutual interference between scanning signal lines, and improve the driving performance of the pixel driving circuit.

[0267] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0268] Figure 16 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of eight circuit units (two unit rows and four unit columns). In this exemplary embodiment, the structure of the pixel driving circuit of this embodiment is substantially the same as that shown in Figure 5 , except that this embodiment includes auxiliary scanning signal lines 44, and the third scanning signal lines 23 and the auxiliary scanning signal lines 44 form a double-layer structure of scanning signal lines.

[0269] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent in the second direction Y, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to the row dividing line, the pixel driving circuits in some adjacent circuit units share the same first initial signal line 41, and the pixel driving circuits in another part of adjacent circuit units share the same second initial signal line 42.

[0270] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to each other in the first direction X, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to a column boundary line.

[0271] In an exemplary embodiment, at least one circuit unit may include at least one auxiliary scanning signal line 44. The shape of the auxiliary scanning signal line 44 may be a straight line or a broken line extending along the first direction X. The orthographic projection of the auxiliary scanning signal line 44 on the display substrate plane at least partially overlaps with the orthographic projection of the third scanning signal line 23 on the display substrate plane. The auxiliary scanning signal line 44 is connected to the third scanning signal line 23 through a via to form a third scanning signal line with a double-layer structure.

[0272] In an exemplary embodiment, the multiple conductive layers may include at least a third gate metal layer and a first source-drain metal layer arranged in sequence along a direction away from the substrate, the third scan signal line 23 may be arranged in the third gate metal layer, and the auxiliary scan signal line 44 may be arranged in the first source-drain metal layer.

[0273] In an exemplary embodiment, at least one circuit unit may further include at least one third initial connection line 76, and the shape of the third initial connection line 76 may be a straight line or a broken line extending along the second direction Y. The first initial connection line 74 may be connected to the first initial signal line 41 on the one hand and to the second initial signal line 42 on the other hand, so that the first initial signal line 41, the second initial signal line 42 and the third initial connection line 76 form a meshed connection structure for transmitting the initial signal.

[0274] In an exemplary embodiment, at least one circuit unit may further include an auxiliary plate, the orthographic projection of the auxiliary plate on the plane of the display substrate at least partially overlapping with the orthographic projection of the second plate on the plane of the display substrate, the auxiliary plate being connected to the first plate via a first connecting electrode, and the auxiliary plate and the second plate forming an auxiliary capacitor.

[0275] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0276] (21) Sequentially forming patterns of a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer. In an exemplary embodiment, the formation process and the formed film layers can be substantially the same as those in the aforementioned embodiment, except that the second conductive layer does not have a power connection line.

[0277] (22) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 17 .

[0278] In an exemplary embodiment, the plurality of via holes include at least first to fourteenth via holes V1 to V14 , sixteenth via hole V16 , and seventeenth via hole V17 , and the via hole structures of the first to fourteenth via holes V14 and sixteenth via hole V16 are substantially the same as those of the previous embodiment.

[0279] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the third scan signal line 23 on the substrate, the sixth insulating layer in the seventeenth via hole V17 is etched away to expose the surface of the third scan signal line 23, and the seventeenth via hole V17 is configured to enable a subsequently formed auxiliary scan signal line to be connected to the third scan signal line 23 through the via hole.

[0280] In an exemplary embodiment, a seventeenth via hole V17 may be provided in each circuit unit.

[0281] (23) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG18A and FIG18B , where FIG18B is a plan view schematic diagram of the fourth conductive layer in FIG18A .

[0282] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first initial signal line 41, an auxiliary initial signal line 43, an auxiliary scanning signal line 44, an auxiliary electrode plate 45, a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57 and an eighth connecting electrode 58, and the structures of the first initial signal line 41, the auxiliary initial signal line 43, and the first connecting electrode 51 to the eighth connecting electrode 58 are basically the same as those in the aforementioned embodiments.

[0283] In an exemplary embodiment, the shape of the auxiliary scanning signal line 44 can be a straight line or a broken line with the main portion extending along the first direction X. The auxiliary scanning signal line 44 can be located between the second electrode 32 and the fourth scanning signal line 24. The auxiliary scanning signal line 44 is connected to the third scanning signal line 23 through the seventeenth via V17.

[0284] In an exemplary embodiment, the orthographic projection of the auxiliary scan signal line 44 on the substrate at least partially overlaps with the orthographic projection of the third scan signal line 23 on the substrate, forming a double-layer structure for the third scan signal line. The present disclosure forms a double-layer structure for the scan signal line. Because the thickness of the first source and drain metal layer is greater than the thickness of the third gate metal layer, the double-layer structure effectively reduces the resistance of the third scan signal line, reduces the voltage drop of the third scan signal, and can improve compensation speed, thereby enhancing display quality and display quality.

[0285] In an exemplary embodiment, the auxiliary plate 45 may be rectangular in shape, and the corners of the rectangle may be chamfered or grooved. The auxiliary plate 45 may be located between the first connection electrode 51 and the fourth connection electrode 54. The orthographic projection of the auxiliary plate 45 on the substrate at least partially overlaps with the orthographic projection of the second plate 32 on the substrate. The auxiliary plate 45 is connected to the first connection electrode 51.

[0286] In an exemplary embodiment, the auxiliary plate 45 and the first connection electrode 51 may be an integral structure connected to each other.

[0287] In an exemplary embodiment, since the first connecting electrode 51 is respectively connected to the first plate 31 and the auxiliary plate 45, the first plate 31 and the auxiliary plate 45 both have the potential of the first node N1, and the second plate 32 has the potential of the first power line, the first plate 31 and the second plate 32 form a storage capacitor, the auxiliary plate 45 and the second plate 32 form an auxiliary capacitor, and the storage capacitor and the auxiliary capacitor are connected in parallel, which effectively increases the capacitance value of the storage capacitor in the pixel driving circuit and improves the driving quality of the pixel driving circuit.

[0288] In an exemplary embodiment, the seventh connection electrode 57 may be in a block shape (eg, a rectangular shape). Unlike the aforementioned embodiment, the seventh connection electrode 57 in each circuit unit may be provided separately.

[0289] (24) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 19 .

[0290] In an exemplary embodiment, the plurality of vias include at least: a twenty-first via V21, a twenty-second via V22, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26 and a twenty-seventh via V27. The above via structure is substantially the same as that in the aforementioned embodiment, except that the twenty-sixth via V26 and the twenty-seventh via V27 are both arranged between the N+2th unit column and the N+3th unit column, and the twenty-sixth via V26 and the twenty-seventh via V27 are configured to enable the subsequently formed third initial connection line to be connected to the first initial signal line 41 and the auxiliary initial signal line 43 respectively through the two vias.

[0291] (25) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG. 20A and FIG. 20B , where FIG. 20B is a planar schematic diagram of the fifth conductive layer in FIG. 20A .

[0292] In an exemplary embodiment, the fifth conductive layer includes at least: a first power line 71, a data signal line 72, an anode connecting electrode 73, a third initial connecting line 76 and a second power line 77. The structures of the first power line 71, the data signal line 72 and the anode connecting electrode 73 are basically the same as those in the aforementioned embodiment, except that the first power line 71 is connected to the fifth connecting electrode 55 and the seventh connecting electrode 57 through the twenty-first via hole V21 and the twenty-second via hole V22, respectively.

[0293] In an exemplary embodiment, the third initial connection line 76 may be in the form of a straight line or a zigzag line extending along the second direction Y. The third initial connection line 76 may be disposed between adjacent first power lines 71. The third initial connection line 76 is connected to the first initial signal line 41 via the twenty-sixth via hole V26 and to the auxiliary initial signal line 43 via the twenty-seventh via hole V27. Since the auxiliary initial signal line 43 is connected to the second initial signal line 42, the connection between the first initial signal line 41 and the second initial signal line 42 extending along the first direction X and the third initial connection line 76 extending along the second direction Y is achieved. This allows the first initial signal line 41, the second initial signal line 42, and the third initial connection line 76 extending along the second direction Y to form a mesh-like interconnected structure within the display area, transmitting the same initial signal. This effectively reduces the resistance of the initial signal lines and the voltage drop of the initial signals, while also effectively improving the uniformity of the initial signals within the display substrate, thereby enhancing display uniformity and improving display quality.

[0294] In an exemplary embodiment, the third preliminary connection line 76 may be disposed between the Nth cell column and the N+1th cell column.

[0295] In an exemplary embodiment, the shape of the second power line 77 can be a straight line or a broken line with the main part extending along the second direction Y. It can be arranged between some adjacent first power lines 71 to form a VSS in pixel structure, which can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, reduce the current density, improve the heat generation phenomenon, effectively improve the uniformity of the second power signal in the display substrate, and effectively improve the display uniformity, but also can greatly reduce the width of the frame power lead, greatly reduce the width of the left and right frames, and improve the screen-to-body ratio, which is conducive to achieving full-screen display.

[0296] In an exemplary embodiment, the second power line 77 may be disposed between the (N+2)th cell column and the (N+3)th cell column.

[0297] In some possible implementations, the fifth conductive layer of at least one circuit unit may further be provided with a data connection line whose main portion extends along the second direction Y, forming a Fanout in Panel or Fanout in AA structure to effectively reduce the width of the lower frame.

[0298] In an exemplary embodiment, the third initial connection line and the second power line can be periodically arranged in multiple unit columns, or the third initial connection line and the data connection line can be periodically arranged in multiple unit columns, or the third initial connection line, the data connection line and the second power line can be periodically arranged in multiple unit columns, and the present disclosure is not limited hereto.

[0299] In an exemplary embodiment, the subsequent process may include forming a second planar layer having at least an anode via disposed thereon, the anode via exposing the anode connection electrode, the anode via being configured to connect a subsequently formed anode to the anode connection electrode through the via.

[0300] At this point, the driving structure layer is prepared on the substrate. Different from the previous embodiment, the second conductive layer is not provided with a power connection line, and the fourth conductive layer is provided with an auxiliary scanning signal line.

[0301] The exemplary embodiments of the present disclosure provide a display substrate, which not only has the technical effects of the aforementioned embodiments, reduces the number of wiring and the number of vias, effectively improves the yield and aperture ratio, but also, by setting a double-layer structure of the third scanning signal line, can effectively reduce the resistance of the third scanning signal line, reduce the voltage drop of the third scanning signal line, can increase the compensation speed, and improve the display quality and display quality.

[0302] The present disclosure provides an auxiliary capacitor, and the auxiliary capacitor is connected in parallel with the storage capacitor, thereby effectively increasing the capacitance value of the storage capacitor in the pixel driving circuit and improving the driving quality of the pixel driving circuit. On the premise of ensuring the capacitance value of the storage capacitor, the area of ​​the electrode plate can be reduced, the space occupied by the pixel driving circuit can be reduced, and the resolution can be further improved.

[0303] The present disclosure forms a VSS in pixel structure through a second power line, which can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, reduce the current density, improve the heating phenomenon, effectively improve the uniformity of the second power signal in the display substrate, and effectively improve the display uniformity, but also can significantly reduce the width of the frame power lead, greatly reduce the width of the left and right frames, and increase the screen-to-body ratio, which is conducive to achieving full-screen display.

[0304] Figure 21 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structures of the first semiconductor layer, the first conductive layer, and the second semiconductor layer. As shown in Figure 21 , the structure of the pixel driving circuit of this embodiment is substantially the same as that shown in Figure 5 , except that the third active layer of the third transistor T3 of this embodiment can be shaped like an inverted Ω.

[0305] Figure 22 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the first semiconductor layer, the first conductive layer, and the second semiconductor layer. As shown in Figure 22 , the structure of the pixel driver circuit in this embodiment is substantially the same as that shown in Figure 5 , except that the third active layer of the third transistor T3 in this embodiment can be in the shape of a straight line.

[0306] The structure and fabrication process described above are merely exemplary. In exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or removed as needed. For example, the first initial signal line may be provided in the third conductive layer, and the second initial signal line may be provided in the fourth conductive layer. Furthermore, the shielding layer may not include shielding connecting strips, which is not a limitation of this disclosure.

[0307] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0308] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. The preparation method may include:

[0309] A pixel driving circuit and at least one initial signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least one initialization transistor, and the initial signal line is connected to the first electrode of the initialization transistor; in at least one circuit unit and a circuit unit adjacent in the pixel column direction, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to a row dividing line, and the first electrodes of the initialization transistors in the two pixel driving circuits are connected to the same initial signal line, and the row dividing line is a straight line located between adjacent unit rows and extending along the unit row direction.

[0310] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0311] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one initialization signal line, the pixel driving circuit including at least one initialization transistor, the initialization signal line being connected to a first electrode of the initialization transistor; in at least one circuit unit and a circuit unit adjacent in the direction of the pixel columns, the pixel driving circuits in the two circuit units are mirror-symmetric with respect to a row boundary, the first electrodes of the initialization transistors in the two pixel driving circuits are connected to the same initialization signal line, and the row boundary is a straight line located between adjacent unit rows and extending along the unit rows.

2. The display substrate according to claim 1, wherein The at least one initial signal line includes a first initial signal line extending along the unit row direction, the at least one initialization transistor includes a first initialization transistor, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first electrodes of the first initialization transistors in the two circuit units are connected to the same first initial signal line, and the first initial signal line is configured to provide a first initial signal to the pixel driving circuit.

3. The display substrate according to claim 2, wherein: The first initialization transistor includes at least a first initialization active layer. In at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first regions of the first initialization active layers in the two circuit units are connected to the same first initial signal line through the same via hole.

4. The display substrate according to claim 3, wherein: In at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first initialization active layers in the two circuit units are interconnected as an integrated structure.

5. The display substrate according to claim 2, wherein: At least one circuit unit further includes at least one first initial connection line extending along the unit column direction, wherein the first initial connection line is connected to the first initial signal line to form a mesh connection structure. The display substrate according to claim 1 , wherein: The at least one initial signal line includes a second initial signal line extending along the unit row direction, the at least one initialization transistor includes a second initialization transistor, and in at least one circuit unit and a circuit unit adjacent to each other in the pixel column direction, the first electrodes of the second initialization transistors in the two circuit units are connected to the same second initial signal line, and the second initial signal line is configured to provide a second initial signal to the pixel driving circuit.

7. The display substrate according to claim 6, wherein: The second initialization transistor includes at least a second initialization active layer, and at least one circuit unit further includes a second initial connection block. The first area of ​​the second initialization active layer is connected to the second initial connection block through a connection electrode. In at least one circuit unit and a circuit unit adjacent to the pixel column direction, the second initial connection blocks in the two circuit units are connected to the same second initial signal line.

8. The display substrate according to claim 6, wherein: At least one circuit unit further includes at least one second initial connection line extending along the unit column direction, wherein the second initial connection line is connected to the second initial signal line to form a mesh connection structure.

9. The display substrate according to claim 6, wherein: At least one circuit unit also includes an auxiliary initial signal line extending along the unit row direction, the orthographic projection of the auxiliary initial signal line on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane, and the auxiliary initial signal line is connected to the second initial signal line to form a second initial signal line with a double-layer structure.

10. The display substrate according to claim 1, wherein The at least one initial signal line includes a first initial signal line and a second initial signal line extending along the unit row direction, and at least one circuit unit also includes at least one third initial connection line extending along the unit column direction, and the third initial connection line is respectively connected to the first initial signal line and the second initial signal line to form a mesh connection structure.

11. The display substrate according to claim 10, wherein: In a direction perpendicular to the display substrate, the display substrate includes a plurality of conductive layers disposed on a base, and the first initial signal line, the second initial signal line, and the initial connection line are disposed in different conductive layers.

12. The display substrate according to claim 11, wherein: The multiple conductive layers include at least a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer arranged in sequence along a direction away from the substrate, the first initial signal line is arranged in the fourth conductive layer, the second initial signal line is arranged in the third conductive layer, and the initial connection line is arranged in the fifth conductive layer, or the first initial signal line is arranged in the third conductive layer, the second initial signal line is arranged in the fourth conductive layer, and the initial connection line is arranged in the fifth conductive layer.

13. The display substrate according to any one of claims 1 to 12, wherein: The at least one initialization transistor includes a first initialization transistor, and the pixel driving circuit also includes a compensation transistor and a driving transistor, the gate electrode of the compensation transistor is connected to the third scanning signal line, the first electrode of the compensation transistor is connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the first initialization transistor and the second electrode of the driving transistor; the first initialization transistor and the compensation transistor are oxide transistors, the driving transistor is a polysilicon transistor, the first initialization transistor is a single-gate structure with a top gate, and the compensation transistor is a double-gate structure with a top gate and a bottom gate.

14. The display substrate according to claim 13, wherein: At least one circuit unit also includes an auxiliary scanning signal line, the orthographic projection of the auxiliary scanning signal line on the display substrate plane at least partially overlaps with the orthographic projection of the third scanning signal line on the display substrate plane, and the auxiliary scanning signal line is connected to the third scanning signal line to form a double-layer structure of the third scanning signal line.

15. The display substrate according to claim 14, wherein: The display substrate includes multiple conductive layers arranged on a base, the multiple conductive layers include at least a gate metal layer and a source-drain metal layer arranged on a side of the gate metal layer away from the base, the third scan signal line is arranged in the gate metal layer, and the auxiliary scan signal line is arranged in the source-drain metal layer.

16. The display substrate according to any one of claims 1 to 12, wherein: The at least one initial signal line includes a first initial signal line and a second initial signal line extending along the unit row direction, and at least one circuit unit also includes at least one scanning signal line or a light-emitting signal line extending along the unit row direction, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit, the orthographic projections of the first initial signal line and the second initial signal line on the display substrate plane do not overlap with the orthographic projections of the scanning signal line on the display substrate plane, and the orthographic projections of the first initial signal line and the second initial signal line on the display substrate plane do not overlap with the orthographic projections of the light-emitting signal line on the display substrate plane.

17. The display substrate according to any one of claims 1 to 12, wherein: At least one circuit unit also includes a power connection line extending along the unit row direction and a first power line extending along the unit column direction, the first power line is configured to provide a first power signal to the pixel driving circuit, and the first power line is connected to the power connection line to form a mesh connection structure.

18. The display substrate according to claim 17, wherein: At least one circuit unit also includes at least one scanning signal line or light-emitting signal line extending along the unit row direction, the scanning signal line is configured to provide a scanning signal to the pixel driving circuit, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit, the orthographic projection of the power connection line on the display substrate plane does not overlap with the orthographic projection of the scanning signal line on the display substrate plane, and the orthographic projection of the power connection line on the display substrate plane does not overlap with the orthographic projection of the light-emitting signal line on the display substrate plane.

19. The display substrate according to any one of claims 1 to 12, wherein: At least one circuit unit also includes a first plate, a second plate and an auxiliary plate; the orthographic projection of the first plate on the display substrate plane at least partially overlaps with the orthographic projection of the second plate on the display substrate plane, and the first plate and the second plate constitute a storage capacitor; the orthographic projection of the auxiliary plate on the display substrate plane at least partially overlaps with the orthographic projection of the second plate on the display substrate plane, the auxiliary plate is connected to the first plate through a first connecting electrode, and the auxiliary plate and the second plate constitute an auxiliary capacitor.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

21. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the method comprising: A pixel driving circuit and at least one initial signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least one initialization transistor, and the initial signal line is connected to the first electrode of the initialization transistor; in at least one circuit unit and a circuit unit adjacent in the pixel column direction, the pixel driving circuits in the two circuit units are mirror-symmetrical with respect to a row dividing line, and the first electrodes of the initialization transistors in the two pixel driving circuits are connected to the same initial signal line, and the row dividing line is a straight line located between adjacent unit rows and extending along the unit row direction.

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