Power conversion device

Abstract

A power conversion device according to an embodiment of the present invention comprises: an input terminal; a rectifier circuit; a reactor having one end connected to a first node of the rectifier circuit and the other end connected to a third node; a plurality of switching elements including first and second switching elements provided by sandwiching a first intermediate node in a first path connecting the third node and a second node; a plurality of rectifier elements including first and second rectifier elements provided by sandwiching a second intermediate node in a second path connecting the third node and a fourth node; a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node; output terminals including a first output terminal connected to the fourth node and a second output terminal connected to the second node; and a control circuit capable of controlling an operation of the plurality of switching elements such that a waveform of an input current flowing through the input terminal is the same as a waveform of an input voltage at the input terminal.

Description

Power Conversion Device

[0001] The present invention relates to a power conversion device that converts electric power.

[0002] A power factor correction (PFC) converter capable of correcting a power factor is often used in power conversion devices. For example, Patent Document 1 discloses a technique related to such a PFC converter.

[0003] International Publication No. 2016 / 016475

[0004] In general, in electronic circuits, it is desirable to simplify the circuit operation, and it is also expected that the circuit operation of such a power conversion device will be simplified.

[0005] It is desirable to provide a power conversion device that can simplify circuit operation.

[0006] A power conversion device according to one embodiment of the present invention includes an input terminal, a rectifier circuit, a reactor, multiple switching elements, multiple rectifier elements, a first capacitor, an output terminal, and a control circuit. The input terminal includes a first input terminal and a second input terminal. The rectifier circuit includes a first element provided in a path connecting the first input terminal and a first node and capable of causing a current to flow from the first input terminal to the first node, a second element provided in a path connecting the second node and the first input terminal and capable of causing a current to flow from the second node to the first input terminal, a third element provided in a path connecting the second input terminal and the first node and capable of causing a current to flow from the second input terminal to the first node, and a fourth element provided in a path connecting the second node and the second input terminal and capable of causing a current to flow from the second node to the second input terminal. The reactor has one end connected to the first node and the other end connected to the third node. The plurality of switching elements includes a first switching element and a second switching element provided on either side of a first intermediate node in a first path connecting the third node and the second node. The plurality of rectifying elements includes a first rectifying element and a second rectifying element provided on either side of a second intermediate node in a second path connecting the third node and a fourth node. The first capacitor has one end connected to the first intermediate node and the other end connected to the second intermediate node. The output terminals include a first output terminal connected to the fourth node and a second output terminal connected to the second node. The control circuit is capable of controlling the operation of the plurality of switching elements so that the waveform of an input current flowing through the input terminal is the same as the waveform of an input voltage at the input terminal.

[0007] According to the power conversion device according to one embodiment of the present invention, the circuit operation can be simplified.

[0008] 1 is a circuit diagram illustrating an example of a configuration of a power conversion device according to an embodiment of the present invention. FIG. 2 is a waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. 1. FIG. 3 is a waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. 1 when the switching duty ratio is small. FIG. 4 is a waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. 1 when the switching duty ratio is medium. FIG. 5 is a waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. 1 when the switching duty ratio is large. FIG. 6 is an explanatory diagram illustrating an operation state of the power conversion device shown in FIG. 1 when the switching duty ratio is small. FIG. 7 is an explanatory diagram illustrating another operation state of the power conversion device shown in FIG. 1 when the switching duty ratio is small. FIG. 8 is an explanatory diagram illustrating another operation state of the power conversion device shown in FIG. 1 when the switching duty ratio is small. FIG. 9 is an explanatory diagram illustrating another operation state of the power conversion device shown in FIG. 1 when the switching duty ratio is medium. FIG. 10 is an explanatory diagram illustrating another operation state of the power conversion device shown in FIG. 1 when the switching duty ratio is medium. FIG. 2 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 when the switching duty ratio is medium. FIG. 3 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 when the switching duty ratio is medium. FIG. 4 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 when the switching duty ratio is medium. FIG. 5 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 when the switching duty ratio is high. FIG. 6 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 when the switching duty ratio is high. FIG. 7 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 when the switching duty ratio is high.10 is an explanatory diagram showing one operating state of the power conversion device shown in FIG. 1 near a zero-cross timing. FIG. 11 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 1 near a zero-cross timing. FIG. 12 is a circuit diagram showing an example configuration of a power conversion device according to a modified example. FIG. 13 is a circuit diagram showing an example configuration of a power conversion device according to another modified example. FIG. 14 is a circuit diagram showing an example configuration of a power conversion device according to another modified example. FIG. 15 is a waveform diagram showing an example operation of the power conversion device shown in FIG. 10 when the switching duty ratio is small. FIG. 16 is a waveform diagram showing an example operation of the power conversion device shown in FIG. 10 when the switching duty ratio is large. FIG. 17 is an explanatory diagram showing one operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is small. FIG. 18 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is small. FIG. 19 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is small. FIG. 19 is an explanatory diagram showing another operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is small. FIG. 19 is an explanatory diagram showing one operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is large. 11 is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is large. FIG. 12 is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. 10 when the switching duty ratio is large.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] 1 illustrates an example of a configuration of a power conversion device (power conversion device 1) according to an embodiment of the present invention. Power conversion device 1 is a PFC converter capable of correcting a power factor. Power conversion device 1 is configured to convert AC power supplied from an AC power source PAC into DC power and supply the converted DC power to a load device LD. The AC power source PAC is, for example, a power grid. Power conversion device 1 includes input terminals T11 and T12, a noise filter 11, a voltage sensor 14, a rectifier circuit 15, a reactor 16, a current sensor 17, transistors S1, S2, and S3, a current sensor 18, diodes D1, D2, and D3, capacitors 19, 20, and 21, a voltage sensor 22, a drive circuit 23, a control circuit 24, and output terminals T21 and T22.

[0011] The input terminals T11 and T12 are configured to receive AC power from an AC power supply PAC.

[0012] The noise filter 11 is configured to make it difficult for noise generated inside the power conversion device 1 to be transmitted to the AC power supply PAC. The noise filter 11 has a capacitor 12 and a transformer 13. One end of the capacitor 12 is connected to the input terminal T11, and the other end is connected to the input terminal T12. The transformer 13 has windings 13A and 13B. One end of the winding 13A is connected to one end of the capacitor 12, and the other end is connected to a node N11. One end of the winding 13B is connected to the other end of the capacitor 12, and the other end is connected to a node N12. Note that the noise filter 11 is not limited to this circuit configuration, and various circuit configurations that can reduce noise transmitted from the power conversion device 1 to the AC power supply PAC can be used.

[0013] One end of the voltage sensor 14 is connected to the node N11, and the other end is connected to the node N12. The voltage sensor 14 is configured to detect the voltage Vin at the node N11 with respect to the voltage at the node N12. The voltage Vin corresponds to the input voltage at the input terminals T11 and T12 of the power conversion device 1.

[0014] The rectifier circuit 15 is a diode bridge circuit and includes diodes D11 to D14. The anode of the diode D11 is connected to the node N11, and the cathode is connected to the node N1. The anode of the diode D12 is connected to the reference voltage line L2, and the cathode is connected to the node N11. The anode of the diode D13 is connected to the node N12, and the cathode is connected to the node N1. The anode of the diode D14 is connected to the reference voltage line L2, and the cathode is connected to the node N12.

[0015] One end of the reactor 16 is connected to the node N1, and the other end is connected to a node N3.

[0016] The current sensor 17 is provided on a path connecting the node N3 and the reference voltage line L2. One end of the current sensor 17 is connected to the source of the transistor S1, and the other end is connected to the reference voltage line L2. The current sensor 17 is configured to detect a current I1 that flows from the source of the transistor S1 toward the reference voltage line L2. This current I1 flows from the node N3 toward the reference voltage line L2 via various paths.

[0017] The transistors S1 to S3 are configured to perform switching operations. The transistors S1 to S3 are configured using, for example, N-type field effect transistors (FETs). While N-type field effect transistors are used in this example, any switching elements may be used. The transistors S1 to S3 are provided in a path connecting the node N3 and the reference voltage line L2. The drain of the transistor S1 is connected to the source of the transistor S2, the source is connected to one end of the current sensor 17, and a control signal G1 is supplied to the gate. The drain of the transistor S2 is connected to the source of the transistor S3, the source is connected to the drain of the transistor S1, and a control signal G2 is supplied to the gate. The drain of the transistor S3 is connected to the node N3, the source is connected to the drain of the transistor S2, and a control signal G3 is supplied to the gate.

[0018] Current sensor 18 is provided on a path connecting node N3 and voltage line L4. One end of current sensor 18 is connected to the cathode of diode D1, and the other end is connected to voltage line L4. Current sensor 18 is configured to detect current I2 flowing from the cathode of diode D1 toward voltage line L4. This current I2 flows from node N3 toward voltage line L4 via various paths.

[0019] Diodes D1 to D3 are provided in a path connecting node N3 and voltage line L4. The anode of diode D1 is connected to the cathode of diode D2, and the cathode is connected to one end of current sensor 18. The anode of diode D2 is connected to the cathode of diode D3, and the cathode is connected to the anode of diode D1. The anode of diode D3 is connected to node N3, and the cathode is connected to the anode of diode D2.

[0020] One end of capacitor 19 is connected to the drain of transistor S1 and the source of transistor S2, and the other end is connected to the anode of diode D1 and the cathode of diode D2. One end of capacitor 20 is connected to the drain of transistor S2 and the source of transistor S3, and the other end is connected to the anode of diode D2 and the cathode of diode D3.

[0021] One end of the capacitor 21 is connected to the voltage line L4, and the other end is connected to the reference voltage line L2.

[0022] One end of the voltage sensor 22 is connected to the voltage line L4, and the other end is connected to the reference voltage line L2. The voltage sensor 22 is configured to detect the voltage Vout on the voltage line L4 relative to the voltage on the reference voltage line L2.

[0023] The drive circuit 23 is configured to generate control signals G1 to G3 based on the control signals G11 to G13 supplied from the control circuit 24, and apply these control signals G1 to G3 to the gates of the transistors S1 to S3, respectively. For example, when applying the control signal G1 to the gate of the transistor S1, the drive circuit 23 generates the control signal G1 based on the voltage at the source of the transistor S1. Similarly, when applying the control signal G2 to the gate of the transistor S2, the drive circuit 23 generates the control signal G2 based on the voltage at the source of the transistor S2. When applying the control signal G3 to the gate of the transistor S3, the drive circuit 23 generates the control signal G3 based on the voltage at the source of the transistor S3.

[0024] The control circuit 24 is configured to control the operation of the power conversion device 1 based on the voltage Vin detected by the voltage sensor 14, the voltage Vout detected by the voltage sensor 22, the current I1 detected by the current sensor 17, and the current I2 detected by the current sensor 18. Specifically, the control circuit 24 controls the switching operations of the transistors S1 to S3 via control signals G11 to G13 based on the voltage Vin so that the voltage Vout is maintained at a predetermined voltage. The control circuit 24 also controls the switching operations of the transistors S1 to S3 via control signals G11 to G13 based on the voltage Vin and the currents I1 and I2 so that the waveform of the input current to the power conversion device 1 becomes the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1.

[0025] The output terminals T21 and T22 are configured to supply the DC power generated by the power conversion device 1 to the load device LD. Within the power conversion device 1, the output terminal T21 is connected to the voltage line L4, and the output terminal T22 is connected to the reference voltage line L2.

[0026] Here, the input terminal T11 and the input terminal T12 correspond to specific examples of a "first input terminal" and a "second input terminal," respectively, in an embodiment of the present disclosure. The rectifier circuit 15 corresponds to a specific example of a "rectifier circuit" in an embodiment of the present disclosure. The diodes D11 to D14 correspond to specific examples of a "first element," a "second element," a "third element," and a "fourth element," respectively, in an embodiment of the present disclosure. The node N1 corresponds to a specific example of a "first node" in an embodiment of the present disclosure. The reference voltage line L2 corresponds to a specific example of a "second node" in an embodiment of the present disclosure. The reactor 16 corresponds to a specific example of a "reactor" in an embodiment of the present disclosure. The node N3 corresponds to a specific example of a "third node" in an embodiment of the present disclosure. The transistors S1 to S3 correspond to specific examples of "plurality of switching elements" in an embodiment of the present disclosure. Transistor S1, transistor S2, and transistor S3 correspond to specific examples of a "first switching element," a "second switching element," and a "third switching element," respectively, in an embodiment of the present disclosure. Diodes D1 to D3 correspond to a specific example of a "plurality of rectifying elements" in an embodiment of the present disclosure. Diodes D1, D2, and D3 correspond to specific examples of a "first rectifying element," a "second rectifying element," and a "third rectifying element," respectively, in an embodiment of the present disclosure. Voltage line L4 corresponds to a specific example of a "fourth node" in an embodiment of the present disclosure. Capacitor 19 corresponds to a specific example of a "first capacitor" in an embodiment of the present disclosure. Capacitor 20 corresponds to a specific example of a "second capacitor" in an embodiment of the present disclosure. Output terminals T21 and T22 correspond to specific examples of a "first output terminal" and a "second output terminal," respectively, in an embodiment of the present disclosure. Control circuit 24 corresponds to a specific example of a "control circuit" in an embodiment of the present disclosure.

[0027] [Operation and Function] Next, the operation and function of the power conversion device 1 of this embodiment will be described.

[0028] (Overall Operation Overview) First, an overview of the overall operation of the power conversion device 1 will be described with reference to FIG. 1 . AC power is supplied to input terminals T11 and T12 of the power conversion device 1 from an AC power supply PAC. A control circuit 24 generates control signals G11 to G13 based on voltages Vin and Vout and currents I1 and I2. A drive circuit 23 generates control signals G1 to G3, respectively, based on the control signals G11 to G13 supplied from the control circuit 24, and applies these control signals G1 to G3 to the gates of transistors S1 to S3, respectively. The transistors S1 to S3 perform switching operations based on the control signals G1 to G3. The control circuit 24 controls the switching operations of the transistors S1 to S3 via the control signals G11 to G13 based on the voltage Vout detected by the voltage sensor 22, so as to maintain the voltage Vout at a predetermined voltage. Furthermore, based on the voltage Vin detected by the voltage sensor 14, the current I1 detected by the current sensor 17, and the current I2 detected by the current sensor 18, the control circuit 24 controls the switching operations of the transistors S1 to S3 via control signals G11 to G13 so that the waveform of the input current to the power conversion device 1 becomes the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1. In this way, the power conversion device 1 converts the AC power supplied from the AC power supply PAC into DC power and supplies the converted DC power to the load device LD.

[0029] (Detailed Operation) An example of the operation of the power conversion device 1 will be described in detail below.

[0030] 2 shows an example of the operation of the power conversion device 1, where (A) shows the waveform of the voltage Vin input to the power conversion device 1, and (B) shows the waveform of the current (reactor current Ir) flowing in the reactor 16 from node N1 to node N3. FIG. 2 shows the waveform for one cycle. As shown in FIG. 2A, a sine-wave AC voltage is input to the power conversion device 1. The voltage Vin has an amplitude of, for example, 300 Vop to 400 Vop (600 Vpp to 800 Vpp). The voltage Vout is, for example, 400 V.

[0031] The control circuit 24 changes the switching duty ratio of the transistors S1 to S3 in accordance with the absolute value of the instantaneous value of the voltage Vin detected by the voltage sensor 14.

[0032] 3A to 3C show an example of the switching operation of the power conversion device 1, where Fig. 3A shows a case where the switching duty ratios of the transistors S1 to S3 are small, Fig. 3B shows a case where the switching duty ratios of the transistors S1 to S3 are medium, and Fig. 3C shows a case where the switching duty ratios of the transistors S1 to S3 are large. Here, the switching duty ratio of the transistor S1 is the proportion of the time period of the pulse period of the control signal G1 within the switching period T. The same is true for the switching duty ratios of the transistors S2 and S3. In each of Figs. 3A to 3C, (A) shows the waveform of the control signal G1, (B) shows the waveform of the control signal G2, (C) shows the waveform of the control signal G3, and (D) shows the waveform of the reactor current Ir.

[0033] 3A to 3C, the control circuit 24 and the drive circuit 23 generate control signals G1 to G3 in units of a switching period T. Specifically, the control circuit 24 generates control signals G11 to G13, and the drive circuit 23 generates control signals G1 to G3 based on the control signals G11 to G13, respectively. The transition timing of the control signal G1 is the same as the transition timing of the control signal G11, the transition timing of the control signal G2 is the same as the transition timing of the control signal G12, and the transition timing of the control signal G3 is the same as the transition timing of the control signal G13. The phase of the control signal G2 lags behind the phase of the control signal G1 by a phase corresponding to 1 / 3 (T / 3) of the switching period T. The phase of the control signal G3 lags behind the phase of the control signal G2 by a phase corresponding to 1 / 3 of the switching period T.

[0034] For example, when the absolute value of voltage Vin is large, as shown in portion W1 in Fig. 2, the control circuit 24 reduces the switching duty ratios of transistors S1 to S3, as shown in Fig. 3A. For example, when the absolute value of voltage Vin is medium, as shown in portion W2 in Fig. 2, the control circuit 24 sets the switching duty ratios of transistors S1 to S3 to medium, as shown in Fig. 3B. For example, when the absolute value of voltage Vin is small, as shown in portion W3 in Fig. 2, the control circuit 24 increases the switching duty ratios of transistors S1 to S3, as shown in Fig. 3C. In this way, the power conversion device 1 converts AC power supplied from the AC power source PAC into DC power by changing the switching duty ratios of transistors S1 to S3 in accordance with the absolute value of the instantaneous value of voltage Vin.

[0035] The operation of the power conversion device 1 will be described in detail below for each of the cases where the switching duty ratio is small (FIG. 3A), medium (FIG. 3B), and large (FIG. 3C).

[0036] (When the switching duty ratio is small) When the switching duty ratio is smaller than 1 / 3, the control circuit 24 and the drive circuit 23 generate the control signals G1 to G3 as shown in FIG. 3A. Specifically, the control signal G1 rises at timing t11 and falls at timing t12 (FIG. 3A(A)). The control signal G2 rises at timing t13 and falls at timing t14 (FIG. 3A(B)). The control signal G3 rises at timing t15 and falls at timing t16 (FIG. 3A(C)). Therefore, the pulse periods of the control signals G1 to G3 do not overlap with each other.

[0037] 4A to 4D show an example of the operating state of the power conversion device 1 when the switching duty ratio is less than 1 / 3. For ease of explanation, the power conversion device 1 is depicted in a simplified form in these figures. Specifically, for example, the noise filter 11, voltage sensors 14 and 22, current sensors 17 and 18, drive circuit 23, and control circuit 24 are not shown. Furthermore, in FIGS. 4A to 4D, transistors S1 to S3 are depicted using switches indicating their on / off states. In FIGS. 4A to 4D, the path of current I is shown when voltage Vin is a positive voltage.

[0038] During the period from timing t11 to t12 (FIG. 3A), the control signal G1 is at a high level, and the control signals G2 and G3 are at a low level (FIGS. 3A(A) to 3A(C)). Therefore, as shown in FIG. 4A, the transistor S1 is on, and the transistors S2 and S3 are off. As a result, as shown in FIG. 4A, the current I flows through the input terminal T11, the diode D11, the reactor 16, the diode D3, the diode D2, the capacitor 19, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir increases, as shown in FIG. 3A(D). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0039] In this example, the operation when the voltage Vin is a positive voltage has been described, but when the voltage Vin is a negative voltage, the current I similarly flows in the order of input terminal T12, diode D13, reactor 16, diode D3, diode D2, capacitor 19, transistor S1, diode D12, and input terminal T11. In other words, the path of the current I is the same in the circuit portion subsequent to rectifier circuit 15 (diodes D11 to D14).

[0040] During the period from timing t12 to t13 (FIG. 3A), the control signals G1 to G3 are at a low level (FIGS. 3A(A) to (C)). Therefore, as shown in FIG. 4B, the transistors S1 to S3 are in an off state. As a result, as shown in FIG. 4B, the current I flows in the following order: input terminal T11, diode D11, reactor 16, diode D3, diode D2, diode D1, capacitor 21 and load device LD, diode D14, and input terminal T12. During this period, the reactor current Ir decreases, as shown in FIG. 3A(D). In this way, the reactor 16 is discharged. The current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0041] During the period from timing t13 to t14 (FIG. 3A), control signal G2 is at a high level, and control signals G1 and G3 are at a low level (FIGS. 3A(A) to 3A(C)). Therefore, as shown in FIG. 4C, transistor S2 is on, and transistors S1 and S3 are off. As a result, as shown in FIG. 4C, current I flows through input terminal T11, diode D11, reactor 16, diode D3, capacitor 20, transistor S2, capacitor 19, diode D1, capacitor 21, load device LD, diode D14, and input terminal T12 in this order. During this period, reactor current Ir increases, as shown in FIG. 3A(D). In this way, reactor 16 is charged. Current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0042] During the period from timing t14 to t15 (FIG. 3A), the control signals G1 to G3 are at a low level (FIGS. 3A(A) to (C)). Therefore, as shown in FIG. 4B, the transistors S1 to S3 are in an off state. As a result, as shown in FIG. 4B, the current I flows through the input terminal T11, diode D11, reactor 16, diode D3, diode D2, diode D1, capacitor 21 and load device LD, diode D14, and input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 3A(D). In this way, the reactor 16 is discharged. The current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0043] During the period from timing t15 to t16 (FIG. 3A), control signal G3 is at a high level, and control signals G1 and G2 are at a low level (FIGS. 3A(A) to 3A(C)). Therefore, as shown in FIG. 4D, transistor S3 is on, and transistors S1 and S2 are off. As a result, as shown in FIG. 4D, current I flows through input terminal T11, diode D11, reactor 16, transistor S3, capacitor 20, diode D2, diode D1, capacitor 21, load device LD, diode D14, and input terminal T12 in this order. During this period, reactor current Ir increases, as shown in FIG. 3A(D). In this way, reactor 16 is charged. Current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0044] During the period from timing t16 to t17 (FIG. 3A), the control signals G1 to G3 are at a low level (FIGS. 3A(A) to (C)). Therefore, as shown in FIG. 4B, the transistors S1 to S3 are in an off state. As a result, as shown in FIG. 4B, the current I flows in the following order: input terminal T11, diode D11, reactor 16, diode D3, diode D2, diode D1, capacitor 21 and load device LD, diode D14, and input terminal T12. During this period, the reactor current Ir decreases, as shown in FIG. 3A(D). In this way, the reactor 16 is discharged. The current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0045] When the switching duty ratio is smaller than 1 / 3, the power conversion device 1 repeats the operation during the period from timing t11 to timing t17.

[0046] (When the switching duty ratio is medium) When the switching duty ratio is greater than 1 / 3 and less than 2 / 3, the control circuit 24 and the drive circuit 23 generate the control signals G1 to G3 as shown in FIG. 3B. Specifically, the control signal G1 rises at timing t21 and falls at timing t24 (FIG. 3B(A)). The control signal G2 rises at timing t23 and falls at timing t26 (FIG. 3B(B)). The control signal G3 rises at timing t25 and falls at timing t28 (FIG. 3B(C)). Thus, during the period from timing t21 to t22, the pulse periods of the control signals G1 and G3 overlap each other; during the period from timing t23 to t24, the pulse periods of the control signals G1 and G2 overlap each other; and during the period from timing t25 to t26, the pulse periods of the control signals G2 and G3 overlap each other.

[0047] 5A to 5F show an example of the operating state of the power conversion device 1 when the switching duty ratio is greater than 1 / 3 and less than 2 / 3.

[0048] During the period from timing t21 to t22 (FIG. 3B), the control signals G1 and G3 are at a high level, and the control signal G2 is at a low level (FIGS. 3B(A) to (C)). Therefore, as shown in FIG. 5A, the transistors S1 and S3 are on, and the transistor S2 is off. As a result, as shown in FIG. 5A, the current I flows through the input terminal T11, the diode D11, the reactor 16, the transistor S3, the capacitor 20, the diode D2, the capacitor 19, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir increases, as shown in FIG. 3B(D). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0049] During the period from timing t22 to t23 (FIG. 3B), the control signal G1 is at a high level, and the control signals G2 and G3 are at a low level (FIGS. 3B(A) to (C)). Therefore, as shown in FIG. 5B, the transistor S1 is on, and the transistors S2 and S3 are off. As a result, as shown in FIG. 5B, the current I flows through the input terminal T11, the diode D11, the reactor 16, the diode D3, the diode D2, the capacitor 19, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 3B(D). In this way, the reactor 16 is discharged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0050] During the period from timing t23 to t24 (FIG. 3B), the control signals G1 and G2 are at a high level, and the control signal G3 is at a low level (FIGS. 3B(A) to (C)). Therefore, as shown in FIG. 5C, the transistors S1 and S2 are on, and the transistor S3 is off. As a result, as shown in FIG. 5C, the current I flows through the input terminal T11, the diode D11, the reactor 16, the diode D3, the capacitor 20, the transistor S2, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir increases, as shown in FIG. 3B(D). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0051] During the period from timing t24 to t25 (FIG. 3B), control signal G2 is at a high level, and control signals G1 and G3 are at a low level (FIGS. 3B(A) to (C)). Therefore, as shown in FIG. 5D, transistor S2 is on, and transistors S1 and S3 are off. As a result, as shown in FIG. 5D, current I flows through input terminal T11, diode D11, reactor 16, diode D3, capacitor 20, transistor S2, capacitor 19, diode D1, capacitor 21, load device LD, diode D14, and input terminal T12 in this order. During this period, reactor current Ir decreases, as shown in FIG. 3B(D). In this way, reactor 16 is discharged. Current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0052] During the period from timing t25 to t26 (FIG. 3B), control signals G2 and G3 are at a high level, and control signal G1 is at a low level (FIGS. 3B(A) to (C)). Therefore, as shown in FIG. 5E, transistors S2 and S3 are on, and transistor S1 is off. As a result, as shown in FIG. 5E, current I flows through input terminal T11, diode D11, reactor 16, transistor S3, transistor S2, capacitor 19, diode D1, capacitor 21, load device LD, diode D14, and input terminal T12 in this order. During this period, reactor current Ir increases, as shown in FIG. 3B(D). In this way, reactor 16 is charged. Current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0053] During the period from timing t26 to t27 (FIG. 3B), control signal G3 is at a high level, and control signals G1 and G2 are at a low level (FIGS. 3B(A) to (C)). Therefore, as shown in FIG. 5F, transistor S3 is on, and transistors S1 and S2 are off. As a result, as shown in FIG. 5F, current I flows through input terminal T11, diode D11, reactor 16, transistor S3, capacitor 20, diode D2, diode D1, capacitor 21, load device LD, diode D14, and input terminal T12 in this order. During this period, reactor current Ir decreases, as shown in FIG. 3B(D). In this way, reactor 16 is discharged. Current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0054] When the switching duty ratio is greater than 1 / 3 and smaller than 2 / 3, the power conversion device 1 repeats the operation during the period from timing t21 to t27.

[0055] (When the switching duty ratio is large) When the switching duty ratio is larger than 2 / 3, the control circuit 24 and the drive circuit 23 generate the control signals G1 to G3 as shown in FIG. 3C. Specifically, the control signal G1 rises at timing t31 and falls at timing t36 (FIG. 3C(A)). The control signal G2 rises at timing t33 ​​and falls at timing t38 (FIG. 3C(B)). The control signal G3 rises at timing t35 and falls at timing t39 (FIG. 3C(C)). Therefore, the pulse periods of the control signals G1 to G3 overlap with each other during the periods from timing t31 to t32, from timing t33 ​​to t34, and from timing t35 to t36. Furthermore, during the period from timing t32 to t33, the pulse periods of the control signals G1 and G3 overlap with each other, during the period from timing t34 to t35, the pulse periods of the control signals G1 and G2 overlap with each other, and during the period from timing t36 to t37, the pulse periods of the control signals G2 and G3 overlap with each other.

[0056] 6A to 6D show an example of the operating state of the power conversion device 1 when the switching duty ratio is greater than 2 / 3.

[0057] During the period from timing t31 to t32 (FIG. 3C), the control signals G1 to G3 are at a high level (FIGS. 3C(A) to (C)). Therefore, as shown in FIG. 6A, the transistors S1 to S3 are in an on state. As a result, as shown in FIG. 6A, the current I flows in the following order through the input terminal T11, the diode D11, the reactor 16, the transistor S3, the transistor S2, the transistor S1, the diode D14, and the input terminal T12. During this period, the reactor current Ir increases, as shown in FIG. 3C(D). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0058] During the period from timing t32 to t33 (FIG. 3C), the control signals G1 and G3 are at a high level, and the control signal G2 is at a low level (FIGS. 3C(A)-(C)). Therefore, as shown in FIG. 6B, the transistors S1 and S3 are on, and the transistor S2 is off. As a result, as shown in FIG. 6B, the current I flows through the input terminal T11, the diode D11, the reactor 16, the transistor S3, the capacitor 20, the diode D2, the capacitor 19, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 3C(D). In this way, the reactor 16 is discharged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0059] During the period from timing t33 ​​to t34 (FIG. 3C), the control signals G1 to G3 are at a high level (FIGS. 3C(A) to (C)). Therefore, as shown in FIG. 6A, transistors S1 to S3 are in an on state. As a result, as shown in FIG. 6A, current I flows in the following order through input terminal T11, diode D11, reactor 16, transistor S3, transistor S2, transistor S1, diode D14, and input terminal T12. During this period, reactor current Ir increases, as shown in FIG. 3C(D). In this way, reactor 16 is charged. Current sensor 17 (FIG. 1) provided between transistor S1 and reference voltage line L2 detects this current I as current I1.

[0060] During the period from timing t34 to t35 (FIG. 3C), the control signals G1 and G2 are at a high level, and the control signal G3 is at a low level (FIGS. 3A(A) to 3A(C)). Therefore, as shown in FIG. 6C, the transistors S1 and S2 are on, and the transistor S3 is off. As a result, as shown in FIG. 6C, the current I flows through the input terminal T11, the diode D11, the reactor 16, the diode D3, the capacitor 20, the transistor S2, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 3C(D). In this way, the reactor 16 is discharged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0061] During the period from timing t35 to t36 (FIG. 3C), the control signals G1 to G3 are at a high level (FIGS. 3C(A) to (C)). Therefore, as shown in FIG. 6A, transistors S1 to S3 are in an on state. As a result, as shown in FIG. 6A, current I flows in the following order through input terminal T11, diode D11, reactor 16, transistor S3, transistor S2, transistor S1, diode D14, and input terminal T12. During this period, reactor current Ir increases, as shown in FIG. 3C(D). In this way, reactor 16 is charged. Current sensor 17 (FIG. 1) provided between transistor S1 and reference voltage line L2 detects this current I as current I1.

[0062] During the period from timing t36 to t37 (FIG. 3C), control signals G2 and G3 are at a high level, and control signal G1 is at a low level (FIGS. 3C(A) to 3C(C)). Therefore, as shown in FIG. 6D, transistors S2 and S3 are on, and transistor S1 is off. As a result, as shown in FIG. 6D, current I flows through input terminal T11, diode D11, reactor 16, transistor S3, transistor S2, capacitor 19, diode D1, capacitor 21, load device LD, diode D14, and input terminal T12 in this order. During this period, reactor current Ir decreases, as shown in FIG. 3C(D). In this way, reactor 16 is discharged. Current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0063] When the switching duty ratio is greater than 2 / 3, the power conversion device 1 repeats the operation during the period from timing t31 to timing t37.

[0064] In this way, the control circuit 24 changes the switching duty ratio of the transistors S1 to S3 in accordance with the absolute value of the instantaneous value of the voltage Vin.

[0065] Furthermore, based on the voltage Vin detected by the voltage sensor 14, the current I1 detected by the current sensor 17, and the current I2 detected by the current sensor 18, the control circuit 24 controls the switching operations of the transistors S1 to S3 so that the waveform of the input current to the power conversion device 1 becomes the same as the waveform of the input voltage (voltage Vin) to the power conversion device 1. Specifically, the control circuit 24 estimates the waveform of the input current to the power conversion device 1 based on the currents I1 and I2. Then, the control circuit 24 controls the switching operations of the transistors S1 to S3 so that the estimated waveform of the input current becomes the same as the waveform of the input voltage (voltage Vin) to the power conversion device 1. This allows the power factor to be improved in the power conversion device 1.

[0066] In the power conversion device 1, as shown in Figures 4A to 4D, 5A to 5F, and 6A to 6D, current I flows from node N3 to the reference voltage line L2 via various paths, and similarly, current I flows from node N3 to the voltage line L4 via various paths.

[0067] For example, a current I flows through transistors S1 to S3 in a direction from node N3 toward reference voltage line L2. Therefore, a current I flows in one direction, from transistor S1 toward reference voltage line L2, through current sensor 17 (FIG. 1) provided between transistor S1 and reference voltage line L2. Therefore, in power conversion device 1, the circuit operation can be simplified compared to a case where current flows bidirectionally, such as in the technology described in Prior Art Document 1. Furthermore, because current sensor 17 provided between transistor S1 and reference voltage line L2 detects such a current flowing in one direction, the configuration of current sensor 17 can be simplified.

[0068] Similarly, a current I flows through diodes D1 to D3 in a direction from node N3 toward voltage line L4. Therefore, a current I flows in one direction, from diode D1 toward voltage line L4, through current sensor 18 (FIG. 1) provided between diode D1 and voltage line L4. Therefore, in power conversion device 1, the circuit operation can be simplified compared to when current flows bidirectionally, as in the technology described in Prior Art Document 1, for example. Furthermore, because current sensor 18 provided between diode D1 and voltage line L4 detects such a current flowing in one direction, the configuration of current sensor 18 can be simplified.

[0069] Furthermore, in the power conversion device 1, because current flows in one direction from node N3 to voltage line L4, three diodes D1 to D3 can be used instead of three transistors. As a result, the circuit operation of the power conversion device 1 can be simplified compared to when three transistors are provided. Furthermore, since the power conversion device 1 does not need to provide these three transistors and a drive circuit for driving these three transistors, the circuit configuration of the power conversion device 1 can be simplified.

[0070] Furthermore, in the power conversion device 1, the cathodes of the diodes D11 and D13 are connected to the node N3 via the reactor 16. This makes it possible to reduce the possibility of a surge current occurring, as will be described below.

[0071] 7A and 7B show an example of the operation of the power conversion device 1 near the zero-cross timing of the AC voltage input to the power conversion device 1. In this example, a case where the AC voltage changes from a positive voltage to a negative voltage will be described. Fig. 7A shows the case where the AC voltage is positive immediately before the zero-cross timing, and Fig. 7B shows the case where the AC voltage is negative immediately after the zero-cross timing.

[0072] 7A, immediately before the zero-crossing timing, the voltage at one end of the AC power supply PAC is higher than the voltage at the other end, so current flows in the following order: one end of the AC power supply PAC, input terminal T11, diode D11, and node N1, and also flows in the following order: reference voltage line L2, diode D14, input terminal T12, and the other end of the AC power supply PAC. Near the zero-crossing timing, the voltage difference between both ends of the AC power supply PAC is approximately 0 V. For convenience of explanation, if the forward voltages of diodes D11 to D14 are assumed to be approximately 0 V, the voltage at input terminal T11, the voltage at input terminal T12, and the voltage at node N1 are also approximately 0 V.

[0073] 7B, immediately after the zero-crossing timing, the voltage at one end of the AC power supply PAC is lower than the voltage at the other end, so current flows in the order of the other end of the AC power supply PAC, input terminal T12, diode D13, and node N1, and also in the order of reference voltage line L2, diode D12, input terminal T11, and one end of the AC power supply PAC. Near the zero-crossing timing, the voltage difference between both ends of the AC power supply PAC is approximately 0 V. For convenience of explanation, if the forward voltages of diodes D11 to D14 are assumed to be approximately 0 V, the voltage at input terminal T11, the voltage at input terminal T12, and the voltage at node N1 are also approximately 0 V.

[0074] In this way, in the power conversion device 1, the voltage at the input terminal T11, the voltage at the input terminal T12, and the voltage at the node N1 are substantially 0 V both immediately before and after the zero-crossing timings. Therefore, in the power conversion device 1, it is possible to reduce the possibility of a surge current occurring near the zero-crossing timings.

[0075] That is, for example, in the technology described in the prior art document, the cathodes of the diodes D11 and D13 are connected to an output node that outputs a DC voltage, and this DC voltage is, for example, several hundred volts. Therefore, the voltages at the input terminals T11 and T12 may change, for example, by several hundred volts near the zero-cross timing. In this case, a surge current may occur.

[0076] On the other hand, in the power conversion device 1, the cathodes of the diodes D11 and D13 are connected to the node N3 via the reactor 16, so the voltages of the input terminals T11 and T12 hardly change near the zero-cross timing, thereby reducing the possibility of surge currents occurring.

[0077] As described above, the power conversion device 1 includes input terminals including a first input terminal (input terminal T11) and a second input terminal (input terminal T12), a first element (diode D11) that is provided in a path connecting the first input terminal (input terminal T11) and a first node (node ​​N1) and that is capable of causing a current to flow from the first input terminal (input terminal T11) to the first node (node ​​N1), and a second element (diode D11) that is provided in a path connecting the second node (reference voltage line L2) and the first input terminal (input terminal T11) and that is capable of causing a current to flow from the second node (reference voltage line L2) to the first input terminal (input terminal T11). a second element (diode D12) that is provided in a path connecting the second input terminal (input terminal T12) and the first node (node ​​N1) and that is capable of causing a current to flow from the second input terminal (input terminal T12) to the first node (node ​​N1); a third element (diode D13) that is provided in a path connecting the second node (reference voltage line L2) and the second input terminal (input terminal T12) and that is capable of causing a current to flow from the second node (reference voltage line L2) to the second input terminal (input terminal T12). a rectifier circuit 15 including a first node (node ​​N1) and a second node (voltage line L4); a reactor 16 having one end connected to a first node (node ​​N1) and the other end connected to a third node (node ​​N3); a first path connecting the third node (node ​​N3) and a second node (reference voltage line L2) including a plurality of switching elements including a first switching element (transistor S1) and a second switching element (transistor S2) provided on either side of a first intermediate node; a plurality of rectifying elements including a first rectifying element (diode D1) and a second rectifying element (diode D2) arranged on either side of a node; a first capacitor (capacitor 19) having one end connected to a first intermediate node and the other end connected to a second intermediate node; output terminals including a first output terminal (output terminal T21) connected to a fourth node (voltage line L4) and a second output terminal (output terminal T22) connected to a second node (reference voltage line L2); and a plurality of rectifying elements arranged such that a waveform of an input current flowing into the input terminal is the same as a waveform of an input voltage at the input terminal.and a control circuit 24 capable of controlling the operation of the plurality of switching elements. As a result, for example, in the power conversion device 1, a current I flows in one direction, from the node N3 toward the reference voltage line L2, through the transistors S1 to S3, so that the circuit operation can be simplified compared to when a current flows bidirectionally. Also, for example, in the power conversion device 1, a current I flows in one direction, from the node N3 toward the voltage line L4, through the diodes D1 to D3, so that the circuit operation can be simplified compared to when a current flows bidirectionally.

[0078] The power conversion device 1 further includes a second capacitor (capacitor 20), and the plurality of switching elements further include a third switching element (transistor S3). In the first path, the first switching element (transistor S1), the second switching element (transistor S2), and the third switching element (transistor S3) are provided in this order from the second node (reference voltage line L2) toward the third node (node ​​N3), and the second switching element (transistor S2) and the third switching element (transistor S3) are provided with a third intermediate node in between. The plurality of rectifier elements further includes a third rectifier element (diode D3). In the second path, the first rectifier element (diode D1), the second rectifier element (diode D2), and the third rectifier element (diode D3) are arranged in this order from the fourth node (voltage line L4) toward the third node (node ​​N3). The second rectifier element (diode D2) and the third rectifier element (diode D3) are arranged with a fourth intermediate node between them. The second capacitor (capacitor 20) has one end connected to the third intermediate node and the other end connected to the fourth intermediate node. By providing three transistors S1 to S3 in this manner, the voltage applied to the reactor 16 in the power conversion device 1 can be reduced compared to, for example, a case in which two transistors are provided (power conversion device 2 described below). As a result, for example, the size of the reactor 16 can be reduced. Furthermore, in the power conversion device 1, the operating frequency can be increased by using three transistors S1 to S3, and therefore the ripple current can be reduced.

[0079] In the power conversion device 1, each of the multiple rectifying elements is a diode, so there is no need to control the switching operation of the transistors, compared to when transistors are used, and the circuit operation can be simplified. Furthermore, there is no need to provide these transistors and a drive circuit for driving them, so the circuit configuration of the power conversion device 1 can be simplified.

[0080] In the power conversion device 1, the input voltage is an AC voltage, and the first path allows current to flow unidirectionally from the third node (node ​​N3) to the second node (reference voltage line L2), while the second path allows current to flow unidirectionally from the third node (node ​​N3) to the fourth node (voltage line L4). This simplifies circuit operation compared to when current flows bidirectionally.

[0081] The power conversion device 1 further includes a first current sensor (current sensor 17) that is provided in the first path between the plurality of switching elements (transistors S1 to S3) and a second node (reference voltage line L2) and is capable of detecting a current flowing toward the second node (reference voltage line L2). The control circuit 24 is configured to control the operation of the plurality of switching elements based on the detection result of the first current sensor (current sensor 17). In the power conversion device 1, a current I flows unidirectionally from the transistor S1 toward the reference voltage line L2, and the current sensor 17 detects the current I flowing in this unidirectional manner. Therefore, the configuration of the current sensor 17 in the power conversion device 1 can be simplified. The power conversion device 1 can improve the power factor by controlling the switching operation of the transistors S1 to S3 using the current sensor 17 with such a simple configuration.

[0082] The power conversion device 1 further includes a second current sensor (current sensor 18) that is provided in the second path between the plurality of rectifying elements (diodes D1 to D3) and a fourth node (voltage line L4) and is capable of detecting a current flowing toward the fourth node (voltage line L4). The control circuit 24 is configured to control the operation of the plurality of switching elements based on the detection result of the second current sensor (current sensor 18). In the power conversion device 1, a current I flows unidirectionally from the diode D1 toward the voltage line L4, and the current sensor 17 detects the current I flowing in this unidirectional manner. Therefore, the configuration of the current sensor 18 in the power conversion device 1 can be simplified. The power conversion device 1 can improve the power factor by controlling the switching operation of the transistors S1 to S3 using the current sensor 18 with such a simple configuration.

[0083] [Effect] As described above, in the present embodiment, there is provided a rectifier circuit including: input terminals including a first input terminal and a second input terminal; a first element provided in a path connecting the first input terminal and a first node and capable of causing a current to flow from the first input terminal to the first node; a second element provided in a path connecting the second node and the first input terminal and capable of causing a current to flow from the second node to the first input terminal; a third element provided in the path connecting the second input terminal and the first node and capable of causing a current to flow from the second input terminal to the first node; and a fourth element provided in the path connecting the second node and the second input terminal and capable of causing a current to flow from the second node to the second input terminal; The power supply comprises a reactor, a plurality of switching elements including a first switching element and a second switching element disposed on either side of a first intermediate node in a first path connecting a third node and a second node, a plurality of rectifying elements including a first rectifying element and a second rectifying element disposed on either side of a second intermediate node in a second path connecting the third node and a fourth node, a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node, output terminals including a first output terminal connected to the fourth node and a second output terminal connected to the second node, and a control circuit capable of controlling the operation of the plurality of switching elements so that the waveform of an input current flowing into the input terminal is the same as the waveform of an input voltage at the input terminal, thereby simplifying circuit operation.

[0084] In this embodiment, the inverter further includes a second capacitor, the plurality of switching elements further includes a third switching element, the first switching element, the second switching element, and the third switching element are provided in this order on the first path from the second node to the third node, the second switching element and the third switching element are provided on either side of a third intermediate node, the plurality of rectifying elements further includes a third rectifying element, the first rectifying element, the second rectifying element, and the third rectifying element are provided in this order on the second path from the fourth node to the third node, the second rectifying element and the third rectifying element are provided on either side of a fourth intermediate node, and the second capacitor has one end connected to the third intermediate node and the other end connected to the fourth intermediate node. This makes it possible to reduce the size of a reactor and reduce ripple current, for example.

[0085] In this embodiment, each of the plurality of rectifying elements is a diode, so that the circuit operation can be simplified and the circuit configuration can be simplified.

[0086] In this embodiment, the input voltage is an AC voltage, and the first path allows current to flow in one direction from the third node to the second node, while the second path allows current to flow in one direction from the third node to the fourth node, thereby simplifying circuit operation.

[0087] In this embodiment, the first path further includes a first current sensor that is provided between the multiple switching elements and the second node and is capable of detecting the current flowing toward the second node, and the control circuit 24 is capable of controlling the operation of the multiple switching elements based on the detection result of the first current sensor, thereby simplifying the configuration of the current sensor.

[0088] In this embodiment, the second path further includes a second current sensor that is provided between the multiple rectifying elements and the fourth node and is capable of detecting the current flowing toward the fourth node, and the control circuit 24 is capable of controlling the operation of the multiple switching elements based on the detection result of the second current sensor, thereby simplifying the configuration of the current sensor.

[0089] [Variation 1] In the above embodiment, diodes D1 to D3 are used, but this is not limiting. Instead, for example, transistors S4 to S6 may be provided as in a power conversion device 1A shown in Figure 8. This power conversion device 1A includes transistors S4 to S6, a drive circuit 23A, and a control circuit 24A.

[0090] The transistors S4 to S6 are configured to perform switching operations. Like the transistors S1 to S3, the transistors S4 to S6 are configured using, for example, N-type field effect transistors. The transistors S4 to S6 are provided on a path connecting the node N3 and the voltage line L4. The drain of the transistor S4 is connected to one end of the current sensor 18, the source is connected to the drain of the transistor S5, and a control signal G4 is supplied to the gate. The drain of the transistor S5 is connected to the source of the transistor S4, the source is connected to the drain of the transistor S6, and a control signal G5 is supplied to the gate. The drain of the transistor S6 is connected to the source of the transistor S5, the source is connected to the node Nd, and a control signal G6 is supplied to the gate.

[0091] The drive circuit 23A is configured to generate control signals G1 to G6 based on the control signals G11 to G16 supplied from the control circuit 24A, respectively, and apply these control signals G1 to G6 to the gates of the transistors S1 to S6, respectively. The drive circuit 23A controls the switching operations of the transistors S4 to S6 by performing so-called synchronous rectification. Specifically, the drive circuit 23A controls the switching operation of the transistor S4 so as to turn on the transistor S4 during the period when the diode D1 is in the on state in the above embodiment. Similarly, the drive circuit 23A controls the switching operation of the transistor S5 so as to turn on the transistor S5 during the period when the diode D2 is in the on state in the above embodiment. The drive circuit 23A controls the switching operation of the transistor S6 so as to turn on the transistor S6 during the period when the diode D3 is in the on state in the above embodiment. In the power conversion device 1A, for example, by using transistors with low on-resistance as the transistors S4 to S6, loss can be reduced, thereby improving power efficiency.

[0092] In the above embodiment, the rectifier circuit 15 is configured using four diodes D11 to D14, but this is not limiting. Instead, the rectifier circuit 15 may be configured using four transistors. In this case, a drive circuit for driving these four transistors must be further provided. The drive circuit 23 controls the switching operation of these four transistors by performing so-called synchronous rectification.

[0093] [Variation 2] In the above embodiment, two current sensors 17 and 18 are provided, but this is not limiting. Alternatively, for example, one of the two current sensors 17 and 18 may be omitted. When the switching duty ratio is small ( FIGS. 3A , 4A to 4D), current sensor 17 detects the current during the period from timing t11 to t12, and current sensor 18 detects the current during the period from timing t12 to t17. When the switching duty ratio is medium ( FIGS. 3B , 5A to 5F), current sensor 17 detects the current during the period from timing t21 to t24, and current sensor 18 detects the current during the period from timing t24 to t27. When the switching duty ratio is large ( FIGS. 3C , 6A to 6D), current sensor 17 detects the current during the period from timing t31 to t36, and current sensor 18 detects the current during the period from timing t36 to t37. Therefore, the control circuit 24 can estimate the waveform of the input current using, for example, only the detection result of the current sensor 17, and similarly, can estimate the waveform of the input current using, for example, only the detection result of the current sensor 18. Then, the control circuit 24 can control the switching operations of the transistors S1 to S3 so that the estimated waveform of the input current becomes the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1.

[0094] Further, as in the power conversion device 1B shown in FIG. 9A and the power conversion device 1C shown in FIG. 9B, another current sensor may be provided instead of these two current sensors 17 and 18.

[0095] The power conversion device 1B includes a current sensor 27B and a control circuit 24B. The current sensor 27B is provided in a path connecting nodes N1 and N3 and is connected in series to the reactor 16. In this example, one end of the current sensor 27B is connected to the other end of the reactor 16, and the other end is connected to node N3. The current sensor 27B is configured to detect a current I3 flowing from node N1 to node N3. The control circuit 24B is configured to control the operation of the power conversion device 1B based on the voltage Vin detected by the voltage sensor 14, the voltage Vout detected by the voltage sensor 22, and the current I3 detected by the current sensor 27B. The control circuit 24B estimates the waveform of the input current of the power conversion device 1B based on the detection result of the current sensor 27B, and controls the switching operations of the transistors S1 to S3 so that the waveform of the estimated input current is the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1B.

[0096] The power conversion device 1C includes a current sensor 27C and a control circuit 24C. The current sensor 27C is provided on the reference voltage line L2, with one end connected to the anodes of diodes D12 and D14 in the rectifier circuit 15 and the other end connected to the output terminal T22. The current sensor 27C is configured to detect a current I4 flowing through the reference voltage line L2 toward the rectifier circuit 15. The control circuit 24C is configured to control the operation of the power conversion device 1C based on the voltage Vin detected by the voltage sensor 14, the voltage Vout detected by the voltage sensor 22, and the current I4 detected by the current sensor 27C. The control circuit 24C estimates the waveform of the input current of the power conversion device 1C based on the detection result of the current sensor 27C and controls the switching operations of the transistors S1 to S3 so that the estimated input current waveform is the same as the waveform of the input voltage (voltage Vin) of the power conversion device 1C.

[0097] [Variation 3] In the above embodiment, three transistors S1 to S3 and three diodes D1 to D3 are provided, but this is not limited to this. Instead, for example, two transistors S1 and S2 and two diodes D1 and D2 may be provided, or for example, four transistors and four diodes may be provided. In other words, a plurality of transistors and the same number of diodes as the plurality of transistors may be provided. Below, a detailed description is given using an example of a power conversion device 2 provided with two transistors S1 and S2 and two diodes D1 and D2.

[0098] 10 shows an example of the configuration of a power conversion device 2 according to this modification. The power conversion device 2 includes input terminals T11 and T12, a noise filter 11, a voltage sensor 14, a rectifier circuit 15, a reactor 16, a current sensor 17, transistors S1 and S2, a current sensor 18, diodes D1 and D2, capacitors 19 and 21, a voltage sensor 22, a drive circuit 33, a control circuit 34, and output terminals T21 and T22. That is, the power conversion device 2 is similar to the power conversion device 1 shown in FIG. 1 except that the transistor S3, the diode D3, and the capacitor 20 are omitted and the drive circuit 23 and the control circuit 24 are replaced with the drive circuit 33 and the control circuit 34.

[0099] The drive circuit 33 is configured to generate control signals G1 and G2 based on control signals G11 and G12 supplied from the control circuit 34, and apply these control signals G1 and G2 to the gates of the transistors S1 and S2, respectively.

[0100] The control circuit 34 is configured to control the operation of the power conversion device 2 based on the voltage Vin detected by the voltage sensor 14, the voltage Vout detected by the voltage sensor 22, the current I1 detected by the current sensor 17, and the current I2 detected by the current sensor 18. Specifically, the control circuit 34 controls the switching operations of the transistors S1 and S2 via control signals G11 and G12 based on the voltage Vin so that the voltage Vout is maintained at a predetermined voltage. The control circuit 34 also controls the switching operations of the transistors S1 and S2 via control signals G11 and G12 based on the voltage Vin and the currents I1 and I2 so that the waveform of the input current to the power conversion device 2 becomes the same as the waveform of the input voltage (voltage Vin) of the power conversion device 2.

[0101] 11A and 11B show an example of the switching operation of the power conversion device 2, where Fig. 11A shows a case where the switching duty ratio of the transistors S1 and S2 is small, and Fig. 11B shows a case where the switching duty ratio of the transistors S1 and S2 is large. In each of Figs. 11A and 11B, (A) shows the waveform of the control signal G1, (B) shows the waveform of the control signal G2, and (C) shows the waveform of the reactor current Ir.

[0102] 11A and 11B, the control circuit 34 and the drive circuit 33 generate the control signals G1 and G2 in units of a switching period T. The phase of the control signal G2 lags behind the phase of the control signal G1 by a phase corresponding to 1 / 2 of the switching period T (T / 2).

[0103] When the absolute value of voltage Vin is large, the control circuit 34 reduces the switching duty ratio of transistors S1 and S2 as shown in Fig. 11A. When the absolute value of voltage Vin is small, the control circuit 34 increases the switching duty ratio of transistors S1 and S2 as shown in Fig. 11B. In this way, the power conversion device 2 converts AC power supplied from the AC power supply PAC into DC power by changing the switching duty ratio of transistors S1 and S2 in accordance with the absolute value of the instantaneous value of voltage Vin.

[0104] (When the switching duty ratio is small) When the switching duty ratio is smaller than 1 / 2, the control circuit 34 and the drive circuit 33 generate the control signals G1 and G2 as shown in Fig. 11A. Specifically, the control signal G1 rises at timing t111 and falls at timing t112 (Fig. 11A(A)). The control signal G2 rises at timing t113 and falls at timing t114 (Fig. 11A(B)). Therefore, the pulse periods of the control signals G1 and G2 do not overlap each other.

[0105] 12A to 12C show an example of the operating state of the power conversion device 2 when the switching duty ratio is less than 1 / 2. 12A to 12C show the path of the current I when the voltage Vin is a positive voltage.

[0106] During the period from timing t111 to t112 (FIG. 11A), the control signal G1 is at a high level, and the control signal G2 is at a low level (FIGS. 11A(A) and 11A(B)). Therefore, as shown in FIG. 12A, the transistor S1 is in an on state, and the transistor S2 is in an off state. As a result, as shown in FIG. 12A, the current I flows in the following order: input terminal T11, diode D11, reactor 16, diode D2, capacitor 19, transistor S1, diode D14, and input terminal T12. During this period, the reactor current Ir increases, as shown in FIG. 11A(C). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 10) provided between the transistor S1 and the reference voltage line L2 detects this current I as a current I1.

[0107] During the period from timing t112 to t113 (FIG. 11A), the control signals G1 and G2 are at a low level (FIG. 11A(A) and (B)). Therefore, as shown in FIG. 12B, the transistors S1 and S2 are in an off state. As a result, as shown in FIG. 12B, the current I flows in the following order: input terminal T11, diode D11, reactor 16, diode D2, diode D1, capacitor 21 and load device LD, diode D14, and input terminal T12. During this period, the reactor current Ir decreases, as shown in FIG. 11A(C). In this way, the reactor 16 is discharged. The current sensor 18 (FIG. 10) provided between diode D1 and voltage line L4 detects this current I as current I2.

[0108] During the period from timing t113 to t114 (FIG. 11A), the control signal G2 is at a high level, and the control signal G1 is at a low level (FIGS. 11A(A) and 11A(B)). Therefore, as shown in FIG. 12C, the transistor S2 is on, and the transistor S1 is off. As a result, as shown in FIG. 12C, the current I flows through the input terminal T11, the diode D11, the reactor 16, the transistor S2, the capacitor 19, the diode D1, the capacitor 21, the load device LD, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir increases, as shown in FIG. 11A(C). In this way, the reactor 16 is charged. The current sensor 18 (FIG. 1) provided between the diode D1 and the voltage line L4 detects this current I as the current I2.

[0109] During the period from timing t114 to t115 (FIG. 11A), the control signals G1 and G2 are at a low level (FIG. 11A(A) and (B)). Therefore, as shown in FIG. 12B, the transistors S1 and S2 are in an off state. As a result, as shown in FIG. 12B, the current I flows through the input terminal T11, diode D11, reactor 16, diode D2, diode D1, capacitor 21 and load device LD, diode D14, and input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 11A(C). In this way, the reactor 16 is discharged. The current sensor 18 (FIG. 10) provided between the diode D1 and the voltage line L4 detects this current I as a current I2.

[0110] When the switching duty ratio is smaller than 1 / 2, the power conversion device 2 repeats the operation during the period from timing t111 to timing t115.

[0111] (When the switching duty ratio is large) When the switching duty ratio is larger than ½, the control circuit 34 and the drive circuit 33 generate the control signals G1 and G2 as shown in FIG. 11B. Specifically, the control signal G1 rises at timing t121 and falls at timing t124 (FIG. 11B(A)). The control signal G2 rises at timing t123 and falls at timing t126 (FIG. 11B(B)). Therefore, the pulse periods of the control signals G1 and G2 overlap with each other during the period from timing t121 to t122 ​​and the period from timing t123 to t124.

[0112] 13A to 13C show an example of the operating state of the power conversion device 2 when the switching duty ratio is greater than 1 / 2.

[0113] During the period from timing t121 to t122 ​​(FIG. 11B), the control signals G1 and G2 are at a high level (FIG. 11B(A) and (B)). Therefore, as shown in FIG. 13A, the transistors S1 and S2 are in an on state. As a result, as shown in FIG. 13A, the current I flows through the input terminal T11, the diode D11, the reactor 16, the transistor S2, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir increases, as shown in FIG. 11B(C). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 10) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0114] During the period from timing t122 ​​to t123 (FIG. 11B), the control signal G1 is at a high level, and the control signal G2 is at a low level (FIGS. 11B(A) and (B)). Therefore, as shown in FIG. 13B, the transistor S1 is in an on state, and the transistor S2 is in an off state. As a result, as shown in FIG. 13B, the current I flows through the input terminal T11, the diode D11, the reactor 16, the diode D2, the capacitor 19, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 11B(C). In this way, the reactor 16 is discharged. The current sensor 17 (FIG. 1) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0115] During the period from timing t123 to t124 (FIG. 11B), the control signals G1 and G2 are at a high level (FIG. 11B(A) and (B)). Therefore, as shown in FIG. 13A, the transistors S1 and S2 are in an on state. As a result, as shown in FIG. 13A, the current I flows through the input terminal T11, the diode D11, the reactor 16, the transistor S2, the transistor S1, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir increases, as shown in FIG. 11B(C). In this way, the reactor 16 is charged. The current sensor 17 (FIG. 10) provided between the transistor S1 and the reference voltage line L2 detects this current I as the current I1.

[0116] During the period from timing t124 to t125 (FIG. 11B), the control signal G2 is at a high level, and the control signal G1 is at a low level (FIGS. 11B(A) and (B)). Therefore, as shown in FIG. 13C, the transistor S2 is on, and the transistor S1 is off. As a result, as shown in FIG. 13C, the current I flows through the input terminal T11, the diode D11, the reactor 16, the transistor S2, the capacitor 19, the diode D1, the capacitor 21, the load device LD, the diode D14, and the input terminal T12 in this order. During this period, the reactor current Ir decreases, as shown in FIG. 11B(C). In this way, the reactor 16 is discharged. The current sensor 18 (FIG. 10) provided between the diode D1 and the voltage line L4 detects this current I as the current I2.

[0117] When the switching duty ratio is greater than 1 / 2, the power conversion device 2 repeats the operation during the period from timing t121 to timing t125.

[0118] [Other Modifications] Two or more of these modifications may be combined.

[0119] Although the present invention has been described above by way of embodiments and modifications, the present invention is not limited to these embodiments and can be modified in various ways.

[0120] For example, in the above embodiment, the power conversion device 1 is provided with the capacitor 21, but this is not limiting. The capacitor 21 may be built into the power conversion device 1 or may be attached externally to the power conversion device 1.

[0121] The effects described in this specification are merely examples, and the effects of the present disclosure are not limited to the effects described in this specification. Therefore, other effects may be obtained with respect to the present disclosure.

[0122] Furthermore, the present disclosure may take the following aspects.

[0123] (1) A rectifier circuit including: an input terminal including a first input terminal and a second input terminal; a first element provided in a path connecting the first input terminal and a first node, and capable of causing a current to flow from the first input terminal to the first node; a second element provided in a path connecting a second node and the first input terminal, and capable of causing a current to flow from the second node to the first input terminal; a third element provided in the path connecting the second input terminal and the first node, and capable of causing a current to flow from the second input terminal to the first node; and a fourth element provided in the path connecting the second node and the second input terminal, and capable of causing a current to flow from the second node to the second input terminal; a reactor having one end connected to the first node and the other end connected to a third node; and a plurality of switching elements including a first switching element and a second switching element provided on either side of a first intermediate node in the first path connecting the third node and the second node. a plurality of rectifying elements including a first rectifying element and a second rectifying element arranged on either side of a second intermediate node in a second path connecting the third node and a fourth node; a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node; output terminals including a first output terminal connected to the fourth node and a second output terminal connected to the second node; and a control circuit capable of controlling operation of the plurality of switching elements so that a waveform of an input current flowing into the input terminal becomes the same as a waveform of an input voltage at the input terminal.(2) The power conversion device according to (1), further comprising a second capacitor, wherein the plurality of switching elements further include a third switching element, wherein the first switching element, the second switching element, and the third switching element are provided in this order on the first path from the second node to the third node, wherein the second switching element and the third switching element are provided with a third intermediate node between them, wherein the plurality of rectifying elements further include a third rectifying element, wherein the first rectifying element, the second rectifying element, and the third rectifying element are provided in this order on the second path from the fourth node to the third node, wherein the second rectifying element and the third rectifying element are provided with a fourth intermediate node between them, and the second capacitor has one end connected to the third intermediate node and the other end connected to the fourth intermediate node. (3) The power conversion device according to (1) or (2), wherein each of the plurality of rectifying elements is a diode. (4) The power conversion device according to (1) or (2), wherein each of the plurality of rectifying elements is a switching element, and the control circuit is further capable of controlling operation of the plurality of rectifying elements. (5) The input voltage is an AC voltage, and a current can flow in one direction in the first path from the third node to the second node, and a current can flow in one direction in the second path from the third node to the fourth node. (6) The power conversion device according to any of (1) to (5), further comprising: a first current sensor provided in the first path between the plurality of switching elements and the second node, the first current sensor being capable of detecting a current flowing toward the second node, and the control circuit being capable of controlling operation of the plurality of switching elements based on a detection result of the first current sensor.(7) The power conversion device according to any one of (1) to (6), further comprising a second current sensor provided in the second path between the plurality of rectifying elements and the fourth node and capable of detecting a current flowing toward the fourth node, wherein the control circuit is capable of controlling operation of the plurality of switching elements based on a detection result of the second current sensor. (8) The power conversion device according to any one of (1) to (7), wherein the power conversion device is capable of outputting a DC voltage from the output terminals, and the control circuit is further capable of controlling operation of the plurality of switching elements so that the DC voltage becomes a predetermined voltage.

Claims

1. A rectifier circuit including: input terminals including a first input terminal and a second input terminal; a first element provided in a path connecting the first input terminal and a first node, and capable of causing a current to flow from the first input terminal to the first node; a second element provided in a path connecting a second node and the first input terminal, and capable of causing a current to flow from the second node to the first input terminal; a third element provided in the path connecting the second input terminal and the first node, and capable of causing a current to flow from the second input terminal to the first node; and a fourth element provided in the path connecting the second node and the second input terminal, and capable of causing a current to flow from the second node to the second input terminal; a reactor having one end connected to the first node and the other end connected to a third node; and a plurality of switching elements including a first switching element and a second switching element provided on either side of a first intermediate node in the first path connecting the third node and the second node. a plurality of rectifying elements including a first rectifying element and a second rectifying element arranged on either side of a second intermediate node in a second path connecting the third node and a fourth node; a first capacitor having one end connected to the first intermediate node and the other end connected to the second intermediate node; output terminals including a first output terminal connected to the fourth node and a second output terminal connected to the second node; and a control circuit capable of controlling operation of the plurality of switching elements so that a waveform of an input current flowing into the input terminal becomes the same as a waveform of an input voltage at the input terminal.

2. The power conversion device according to claim 1, further comprising a second capacitor, wherein the plurality of switching elements further include a third switching element, wherein the first switching element, the second switching element, and the third switching element are provided in this order on the first path from the second node to the third node, wherein the second switching element and the third switching element are provided with a third intermediate node between them, wherein the plurality of rectifying elements further include a third rectifying element, wherein the first rectifying element, the second rectifying element, and the third rectifying element are provided in this order on the second path from the fourth node to the third node, wherein the second rectifying element and the third rectifying element are provided with a fourth intermediate node between them, and wherein the second capacitor has one end connected to the third intermediate node and the other end connected to the fourth intermediate node.

3. The power conversion device according to claim 1, wherein each of the plurality of rectifying elements is a diode.

4. The power conversion device according to claim 1, wherein each of the plurality of rectifying elements is a switching element, and the control circuit is further capable of controlling the operation of the plurality of rectifying elements.

5. The power conversion device according to claim 1, wherein the input voltage is an AC voltage, and the first path allows a current to flow in one direction from the third node to the second node, and the second path allows a current to flow in one direction from the third node to the fourth node.

6. The power conversion device according to claim 1, further comprising a first current sensor provided in the first path between the plurality of switching elements and the second node, capable of detecting a current flowing toward the second node, and wherein the control circuit is capable of controlling the operation of the plurality of switching elements based on the detection result of the first current sensor.

7. The power conversion device according to claim 1, further comprising a second current sensor provided in the second path between the plurality of rectifying elements and the fourth node, capable of detecting a current flowing toward the fourth node, and wherein the control circuit is capable of controlling the operation of the plurality of switching elements based on the detection result of the second current sensor.

8. The power conversion device according to claim 1, wherein the power conversion device is capable of outputting a DC voltage from the output terminal, and the control circuit is further capable of controlling the operation of the plurality of switching elements so that the DC voltage becomes a predetermined voltage.

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