Array substrate and manufacturing method therefor, and display panel

Abstract

An array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises a base substrate (101); a first data line (102), which extends in a first direction (Y) on the base substrate (101), the first data line (102) comprising a break (O); a bridging structure (103), which is connected to the first data line (102) at two ends of the break (O); a first transistor (104), a first electrode (S) of the first transistor (104) being connected to the first data line (102); and a first pixel electrode (105), the first pixel electrode (105) being insulated from a second electrode (D) of the first transistor (104).

Description

Array substrate, manufacturing method thereof and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display panel. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a manufacturing method thereof, and a display panel, and the specific solutions are as follows:

[0005] In one aspect, the present disclosure provides an array substrate, comprising:

[0006] substrate;

[0007] A first data line extending along a first direction on the base substrate, wherein the first data line includes a break;

[0008] a bridge structure connected to the first data lines at both ends of the break;

[0009] a first transistor, wherein a first electrode of the first transistor is connected to the first data line;

[0010] A first pixel electrode is provided, wherein the first pixel electrode and the second electrode of the first transistor are insulated from each other.

[0011] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the bridge structure is connected to the second electrode of the first transistor.

[0012] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes an insulating layer located between the layer where the first data line is located and the layer where the first pixel electrode is located;

[0013] The insulating layer includes a via hole, and the insulating layer around the via hole is arranged in contact with the second electrode of the first transistor;

[0014] The orthographic projection of the first pixel electrode on the base substrate and the orthographic projection of the via hole on the base substrate do not overlap with each other.

[0015] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first pixel electrode includes a relief portion, and a distance between an orthographic projection of the relief portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than or equal to 4 μm.

[0016] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the avoidance portion is a recessed structure that is recessed away from the via hole in the first direction.

[0017] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the avoidance portion is a protruding structure protruding toward the via hole in the first direction.

[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the avoidance portion is a notch structure facing the via hole in the first direction and away from the first data line in the second direction, and the second direction intersects with the first direction.

[0019] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a gate line extending along a second direction, and the avoidance portion is a non-closed structure arranged around the via on both sides of the via extending along the first direction, and on the side of the via extending in the second direction and away from the gate line, and the second direction intersects with the first direction.

[0020] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a gate line extending along a second direction, and the avoidance portion is a closed structure facing the via hole in the first direction and away from the gate line in the second direction, and the second direction intersects with the first direction.

[0021] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the base substrate includes a plurality of sub-pixel regions, and the sub-pixel regions include opening regions and non-opening regions;

[0022] The via hole is located in the non-opening area;

[0023] The avoidance portion is located in the non-opening area, or the avoidance portion partially overlaps with the non-opening area and the opening area respectively.

[0024] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a distance between an orthographic projection of the avoidance portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than or equal to 10 μm.

[0025] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the base substrate includes a plurality of sub-pixel regions, and the sub-pixel regions include opening regions and non-opening regions;

[0026] The first pixel electrode is located in the opening area, and the via hole is located in the non-opening area.

[0027] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a conductive pattern arranged in the same layer as the first pixel electrode in the non-opening area, the spacing between the conductive pattern and the first pixel electrode in the first direction is greater than or equal to 4 μm, and the conductive pattern covers and fills the via hole.

[0028] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second pixel electrode, a second transistor, a second data line, a third transistor, and a third pixel electrode; wherein,

[0029] A first electrode of the second transistor is connected to the first data line, a second electrode of the second transistor is connected to the second pixel electrode, and a pattern of the second pixel electrode is different from a pattern of the first pixel electrode;

[0030] The second data lines are continuously arranged, connected to the first electrode of the third transistor, the third pixel electrode is connected to the second electrode of the third transistor, and the pattern of the third pixel electrode is the same as that of the second pixel electrode.

[0031] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the bridge structure is provided in the same layer as the first data line, the first electrode and the second electrode of the first transistor.

[0032] On the other hand, the present disclosure provides a display panel, comprising the array substrate provided in the embodiments of the present disclosure, and an opposite substrate disposed opposite to the array substrate.

[0033] In another aspect, the present disclosure provides a method for manufacturing an array substrate, comprising:

[0034] providing a substrate;

[0035] [Corrected 01.11.2024 according to Rule 91] Patterning a first electrode and a second electrode of a first transistor, and a first data line on the base substrate, wherein the first data line extends along a first direction and includes a break, and the first data line is connected to the first electrode of the first transistor;

[0036] forming a bridge structure by a sputtering coating process, so as to connect the first data lines at both ends of the fracture by using the bridge structure;

[0037] A first pixel electrode insulated from the second electrode of the first transistor is formed by patterning on the layer where the first data line is located.

[0038] In some embodiments, in the above-mentioned manufacturing method provided by the embodiment of the present disclosure, the base substrate includes a plurality of sub-pixel regions, and the sub-pixel regions include opening regions and non-opening regions;

[0039] After sputtering to form the bridge structure and before patterning to form the first pixel electrode, the method further includes:

[0040] An insulating layer having a via hole is patterned, wherein the via hole is located in the non-opening area, and the insulating layer around the via hole is in contact with the second electrode of the first transistor.

[0041] In some embodiments, in the above-mentioned manufacturing method provided in the embodiments of the present disclosure, patterning a first pixel electrode insulated from the second electrode of the first transistor on the layer where the first data line is located specifically includes:

[0042] Patterning a first pixel electrode on the layer where the first data line is located to cover the opening area and to cover and fill the via hole in the non-opening area;

[0043] At least the pattern of the first pixel electrode at the via hole is removed to form a relief portion, and a distance between an orthographic projection of the relief portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than or equal to 4 μm.

[0044] In some embodiments, in the above-mentioned manufacturing method provided in the embodiments of the present disclosure, patterning a first pixel electrode insulated from the second electrode of the first transistor on the layer where the first data line is located specifically includes:

[0045] Patterning a pixel electrode pattern on the layer where the first data line is located to cover the opening area and to cover and fill the via hole in the non-opening area;

[0046] A portion of the pixel electrode pattern close to the non-opening area is removed to form a first pixel electrode located in the opening area and a conductive pattern located in the non-opening area, wherein a distance between the first pixel electrode and the conductive pattern in the first direction is greater than or equal to 4 μm.

[0047] [Corrected 01.11.2024 according to Rule 91] In some embodiments, in the above-mentioned manufacturing method provided in the embodiment of the present disclosure, while patterning the first electrode and the second electrode of the first transistor and the first data line, the method further includes:

[0048] [Corrected 01.11.2024 according to Rule 91] patterning a first electrode and a second electrode of a second transistor, a first electrode and a second electrode of a third transistor, and a second data line disposed continuously therebetween, the first data line being connected to the first electrode of the second transistor, and the second data line being connected to the first electrode of the third transistor;

[0049] While patterning to form the first pixel electrode, it also includes: patterning to form a second pixel electrode connected to the second electrode of the second transistor, and a third pixel electrode connected to the second electrode of the third transistor, and the pattern of the second pixel electrode is the same as the pattern of the third pixel electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of a repair line defect in the related art;

[0051] Figure 2 is a schematic diagram showing the principle of abnormal bright spots caused by the bridge structure;

[0052] FIG3 is a schematic diagram showing the connection between a transistor and a pixel electrode;

[0053] FIG4 is a schematic diagram showing the principle of welding the pixel electrode and the common electrode line;

[0054] Figure 5 is a picture of sputtering / diffusion of the bridge structure;

[0055] Figure 6 is a schematic diagram showing the principle of line failure caused by bridge repair;

[0056] FIG7 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0057] FIG8 is a schematic diagram of the enlarged structure of the via hole and the pixel electrode in the Z1 region in FIG7;

[0058] FIG9 is a schematic diagram of the cross-sectional structure along line II' in FIG7;

[0059] FIG10 is a schematic structural diagram of the layer where the gate lines are located in FIG7;

[0060] FIG11 is a schematic structural diagram of the active layer in FIG7 ;

[0061] FIG12 is a schematic structural diagram of the layer where the data line is located in FIG7;

[0062] FIG13 is a schematic structural diagram of the layer where the vias are located in FIG7 ;

[0063] FIG14 is a schematic structural diagram of the layer where the pixel electrode is located in FIG7 ;

[0064] FIG15 is a schematic structural diagram of a pixel electrode provided in an embodiment of the present disclosure;

[0065] FIG16 is an enlarged structural diagram of the Z2 region in FIG15 ;

[0066] FIG17 is a schematic structural diagram of a pixel electrode provided in an embodiment of the present disclosure;

[0067] FIG18 is an enlarged structural diagram of the Z3 region in FIG17 ;

[0068] FIG19 is a schematic structural diagram of a pixel electrode provided in an embodiment of the present disclosure;

[0069] FIG20 is an enlarged structural diagram of the Z4 region in FIG19 ;

[0070] FIG21 is a schematic structural diagram of a pixel electrode provided in an embodiment of the present disclosure;

[0071] FIG22 is an enlarged structural diagram of the Z5 region in FIG21 ;

[0072] FIG23 is a schematic diagram of a structure of a pixel electrode provided in an embodiment of the present disclosure;

[0073] FIG24 is an enlarged structural diagram of the Z6 region in FIG23 ;

[0074] FIG25 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

[0075] FIG26 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0076] FIG. 27 is a schematic diagram of the cross-sectional structure along line II-II′ in FIG. 26 . DETAILED DESCRIPTION

[0077] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0078] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0079] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0080] As user demand for high-end MNT displays grows, the inventors have developed a four-in-one high-end curved display featuring ultra-wide, high-resolution, curved, and high-refresh rates to enhance product competitiveness. As MNT product resolution increases, pixel density continues to rise, and line widths gradually become thinner, the proportion of defective bright lines requiring repair increases significantly. For example, in Figure 1, after the data line (SD) layer is fabricated, a broken data line (SD) is discovered. In this case, the broken data line (SD) can be repaired by bridging it using a bridge structure (BG) to restore the connection.

[0081] When the data line (SD) is bridged for repair, a parasitic capacitance exists between the pixel electrode (P) and the bridge structure (BG), as shown in Figure 2. The saturation potential of this parasitic capacitance is Vp1. The pixel electrode (P) is affected by the saturation potential Vp1 and its potential is pulled down. At this time, the potential Vpix of the pixel electrode (P) is not equal to the common potential Vcom, resulting in an electric field formed between the pixel electrode (P) and the common electrode (CF Com). The liquid crystal molecules are deflected by the electric field, causing the pixel to be abnormally illuminated due to the presence of the bridge structure (BG).

[0082] In some embodiments, as shown in FIG3 , the drain (D) of the transistor (TFT) is connected to the pixel electrode (P). When an abnormal bright spot defect is detected, the drain (D) of the transistor (TFT) can be disconnected and laser irradiation can be used to connect the pixel electrode (P) to the common electrode line (Ar Com) (as shown in FIG4 ). This ensures that the potential Vpix of the pixel electrode (P) is equal to the common potential Vcom, thereby achieving a pixel dark spot. However, as resolution continues to increase and pixel area becomes smaller, the space for bridge repair is becoming increasingly narrow. During the bridge film growth process, due to film sputtering / diffusion (as shown in FIG5 ), the bridge structure (BG) contacts the drain (D), causing the data line (SD) to connect to the pixel electrode (P) through the bridge structure (BG), the drain (D), and then the pixel electrode (P) (as shown in FIG6 ). When the dark spot action connects the pixel electrode (P) to the common electrode line (Ar Com), it also causes the data line (SD) to connect to the common electrode line (Ar Com), resulting in a bright line defect.

[0083] To solve the above technical problems, an embodiment of the present disclosure provides an array substrate. FIG7 is a schematic structural diagram of an array substrate provided by the present disclosure, specifically relating to three sub-pixels (i.e., one pixel) and the layout thereof; FIG8 is an enlarged structural diagram of a via hole and a pixel electrode in the Z1 region of FIG7; FIG9 is a schematic cross-sectional structural diagram along line II' of FIG7; and FIG10 to FIG14 are schematic diagrams of each single film layer in FIG7. As shown in FIG7 to FIG14, the array substrate provided by the embodiment of the present disclosure includes:

[0084] A base substrate 101, comprising a plurality of sub-pixel regions (e.g., a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region B) arranged in an array; optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like;

[0085] The first data line 102 extends along the first direction Y on the base substrate 101. The first data line 102 is a broken line including a break O. Optionally, the material of the first data line 102 may include a metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), or copper (Cu). The first data line 102 may have a single-layer structure or a stacked-layer structure. For example, the first data line 102 may have a stacked-layer structure consisting of a titanium metal layer / an aluminum metal layer / a titanium metal layer.

[0086] The bridge structure 103 is connected to the first data line 102 at both ends of the break O. Optionally, the bridge structure 103 and the first data line 102 are provided in the same layer. In some embodiments, the material of the bridge structure 103 can be the same as or different from that of the first data line 102. For example, the bridge structure 103 and the first data line 102 can both be made of copper, or the bridge structure 103 can be made of tungsten and the first data line 102 can be made of copper. Tungsten has better ductility and corrosion resistance than copper. Therefore, a bridge structure 103 made of tungsten has more stable performance and better repair effect.

[0087] A first transistor 104, wherein a first electrode S of the first transistor 104 is connected to the first data line 102. Optionally, the first electrode S of the first transistor 104 and the first data line 102 are integrally provided;

[0088] The first pixel electrode 105 is different from the related art in which the first pixel electrode 105 is connected to the second electrode D of the first transistor 104. In the present disclosure, the first pixel electrode 105 is insulated from the second electrode D of the first transistor 104. Optionally, the material of the first pixel electrode 105 may include transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO). The first electrode S of the first transistor 104 can be a source and the second electrode D can be a drain, or the first electrode S of the first transistor 104 can be a drain and the second electrode D can be a source.

[0089] In the present disclosure, the first pixel electrode 105 and the second electrode D of the first transistor 104 are insulated from each other, thereby preventing the bridge structure 103 from being connected to the first pixel electrode 105 through the second electrode D of the first transistor 104. Therefore, even if the bridge structure 103 is connected to the second electrode D of the first transistor 104 due to sputtering / diffusion or the like, it will not cause the first data line 102 to be connected to the first pixel electrode 105, thereby effectively preventing bright line defects.

[0090] It should be noted that the present disclosure is not only applicable to the above-mentioned poor bright line caused by the bridge repair of the first data line 102, but can also be applied to situations where there is insufficient space to perform the drain cutting operation, foreign matter causes the data line and the pixel electrode to be conductive, resulting in abnormal pixel lighting, and the common electrode line (Ar Com) is broken and the relevant technology cannot be used to short-circuit the common electrode line (Ar Com) and the pixel electrode to lower the pixel potential.

[0091] 9 , the bridge structure 103 may be connected to the second electrode D of the first transistor 104 due to sputtering / diffusion, etc. Of course, if the distance between the bridge structure 103 and the second electrode D of the first transistor 104 is large enough, the two may not be connected due to metal sputtering / diffusion, etc.

[0092] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 7 to 9 and Figures 12 to 14, an insulating layer 106 may also be included between the layer where the first data line 102 is located and the layer where the first pixel electrode 105 is located. Optionally, the insulating layer 106 includes a passivation layer (PVX), a color resist layer (RGB), a flat layer (ORG), etc.; according to the capacitance formula C = εs / (4πkd), it can be seen that the capacitance C is proportional to the area s and inversely proportional to the capacitor plate spacing d. The insulating layer 106 of the present disclosure includes the color resist layer (RGB) and the flat layer (ORG), so that the capacitor plate spacing d is larger, so the capacitance C is smaller, and the probability of abnormal lighting of pixels due to bridging is reduced (that is, the occurrence rate of capacitor bright spots is reduced). Continuing to refer to Figures 7 to 9 and Figures 12 to 14, it can be seen that the insulating layer 106 includes a via V, and the insulating layer 106 around the via V is arranged in contact with the second electrode D of the first transistor 104. In other words, the via V will expose a local area of ​​the second electrode D of the first transistor 104; the orthographic projection of the first pixel electrode 105 on the base substrate 101 and the orthographic projection of the via V on the base substrate 101 do not overlap with each other, so that the first pixel electrode 105 and the second electrode D of the first transistor 104 are insulated from each other.

[0093] Alternatively, the present disclosure may employ relevant techniques to first fabricate a first pixel electrode 105 connected to the second electrode D of the first transistor 104 via a via V, and then strip away the first pixel electrode 105 at the via V (illustratively, the dotted area in FIG8 and FIG9 represents the portion of the pattern where the first pixel electrode 105 is stripped away), thereby insulating the first pixel electrode 105 from the second electrode D. Alternatively, the first pixel electrode 105 may be directly fabricated without covering the via V to ensure that the first pixel electrode 105 is insulated from the second electrode D. Given that directly fabricating the first pixel electrode 105 without covering the via V requires the development of a new mask for the pixel electrode layer, which is costly, the present disclosure prefers the solution of stripping away the first pixel electrode 105 at the via V.

[0094] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG7 and FIG8 , the first pixel electrode 105 includes a relief portion 501, and the distance l between the orthographic projection of the relief portion 501 on the base substrate 101 and the orthographic projection of the via hole V on the base substrate 101 is greater than or equal to 4 μm. This ensures that the first pixel electrode 105 at the via hole V is completely peeled off, and prevents the first pixel electrode 105 from being shorted to the second electrode D of the first transistor 104 due to peeling residue. It should be understood that with advancements in technology, equipment, etc., the distance l between the orthographic projection of the relief portion 501 on the base substrate 101 and the orthographic projection of the via hole V on the base substrate 101 may be less than 4 μm.

[0095] In some embodiments, as shown in FIG7 and FIG8 , the avoidance portion 501 may be a recessed structure recessed away from the via hole V in the first direction Y. In other words, the avoidance portion 501 is located on the side of the via hole V facing the opening area OA and is recessed away from the via hole V along the first direction Y. Optionally, provided that the distance l between the orthographic projection of the avoidance portion 501 on the base substrate 101 and the orthographic projection of the via hole V on the base substrate 101 is greater than or equal to 4 μm, the avoidance portion 501 may be located within the non-opening area UOA or may overlap with the opening area OA as shown in FIG7 . Optionally, when the avoidance portion 501 overlaps with the opening area OA, the distance l between the orthographic projection of the avoidance portion 501 on the base substrate 101 and the orthographic projection of the via hole V on the base substrate 101 may be greater than or equal to 10 μm.

[0096] In some embodiments, as shown in Figures 15 and 16, the avoidance portion 501 can also be a protruding structure protruding toward the via hole V in the first direction Y, which is equivalent to the avoidance portion 501 being located on the side of the via hole V toward the opening area OA, and protruding in the direction close to the via hole V in the first direction Y. Optionally, the avoidance portion 501 is located in the non-opening area UOA.

[0097] In some embodiments, as shown in Figures 12, 17 and 18, the avoidance portion 501 can also be an "L-shaped" notch structure facing the via V in the first direction Y and away from the first data line 102 in the second direction X, which is equivalent to the avoidance portion 501 being open on the side facing the via V in the first direction Y and the side away from the first data line 102 in the second direction X. Optionally, the avoidance portion 501 can extend from the non-opening area UOA to partially overlap with the opening area OA. At this time, the distance l between the orthographic projection of the avoidance portion 501 on the base substrate 101 and the orthographic projection of the via V on the base substrate 101 can be greater than or equal to 10μm.

[0098] In some embodiments, as shown in Figures 10, 19 and 20, a gate line 107 (GT) extending along the second direction X may also be included, and the avoidance portion 501 is a non-closed structure arranged around the via V on both sides of the via V extending along the first direction Y, and on the side of the via V extending along the second direction X and away from the gate line 107. In other words, the non-closed structure can be open only on the side facing the gate line 107. Optionally, the avoidance portion 501 is located in the non-opening area UOA, and the distance l between the orthographic projection of the avoidance portion 501 on the base substrate 101 and the orthographic projection of the via V on the base substrate 101 can be greater than or equal to 4μm.

[0099] In some embodiments, as shown in FIG10 , FIG21 , and FIG22 , the avoidance portion 501 is a closed structure that faces the via hole V in the first direction Y and is away from the gate line 107 in the second direction X. The closed structure may surround the via hole V on both sides extending along the first direction Y and on both sides extending along the second direction X. In other words, the orthographic projection of the via hole V on the base substrate 101 is located within the orthographic projection of the closed structure on the base substrate 101. Optionally, the via hole V and the avoidance portion 501 are located within the non-opening area UOA, and the orthographic projection of the via hole V on the base substrate 101 is retracted by more than 4 μm compared to the orthographic projection of the closed structure on the base substrate 101.

[0100] In some embodiments, as shown in Figures 23 and 24, the first pixel electrode 105 can be located in the opening area OA, and the via V can be located in the non-opening area UOA; optionally, a conductive pattern 108 is provided in the non-opening area UOA, which is provided in the same layer and material as the first pixel electrode 105, and the conductive pattern 108 covers and fills the via V. Optionally, in order to insulate the conductive pattern 108 from the first pixel electrode 105, thereby ensuring that the first pixel electrode 105 is insulated from the via V, the spacing L between the conductive pattern 108 and the first pixel electrode 105 in the first direction Y can be greater than or equal to 4μm. Optionally, the pattern of the first pixel electrode 105 in the opening area OA can be the shape shown in Figure 23, or the shape shown in Figures 7, 15, 17, 19, and 21, or other shapes, which are not specifically limited in this disclosure. In a specific implementation, the first pixel electrode 105 in the opening area OA is not connected to the first data line 102 and is a dark spot. Although the conductive pattern 108 is connected to the first data line 102 through the first transistor 104 and is a bright spot, the conductive pattern 108 will be blocked by the black matrix (BM) in the non-opening area UOA and will not affect the display quality.

[0101] The above is only an introduction to the first pixel electrode 105 that needs to be repaired due to the bridging of the first data line 102. It should be understood that, as shown in Figures 10 to 14, the present disclosure may also include a second pixel electrode 109 connected to the first data line 102 and not affected by the bridging, a second transistor 110 connecting the first data line 102 and the second pixel electrode 109, a second data line 111 that is produced synchronously with the first data line 102 and is not broken (that is, the second data line 111 is continuously arranged), a third pixel electrode 112 that is produced synchronously with the second pixel electrode 109 and connected to the second data line 111, and a third transistor 113 connecting the second data line 111 and the third pixel electrode 112. Alternatively, as shown in Figures 7 and 10 to 14, the first electrode S of the second transistor 110 is integrally provided with the first data line 102, and the second electrode D of the second transistor 110 is connected to the second pixel electrode 109 via a via V; the first electrode S of the third transistor 113 is integrally provided with the second data line 111, and the second electrode D of the third transistor 113 is connected to the third pixel electrode 112 via a via V. The pattern of the second pixel electrode 109 is the same as the pattern of the third pixel electrode 112, and different from the pattern of the first pixel electrode 105. In some embodiments, a pattern identical to that of the second pixel electrode 109 and the third pixel electrode 112 can be first formed in the sub-pixel region where the first pixel electrode 105 is to be formed, and then the pattern within the short dotted line region shown in Figures 8, 16, 18, 20, 22, and 24 can be removed to obtain the first pixel electrode 105.

[0102] In some embodiments, as shown in FIG7, FIG10 and FIG14, a common electrode line 114 may be provided in the layer where the gate line 107 is located. The common electrode line 114 overlaps with the edges of the pixel electrodes (e.g., the first pixel electrode 105, the second pixel electrode 109, and the third pixel electrode 112) to form a storage capacitor (Cst).

[0103] Optionally, as shown in Figures 7, 10, 12 and 14, a shielding electrode 115 may also be provided in the layer where the pixel electrodes (for example, the first pixel electrode 105, the second pixel electrode 109, and the third pixel electrode 112) are located. The shielding electrode 115 covers the data lines (for example, the first data line 102 and the second data line 111) and the gate line 107 to reduce the electric field disorder caused by the coupling capacitance between the shielding data line and the pixel electrode, and between the gate line 107 and the pixel electrode, thereby reducing the influence of the coupling capacitance on the liquid crystal deflection and improving the crosstalk problem.

[0104] In some embodiments, as shown in Figures 7 and 11, the active layer AC of the transistor (for example, the first transistor 104, the second transistor 110, and the third transistor 113) can be made of one or more materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene.

[0105] Other essential components of the array substrate (such as the gate insulation layer 116 ) are well understood by those skilled in the art and are not described in detail herein and should not be construed as limiting the present disclosure.

[0106] Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing the above-mentioned array substrate. Since the principle of solving the problem by the manufacturing method is similar to the principle of solving the problem by the above-mentioned array substrate, the implementation of the manufacturing method substrate provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned array substrate provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0107] In some embodiments, the above-mentioned manufacturing method provided in the embodiment of the present disclosure, as shown in FIG25 , may include the following steps:

[0108] S2501, providing a substrate;

[0109] [Corrected 01.11.2024 according to Rule 91] S2502, patterning a first electrode and a second electrode of a first transistor and a first data line on a base substrate, wherein the first data line extends along a first direction and includes a break, and the first data line is connected to the first electrode of the first transistor;

[0110] S2503, forming a bridge structure by using a sputtering coating process, so as to connect the first data lines at both ends of the fracture by using the bridge structure;

[0111] S2504 , patterning a first pixel electrode on the layer where the first data line is located, the first pixel electrode being insulated from the second electrode of the first transistor.

[0112] In some embodiments, in the above-mentioned manufacturing method provided by the embodiments of the present disclosure, the base substrate includes a plurality of sub-pixel regions, and the sub-pixel regions include opening regions and non-opening regions;

[0113] After performing step S2503 of sputtering to form the bridge structure and before performing step S2504 of patterning to form the first pixel electrode, the following steps may be further performed:

[0114] An insulating layer having a via hole is formed by patterning. The via hole is located in the non-opening area, and the insulating layer around the via hole is in contact with the second electrode of the first transistor.

[0115] In some embodiments, the above step S2504 patterns the first pixel electrode on the layer where the first data line is located, and forms the first pixel electrode that is insulated from the second electrode of the first transistor. This can be achieved in the following two ways:

[0116] One implementation method is: patterning on the layer where the first data line is located to form a first pixel electrode covering the opening area and covering and filling the via in the non-opening area; at least removing the pattern of the first pixel electrode at the via to form an avoidance portion, and the distance between the orthographic projection of the avoidance portion on the base substrate and the orthographic projection of the via on the base substrate is greater than or equal to 4μm.

[0117] Another implementation method is: patterning on the layer where the first data line is located to form a pixel electrode pattern that covers the opening area and covers and fills the vias in the non-opening area; removing part of the pixel electrode pattern close to the non-opening area to form a first pixel electrode located in the opening area and a conductive pattern located in the non-opening area, and the spacing between the first pixel electrode and the conductive pattern in the first direction is greater than or equal to 4μm.

[0118] [Corrected 01.11.2024 according to Rule 91] In some embodiments, while executing the above-mentioned step S2502 to pattern the first electrode and the second electrode of the first transistor and the first data line, the first electrode and the second electrode of the second transistor, the first electrode and the second electrode of the third transistor, and a continuously arranged second data line can also be synchronously patterned, wherein the first electrode of the second transistor is connected to the first data line, and the second data line is connected to the first electrode of the third transistor; optionally, while executing step S2504 to pattern the first pixel electrode, the second pixel electrode connected to the second electrode of the second transistor and the third pixel electrode connected to the second electrode of the third transistor can also be synchronously patterned, and the pattern of the second pixel electrode is the same as the pattern of the third pixel electrode, for example, the patterns of the second pixel electrode and the third pixel electrode both cover the opening area and extend into the non-opening area to cover and fill the via.

[0119] Based on the same inventive concept, embodiments of the present disclosure provide a display panel, optionally a curved display panel. In some embodiments, as shown in Figures 26 and 27 , the display panel provided by embodiments of the present disclosure includes the aforementioned array substrate 001 provided by embodiments of the present disclosure, and an opposing substrate 002 disposed opposite array substrate 001.

[0120] In some embodiments, as shown in Figures 26 and 27, the opposing substrate 002 may include a substrate 200, a black matrix 201 and a spacer 202, the black matrix 201 is a grid structure, optionally, the data lines (for example, the first data line 102 and the second data line 111), the transistors (for example, the first transistor 104, the second transistor 110 and the third transistor 113), the gate line 107, and the conductive pattern 108 are located in the black matrix area, the spacer 202 is located on the side of the black matrix 201 facing the array substrate 001, and the orthographic projection of the spacer 202 on the base substrate 101 overlaps with the orthographic projection of the transistors (for example, the first transistor 104, the second transistor 110, the third transistor 113) on the base substrate 101.

[0121] In some embodiments, as shown in FIG27 , the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer 003 between an array substrate 001 and an opposing substrate 002. In some embodiments, a first polarizer 004 may be provided on a side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be provided on a side of the opposing substrate 002 away from the array substrate 001. The polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0122] In some embodiments, the above-mentioned display panel provided by the embodiments of the present disclosure can be applied to: displays, projectors, 3D printers, virtual reality devices, mobile phones, tablet computers, televisions, laptops, digital photo frames, navigators, smart watches, fitness wristbands, personal digital assistants, and any other products or components with display functions.

[0123] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0124] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A first data line extending along a first direction on the base substrate, wherein the first data line includes a break; a bridge structure connected to the first data lines at both ends of the break; a first transistor, wherein a first electrode of the first transistor is connected to the first data line; A first pixel electrode is provided, wherein the first pixel electrode and the second electrode of the first transistor are insulated from each other.

2. The array substrate according to claim 1, wherein: The bridge structure is connected to the second electrode of the first transistor.

3. The array substrate according to claim 1 or 2, wherein: It also includes an insulating layer located between the layer where the first data line is located and the layer where the first pixel electrode is located; The insulating layer includes a via hole, and the insulating layer around the via hole is arranged in contact with the second electrode of the first transistor; The orthographic projection of the first pixel electrode on the base substrate and the orthographic projection of the via hole on the base substrate do not overlap with each other.

4. The array substrate according to claim 3, wherein: The first pixel electrode includes a relief portion, and a distance between an orthographic projection of the relief portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than or equal to 4 μm.

5. The array substrate according to claim 4, wherein: The avoiding portion is a recessed structure that is recessed away from the via hole in the first direction.

6. The array substrate according to claim 4, wherein: The avoiding portion is a protruding structure protruding toward the via hole in the first direction.

7. The array substrate according to claim 4, wherein: The avoiding portion is a notch structure that faces the via hole in the first direction and is away from the first data line in a second direction, and the second direction intersects with the first direction.

8. The array substrate according to claim 4, wherein: It also includes a gate line extending along a second direction, and the avoidance portion is a non-closed structure arranged around the via on both sides of the via extending along the first direction, and on a side of the via extending in the second direction and away from the gate line, and the second direction intersects with the first direction.

9. The array substrate according to claim 4, wherein: It also includes a gate line extending along a second direction, the avoidance portion is a closed structure facing the via hole in the first direction and away from the gate line in the second direction, and the second direction intersects with the first direction.

10. The array substrate according to any one of claims 4 to 9, wherein: The base substrate includes a plurality of sub-pixel areas, and the sub-pixel areas include opening areas and non-opening areas; The via hole is located in the non-opening area; The avoidance portion is located in the non-opening area, or the avoidance portion partially overlaps with the non-opening area and the opening area respectively.

11. The array substrate according to claim 10, wherein: A distance between an orthographic projection of the avoidance portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than or equal to 10 μm.

12. The array substrate according to any one of claims 4 to 9, wherein: The base substrate includes a plurality of sub-pixel areas, and the sub-pixel areas include opening areas and non-opening areas; The first pixel electrode is located in the opening area, and the via hole is located in the non-opening area.

13. The array substrate according to claim 12, wherein: It also includes a conductive pattern arranged in the same layer as the first pixel electrode in the non-opening area, the distance between the conductive pattern and the first pixel electrode in the first direction is greater than or equal to 4μm, and the conductive pattern covers and fills the via hole.

14. The array substrate according to any one of claims 1 to 13, wherein: It also includes a second pixel electrode, a second transistor, a second data line, a third transistor and a third pixel electrode; wherein, A first electrode of the second transistor is connected to the first data line, a second electrode of the second transistor is connected to the second pixel electrode, and a pattern of the second pixel electrode is different from a pattern of the first pixel electrode; The second data lines are continuously arranged, connected to the first electrode of the third transistor, the third pixel electrode is connected to the second electrode of the third transistor, and the pattern of the third pixel electrode is the same as that of the second pixel electrode.

15. The array substrate according to any one of claims 1 to 14, wherein: The bridge structure is arranged in the same layer as the first data line, the first electrode and the second electrode of the first transistor.

16. A display panel, wherein: The invention comprises the array substrate according to any one of claims 1 to 15, and an opposite substrate arranged opposite to the array substrate.

17. [Corrected 01.11.2024 according to Rule 91] A method for manufacturing an array substrate, wherein: include: providing a substrate; Forming a first electrode and a second electrode of a first transistor and a first data line on the base substrate, wherein the first data line extends along a first direction and includes a break, and the first data line is connected to the first electrode of the first transistor; forming a bridge structure by a sputtering coating process, so as to connect the first data lines at both ends of the fracture by using the bridge structure; A first pixel electrode insulated from the second electrode of the first transistor is formed by patterning on the layer where the first data line is located.

18. The production method according to claim 17, wherein: The base substrate includes a plurality of sub-pixel areas, and the sub-pixel areas include opening areas and non-opening areas; After sputtering to form the bridge structure and before patterning to form the first pixel electrode, the method further includes: An insulating layer having a via hole is patterned, wherein the via hole is located in the non-opening area, and the insulating layer around the via hole is in contact with the second electrode of the first transistor.

19. The production method according to claim 18, wherein: Patterning a first pixel electrode on the layer where the first data line is located and insulated from the second electrode of the first transistor specifically includes: Patterning a first pixel electrode on the layer where the first data line is located to cover the opening area and to cover and fill the via hole in the non-opening area; At least the pattern of the first pixel electrode at the via hole is removed to form a relief portion, and a distance between an orthographic projection of the relief portion on the base substrate and an orthographic projection of the via hole on the base substrate is greater than or equal to 4 μm.

20. The production method according to claim 18, wherein: Patterning a first pixel electrode on the layer where the first data line is located and insulated from the second electrode of the first transistor specifically includes: Patterning a pixel electrode pattern on the layer where the first data line is located to cover the opening area and to cover and fill the via hole in the non-opening area; A portion of the pixel electrode pattern close to the non-opening area is removed to form a first pixel electrode located in the opening area and a conductive pattern located in the non-opening area, wherein a distance between the first pixel electrode and the conductive pattern in the first direction is greater than or equal to 4 μm.

21. [Corrected 01.11.2024 according to Rule 91] A method according to any one of claims 17 to 20, wherein: While patterning and forming the first electrode and the second electrode of the first transistor and the first data line, the method further includes: Patterning a first electrode and a second electrode of a second transistor, a first electrode and a second electrode of a third transistor, and a second data line arranged continuously, wherein the first data line is connected to the first electrode of the second transistor, and the second data line is connected to the first electrode of the third transistor; While composing to form the first pixel electrode, it also includes: composing to form a second pixel electrode connected to the second electrode of the second transistor, and a third pixel electrode connected to the second electrode of the third transistor, and the pattern of the second pixel electrode is the same as the pattern of the third pixel electrode.

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