Resistive memory element and preparation method therefor

Abstract

Provided are a resistive memory element and a preparation method therefor. The resistive memory element comprises: a lower electrode and an upper electrode, wherein a resistive layer (4) is disposed between the upper electrode and the lower electrode; and a recessed hole is formed in the upper electrode, the recessed hole is filled with oxide dielectric (53), the oxide dielectric (53) filling the recessed hole for planarization. The upper electrode may be of a single-layer structure; in this case, the recessed hole is formed in an upper surface of the upper electrode, and by performing chemical mechanical polishing on an oxide dielectric layer deposited on the upper surface of the upper electrode and stopping at the upper surface of the upper electrode, the oxide dielectric can fill the recessed hole for planarization. The upper electrode may comprise a first upper electrode layer (52) and a second upper electrode layer (54); in this case, the recessed hole is formed in an upper surface of the first upper electrode layer (52), and by performing chemical mechanical polishing on the oxide dielectric layer formed on the first upper electrode layer (52) and stopping at the upper surface of the first upper electrode layer (52), the oxide dielectric can fill the recessed hole for planarization. The resistive memory element and the preparation method therefor can solve the problem of voids easily forming in the structure of each layer in a resistive memory.

Description

Resistive memory element and preparation method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese patent application number 202410241380.1, filed on March 4, 2024, entitled “Resistive Memory Element and Method for Making the Same”. Technical Field

[0002] The disclosed embodiments relate to the field of semiconductor technology, and more specifically, to a resistive memory element and a method for preparing the same. Background Art

[0003] Currently, most existing ReRAM (resistive random access memory) structures use a MIM structure (i.e., a structure with a dielectric material sandwiched between two layers of metal electrodes). The upper and lower electrodes are both metal plates, with a resistive switching layer in the middle. The traditional manufacturing process for this MIM ReRAM structure generally involves depositing a dielectric layer on a copper metal substrate, performing masked photolithography and etching, depositing the lower electrode metal layer, and chemically polishing it. Subsequently, a resistive switching layer is deposited on the lower electrode metal layer, followed by depositing an upper electrode metal layer on the resistive switching layer. Finally, masking and etching the upper electrode metal layer are performed on the upper electrode metal layer, thus forming the entire RRAM (resistive random access memory) device.

[0004] However, the transmission fabrication process for this MIM-structured ReRAM presents a series of challenges. For example, metal residue on the RRAM sidewalls from etching the top electrode can easily lead to leakage; the top electrode needs to be cleaned after etching, but current cleaning solutions are not very compatible with RRAM materials (especially the top electrode), which can easily cause undercutting of the top electrode, affecting the RRAM's electrical uniformity and reliability; and the lack of concentration of conductive filaments can lead to high Vform (device voltage).

[0005] To solve the above-mentioned technical problems, those skilled in the art have proposed corresponding improved processes. The specific improved process scheme is shown in Figure 1 and includes the following steps: first, a portion of the lower electrode (BE film 1, the first layer of the lower electrode 2') is prepared on a copper metal substrate 1' by thin film deposition, photolithography, etching, thin film deposition, chemical mechanical polishing and other processes, followed by thin film deposition of a portion of the lower electrode (BE film 2, the second layer of the lower electrode) 3' and a resistive layer 4' (SL). The entire process corresponds to the first step in Figure 1; then, an upper electrode layer 5' and a mask layer 6' are deposited on the resistive layer and corresponding photolithography and etching are performed; then, a sidewall layer 7' is deposited above the mask layer and on the resistive layer; finally, the sidewall layer is deposited accordingly and the mask layer and the upper electrode are etched and cleaned accordingly to complete the entire RRAM preparation.

[0006] Although the aforementioned improved process solves the aforementioned technical problem by dividing the bottom electrode into two parts (BE film 1 and BE film 2) and performing deposition and etching separately, this improvement solution also introduces certain risks. Specifically, since the via CD (feature dimension of the through hole) of BE film 2 cannot be too large, certain voids 8' (as shown in FIG. 2 ) are easily formed in the RRAM during the subsequent deposition of the HM film / SPA film (mask layer or top electrode layer). This leads to the risk of eating through the RRAM film (resistive memory layer structure) during the copper connection line etching process (using AIO ET, a back-end integrated etching process) (as shown in the last step in FIG. 2 ), ultimately causing RRAM leakage.

[0007] In view of this situation, there is an urgent need for a method that can effectively prevent the formation of voids in the resistive memory layer structure. Summary of the Invention

[0008] In view of the above problems, the purpose of the present disclosure is to provide a novel resistive memory element and a method for manufacturing the same, so as to solve the problem that voids are easily formed in the resistive memory layer structure.

[0009] The resistive memory element provided by the disclosed embodiment includes a lower electrode and an upper electrode, a resistive switching layer is provided between the upper electrode and the lower electrode, a concave hole is formed on the upper electrode, and an oxide medium is filled in the concave hole; and the oxide medium fills the concave hole.

[0010] In addition, a preferred solution is that the lower electrode includes a first lower electrode layer and a second lower electrode layer disposed on the first lower electrode layer, and the resistive layer is disposed between the second lower electrode layer and the upper electrode.

[0011] In addition, a preferred solution is that a sidewall is provided on the sidewall of the upper electrode facing away from the resistive memory element, and the sidewall covers the sidewall of the upper electrode.

[0012] In addition, a preferred solution is that an upper electrode hard mask layer is provided on the upper electrode, and the sidewall spacer covers the sidewall of the upper electrode hard mask layer.

[0013] In addition, a preferred solution is that the material of the second layer of the lower electrode includes tungsten.

[0014] In addition, a preferred solution is that the material of the upper electrode includes at least one of TiN, AlN, Ti, W, Ru, Ir, Ni, Pt, Cu, Ag, Au, and Al.

[0015] In addition, a preferred solution is that the upper electrode is a single-layer structure, the concave hole is formed on the upper surface of the upper electrode, the concave hole is filled with an oxide medium, and the oxide medium fills the upper surface of the upper electrode.

[0016] In addition, a preferred solution is that the upper electrode includes a first upper electrode layer arranged on the resistive layer and a second upper electrode layer arranged on the first upper electrode layer; wherein the concave hole is formed on the upper surface of the first upper electrode layer, and the concave hole is filled with an oxide medium, and the oxide medium fills the upper surface of the first upper electrode layer.

[0017] In addition, a preferred solution is that the first upper electrode layer and the second upper electrode layer contain at least one same material; or, the material contained in the first upper electrode layer and the material contained in the second upper electrode layer are different.

[0018] In addition, it is preferred that the material of the oxide medium includes silicon oxide.

[0019] On the other hand, the disclosed embodiment also provides a method for preparing a resistive memory element as described above, the preparation method comprising: sequentially preparing a lower electrode first layer, a lower electrode second layer, a resistive switching layer, and an upper electrode on a copper substrate; wherein a recess is formed on the upper electrode; depositing an oxide dielectric layer on the upper electrode; chemically and mechanically polishing the oxide dielectric layer so that the oxide dielectric fills the recess; preparing a mask layer on the upper electrode, and preparing a sidewall layer.

[0020] In addition, a preferred solution is that the upper electrode is a single-layer structure, and the preparation method includes: sequentially preparing a lower electrode first layer, a lower electrode second layer, a resistive layer and an upper electrode on a copper substrate; wherein a concave hole is formed on the upper surface of the upper electrode; depositing an oxide dielectric layer on the upper electrode; wherein the oxide dielectric layer covers the upper surface of the upper electrode; chemically mechanically polishing the oxide dielectric layer and stopping it on the upper surface of the upper electrode; wherein the concave hole is filled with an oxide dielectric, and the oxide dielectric fills the upper surface of the upper electrode; preparing a mask layer on the upper electrode, and preparing a sidewall layer.

[0021] In addition, a preferred solution is that the upper electrode has a double-layer structure, and the preparation method includes: sequentially preparing a lower electrode first layer, a lower electrode second layer, a resistive switching layer and an upper electrode first layer on a copper substrate; wherein a concave hole is formed on the upper surface of the upper electrode first layer; depositing an oxide dielectric layer on the upper electrode first layer; wherein the oxide dielectric layer covers the upper surface of the upper electrode first layer; chemically mechanically polishing the oxide dielectric layer and stopping on the upper surface of the upper electrode first layer; wherein the concave hole is filled with an oxide dielectric, and the oxide dielectric fills the upper surface of the upper electrode first layer; sequentially preparing an upper electrode second layer and a mask layer on the upper electrode first layer, and preparing a sidewall layer.

[0022] In addition, a preferred solution is to sequentially prepare the upper electrode second layer and the mask layer on the upper electrode first layer, and the process of preparing the sidewall layer includes: sequentially depositing the upper electrode second layer and the mask layer on the upper electrode first layer, photolithography and etching the upper electrode hard mask layer, the upper electrode first layer, the upper electrode second layer and the resistive layer, and making the lowest point of etching stay above the lower electrode second layer; depositing the sidewall layer on the upper electrode hard mask layer so that the sidewall layer covers the upper electrode hard mask layer, the upper electrode first layer, the upper electrode second layer and the sidewall of the resistive layer; etching the sidewall layer and the lower electrode first layer so that the sidewall layer forms a sidewall outside the sidewall of the resistive layer, the upper electrode first layer and the upper electrode second layer.

[0023] In addition, a preferred solution is that after the sidewalls are manufactured, the step further includes: processing the mask layer and the second layer of the upper electrode using a back-end integrated etching process.

[0024] Compared with the prior art, the resistive memory element and the method for manufacturing the same according to the embodiments of the present disclosure have the following beneficial effects:

[0025] In the existing resistive memory fabrication process, during the deposition of the resistive memory layer structure, due to the structural influence of the lower electrode second layer, a recessed hole is formed on the upper surface of the upper electrode first layer. The resistive memory element and its fabrication method provided in the disclosed embodiments use oxide deposition and oxide chemical mechanical polishing processes to fill the recessed hole on the upper surface of the upper electrode first layer with an oxide dielectric layer. During the subsequent deposition of the upper electrode second layer and the mask layer, no voids are formed within the resistive memory layer structure, thereby avoiding the risk of RRAM being eaten through during the subsequent AIO etching (back-end integrated etching process).

[0026] To achieve the above and related purposes, one or more aspects of the present disclosure include features that will be described in detail below and particularly pointed out in the claims. The following description and the accompanying drawings set forth certain exemplary aspects of the present disclosure in detail. However, these aspects are merely indicative of the various ways in which the principles of the present disclosure may be employed. Furthermore, the present disclosure is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present disclosure, other objects and results of the present disclosure will become more apparent and readily understood. In the accompanying drawings:

[0028] FIG1 is a flow chart of a conventional RRAM preparation process without generating voids;

[0029] FIG2 is a flow chart of a conventional RRAM preparation process in the case of void generation;

[0030] FIG3 is a flow chart of a process for preparing a resistive memory element according to an embodiment of the present disclosure when the upper electrode has a single-layer structure;

[0031] FIG4 is a flow chart of a process for preparing a resistive memory element according to an embodiment of the present disclosure when the upper electrode has a double-layer structure;

[0032] Reference numerals: copper substrate 1 , lower electrode first layer 2 , lower electrode second layer 3 , resistive switching layer 4 , first dielectric layer 51 , upper electrode first layer 52 , oxide dielectric 53 , upper electrode second layer 54 , mask layer 6 , sidewall 7 .

[0033] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0034] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0035] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or components referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as limiting the present disclosure; the terms "first", "second", and "third" are only used for descriptive purposes and should not be understood as indicating or implying relative importance; in addition, unless otherwise expressly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or it can be internal communication between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0036] Before introducing in detail the structure of the resistive memory element and its preparation method provided by the embodiments of the present disclosure, a brief introduction to RRAM is required. Resistive random access memory (RRAM) is a non-volatile memory based on the reversible conversion of the resistance of non-conductive materials between a high resistance state and a low resistance state under the action of an external electric field. As an important electronic component of a resistive random access memory chip, the resistance of the memristor changes with the level of the applied voltage. Compared with other non-volatile storage technologies, RRAM is a high-speed memory. The obstacle that engineers encountered on the road to the intensive research and development of memristor technology is precisely the stealth path of resistive random access memory (RRAM).

[0037] The structure of the resistive memory element provided by the present disclosure and its preparation process are described in detail below. FIG3 shows the process of preparing the resistive memory element according to an embodiment of the present disclosure.

[0038] As can be seen from the last step diagram in Figure 3, the resistive memory element provided by the embodiment of the present disclosure mainly includes a copper substrate 1 for supporting the main structure of RRAM, a lower electrode arranged on the copper substrate 1, a resistive layer 4 arranged on the lower electrode, and an upper electrode arranged on the resistive layer 4, wherein the resistive layer 4 is arranged between the upper electrode and the lower electrode, a concave hole is formed on the upper electrode, and an oxide medium is filled in the concave hole; and the oxide medium fills the concave hole.

[0039] Specifically, the upper electrode can be configured as a double-layer structure or a single-layer structure. When the upper electrode has a double-layer structure, the upper electrode includes a first upper electrode layer 52 disposed on the resistive layer 4 and a second upper electrode layer 54 disposed on the first upper electrode layer 52. The lower electrode includes a first lower electrode layer 2 and a second lower electrode layer 3 disposed on the first lower electrode layer 2. The first lower electrode layer 2 is disposed on the copper substrate 1, and the resistive layer 4 is disposed between the second lower electrode layer 3 and the first upper electrode layer 52. When the upper electrode has a single-layer structure, the resistive layer 4 is directly disposed between the second lower electrode layer 3 and the upper electrode.

[0040] It should be noted that for the resistive memory element, since the characteristic size of the through hole of the second layer 3 of the lower electrode is certain and cannot be too large, during the actual preparation process, a concave hole corresponding to the through hole of the second layer 3 of the lower electrode will be formed on the upper surface of the first layer 52 of the upper electrode. Due to the existence of the concave hole, it is easy to cause certain voids to be formed in the entire resistive memory element layer structure, resulting in the risk of eating through the RRAM film in the subsequent back-end integrated etching process, and ultimately causing RRAM leakage.

[0041] To solve this technical problem, the solution provided in the embodiment of the present disclosure fills the concave hole with an oxide medium 53 (such as silicon oxide) through oxide deposition and oxide chemical mechanical polishing processes, and makes the oxide medium 53 fill the concave hole on the upper surface of the first layer 52 of the upper electrode, so as to avoid the subsequent deposition process of the second layer 54 of the upper electrode. The concave hole will still appear, thereby avoiding the risk of RRAM being eaten through during the subsequent back-end integrated AIO etching process.

[0042] Furthermore, to prevent metal from splashing back onto the upper electrode during the etching process of the lower electrode second layer 3 and thus affecting the electrical properties of the RRAM, the resistive memory element provided in the disclosed embodiments can be provided with a sidewall spacer 7 on the sidewalls of the upper electrode, and the sidewall spacer 7 is formed before the etching process of the lower electrode second layer 3. With this configuration, the sidewall spacer 7 can block the splashing metal during the etching process of the lower electrode second layer 3, preventing the splashing metal from contacting the upper electrode, thereby ensuring the electrical performance of the RRAM.

[0043] For RRAM, in order to realize its electrical characteristics, it is usually necessary to set a resistive switching layer 4 between the upper electrode and the lower electrode (i.e., between the lower electrode second layer 3 and the upper electrode first layer 52) to achieve the desired resistance switching effect.

[0044] In addition, in order to protect the upper electrode, a mask layer 6 may be provided above the upper electrode second layer 54 , and the sidewalls 7 may cover the sidewalls of the mask layer 6 .

[0045] Specifically, in order to improve the electrical performance of RRAM, under normal circumstances, the upper electrode and the lower electrode are both arranged into a double-layer structure, that is, the upper electrode includes an upper electrode first layer 52 arranged on the resistive layer 4 and an upper electrode second layer 54 arranged on the upper electrode first layer 52; the lower electrode includes a lower electrode first layer 2 arranged on the copper substrate 1 and a lower electrode second layer 3 arranged on the lower electrode first layer 2, a concave hole is formed on the upper surface of the upper electrode first layer, and the concave hole is filled with an oxide medium, and the oxide medium fills the upper surface of the upper electrode first layer.

[0046] Of course, the upper electrode can also be set as a single-layer structure, that is, the upper electrode only includes a layer structure set on the resistive layer 4, a concave hole is formed on the upper surface of the upper electrode, and the concave hole is filled with an oxide medium, and the oxide medium fills the upper surface of the upper electrode.

[0047] It should be noted that the material of the top electrode is typically selected from at least one of TiN, AlN, Ti, W, Ru, Ir, Ni, Pt, Cu, Ag, Au, and Al, with TiN and AlN being preferred. The top electrode first layer 52 and the top electrode second layer 54 may contain at least one of the same material. Alternatively, the material contained in the top electrode first layer 52 and the material contained in the top electrode second layer 54 are different, that is, the top electrode first layer 52 and the top electrode second layer 54 may be made of the same or different materials. Furthermore, the bottom electrode first layer 2 and the bottom electrode second layer 3 may also be made of the same or different materials. For example, the bottom electrode second layer 3 is typically configured as a tungsten film layer to achieve the desired electrical effect. The top electrode first layer 52 is typically made of AlN (aluminum nitride), and the top electrode second layer 54 is typically made of TIN (titanium nitride). Of course, the selection of materials for the top electrode first layer 52, the top electrode second layer 54, the bottom electrode first layer 2, and the bottom electrode second layer 3 is not limited here as long as they can meet the corresponding electrical properties.

[0048] To explain in detail how the resistive memory element and its preparation process provided by the present disclosure avoid the generation of voids in the RRAM layer structure, the preparation method of the resistive memory element provided by the present disclosure is described in detail below.

[0049] As shown in FIG3 , the method for preparing the resistive memory element provided in the embodiment of the present disclosure includes:

[0050] A lower electrode first layer 2, a lower electrode second layer 3, a resistive switching layer 4 and an upper electrode are sequentially prepared on a copper substrate; wherein a concave hole is formed on the upper electrode;

[0051] depositing an oxide dielectric layer on the upper electrode;

[0052] Performing chemical mechanical polishing on the oxide dielectric layer so that the oxide dielectric 53 fills the concave hole;

[0053] A mask layer is prepared on the upper electrode, and a sidewall layer is prepared.

[0054] Specifically, when the upper electrode is a single-layer structure, the preparation method includes:

[0055] A lower electrode first layer 2, a lower electrode second layer 3, a resistive switching layer 4 and an upper electrode are sequentially prepared on a copper substrate 1; wherein a concave hole is formed on the upper surface of the upper electrode;

[0056] Depositing an oxide dielectric layer on the upper electrode; wherein the oxide dielectric layer covers the upper surface of the upper electrode;

[0057] The oxide dielectric layer is chemically and mechanically polished and stops at the upper surface of the upper electrode; wherein the concave hole is filled with the oxide dielectric, and the oxide dielectric fills the upper surface of the upper electrode;

[0058] A mask layer is prepared on the upper electrode, and a sidewall layer is prepared.

[0059] Specifically, when the upper electrode has a double-layer structure, the preparation method includes:

[0060] A lower electrode first layer 2, a lower electrode second layer 3, a resistive switching layer 4 and an upper electrode first layer 52 are sequentially prepared on a copper substrate 1; wherein a concave hole is formed on the upper surface of the upper electrode first layer 52;

[0061] Depositing an oxide dielectric layer on the first upper electrode layer 52; wherein the oxide dielectric layer 53 covers the upper surface of the first upper electrode layer 52;

[0062] The oxide dielectric layer 53 is chemically mechanically polished and stops at the upper surface of the first upper electrode layer 52; wherein the concave hole is filled with the oxide dielectric 53, and the oxide dielectric 53 fills the upper surface of the first upper electrode layer 52;

[0063] The second upper electrode layer 54 and the mask layer 6 are sequentially formed on the first upper electrode layer 52 , and the sidewall spacer 7 is also formed.

[0064] Through the above steps of the method for preparing a resistive memory element provided by the embodiment of the present disclosure, it can be seen that, based on the original RRAM preparation process route, the embodiment of the present disclosure improves the process. During the deposition of the RRAM film (the layer structure of the resistive memory), due to the influence of the structure of the second layer 3 of the lower electrode, there will be concave holes on the surface of the first layer 52 of the upper electrode. Through oxide deposition and oxide chemical mechanical polishing processes, the oxide dielectric layer 53 is used to fill the ALN concave holes. During the subsequent deposition of the second layer 54 of the upper electrode and the mask layer 6, no voids are formed in the layer structure of the resistive memory, thereby avoiding the risk of the resistive memory being eaten through during the subsequent back-end integrated etching process.

[0065] Specifically, under normal circumstances, an upper electrode hard mask layer 6 needs to be set on the upper electrode. Therefore, after the lower electrode second layer 3, the resistive layer 4, the upper electrode first layer 52 and the upper electrode second layer 54 are deposited in sequence on the lower electrode first layer 2, a mask layer 6 needs to be deposited on the upper electrode second layer 54.

[0066] Furthermore, the process of sequentially preparing the upper electrode second layer 54 and the mask layer 6 on the upper electrode first layer 52 and preparing the sidewall spacer 7 may include:

[0067] The second upper electrode layer 54 and the mask layer 6 are sequentially deposited on the first upper electrode layer 52.

[0068] Performing photolithography and etching on the upper electrode hard mask layer 6, the upper electrode first layer 52, the upper electrode second layer 54, and the resistive layer 4, and making the lowest etching point stay above the lower electrode second layer 3;

[0069] Depositing a sidewall spacer 7 on the top electrode hard mask layer 6 so that the sidewall spacer 7 covers the top electrode hard mask layer 6, the top electrode first layer 52, the top electrode second layer 54 and the sidewall of the resistive layer 4;

[0070] The sidewall spacer 7 and the lower electrode first layer 2 are etched to form a sidewall spacer 7 outside the sidewalls of the resistive layer 4 , the upper electrode first layer 52 and the upper electrode second layer 54 .

[0071] In addition, after the sidewall 7 is manufactured, the following steps may be performed: the mask layer 6 and the second upper electrode layer 54 are processed using a back-end integrated etching process.

[0072] It can be seen from the above specific embodiments that the resistive memory element and the preparation method thereof provided in the disclosed embodiment can ensure that no voids are introduced into the RRAM layer structure due to the structure of the second layer 3 of the lower electrode by introducing oxide dielectric layer deposition and oxide dielectric layer chemical mechanical polishing processes, thereby avoiding the problem of eating through the RRAM during the AIO etching process, resulting in RRAM leakage or even failure, and improving process controllability.

[0073] The resistive memory element and its preparation method according to the present disclosure are described above by way of example with reference to FIG3 and FIG4 . However, those skilled in the art will appreciate that various improvements may be made to the resistive memory element and its preparation method proposed in the present disclosure without departing from the scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the contents of the appended claims.

Claims

1. A resistive memory element, comprising a lower electrode and an upper electrode, wherein a resistive switching layer is provided between the upper electrode and the lower electrode, wherein: A concave hole is formed on the upper electrode, and an oxide medium is filled in the concave hole; and The oxide medium fills the concave holes.

2. The resistive memory element according to claim 1, wherein The lower electrode includes a first lower electrode layer and a second lower electrode layer arranged on the first lower electrode layer, and the resistive layer is arranged between the second lower electrode layer and the upper electrode.

3. The resistive memory element according to claim 2, wherein: A sidewall is provided on a sidewall of the upper electrode facing away from the resistive memory element, and the sidewall covers the sidewall of the upper electrode.

4. The resistive memory element according to claim 3, wherein: An upper electrode hard mask layer is provided on the upper electrode, and the sidewall spacer covers the sidewall of the upper electrode hard mask layer.

5. The resistive memory element according to claim 4, wherein: The material of the second layer of the lower electrode includes tungsten.

6. The resistive memory element according to any one of claims 1 to 5, wherein: The material of the upper electrode includes at least one of TiN, AlN, Ti, W, Ru, Ir, Ni, Pt, Cu, Ag, Au, and Al.

7. The resistive memory element according to claim 6, wherein: The upper electrode is a single-layer structure. The concave hole is formed on the upper surface of the upper electrode. The concave hole is filled with an oxide medium, and the oxide medium fills the upper surface of the upper electrode.

8. The resistive memory element according to claim 6, wherein: The upper electrode includes a first upper electrode layer provided on the resistive layer and a second upper electrode layer provided on the first upper electrode layer; wherein, The concave hole is formed on the upper surface of the first layer of the upper electrode. The concave hole is filled with an oxide medium, and the oxide medium fills the upper surface of the first layer of the upper electrode.

9. The resistive memory element according to claim 8, wherein The first upper electrode layer and the second upper electrode layer contain at least one same material; or, the material contained in the first upper electrode layer and the material contained in the second upper electrode layer are different.

10. The resistive memory element according to claim 1, wherein The material of the oxide medium includes silicon oxide.

11. A method for preparing a resistive memory element according to any one of claims 1 to 10, characterized in that: The preparation method comprises: A lower electrode first layer, a lower electrode second layer, a resistive switching layer and an upper electrode are sequentially prepared on a copper substrate; wherein a concave hole is formed on the upper electrode; depositing an oxide dielectric layer on the upper electrode; performing chemical mechanical polishing on the oxide dielectric layer so that the oxide dielectric fills the concave hole; A mask layer is prepared on the upper electrode, and a sidewall layer is prepared.

12. The method for preparing a resistive memory element according to claim 11, wherein: The upper electrode has a single-layer structure, and the preparation method includes: A lower electrode first layer, a lower electrode second layer, a resistive switching layer and an upper electrode are sequentially prepared on a copper substrate; wherein a concave hole is formed on the upper surface of the upper electrode; Depositing an oxide dielectric layer on the upper electrode; wherein the oxide dielectric layer covers the upper surface of the upper electrode; The oxide dielectric layer is subjected to chemical mechanical polishing and stops at the upper surface of the upper electrode; wherein the concave hole is filled with an oxide dielectric, and the oxide dielectric fills the upper surface of the upper electrode; A mask layer is prepared on the upper electrode, and a sidewall layer is prepared.

13. The method for preparing a resistive memory element according to claim 11, wherein: The upper electrode has a double-layer structure, and the preparation method includes: A lower electrode first layer, a lower electrode second layer, a resistive switching layer, and an upper electrode first layer are sequentially prepared on a copper substrate; wherein a concave hole is formed on the upper surface of the upper electrode first layer; Depositing an oxide dielectric layer on the first upper electrode layer; wherein the oxide dielectric layer covers the upper surface of the first upper electrode layer; The oxide dielectric layer is subjected to chemical mechanical polishing and stops at the upper surface of the first upper electrode layer; wherein the concave hole is filled with an oxide dielectric, and the oxide dielectric fills the upper surface of the first upper electrode layer; The second upper electrode layer and the mask layer are sequentially prepared on the first upper electrode layer, and the sidewall layer is also prepared.

14. The method for preparing a resistive memory element according to claim 13, wherein: The process of sequentially preparing the second upper electrode layer and the mask layer on the first upper electrode layer and preparing the sidewall layer includes: Depositing a second upper electrode layer and a mask layer in sequence on the first upper electrode layer; Performing photolithography and etching on the upper electrode hard mask layer, the upper electrode first layer, the upper electrode second layer, and the resistive layer, and making the lowest etching point stay above the lower electrode second layer; Depositing a spacer layer on the upper electrode hard mask layer so that the spacer layer covers the upper electrode hard mask layer, the upper electrode first layer, the upper electrode second layer and the sidewall of the resistive switching layer; The sidewall spacer layer and the first lower electrode layer are etched so that the sidewall spacer layer forms sidewalls outside the sidewalls of the resistive layer, the first upper electrode layer, and the second upper electrode layer.

15. The method for preparing a resistive memory element according to claim 14, wherein: After the side wall is manufactured, the method further includes: The mask layer and the second upper electrode layer are processed using a back-end integrated etching process.

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