Optoelectronic device and method for manufacturing an optoelectronic device

Abstract

The invention concerns an optoelectronic device, in particular µLED, comprising a semiconductor layer stack of at least a first layer of a first conductivity type, a second layer of a second conductivity type as well as an active region between the first and second layer. The semiconductor layer stack comprises bottom surface and a light emitting surface opposite the bottom surface, a first side wall portion extending from the bottom surface into the direction of the light emitting surface until a level between the active region and the light emitting surface, a second side wall portion extending from a level between the active region and the light emitting surface until the light emitting surface, and a plateau connecting the first and second side wall portion. The optoelectronic device further comprises a material layer covering at least portions of the first side wall portion, a first contact element arranged on the bottom surface and electrically contacting the second layer, and a second contact element arranged on the plateau and electrically contacting the first layer.

Description

[0001] OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC

[0002] DEVICE

[0003] The present application claims priority from German patent application DE 10 2024 106 528.1 filed on March 07, 2024, the disclosure of which is incorporated by way for reference in its entirety.

[0004] The present invention concerns an optoelectronic device, in particular pLED, in a flip chip configuration. The present invention further concerns a method for manufacturing such an optoelectronic device .

[0005] BACKGROUND pLEDs are optoelectronic devices that comprise a lateral dimension in the range from a few pm to about 40 pm. Such devices provide a variety of different applications, including but not limited to displays .

[0006] They are usually processed in arrays of several thousands of devices, and subsequently transferred from their growth substrate or an intermediate carrier to a target substrate (e.g. display backplane) . To date optoelectronic devices and in particular p-LEDs are manufactured in such a way that the finished devices can be transferred to a driver substrate (e.g. display backplane) by a respective transfer process (e.g. stamping, LIFT, ... ) . If a subsequent processing of the devices on backplane level, for example electrically contacting a top contact, is to be avoided, optoelectronic devices in a flip chip configuration (horizontal pLEDs) are necessary, which have both electric contacts (p and n) on the same side of the device.

[0007] However, the space consumption of e.g. horizontal pLEDs on a production wafer is larger, while comparable vertical pLEDs can be designed smaller and thus consume less material of an expensive production wafer. This is due to the fact that the provision of both contacts on the same side of the pLED requires more space for known horizontal pLEDs , which means that more expensively grown semiconductor material has to be removed .

[0008] It is thus an obj ect of the present application to provide an enhanced optoelectronic device , in particular pLED, in a flip chip configuration, as well as an enhanced method for manufacturing such an optoelectronic device , which overcomes at least some of aforementioned aspects .

[0009] SUMMARY OF THE INVENTION

[0010] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0011] The core of the invention is to provide a method for manufacturing optoelectronic devices , in particular pLEDs , as well as an optoelectronic device that is horizontally contactable but still consumes as less space as possible of the material of its production wafer . The optoelectronic device therefore comprises a contact nose protruding of the core of its semiconductor layer stack, which forms a plateau on which a second contact element is arranged that is contactable from the same side as a first contact element arranged on the core of the semiconductor layer stack . In particular, the contact nose is made of the same material as a layer of the semiconductor layer stack and protrudes from the core of the semiconductor layer stack, so that a plurality of such optoelectronic devices can be arranged opposite one another in an interlocking manner during their manufacture , but at a distance from one another and thus in a particularly space-saving manner .

[0012] A key aspect lies in the interaction of several process and design features such as for example : a contact nose protruding of the core of the semiconductor layer stack of an optoelectronic device , to form a plateau on which a contact element is arranged; horizontal contactable orientation of contact pads , so that the optoelectronic device can directly be transferred using e . g . a LI FT process ; a mirror around the remaining semiconductor layer stack structure ( optical cavity) ; and arrangement of semiconductor layer stack portions on production wafer opposite one another in an interlocking manner, but at a distance from one another (particularly space-saving ) .

[0013] According to a first aspect an optoelectronic device , in particular pLED, is provided . The optoelectronic device comprises a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and the second layer . The semiconductor layer stack further comprises a bottom surface and a light emitting surface opposite the bottom surface , a first side wall portion extending from the bottom surface into the direction of the light emitting surface until a level between the active region and the light emitting surface , a second side wall portion extending from the level between the active region and the light emitting surface until the light emitting surface , and a plateau connecting the first and second side wall portion . The semiconductor layer stack can in particular be configured to emit light of a desired wavelength or wavelength range when electrically powered .

[0014] The optoelectronic device further comprises a material layer covering at least portions of the first side wall portion as well as in particular portions of the bottom surface . In addition, the optoelectronic device comprises a first contact element arranged on the bottom surface electrically contacting the second layer, and a second contact element arranged on the plateau electrically contacting the first layer .

[0015] The optoelectronic device can in particular be a small light emitting component / element such as a small LED or pLED . A pLED can in particular be a very small LED with edge lengths down to 30 pm, down to 10 pm, down to 5 pm or even less . Such small LEDs can be free of a growth substrate and require a special handling and processing to improve their IQE and light outcoupling efficiency . One approach to improve the IQE of the pLED is to cover the first side wall portions with a regrowth layer . A possible approach to improve the outcoupling efficiency and light directionality of the light emitted by the pLED is to provide outcoupling structures and / or reflective structures on / in the pLED .

[0016] According to some aspects , the semiconductor layer stack comprises a semiconductor material such as for example Indium Gallium Aluminium Phosphide ( InGaAlP ) or Gallium Nitride ( GaN) . The semiconductor layer stack comprises at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer . The first layer can for example be a semiconductor layer that is n-doped, whereas the second layer can for example be a semiconductor layer that is p-doped . The two layers can thus form a pn-j unction with the active region arranged in-between . The active region can for example comprise a quantum well or multi quantum well structure , or can for example comprise quantum dots .

[0017] The first and second side wall portion can result from each an etching step in particular mesa etching step . The first and second side wall portion can in particular result from each a mesa etching step of the semiconductor layer stack from the same side of the semiconductor layer stack, namely the bottom surface of the semiconductor layer stack . The etching steps can thereby be a combination of dry and wet etching steps . By means of these etching steps in combination with a respective arrangement of contact layers / elements , a particularly advantageous structure can be achieved .

[0018] The term side wall portion shall in this regard be understood as at least portions of the side walls of the respective structure being etched . The respective structure being etched resulting in the first and second side wall portions can in particular be the semiconductor layer stack . According to some aspects , the material layer comprises a regrowth layer covering the first side wall portion . In addition or as an alternative , the material layer comprises a dielectric layer arranged between the first and second contact elements and / or between the bottom surface and the first contact element and / or between the first side wall portion and the second contact element . Apart from quantum well intermixing, the material layer can be regrown with a semiconductor material and / or contain SiO2, A12O3and any other suitable material . In some instances , the material layer forms a portion of the outer surface of the later optoelectronic device and / or is formed between the first and second contact element and / or between the bottom surface and the first contact element and / or between the first side wall portion and the second contact element . The material layer can in particular be configured as or comprise a dielectric material layer electrically isolating layers / components within the later optoelectronic device preventing a short .

[0019] The material layer can for example comprise or consist of SiCh , silicon nitride , Nb2Os , HfO2 , AI2O3 , or a stack of a combination of aforementioned materials . The material layer or portions thereof can in particular be deposited using physical vapor deposition ( PVD) , plasma-enhanced chemical vapor deposition ( PECVD) or atomic layer deposition (ALD ) .

[0020] In some aspects , the second contact element electrically contacts the first layer from a side facing away from the light emitting surface . This can in particular result from the fact that the plateau is exposed from a side facing away from the light emitting surface and a contact layer electrically contacting the first layer contacts the exposed side of the first layer, namely the plateau . In addition, the second contact element can electrically contact the first layer along the second side wall portion or at least along a sub portion of the second side wall portion . Alternatively or in addition to this , the second contact element can extend from the plateau into the first layer thereby electrically contacting the first layer . For example the second contact element can extend through the first layer from the plateau to the light emitting surface thereby electrically contacting the first layer and optionally a transparent conductive contact layer arranged on the light emitting surface .

[0021] In some aspects , the light emitting surface is free of a metal . In particular the optoelectronic device is of a flip chip configuration and both electric contacts for powering the optoelectronic device are arranged on the same side of the optoelectronic device , namely the same side as the bottom surface of the semiconductor layer stack . By contacting the first layer via the plateau from the same side as the bottom surface of the semiconductor layer stack, a further conductive material on the light emitting surface can be dispensed with . However , for current spreading reasons it can also be advantageous to have a transparent conductive contact layer arranged on the light emitting surface , that is electrically connected to the second contact element .

[0022] In some aspects , the first side wall portion extends until the same level as the level from which the second side wall portion extends until the light emitting surface . In particular , the first side wall portion can be adj acent to the second sidewall portion and can be contiguous except , for example , for a lateral offset from each other . However , it can also be conceivable that due to a further intermediate etching step further side wall portions are formed between the first and second side wall portions . It can also be conceivable that due to the chosen parameters of the first and second etching step, the first and second side wall portions are substantially contiguous , thus no or substantially no lateral offset between the first and second sidewall portions is present . The plateau can in such a case be formed by a side wall portion itself , for example the second side wall portion .

[0023] In some aspects , the semiconductor layer stack comprises a protrusion, in particular of the material of the first layer , which protrudes laterally from the first layer and forms the plateau . The protrusion can in particular also be called a contact nose , as it specifically serves to provide an electric connection to the first layer on the same side of the optoelectronic device as the bottom surface . The protrusion can in particular extend / protrude from a plane defined by the first side wall portion . The protrusion in particular is of the material of the first layer , however, can also be of any other conductive material being electrically connected to the first layer . For example , the material of the protrusion can be the same material as of the second contact element or can even be comprised by the second contact element . The protrusion can comprise a thickness in a direction perpendicular to the light emitting surface that is equal to or smaller than the thickness of the first layer . The protrusion in particular extends form a level similar to that of the light emitting surface to a level between the light emitting surface and the active region .

[0024] In lateral direction, the protrusion can in some aspects be limited to a central lateral region of the first layer, in particular at most 70% , 60% or 50% of the lateral extension of the first layer . By means of the term lateral extension it can in particular be understood a direction that is perpendicular to a perpendicular on the light emitting surface as well as is arranged within the first side wall portion . The protrusion can therefore also be called a contact nose at it can protrude laterally limited as well as limited in terms of thickness out of the first layer .

[0025] In some aspects , the semiconductor layer stack comprises at least two protrusion protruding from the first layer on two opposing sides of the first layer or can comprise a circumferential protrusion protruding laterally from the first layer circumferentially in all directions . Hence the optoelectronic can also comprise at least two second contact elements arranged on the at least two resulting plateaus or a circumferential second contact element circumferentially surrounding the semiconductor layer stack contacting the second layer .

[0026] In some aspects , the first side wall portion comprises portions of the first layer , the second layer and the active region . In particular, the first side wall portion comprises a whole side surface of the second layer and the active region as well as a side surface portion of the first layer between the active region and the light emitting surface . The second side wall portion can on the other hand comprise a portion of the first layer, but in particular not the second layer and the active region . In particular , the second side wall portion comprises a side surface portion of the first layer between the active region and the light emitting surface .

[0027] According to some aspects , the first side wall portion and / or the second side wall portion are inclined . Due to a mesa etching, the resulting side wall portions can be inclined with respect to a perpendicular of the light emitting surface or bottom surface . In particular, the resulting side wall portions can be inclined such that a cross section of the semiconductor layer stack closer to the bottom surface is smaller than a cross section of the semiconductor layer stack closer to the light emitting surface . The mesa etching can in particular leave a truncated pyramid or truncated cone in each case , the outer surfaces of which form the first and second side wall portion at least in places . In particular , the mesa etching can leave a truncated pyramid or truncated cone of different sizes stacked on top of each other , the outer surfaces of which form the inclined and laterally distant from each other side wall portions at least in places .

[0028] In some aspects , the first contact element comprises a first contact layer arranged on the bottom surface and / or a first reflective layer arranged on the first contact layer and / or the bottom surface . In addition or as an alternative , the first contact element comprises a first contact pad arranged on the first contact layer, the first reflective layer or the bottom surface . The first contact element can in particular comprise a first contact layer in particular also being reflective arranged on the bottom surface forming a mirror at the bottom surface of the semiconductor layer stack . The first contact layer can however also be of a transparent conductive material and a first reflective layer can be arranged on the first contact layer or below the first contact layer forming a mirror at the bottom surface of the semiconductor layer stack . The first contact pad can for example be a contact pad arranged on the first contact layer only in an area opposite the bottom surface or can be in form of a layer covering the whole first contact layer .

[0029] In some aspects , the second contact element comprises a second contact layer arranged on the plateau electrically contacting the first layer . In addition or as an alternative , the second contact element comprises a second reflective layer arranged on the second contact layer and / or the plateau and / or the material layer . Further , the second contact element may comprise a second contact pad / metal layer arranged on the second contact layer , the second reflective layer , the material layer and / or the plateau, the second contact pad electrically contacting the second contact layer and / or the first layer . The second contact element can in particular comprise a second contact layer in particular also being reflective arranged on the second side wall portion forming a mirror around the remaining semiconductor layer stack structure ( optical cavity) . The second contact layer can however also be of a transparent conductive material and a second reflective layer can be arranged on the second contact layer or below the second contact layer forming a mirror around the remaining semiconductor layer stack structure ( optical cavity) . The second contact pad can for example be a contact pad arranged on the second contact layer only in an area opposite the plateau or can extend from the plateau up to a level of the first contact element and in particular first contact pad along the first side wall portion .

[0030] According to some aspects , the second contact element covers at least portions of the second side wall portion as well as extends along the first side wall portion electrically isolated from it . An advantage of this can be that the semiconductor layer stack is encapsulated completely but not the light emitting surface , in particular by a reflective material forming a mirror cavity for the optoelectronic device and protecting the material of the semiconductor layer stack .

[0031] In some aspects , the first layer comprises a buried contact layer arranged between the active region and the light emitting surface of the semiconductor layer stack . The buried contact layer can for example be of InGaAlP with an Aluminium and / or Gallium content of 50 to 80% . The buried contact layer can also be of InAlP with an Aluminium content of 50 to 80% . The buried contact layer can for example be a few to a few hundred nanometres thick . For example , the buried contact layer can comprise a thickness of less than 500nm, less than 250nm, less than lO Onm or less than l Onm.

[0032] The first side wall portion can in such a case extend from the bottom surface until the buried contact layer while the second side wall portion extends from the buried contact layer until the light emitting surface . By means of etching the first side wall portion, the buried contact layer can be exposed such that the plateau is formed by the buried contact layer and the second contact element arranged on the plateau electrically contacts the buried contact layer .

[0033] According to a second aspect , a method for manufacturing an optoelectronic device is provided . The method can in particular be a method for manufacturing an optoelectronic device according to at least some of aforementioned aspects . Hence all aspects already described for the optoelectronic device can in the same way be applied to the method for manufacturing the same .

[0034] According to some aspects , the method for manufacturing an optoelectronic device comprises the following steps : providing a semiconductor layer stack of at least a first layer of a first conductivity type , a second layer of a second conductivity type as well as an active region between the first and second layer , on a growth substrate ; structuring the semiconductor layer stack such that the structured semiconductor layer stack comprises a bottom surface , a first side wall portion extending from the bottom surface into a direction away from the bottom surface until a level between the active region and the growth substrate , and a second side wall portion extending from the level between the active region and the growth substrate further into the second layer, wherein the first and the second side wall portion are connected by a plateau; providing a material layer covering at least portions of the first side wall portion; providing a first contact element on the bottom surface electrically contacting the second layer; providing a second contact element on the plateau electrically contacting the first layer; depositing a sacrificial layer at least partially covering the first and / or second contact element and / or the material layer ; structuring the sacrificial layer to form a recess thereby exposing a portion of the first and / or second contact element and / or the material layer and / or the semiconductor layer stack; depositing a bond layer on the sacrificial layer and into the recess ; attaching a temporary carrier to the bond layer ; backside processing the semiconductor layer stack, thereby removing the growth substrate , and exposing portions of the sacrificial layer and a light emitting surface of the at least one optoelectronic device ; and removing the sacrificial layer , in particular by one of dryetching , wet-etching, plasma-etching or dissolving in a solvent .

[0035] The first and second side wall portion can result from each an etching step in particular mesa etching step . The first and second side wall portion can in particular result from each a mesa etching step of the semiconductor layer stack from the same side of the semiconductor layer stack, namely the bottom surface of the semiconductor layer stack . The etching steps can thereby be a combination of dry and wet etching steps , wherein in particular a first etching step for generating the first side wall portion and a second etching step for generating the second side wall portion can be a dry etching step . In case of the need of exposing a buried contact layer , a wet etching step can be required . Such a wet etching step can be a step using aqueous solutions of K3Fe (CN)6, K2CO3and / or K2HCO3. By means of this , a reliable exposure of the buried contact layer can be achieved even if the buried contact layer is only a few to a few hundred nanometres thick .

[0036] In some aspects , the structuring of the semiconductor layer stack can comprises the step of depositing a structured mas k ( s ) , for example hard mas k ( s ) , on the semiconductor layer stack . The material of the mas k can be suitable as the first contact element or a first portion of the first contact element and may comprise transparent conductive oxides or another conductive material . By doing so , the structured mas k material may remain on the bottom surface of the semiconductor layer stack after the mesa etching step .

[0037] In some aspects , the structuring of the semiconductor layer stack, in particular to receive the second side wall portion, comprises a structuring into remaining portions of the semiconductor layer stack to a depth greater than the depth of the structuring step to receive the first side wall portion . At least the step of structuring resulting in the first side wall portion will stop prior to reaching the growth substrate . Generally, after each structuring step, some cleaning or protecting the exposed surface may be conducted .

[0038] In some aspects , the step of providing the second contact element is conducted such that the second contact element electrically contacts the first layer from a side facing away from the growth substrate . This can in particular result from the fact that the plateau is exposed from a side facing away from the light emitting surface and a contact layer electrically contacting the first layer contacts the exposed side of the first layer, namely the plateau . In addition, the second contact element can be provided along the second side wall portion or at least along a sub portion of the second side wall portion . Alternatively or in addition to this , the second contact element can be provided such that the second contact element extends from the plateau into the first layer thereby electrically contacting the first layer . For example , the second contact element can extend through the first layer from the plateau to the light emitting surface thereby electrically contacting the first layer and optionally a transparent conductive contact layer arranged on the light emitting surface .

[0039] In some aspects , the step of structuring the semiconductor layer stack is conducted such that the semiconductor layer stack comprises a protrusion of the material of the first layer, which protrudes laterally from the first layer of the later at least one optoelectronic device and forms the plateau . The protrusion can in particular extend / protrude from a plane defined by the first side wall portion . The protrusion in particular is of the material of the first layer .

[0040] In lateral direction, the protrusion can in some aspects be limited to a central lateral region of the first layer, in particular at most 70% , 60% or 50% of the lateral extension of the first layer . By means of the term lateral extension it can in particular be understood a direction that is perpendicular to a perpendicular on the bottom surface as well as is arranged within the first side wall portion . The protrusion can therefore also be called a contact nose at it can protrude laterally limited as well as limited in terms of thickness out of the first layer .

[0041] In some aspects , the step of structuring the semiconductor layer stack is conducted such that the semiconductor layer stack comprises at least two protrusion protruding from the first layer on two opposing sides of the first layer or can comprise a circumferential protrusion protruding laterally from the first layer circumferentially in all directions . Hence the optoelectronic can also comprise at least two second contact elements arranged on the at least two resulting plateaus or a circumferential second contact element circumferentially surrounding the semiconductor layer stack contacting the second layer .

[0042] In some aspects , the step of providing the material layer comprises : providing a regrowth layer on the first and / or second side wall portion; and / or providing a dielectric layer between the first and second contact element and / or between the bottom surface and the first contact element and / or between the first side wall portion and the second contact element .

[0043] In some aspects , the method further comprises a step of providing a transparent conductive contact layer on the light emitting surface of the at least one optoelectronic device that is electrically connected to the second contact element .

[0044] In some aspects , the step of structuring the semiconductor layer stack is conducted such that protrusions of the material of the first layer , which protrude laterally from the first layer of later optoelectronic devices each form a plateau, and such that the protrusions are arranged opposite each other in an interlocking manner but at a distance from each other . In particular , the protrusions made of the same material as a layer of the semiconductor layer stack protrude from the core of the semiconductor layer stack, so that a plurality of such optoelectronic devices can be arranged opposite one another in an interlocking manner during their manufacture , but at a distance from one another and thus in a particularly space-saving manner .

[0045] In addition to the steps described, the inventor proposes steps for processing the optoelectronic device , that result in the device being held from below, so there is no interference with the contact to a die or a carrier suitable for laser-induced forward transfer (LIFT ) . Holding structures made of the bond layer can thereby be configured to be not broken but lose their mechanical contact to the optoelectronic device during the transfer , specifically at an interface between the material of the bond layer and the material of the optoelectronic device facing the bond layer .

[0046] According to some aspects , the bond layer is carefully selected and free of semiconductor component . It comprises an organic compound or a thin layer of solder material . Both approaches avoid the formation of particles or rupture and residues on the interface . A following transfer process of the at least one optoelectronic device leaves a defined surface on the underside of the optoelectronic device , the contact area or the surface of the device used for bonding to the target substrate .

[0047] According to some aspects a planarization step of the sacrificial layer material prior to bonding the device with a growth substrate to a temporary carrier takes place . This avoids the filling of areas on the sides of optoelectronic devices by bond material . The bond material is different from the material of the sacrificial layer, such that removal of the sacrificial layer is easily achievable using substances that do not affect the bond material or the device ' s surface .

[0048] The sacrificial layer with a dedicated opening / recess for the bond material to be attached to the optoelectronic device enables a maximum access area for the etchant used to remove the sacrificial layer in subsequent process steps . A planarization allows the openings in the sacrificial layer, which define a holding structure after filling with bond material , to be designed with lithographic precision .

[0049] This - in combination with the material selection for the bond layer and surface of the optoelectronic device - is crucial to be able to control the adhesion force of the optoelectronic devices on the carrier for the transfer process . In addition, planarization of the sacrificial layer enables a particularly thin layer to be bonded to the substrate , which means that metallic ( thin-film) solders can be used as the material for the bond layer in addition to organic polymers . These are particularly resistant to the etching medium used for undercutting .

[0050] In accordance with some aspects , the sacrificial layer can be structured and at least one recess is formed therein, thereby exposing a portion of the material layer and / or the first contact element and / or the second contact element and / or the semiconductor layer stack . The area of the optoelectronic devices surface being exposed is dependent on the location of the recess . In some aspects , the exposed surface only contains one material . In some other aspects , the exposed surface can include two materials , i . e . a dielectric and a contact layer adj acent to it .

[0051] According to some aspects , a bond layer is deposited into the recess , the bond material also extending above the recess and forming an even surface in some instances . The bond layer may comprise an organic material or a metallic alloy, in particular containing gold . The composition of the bond layer is different from the sacrificial layer but selected such that any etchant used for removing the sacrificial layer does not affect the bond layer material or the surface of the optoelectronic device .

[0052] According to some aspects , a temporary carrier is attached to the bond layer . After the attachment of the temporary carrier, the growth substrate as well as a potential buffer layer can be removed to expose the light emitting surface of the semiconductor layer stack . If needed, material of the semiconductor layer stack is also removed until portions of the sacrificial layer are exposed . This will provide access to the sacrificial layer .

[0053] The proposed steps provide several benefits . The method can be used for a plurality of semiconductor devices to be processed on their growth substrate by patterned etching from continuous semiconductor layer stack . The sacrificial layer fills the gap between the plurality of mesa structured layer stacks . The surface of the sacrificial layer facing away from the mesa structured semiconductor layer stacks (within experimental accuracy) is essentially co-planar with the growth substrate and comprises openings in the ( lateral ) regions of the semiconductor elements . The bond material fills the openings and mechanically bonds the semiconductor layer stack to the temporary carrier .

[0054] A holding structure formed of the bond layer in the at least one recess , it ' s number per optoelectronic device , its shape , form and the chosen material provides a flexible yet precise control of the adhesive force between the devices and the holding structure .

[0055] Some aspects concern the selection of material for the sacrificial layer . Such selection should be based on a combination of the desired bond material as well as the material of the outer surface of the optoelectronic device . The material for the sacrificial layer can be selected based on all layers that are in direct contact with the etchant used for removing the sacrificial layer .

[0056] In some aspects , the material of the sacrificial layer is selected to be ZnO if the material layer comprises SiO2or Si3N4, and / or a first and / or second contact element at the outer surface of the optoelectronic device comprises Au or Ag and in particular a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . Dissolving ZnO would be an inorganic implementation . However, ZnO is easily removed with diluted HC1 that leaves SiO2, Si3N4or noble metals like Au, Pd, Pt and Ag unaffected .

[0057] As an alternative , one can use organic materials and compounds for the sacrificial layer . Polystyrene , particularly solute in Ethylacetate or Toluol and is suitable if the material layer comprises SiO2or Si3N4 and / or a first and / or second contact element at the outer surface of the optoelectronic device comprises Au or Ag and in particular a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . Polystyrene has the benefit that it is dissolvable in organic solvents , facilitating the later sacrificial layer removal .

[0058] Other forms of Polystyrene are possible , for example when melted and planarized by pressing if a first and / or second contact element at the outer surface of the optoelectronic device comprises one of Au and Ag, an Au containing alloy, or a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . Polyvinylalcohol , PVA is also a suitable material if the material layer comprises SiO2. It also has the benefit that it is dissolvable in H20 . A similar material is Polyvinylacetate , PVAc, if the material layer comprises SiO2or Si3N4 . It can be dissolved in Ethyl acetate . Finally, soft-baked photoresist can be used, if a first and / or second contact element at the outer surface of the optoelectronic device comprises one of Au and Ag, an Au containing alloy, or a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn . All organic materials as sacrificial layer material can also be removed by an oxygen-based plasma-etching process if a first and / or second contact element at the outer surface of the optoelectronic device comprises one of Au, an Au containing alloy, or a solderable layer such as for example AuSn, InSn, AulnSn, NilnSn .

[0059] Some or all of the material of the sacrificial layer can be deposited by various means , further increasing the flexibility and optimizing the process . For example , deposition techniques include spinning, sputtering, or spraying the sacrificial layer material on a first and / or second contact element at the outer surface of the optoelectronic device and / or the surface of the material layer . In some aspects , viscosity is adj usted by adding a suitable solvent . Consequently, some techniques are also used to planarize the sacrificial layer .

[0060] For example , sacrificial layer material together with a solvent is deposited using one of the above-mentioned techniques . The solvent is vaporized, leaving a substantially planar and even surface of sacrificial layer material . Other deposition techniques include melting sacrificial layer material or pressing molten and low viscous sacrificial layer material are also possible .

[0061] Depositing the bond layer on the sacrificial layer and the at least one recess may include a vapor deposition of the bond layer material . In some aspects a thin film solder material based on a gold allow like AuSn, AulnSn, but also InSn or NilnSn solder material is suitable . Alternatively, the bond layer material may be spinned, sputtered or evaporated onto the sacrificial layer . In some aspects , the bond material comprises an organic compound . Consequently, the bond material may comprise a solvent to adj ust its viscosity . This will provide an even surface after the solvent has evaporated . Further deposition techniques may be used depending on the material , For example , one may use melting bond layer material on the surface or pressing molten or low viscous bond layer material on the surface of the sacrificial layer .

[0062] Different bond layer materials are suitable , particular bond layer materials that are different in its etching characteristics from the material of the sacrificial layer . In some aspects , the bond layer material comprises one of Benzocyclobuthene or epoxy resin, that is at least partially cured at room temperature or slightly elevated temperature , particularly if the sacrificial layer comprises an organic compound and / or if the first and / or second contact elements contain a solderable material stack . The bond layer material comprises in other aspects polystyrene if the sacrificial layer comprises PVA, or the bond layer material comprises epoxy resin or Benzocyclobuthene if the sacrificial layer comprises polystyrene . The various combinations are also stated further below .

[0063] In some aspects , the bond layer is cured after the temporary carrier is attached to the bond layer . For curing purposes , thermal or optical measures can be used . Of course , the curing process can be divided to fit the attachment and planarization process .

[0064] After attaching the temporary carrier , the semiconductor layer stack can be freed of the growth substrate . The temporary carrier acts as a new substrate for such process steps . Various methods of removing the growth substrate are known in the art . This will expose the semiconductor layer stack from the front side . A possible continuous portion of the semiconductor layer stack can also be removed to separate the individual optoelectronic devices embedded within the sacrificial layer . Removing the continuous portion of the semiconductor layer stack includes but is not limited to mechanical grinding, polishing , chemical mechanical polishing, CMP , wet or dry etching or combinations thereof . The front side of the optoelectronic devices namely a light emitting surface of the semiconductor layer stack opposite the bottom surface is then exposed and can be further processed .

[0065] Finally, the proposed method may include removal of the sacrificial layer , in particular by one of dry-etching , wet-etching, plasmaetching , or dissolving in a solvent , in particular in water . Again, the selected removal process depends on the combination of the material of the semiconductor' s surface , the material of the sacrificial layer and the bond material . The optoelectronic device is then held by the bond material , defining a specific adhesion force at the interface . This will allow an easy transfer process onto a target substrate or a carrier for a subsequent LI FT process using a stamp, for example .

[0066] In some aspects , before or after the removal of the sacrificial layer the semiconductor layer stack opposite the bottom surface is covered by a passivation layer . This passivation layer can contain or consist of SiO2 , AI2O3 , SisN HfO2 or other suitable dielectric materials .

[0067] Another aspect concerns an arrangement of optoelectronic devices according to some of aforementioned aspects that are arranged adj acent to one another on a carrier substrate . Such an optoelectronic arrangement comprises a carrier substrate with a plurality of first and a second contact pads as well as a plurality of optoelectronic devices according to some of aforementioned aspects being arranged on the carrier substrate with each the first and second contact element of an optoelectronic device being electrically coupled to a first and second contact pad .

[0068] In some aspects , the carrier substrate comprises a plurality of cavities extending from a top surface of the carrier substrate into the carrier substrate , wherein each a first contact pad is arranged on a bottom surface of the cavities and the second contact pads are arranged on the top surface . The optoelectronic devices are in particular conf igured / designed to match the arrangement of the first and second contact pads electrically contacting the same . SHORT DESCRIPTION OF THE DRAWINGS

[0069] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

[0070] Fig . 1 to 8 show steps for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0071] Fig . 9 to 11 show steps for manufacturing an optoelectronic arrangement in accordance with some aspects of the proposed principle ;

[0072] Fig . 12A and 12B show a cross sectional view and a top view of a step for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0073] Fig . 13A to 13C show each a top view of further embodiments of a step for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

[0074] Fig . 14A and 14B show each a top and a cross sectional view of an optoelectronic device ;

[0075] Fig . 15A to 15G show a cross sectional view as well as top views of embodiments of an optoelectronic device in accordance with some aspects of the proposed principle ; and

[0076] Fig . 16A to 16C show each a top view of a step for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle . DETAILED DESCRIPTION

[0077] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea .

[0078] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

[0079] Figures 1 to 9 show steps for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle .

[0080] In a first step, as shown in figure 1 , a growth substrate 2 is provided with a semiconductor layer stack 3 epitaxially grown on top . The semiconductor layer stack comprises a first layer 4 of a first conductivity type , a second layer 5 of a second conductivity type as well as an active region 6 between the first and second layer 4 , 5 . The active region 6 in the embodiment shown is in particular in form of a multi quantum well structure .

[0081] In a second step , as shown in figure 2 , the semiconductor layer stack 3 is structured thereby remaining first portions of the semiconductor layer stack 3 and removing second portions of the semiconductor layer stack, wherein the first portions are in the embodiment shown still connected by a common residue layer of the first layer 4 . The remained portions each form the semiconductor layer stack portion of a later optoelectronic device 1 . The remained portions are each formed to comprise in a first step each a bottom surface 8 and inclined first side wall portions 9a extending from the bottom surface 8 into the direction of the growth substrate 2 . Therefore a structured contact layer , in particular a first portion of a first contact element 7 is deposited on a surface of the semiconductor layer stack 3 . The first portion of the first contact element 7 can for example form a structured mas k which is suitable as a mas k for a subsequent etching step but can also be deposited / grown on the semiconductor layer stack 3 after a mesa etching of the semiconductor layer stack 3 has been performed . In the embodiment shown, the first portion of a first contact element 7 comprises a first contact layer 7a . The first contact layer 7a can for example be of a transparent conductive material such as a TCO or can for example be of a metal and can comprise for example a solder material or solder material layer on a surface facing away from the second layer 5 . A solder material can for example comprise a metal layer stack consisting of AuSn, AulnSn, InSn, NiSn, NilnSn, SnAgCu .

[0082] The first etching is performed such that the etching does not go through the whole first layer 4 but stops well before reaching the growth substrate 2 . The resulting first side wall portions 9a are thus extending from the bottom surface 8 into a direction away from the bottom surface 8 until a level between the active region 6 and the growth substrate 2 . The exposed portions are thereby as shown in cross section in form of a trapezoid arranged on a residue of the first layer 4 .

[0083] Then a second etching step into the semiconductor layer stack 3 and in particular further into the first layer 4 is performed to form second side wall portions 9b . The etching is in particular be conducted such that the second side wall portions 9b are at least in places laterally shifted with regard to the first side wall portions forming at least one plateau 22 regarded to each a semiconductor layer stack portion of a later optoelectronic device 1 . The second etching too is performed such that the etching does not go through the whole first layer 4 but stops well before reaching the growth substrate 2 . The resulting first second wall portions 9b are thus extending from the plateau 22 into the direction of the growth substrate 2 until a level between the plateau 22 and the growth substrate 2 .

[0084] Then a material layer 10 is provided on the mesa etched structure following the shape of the mesa etched structure . The material layer 10 can be provided such that it covers at least the first side wall portions 9a . In the embodiment shown, the material layer 10 covers the first side wall portions 9a , the plateaus 22 and the second side wall portions 9b . The material layer 10 can for example be a layer provided on exposed first side wall portions 9a and other exposed surfaces and can be regrown with a semiconductor material or any other suitable materials to confine charge carriers within a central region of the active region 6 . The material layer 10 can however also be a structured dielectric / passivation layer of for example SiO2 and / or AI2O3 provided by means of ALD that covers the first side wall portions 9a , the plateaus 22 and the second side wall portions 9b .

[0085] The semiconductor layer stack 3 and in particular the first layer 4 can in addition also comprise a buried contact layer 19 arranged between the active region 6 and the growth substrate 2 ( see embodiment shown in Figure 15A) , wherein the buried contact layer 19 is for example a layer of a similar material as the first layer 4 but with a higher doping concentration . The buried contact layer 19 can for example of a thickness between 500 nm and 50nm . In this case the first side wall portion 9a can extend from the bottom surface 8 to the buried contact layer 19 and the plateau 22 can be formed by the buried contact layer 19 .

[0086] In a further step , as shown in Figure 3A, second portions of the first contact elements 7 , namely a first contact pad 7b , is provided on the first contact layers 7a . In addition, second contact elements 16 are provided on the mesa etched structure namely the plateaus 22 electrically contacting the first layer 4 . The second contact elements 16 can in particular be provided in form of a contact pad together with a first contact pad 7b of the first contact element 7 serving as a connection area for applying a potential to the later optoelectronic device 1 from the same side of the optoelectronic device .

[0087] Figure 3B shows an alternative approach, where the second contact elements 16 are provided not only as "thin" contact pads but extend from the plateaus 22 along the first side wall portions 9a until a height similar to that of the first contact elements 7 . By this a surface mountable ( SMT ) device can be provided .

[0088] As shown in figures 4A and 4B, a sacrificial layer 11 is then deposited on the material layer 10 as well as on the first and second contact element 7 , 16 . The sacrificial layer 11 in particular covers all exposed surfaces of the later optoelectronic devices . The sacrificial layer 11 thereby comprises one of a metal-oxide or an organic material . In the embodiment shown the sacrificial layer 11 is applied in form of a layer extending with a substantially equal thickness along the underlying structure , the sacrificial layer can however also be provided to fill up completely all gaps resulting from the mesa etching . In particular in later case , the sacrificial layer 11 can then be planarized to form an even surface . Such an even surface of the sacrificial layer 11 facing away from the semiconductor layer stack 3 (within experimental accuracy) can be substantially co-planar with the growth substrate 2 .

[0089] The deposition of the sacrificial layer 11 can for example comprise a spinning, sputtering, or spraying of the sacrificial layer material on the exposed surface ( s ) of the later optoelectronic devices 1 . A possible planarization of the sacrificial layer 11 can comprise a mechanical planarization such as for example grinding and / or polishing , a chemical planarization using for example an etchant , a chemical mechanical polishing (CMP ) , or by melting and / or pressing molten or low viscous sacrificial layer material on the surface the exposed surface ( s ) . In case of molten / liquid sacrificial layer material being deposited the exposed surface ( s ) , the step of planarization can be dispensed with in such that the planarization can take place over time by itself as the molten sacrificial layer material levels itself over time .

[0090] The sacrificial layer 11 is then in a subsequent step structured to provide recess ( es ) 13 in the sacrificial layer 11 . Due to structuring the sacrificial layer 11 , thereby generating the recess ( es ) 13 , a portion of the first contact elements 7 is exposed . The area being exposed is dependent on the position where a holing structure is desired to be later provided . In the embodiment shown, only a portion of the first contact elements 7 is exposed, however it can also be conceivable to expose other areas as well as other material or material combinations .

[0091] As shown in Figure 5 , a bond layer 14 is then provided on the sacrificial layer 11 and into the recess ( es ) 13 . In the embodiment shown, the bond layer 14 forms an even surface 12 opposite the semiconductor layer stack 3 . The bond layer 14 can for example comprise an organic material , a gold alloy or can be a ( thin film) solder material or combinations thereof . The composition of the bond layer 14 is however different form the sacrificial layer 11 and selected such that an etchant used for removing the sacrificial layer 11 does not or not substantially affect the bond layer 11 , the first and second contact element 7 , 16 , the material layer 10 and any other exposed surface ( s ) of the semiconductor layer stack 3 . The bond layer 14 can for example be provided by means of a spin-on process or sputtering the material of the bond layer 14 onto the sacrificial layer 11 and into the recess ( es ) 13 . The bond layer material within the recesses 13 contacting the exposed portion ( s ) of the first contact elements 7 together with the rest of the bond layer 14 forms a later holding structure 18 for the optoelectronic devices 1 .

[0092] A temporary carrier 15 is then attached to the bond layer 14 , for example by means of bonding ( see Figure 6 ) . After the attachment of the temporary carrier 15 , the growth substrate 2 as well as a potential buffer layer is removed, as shown in Figure 7 , to expose light emitting surfaces 17 of the semiconductor layer stack 3 , in particular the first layer 4 . The semiconductor layer stack 3 , in particular the first layer 4 can, if necessary be thinned to remove a connected residue of the first layer 4 . By means of this , the semiconductor layer stack portions later forming an optoelectronic device 1 can be singulated and access to the sacrificial layer 11 is provided . The growth substrate 2 removal and / or thinning can for example comprise LLO , grinding, dry etching , wet etching , CMP , or combinations thereof . After the step of thinning , portions of the semiconductor layer stack 3 are separated each exposing a light emitting surface 17 of the semiconductor layer stack portions .

[0093] The sacrificial layer 11 is then removed to expose the optoelectronic devices 1 attached to the holding structure 18 as shown in the embodiment in Figures 8 . Due to the good accessibility of the sacrificial layer 11 , the sacrificial layer 11 can easily be removed . The removal of the sacrificial layer 11 can for example be done by one of dry-etching, wet-etching or plasma-etching . The selected removal process thereby depends on the combination of the material of the material layer 10 , the first and second contact element 7 , 16 as well as the material of the bond layer 14 . The optoelectronic devices 1 are then held by the holding structure 18 , defining a specific adhesion force at the interface between the holding structure 18 and the first contact elements 7 . This will allow an easy subsequent transfer process onto a target substrate .

[0094] The holding structure 18 can also be configured to be arranged contacting the material layer 10 and / or the first and / or the second contact element 7 , 16 at one , two or even more positions of the optoelectronic devices 1 . The holding structure 18 can for example be configured to be arranged contacting the first contact element 7 at a side surface or at side surfaces of the optoelectronic devices 1 . The holding structure 18 can also be configured to be arranged contacting two or more optoelectronic devices 1 at a time . These embodiments are however only to be understood as exemplary and shall not be limiting in any way . The described structures can for example be combined or changed in any possible way . As shown in Figure 8 on the right as well as indicated by means of the double wave line , the optoelectronic devices 1 can comprise a transparent contact layer 23 arranged on the light emitting surface 17 that is electrically coupled to the second contact element 16 . Th second contact element can therefore extend from the plateau 22 along the second side wall portion 9b to the light emitting surface 17 to electrically connect to the transparent contact layer 23 . By means of this an emission of light through the transparent contact layer 23 can still be provided while an enhanced current spreading into the first layer 4 can be provided by means of the transparent contact layer 23 .

[0095] Figures 9 to 11 show possible subsequent steps for manufacturing an optoelectronic arrangement 30 in accordance with some aspects of the proposed principle . The optoelectronic devices 1 manufactured according to some of aforementioned aspects are therefore lifted off the holding structure 18 by means of a transfer device 24 . The transfer device can for example be in form of a stamp lifting off the optoelectronic devices 1 from the holding structure 8 .

[0096] The optoelectronic devices 1 are then transferred to a carrier substrate 25 . The carrier substrate 25 comprises a plurality of first and a second contact pads 20 , 21 , wherein each a first contact pad 20 is arranged on a bottom surface 28 of a cavity 27 extending from a top surface 26 of the carrier substrate 25 into the carrier substrate 25 and wherein the second contact pads 21 are arranged on the top surface 26 . The cavities 27 and thus the first and a second contact pads 20 , 21 thereby match the orientation and arrangement of the first and second contact elements 7 , 16 allowing s direct connection between the first and a second contact pads 20 , 21 and the first and second contact elements 7 , 16 .

[0097] Figure 12A and 12B show a cross sectional view and a top view of a further possible step for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle . In particular the two Figures show a possible embodiment of the orientation of the optoelectronic devices being manufactured in accordance with some aspects of the proposed principle . Contrary to the embodiment shown, the optoelectronic devices can be manufactured with the protrusions 31 or second side wall portions 9b facing each other respectively .

[0098] By means of this and in particular in conj unction with the embodiments shown in Figures 13A to 13C the second contact elements 16 can be provided in such a manner that these are separated when pixelating the optoelectronic devices ( indicated by the separation lines in Figures 13A and 13B ) . In addition, as shown in Figure 13C , a redundant device can be provided in which two optoelectronic devices 1 are connected by means of a common transparent contact layer 23 .

[0099] A further advantage of the optoelectronic devices in particular with regard to its manufacture and cost per piece is explained with regard to Figures 14A to 16C .

[0100] Figures 14A and 14B show each a top and a cross sectional view of an optoelectronic device 1 . Figure 14A shows a conventional vertically contactable optoelectronic device 1 whereas Figure 14B shows a conventional horizontally contactable optoelectronic device 1 in cross section . The top view on the other hand shows each a wafer area 29 needed for manufacturing such an optoelectronic device . It can be seen that a vertically contactable optoelectronic device 1 consumes less wafer area 29 as a horizontally contactable optoelectronic device 1 . In particular one can say, a vertically contactable optoelectronic device 1 consumes one area unit of a production wafer whereas a horizontally contactable optoelectronic device 1 consumes two area units of the production wafer .

[0101] As the material of the production wafer is very costly, but horizontally contactable optoelectronic devices 1 are favoured for some applications the inventor suggests the optoelectronic devices in accordance with some aspects of the proposed principle which is horizontally contactable but designed to consume less wafer area 29 . In particular the contact nose forming the plateau 22 for providing the second contact element 16 already saves wafer area 29 for manufacture of the optoelectronic devices 1 compared to the embodiment shown in Figure 14B .

[0102] Figures 15A to 15G now show a further improvement and thus an efficient use of the available wafer area . As can be seen in particular from Figures 15B to 15G the protrusions 31 are spatially limited to a central region of the lateral extension of the semiconductor layer stack 3 . Figures 15B to 15G thereby show variations of how far the protrusions 31 protrude from the semiconductor layer stack 3 and in the number of protrusions 31 protruding from the semiconductor layer stack 3 . However, these examples are only to be understood es exemplary and can be optimized with regard to its specific need .

[0103] This specific form enhances an efficient use of the available wafer area as the optoelectronic devices 1 and in particular their protrusions can be arranged opposite each other in an interlocking manner but at a distance from each other as shown in Figures 16A to 16C . The amount of wafer area 29 used compared to a vertically contactable optoelectronic device is hence not significantly larger while providing a horizontally contactable optoelectronic device 1 . For example such a horizontally contactable device can only be 10% , 20% or only 30% larger than a comparable vertically contactable optoelectronic device .

[0104] LIST OF REFERENCES

[0105] 1 optoelectronic device

[0106] 2 growth substrate 3 semiconductor layer stack

[0107] 4 first layer

[0108] 5 second layer

[0109] 6 active region

[0110] 7 contact element 7a contact layer

[0111] 7b contact pad

[0112] 8 bottom surface

[0113] 9a , 9b side wall portion

[0114] 10 material layer 11 sacrificial layer

[0115] 12 even surface

[0116] 13 recess

[0117] 14 bond layer

[0118] 15 temporary carrier 16 contact element

[0119] 17 light emitting surface

[0120] 18 holding structure

[0121] 19 buried contact layer

[0122] 20 contact pad 21 contact pad

[0123] 22 plateau

[0124] 23 transparent contact layer

[0125] 24 transfer device

[0126] 25 carrier substrate 26 top surface

[0127] 27 cavity

[0128] 28 bottom surface

[0129] 29 wafer area

[0130] 30 optoelectronic arrangement 31 protrusion

Claims

CLAIMS1. Optoelectronic device (1) , in particular pLED, comprising: a semiconductor layer stack (3) of at least a first layer (4) of a first conductivity type, a second layer (5) of a second conductivity type as well as an active region (6) between the first and second layer (4, 5) , wherein the semiconductor layer stack (3) comprises: a bottom surface (8) and a light emitting surface (17) opposite the bottom surface (8) ; a first side wall portion (9a) extending from the bottom surface (8) into the direction of the light emitting surface (17) until a level between the active region (6) and the light emitting surface (17) ; a second side wall portion (9b) extending from a level between the active region (6) and the light emitting surface (17) until the light emitting surface (17) ; and a plateau (22) connecting the first and second side wall portion (9a, 9b) ; a material layer (10) covering at least portions of the first side wall portion (9a) ; a first contact element (7) arranged on the bottom surface (8) and electrically contacting the second layer (5) ; and a second contact element (16) arranged on the plateau (22) and electrically contacting the first layer (4) ; wherein the first layer (4) comprises a buried contact layer (19) arranged between the active region (5) and the light emitting surface (17) of the semiconductor layer stack (3) , wherein the first side wall portion (9a) extends from the bottom surface (8) until the buried contact layer (19) , and wherein the second contact element (16) is arranged on the plateau (22) electrically contacting the buried contact layer (19) .

2. Optoelectronic device according to claim 1, wherein the second contact element (16) electrically contacts the first layer (4) from a side facing away from the light emittingsurface (17) and / or along the second side wall portion (9b) and / or extends from the plateau (22) into the first layer (4) .

3. Optoelectronic device according to claim 1 or 2 , wherein the semiconductor layer stack (3) comprises a protrusion (31) of the material of the first layer (4) , which protrudes laterally from the first layer (4) and forms the plateau (22) .

4. Optoelectronic device according to claim 3, wherein the protrusion (31) is limited to a central lateral region of the first layer (4) , in particular at most 70% of the lateral extent of the first layer (4) .

5. Optoelectronic device according to any one of the preceding claims , wherein the light emitting surface (17) is free of a metal.

6. Optoelectronic device according to any one of the preceding claims , wherein the first side wall portion (9a) comprises portions of the first layer (4) , the second layer (5) and the active region (6) .

7. Optoelectronic device according to any one of the preceding claims , wherein the second side wall portion (9b) comprises portions of the first layer (4) , but in particular not the second layer (5) and the active region (6) .

8. Optoelectronic device according to any one of the preceding claims , wherein the first side wall portion (9a) and the second side wall portion (9b) are laterally distant from each other.

9. Optoelectronic device according to any one of the preceding claims ,wherein the first side wall portion (9a) and / or the second side wall portion (9b) are inclined.

10. Optoelectronic device according to any one of the preceding claims , wherein the material layer (10) comprises a regrowth layer covering the first and second side wall portion (9a, 9b) .

11. Optoelectronic device according to any one of the preceding claims , wherein the first contact element (7) comprises: a first contact layer (7a) arranged on the bottom surface ( 8 ) ; and / or a first reflective layer arranged on the first contact layer (7a) or the bottom surface (8) ; and / or a first contact pad (7b) arranged on the first contact layer (7a) , the first reflective layer or the bottom surface (8) .

12. Optoelectronic device according to any one of the preceding claims , wherein the second contact element (16) comprises: a second contact layer arranged on the plateau (22) electrically contacting the first layer (4) ; and / or a second reflective layer arranged on the second contact layer and / or the plateau (22) ; and / or a second contact pad arranged on the second contact layer, the second reflective layer and / or the plateau (22) ; wherein in particular the second contact element (16) extends until a height of the bottom surface (8) .

13. Optoelectronic device according to any one of the preceding claims , wherein the second contact element (16) covers at least portions of the second side wall portion (9b) ; and wherein in particular a transparent conductive contact layer (23) is arranged on the light emitting surface (17) being electrically connected to the second contact element (16) .

14. Method for manufacturing at least one optoelectronic device (1) comprising the steps :Providing a semiconductor layer stack (3) of at least a first layer (4) of a first conductivity type, a second layer (5) of a second conductivity type as well as an active region (6) between the first and second layer (4, 5) , on a growth substrate (2) ;Structuring the semiconductor layer stack (3) such that the structured semiconductor layer stack (3) comprises a bottom surface (8) and a first side wall portion (9a) extending from the bottom surface (8) into a direction away from the bottom surface (8) until a level between the active region (6) and the growth substrate (2) as well as a second side wall portion (9b) extending from the level between the active region (6) and the growth substrate (2) further into the second layer (5) , wherein the first and the second side wall portion (9a, 9b) are connected by a plateau (22) ;Providing a material layer (10) covering at least portions of the first side wall portion (9a) ;Providing a first contact element (7) on the bottom surface (8) electrically contacting the second layer (5) ;Providing a second contact element (16) on the plateau (22) electrically contacting the first layer (4) ;Depositing a sacrificial layer (11) at least partially covering the first and / or second contact element (7, 16) and / or the material layer (10) ;Structuring the sacrificial layer (11) to form a recess (13) thereby exposing a portion of the first and / or second contact element (7, 16) and / or the material layer (10) and / or the semiconductor layer stack (3) ;Depositing a bond layer (14) on the sacrificial layer (11) and into the recess (13) ;Optionally attaching a temporary carrier (15) to the bond layer ( 14 ) ;Backside processing the semiconductor layer stack (3) , thereby removing the growth substrate (2) , and exposing portionsof the sacrificial layer (11) and a light emitting surface (17) of the at least one optoelectronic device (1) ; andRemoving the sacrificial layer (11) , in particular by one of dry-etching, wet-etching, plasma-etching or dissolving in a solvent; wherein the first layer (4) comprises a buried contact layer (19) arranged between the active region (5) and the light emitting surface (17) of the semiconductor layer stack (3) , wherein the first side wall portion (9a) extends from the bottom surface (8) until the buried contact layer (19) , and wherein the second contact element (16) is arranged on the plateau (22) electrically contacting the buried contact layer (19) .

15. The method according to claim 14, wherein the step of providing the second contact element (16) is conducted such that the second contact element (16) electrically contacts the first layer (4) from a side facing away from the growth substrate (2) and / or along the second side wall portion (9b) and / or such that the second contact element (16) extends from the plateau (22) into the first layer (4) .

16. The method according to claim 1':or 15, wherein the step of structuring the semiconductor layer stack (3) is conducted such that the semiconductor layer stack (3) comprises a protrusion (31) of the material of the first layer (4) , which protrudes laterally from the first layer (4) of the later at least one optoelect sonic device (1) and forms the plateau (22 ) .

17. The method according to claim 16, wherein the protrusion (31) is limited to a central lateral region of the first layer (4) of the later at least one optoelectronic device (1) , in particular at most 70% of the lateral extent of the first layer (4) of the later at least one optoelectronic device (1) .

18. The method according to any one of claims 14 to 17, wherein the step of providing the material layer (10) comprises: providing a regrowth layer on the first and / or second side wall portion (9a, 9b) ; and / or providing a dielectric layer between the first and second contact element (7, 16) and / or between the bottom surface (8) and the first contact element (7) and / or between the first side wall portion (9a) and the second contact element (16) .

19. The method according to any one of claims 14 to 18, further comprising a step of providing a transparent conductive contact layer (23) on the light emitting surface (17) of the at least one optoelectronic device (1) being electrically connected to the second contact element (16) .

20. The method according to any one of claims 14 to 19, wherein the step of structuring the semiconductor layer stack (3) is conducted such that protrusions (31) of the material of the first layer (4) , which protrude laterally from the first layer (4) of later optoelectronic devices (1) each forming a plateau (22) , are arranged opposite each other in an interlocking manner but at a distance from each other.

21. Optoelectronic arrangement (30) comprising: a carrier substrate (25) with a plurality of first and a second contact pads (20, 21) ; and a plurality of optoelectronic devices (1) according to any one of claims 1 to 13 being arranged on the carrier substrate (25) with each the first and second contact element (7, 16) of an optoelectronic device (1) being electrically coupled to a first and second contact pad (20, 21) .

22. Optoelectronic arrangement according to claim 21, wherein the carrier substrate (25) comprises a plurality of cavities (27) extending from a top surface (26) of the carrier substrate (25) into the carrier substrate (25) ,wherein each a first contact pad (20) is arranged on a bottom surface (28) of the cavities (27) , and wherein the second contact pads (21) are arranged on the top surface (26) .

Images