Data processing method, storage device, and electronic device

Abstract

Embodiments of the present invention relate to the technical field of storage, and provide a data processing method, a storage device, and an electronic device. The storage device further comprises a controller and a nonvolatile memory connected to the controller. The nonvolatile memory comprises an SLC memory cell group and a QLC memory cell group. The data processing method can be applied to the controller and comprises: receiving data to be written transmitted for the storage device; caching said data to the SLC memory cell group; and writing said data cached in the SLC memory cell group into the QLC memory cell group.

Description

[0001] Data Processing Method, Storage Device, and Electronic Device Cross-Reference This disclosure claims priority to Chinese patent application number 202410258906.7, filed with the China Patent Office on March 6, 2024, entitled "Data Processing Method, Storage Device, and Electronic Device," the entire contents of which are incorporated herein by reference. Technical Field: Embodiments of the present disclosure relate to the field of storage technology, and more particularly to a data processing method, storage device, and electronic device. Background: With the continued rapid growth of massive data, reducing storage costs has become critical for cloud services. One effective way to reduce storage costs is to increase storage density. Quad-Level Cell (QLC) NAND Flash, using a three-dimensional (3D) stacking process and a four-layer storage structure, is currently a high-density flash memory available for commercialization. In recent years, with improvements in production processes, the data retention and durability of 3D QLC NAND have been significantly enhanced. Therefore, improving the performance of 3D QLC NAND and enabling its wider application is particularly important. SUMMARY OF THE INVENTION Embodiments of the present disclosure provide a data processing method, a storage device, and an electronic device to alleviate or resolve technical problems existing in the prior art. In a first aspect, embodiments of the present disclosure provide a data processing method applied to a controller of a storage device. The storage device also includes a non-volatile memory connected to the controller. The non-volatile memory includes a single-level cell (SLC) storage cell group and a quad-level cell (QLC) storage cell group. The method includes: receiving data to be written transmitted to the storage device; caching the data to be written in the SLC storage cell group; and writing the data to be written cached in the SLC storage cell group to the QLC storage cell group. In a second aspect, embodiments of the present disclosure provide a storage device comprising a controller and a non-volatile memory connected to the controller, wherein the non-volatile memory comprises an SLC memory cell group and a QLC memory cell group, and the controller is configured to implement the data processing method of the embodiments of the present disclosure. In a third aspect, embodiments of the present disclosure provide an electronic device comprising the storage device of the embodiments of the present disclosure. In a fourth aspect, embodiments of the present disclosure further provide a computer program product comprising a computer program, wherein when executed by a processor, the computer program implements any of the aforementioned methods.In a fifth aspect, embodiments of the present disclosure further provide a computer program product comprising a non-volatile computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements any of the aforementioned methods. In a sixth aspect, embodiments of the present disclosure further provide a computer program. When executed by a processor, the computer program implements any of the aforementioned methods. In embodiments of the present disclosure, SLC storage units configured within non-volatile memory (QLC NAND media) serve as a write cache, overcoming the capacity limitations of volatile memory caches such as dynamic random access memory (DRAM), leveraging the high concurrency and throughput advantages of NAND flash memory (NAND), and overcoming the bandwidth bottleneck of DRAM controllers. Furthermore, the non-volatility of SLC eliminates the power-failure protection required for corresponding volatile memory capacities. This eliminates the limitations imposed by storage devices' DRAM capacity, bandwidth, and power-failure protection, thereby improving the write performance of QLC solid-state drives and enabling them to be used in a wider range of application scenarios, thereby reducing costs through scale. The above description is merely an overview of the technical solutions of the present disclosure. To better understand the technical solutions of the present disclosure, implementation is possible in accordance with the contents of this description. To further enhance the understanding of the aforementioned and other objectives, features, and advantages of the present disclosure, specific embodiments of the present disclosure are described below. In the accompanying drawings, unless otherwise specified, identical reference numerals throughout the various figures denote identical or similar components or elements. The drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments of the present disclosure and should not be construed as limiting the scope of the present disclosure.Figure 1 is a schematic diagram of the architecture of an exemplary storage device; Figure 2 is a schematic diagram of the architecture of a storage device provided in an embodiment of the present disclosure; Figure 3 is a schematic diagram of the architecture of a storage device provided in an embodiment of the present disclosure; Figure 4 is a flow chart of a data processing method provided in an embodiment of the present disclosure; Figure 5 is a schematic diagram of the asynchronous data migration process from an SLC storage cell group to a QLC storage cell group in an embodiment of the present disclosure; Figure 6A is a schematic diagram of write and read operations for a QLC storage cell in a related technical solution; Figure 6B is a schematic diagram of unbalanced write and read operations for a QLC storage cell in an embodiment of the present disclosure; Figure 7A is a schematic diagram of the media state of the non-volatile memory 203 at the moment of full write in an embodiment of the present disclosure; Figure 7B is a schematic diagram of the media state during the read cache process of the non-volatile memory 203 in an embodiment of the present disclosure; Figure 8 is a schematic diagram of data transfer in an embodiment of the present disclosure; Figure 9 is a flow chart of the data processing method provided in an embodiment of the present disclosure; and Figure 10 is a diagram illustrating an application example of the data processing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS The following only briefly describes certain exemplary embodiments. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are to be considered illustrative in nature and not restrictive. To facilitate understanding of the technical solutions of the embodiments of the present disclosure, the following describes related technologies of the embodiments of the present disclosure. The following related technologies, as optional solutions, can be combined with the technical solutions of the embodiments of the present disclosure in any manner and are all within the scope of protection of the embodiments of the present disclosure. Application Scenarios: Non-volatile memory (NVM) is a type of computer memory, as opposed to volatile memory. It is called "non-volatile" because it can retain stored data even in the event of a power outage, i.e., it has data retention capabilities. Unlike volatile memory, non-volatile memory can retain data for long periods of time without requiring a power supply. Common non-volatile memories include read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory.Among them, flash memory mainly includes NAND flash memory and NOR flash memory (NOR for short). NAND is often used as a storage medium for solid state drives (SSDs).

[0002] NAND can be categorized into at least four types based on chip type: SLC NAND, Multi-Level Cell (MLC) NAND, Trinary Level Cell (MLC-TLC) NAND, and QLC NAND. A cell is the smallest storage unit or particle in NAND, performing data storage. Each cell in SLC NAND stores one bit of data; each cell in MLC NAND stores two bits of data; each cell in TLC NAND stores three bits of data; and each cell in QLC NAND stores four bits of data. As the amount of data stored per cell increases, the storage density and capacity of SLC NAND, MLC NAND, TLC NAND, and QLC NAND also increase. However, data retention (related to the number of erasures and lifespan), storage speed, and cost are generally negatively correlated with storage density. QLC NAND is the highest-density flash memory currently available for commercialization. With improvements in production processes, QLC NAND's data retention and endurance have significantly improved, with its lifespan approaching that of TLC NAND. In many scenarios, SSDs using QLC NAND as the storage medium (QLC SSDs) now meet lifespan requirements. This has accelerated the commercialization of low-cost 3D QLC SSDs, effectively reducing costs. However, each cell in QLC NAND stores 4 bits of data, corresponding to 16 voltage levels, while each cell in TLC NAND stores 3 bits of data, corresponding to 8 voltage levels. Therefore, within the limited threshold voltage distribution range, QLC NAND requires smaller write voltage pulses for gradual writing compared to TLC NAND, resulting in longer write times. Similarly, when reading, the need to identify which of the 16 voltage levels is being used results in longer read times. Therefore, QLC NAND has longer read and write latencies than TLC NAND. In other words, QLC SSD access performance (such as latency and throughput) is still significantly lower than TLC SSDs, and therefore cannot meet user needs in some scenarios. These shortcomings limit the wider application of 3D QLC SSDs and also restrict larger-scale cost savings. Therefore, exploring 3D QLC SSD performance improvements can promote the commercialization of low-cost storage media in a wider range of scenarios, thereby achieving significant benefits in hyperscale infrastructure deployments.Figure 1 is a schematic diagram of the architecture of an exemplary storage device. As shown in Figure 1 , storage device 100 is a QLC SSD, comprising an SSD controller 101, volatile memory 102, non-volatile memory 103, a capacitor bank 104, and a host interface 105. Volatile memory 102 can be static random access memory (SRAM) or DRAM. Volatile memory 102 can be on-chip memory, such as on-chip DRAM, or off-chip memory, such as off-chip DRAM. Non-volatile memory 103 is a QLC NAND, comprising multiple QLC NAND units. Each QLC NAND unit includes multiple cells, and each cell can store 4 bits of data. As shown in Figure 1, storage device 100 uses large-capacity volatile memory 102 (such as DRAM) as a write cache. The operating principle is as follows: When a user writes data to storage device 100, the data is first cached in DRAM under the control of SSD controller 101, and a write success notification is then sent to the host. The data is then asynchronously moved from the DRAM write cache to the QLC NAND cells of non-volatile memory 103 for persistence. Because data entering the DRAM write cache requires power loss protection circuitry within storage device 100 to provide the energy required to persist large amounts of data in the event of a failure, current engineering implementations use supercapacitors provided by capacitor bank 104. However, the reliability of this function is limited by the capacity of capacitor bank 104. This solution has the following disadvantages: (1) The power that the supercapacitors of capacitor group 104 can provide is still relatively limited. Therefore, the power required to persist a large amount of data when a fault occurs is limited. (2) The amount of data written in a single QLC NAND is significantly larger than that of TLC NAND, and the write latency is significantly greater than that of TLC NAND. Therefore, under the premise of maintaining the same write throughput, the capacity requirement of on-chip DRAM increases significantly.Therefore, it is necessary to use high-cost low-power double data rate dynamic random access memory (LPDDR DRAM) as on-chip DRAM. Therefore, this solution will bring about a significant increase in cost. (3) There is a bandwidth limitation between the DRAM and the memory controller of the SSD controller, which leads to memory throughput bottlenecks and link bottlenecks, and then memory overflow. (4) After the on-chip DRAM capacity increases, the power-off protection function of the storage device 100 will become unstable due to device limitations. Under fluctuating conditions, the probability of data loss increases, which directly affects the data reliability and availability of the storage device 100. In view of the various disadvantages of using large-capacity DRAM as a write cache in the storage device 100, the embodiment of the present disclosure provides a technical solution for improving write performance and read performance in QLC SSD. Figure 2 is a schematic diagram of the architecture of a storage device provided by the embodiment of the present disclosure. As shown in FIG2 , the storage device 200 is a QLC SSD, including a controller 201 and a non-volatile memory 203. The controller 201 and the non-volatile memory 203 are connected, thereby establishing an electrical and communication connection between the controller 201 and the non-volatile memory 203. The non-volatile memory 203 includes an SLC memory cell group and a QLC memory cell group. Specifically, the SLC memory cell group includes multiple SLC memory cells (i.e., multiple SLC NAND cells), and the QLC memory cell group includes multiple QLC memory cells (i.e., multiple QLC NAND cells). Each SLC memory cell includes multiple cells, each storing one bit of data. Exemplarily, the SLC memory cell may be a pseudo single-level cell (pseudo single-level cell, abbreviated as pSLC) NAND cell. Each QLC memory cell includes multiple cells, each storing four bits of data. Controller 201 can control and implement functions such as communication and data transmission, receiving and parsing input / output (I / O) requests, and maintaining one or more request queues. In the disclosed embodiment, controller 201 can be used to control data write operations, including: receiving data to be written transmitted to storage device 200; caching the data to be written in the SLC storage cell group; and writing the data to be written cached in the SLC storage cell group to the QLC storage cell group.That is, in the disclosed embodiment, the SLC storage cell group serves as a write cache. Data written to the SLC storage cell group is temporarily stored in the SLC storage cell group. The backend asynchronously initiates a write operation from the SLC storage cell group to the QLC storage cell group, thereby persisting the data to be written to the QLC storage cell group. Figure 3 is a schematic diagram of the architecture of a storage device provided in the disclosed embodiment. As shown in Figure 3, storage device 300 is a QLC SSD, including a controller 201, a volatile memory 302, and a non-volatile memory 203. The controller 201 and the volatile memory 302 are connected, and the volatile memory 302 and the non-volatile memory 203 are connected. This allows for electrical and communication connections between the controller 201 and the volatile memory 302, as well as electrical and communication connections between the volatile memory 302 and the non-volatile memory 203. Volatile memory 302 may be SRAM or DRAM. Volatile memory 302 may be on-chip memory, such as on-chip DRAM, or off-chip memory, such as off-chip DRAM, which is not limited in the present embodiment. In other words, in storage device 300, volatile memory 302 and the SLC storage cell group may function as a parallel write cache. Specifically, under the control of the controller 201, the data to be written is preferentially cached in the volatile memory 202 (path A in FIG3 ), and then asynchronously written to the QLC storage cell group for persistence (path C in FIG3 ). When the volatile memory 202 encounters a capacity bottleneck or a throughput bottleneck, causing the cache of the volatile memory 202 to enter a saturated state, the data to be written is cached in the SLC storage cell group (path B in FIG3 ). The data written to the SLC storage cell group is temporarily stored in the SLC storage cell group until an SLC storage cell group is full. At this time, the backend asynchronously initiates a write operation from the SLC storage cell group to the QLC storage cell group, thereby persisting the data to be written in the QLC storage cell group.In the disclosed embodiments, the large-capacity SLC storage units configured within the non-volatile memory 203 (QLC NAND media) serve as a write cache. This overcomes the capacity limitations of volatile memory caches such as DRAM, leverages NAND's high concurrency and throughput advantages, and overcomes the bandwidth bottleneck of the DRAM controller. Furthermore, the non-volatility of SLC eliminates the power-failure protection required for corresponding volatile memory capacity. This eliminates the limitations imposed by the storage device's DRAM capacity, bandwidth, and power-failure protection, improving the write performance of the QLC SSD and narrowing the performance gap between QLC SSDs and TLC SSDs. This enables QLC SSDs to be used in a wider range of application scenarios, reducing costs through scale. It should be noted that the aforementioned application scenarios or examples provided in the disclosed embodiments are for ease of understanding and are not specifically limited in the disclosed embodiments. Furthermore, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display) involved in this disclosure are all authorized by the user or fully authorized by all parties. The collection, use, and processing of the relevant data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation portals are provided for users to select, edit, authorize, or reject. The following detailed description of the technical solutions of this disclosure and how they address the aforementioned technical issues is provided using specific embodiments. The specific embodiments listed above may be combined with each other, and identical or similar concepts or processes may not be described in detail in certain embodiments. The embodiments of this disclosure can be applied to the storage device 200 shown in FIG. FIG. 4 is a flowchart of a data processing method provided in this embodiment of the disclosure, which can be applied to the controller 201 of the storage device 200. That is, the data processing method can be implemented by the controller 201 of the storage device 200. As shown in FIG. 2 and FIG. 4 , the data processing method may include: Step S401: Receive data to be written to the storage device 200. The storage device 200 may be provided with a host interface for receiving data to be written, input by a host user. The data to be written is data that needs to be written to the storage device for persistence. When the storage device 200 is installed in an electronic device (host), the host interface can serve as an interface between the storage device and the electronic device, enabling interactive operations such as reading and writing data on the storage device 200.The host interface can be internally connected to the controller 201. During the corresponding data write process, the host interface transmits the data to be written, provided by the storage engine on the electronic device, to the controller 201. For example, when any application or electronic device transmits data to be written to the storage device 200, the controller 201 receives the data to be written and implements the write operation described below for the data to be written. Step S402: Cache the data to be written in the SLC storage cell group. For example, after receiving the data to be written, the controller 201 can write the data to be written to the SLC storage cell group of the non-volatile memory 203 for caching and provide feedback to the host indicating that the data was written successfully, thereby not affecting the host's perception of write latency. Step S403: Write the data to be written cached in the SLC storage cell group to the QLC storage cell group. Under the control of the controller 201, the data to be written cached in the SLC storage cell group can be asynchronously written to the QLC storage cell group of the non-volatile memory 203 for persistence. For example, when the storage space of a group of SLC storage cell groups is full, an asynchronous write operation can be initiated from the SLC storage cell groups to the QLC storage cell groups. For example, the backend bandwidth initiates a sequential large-block read operation from the SLC storage cell groups to a sequential large-block write operation in the QLC storage cell groups. In the disclosed embodiment, the SLC storage cell groups are used as write caches, temporarily storing data written to the SLC storage cell groups there. The backend asynchronously initiates the write operation from the SLC storage cell groups to the QLC storage cell groups. This eliminates limitations imposed by storage devices such as DRAM capacity, bandwidth, and power-failure protection, thereby improving the write performance of the QLC SSD. It should be noted that the controller 201 can be a multi-channel controller, with each channel corresponding to a cache channel formed by M1 SLC storage cell groups and a storage channel formed by M2 QLC storage cell groups. During write operations, the channels are initiated in parallel, thereby increasing throughput. M1 and M2 are positive integers and are not limited to 1. The ratio of M1 to M2 can be adjusted based on a balance between storage capacity and throughput, which is not limited in the presently disclosed embodiment. In one embodiment, in step S403, writing the to-be-written data cached in the SLC storage cell group to the QLC storage cell group may include: reading N data pages from the SLC storage cell group; and writing the read N data pages to N / 4 QLC storage cells, where N is a positive integer greater than or equal to 1.As previously mentioned, each SLC storage cell group includes multiple SLC storage cells. Each read operation can read a data page (also called a flash memory page) from each SLC storage cell. Assuming that each SLC storage cell group includes N SLC storage cells, each read operation can read N data pages from each SLC storage cell group. For example, FIG5 illustrates an asynchronous data migration process from an SLC storage cell group to a QLC storage cell group in accordance with an embodiment of the present disclosure. As shown in FIG5 , during the asynchronous data migration process from an SLC storage cell group to a QLC storage cell group, N data pages are read from each SLC storage cell group, folded and merged, and written to the page buffers of N / 4 QLC storage cells. Then, writing to these N / 4 QLC storage cells begins. For example, with an SLC storage cell group as one group and four QLC storage cell groups as four groups, the N data pages read from the SLC storage cell group are first written to the page cache of the N / 4 QLC storage cells in the first group; the N pages read from the SLC storage cell group a second time are written to the page cache of the N / 4 QLC storage cells in the second group; the N pages read from the SLC storage cell group a third time are written to the page cache of the N / 4 QLC storage cells in the third group; and the N pages read from the SLC storage cell group a fourth time are written to the page cache of the N / 4 QLC storage cells in the fourth group. After the four groups of QLC storage cells are successfully written, the above operation is repeated until all valid data in the SLC storage cell groups storing data is completely moved. Placing the N data pages read from the SLC storage cell group into different storage cell groups each time ensures uniformity in the data reading process, but the disclosed embodiments are not limited thereto and can be configured based on the grouping of storage cell groups and load requirements. As can be seen, in the technical solution of the disclosed embodiments, data migration from the SLC storage cell group to the QLC storage cell group is asynchronous noisy data migration. Specifically, the original data read from the SLC storage cell group is directly written to the QLC storage cell group. That is, during the data migration process from the SLC storage cells to the QLC storage cells, the controller does not need to perform data encoding and decoding to eliminate noise. This shortens the write time (or migration time) of the data to be written, which is cached in the SLC storage cell group, to the QLC storage cell group. It also reduces controller resource overhead, avoiding resource usage for concurrent host-side read and write operations.In one embodiment, writing the N read data pages into N / 4 QLC storage cells may include: in response to the presence of failed data blocks in the N read data pages, updating the mapping relationship between logical block addresses and physical block addresses of valid data blocks in the N read data pages, and sequentially writing the valid data blocks into the N / 4 QLC storage cells. A data page may include multiple data blocks, such as Logical Block Address (LBA) data blocks. In data storage, LBA is a common data addressing scheme, with each LBA corresponding to a specific data block. During data migration from an SLC storage cell group to a QLC storage cell group, data pages read from the SLC storage cell group may contain failed data blocks. In this case, only valid data blocks need to be fully copied, the mapping relationship between the valid data blocks from logical block addresses to physical block addresses (PBA) needs to be updated, and the valid data blocks need to be written sequentially into the QLC storage cell group. For example, if six LBA data blocks, ABCDEF, are read from an SLC storage cell group, and during the copy process, controller 201 detects that data blocks C and E have become invalid (e.g., they have been updated or deleted by the host), then there is no need to copy data blocks C and E; only valid data blocks ABDF need to be copied. Specifically, this can be accomplished by sequentially moving valid data blocks ABDF in units of LBA data block size and updating the LBA-to-PBA mapping to fill the "holes" in the six data blocks. This ensures correct data access and maximizes storage space utilization, avoiding space waste caused by "holes." In one embodiment, the method of this disclosed embodiment may further include: in response to data to be written cached in the SLC storage cell group being written to the QLC storage cell group, erasing the data to be written cached in the SLC storage cell group. When data in an SLC storage cell group is successfully moved to a QLC storage cell group, the data in the SLC storage cell group is erased, thereby placing the SLC storage cell group in a write cache resource pool to free up resources for subsequent cache allocation. In one embodiment, the method of the disclosed embodiment may further include updating a data refresh time for the QLC storage cell group in response to data to be written from the SLC storage cell group being written to the QLC storage cell group. The SLC storage cells and the QLC storage cells have different data retention capabilities.Each cell in an SLC storage unit stores only one bit of data, resulting in strong data retention. In contrast, each cell in a QLC storage unit stores four bits of data, resulting in relatively weak data retention. To improve write efficiency, the disclosed embodiment employs direct data copying with noise. This means that data is transferred asynchronously from the SLC storage unit group to the QLC storage unit group. Consequently, after a period of storage in the SLC storage unit group, some erroneous data bits (i.e., noise) are generated. These bits are then written directly to the QLC storage unit group without undergoing error correction code (ECC) decoding to correct the noise. Therefore, a predicted data refresh deadline is calculated based on the data retention capabilities of the SLC and QLC storage units. Data stored in the QLC storage units is then actively or passively refreshed before this deadline. This ensures that data is refreshed before it degrades to the point where it cannot be read correctly, thus preventing data from being read incorrectly and maintaining data integrity and readability. In one embodiment, an SLC storage cell group includes multiple SLC storage cells, and a QLC storage cell group includes multiple QLC storage cells. Two bits of data to be written are written into the upper two bits of the QLC storage cells, and two bits of preset padding data are written into the lower two bits of the QLC storage cells. The method of this embodiment of the present disclosure may further include: reading the data in the upper two bits of the QLC storage cells each time. Based on this, this embodiment of the present disclosure provides a scheme for asymmetrically writing data to and reading data from the QLC storage cells. Specifically, when writing data to the QLC storage cells, a write method is used in which four bits of data are stored per cell. Specifically, for each cell of the QLC storage cells, two bits of data to be written are written into the upper two bits, while two bits of preset padding data are written into the lower two bits, i.e., two bits of data are padded in a virtual mode. The preset padding data may be a preset value or a value generated according to an algorithm or rule, and this embodiment of the present disclosure is not limited thereto. Furthermore, when reading data from the QLC storage cells, a read method is used in which two bits of data are read per cell (similar to an MLC read method). Specifically, for each cell of the QLC storage unit, the upper two bits of data are read.Figure 6A illustrates write and read operations for a QLC storage cell in a related art solution. As shown in Figure 6A , when writing data to a QLC storage cell, four bits of original data to be written are stored per cell, corresponding to 16 voltage levels. Therefore, when reading data from the QLC storage cell, the data must be identified as belonging to one of the 16 voltage levels, requiring up to 15 reads, resulting in a longer read time. Figure 6B illustrates unbalanced write and read operations for a QLC storage cell in an embodiment of the present disclosure. As shown in Figure 6B , since the lower two bits are written with pre-set padding data during a write, only the upper two bits need to be read during a read, requiring only three reads at most. This indicates that the unbalanced write and read scheme of the present disclosure can significantly reduce read latency for QLC storage cells, thereby improving cache hit rate and read performance. In one embodiment, based on the above unbalanced write and read scheme, the present disclosure also provides a solution for a convertible MLC read cache and a non-convertible SLC read cache based on redundant capacity. Specifically, the stored data in the non-volatile memory 203 is divided into first stored data (hot data HS), second stored data (warm data HM), and third stored data (cold data C) based on access frequency from high to low. The QLC storage cell group includes a first QLC storage cell serving as usable capacity and a second QLC storage cell serving as redundant capacity. The SLC storage cell group is used to store the first stored data, and the first QLC storage cell is used to store the second and third stored data. The method of this embodiment of the present disclosure may further include: reading four bits of data from the first QLC storage cell where the second stored data is located; converting the read data into two data groups, wherein the upper two bits of data of each data group are derived from the read data, and the lower two bits of data of each data group are derived from preset padding data; and writing each data group into one first QLC storage cell. Exemplarily, the first stored data (hot data HS), the second stored data (warm data HM), and the third stored data (cold data C) are classified based on data access frequency and importance. For example, hot data is usually accessed and modified frequently, such as real-time transaction data and user session data; warm data is accessed less frequently than hot data; cold data is accessed less frequently than warm data and may not be accessed for a long time, but needs to be retained for various reasons (such as compliance, backup, etc.).Figure 7A is a schematic diagram of the media state at the moment the non-volatile memory 203 is fully written, according to an embodiment of the present disclosure. Figure 7B is a schematic diagram of the media state during the read caching process of the non-volatile memory 203, according to an embodiment of the present disclosure. Figures 7A and 7B illustrate the internal media conversion process of the non-volatile memory 203 after its nominal capacity is fully written. The following describes in detail the solutions for convertible MLC read caching and non-convertible SLC read caching based on redundant capacity, in conjunction with Figures 7A and 7B. Figure 7A illustrates the media state at the moment the non-volatile memory 203 is fully written. In Figure 7A, first stored data (e.g., hot data HS) and second stored data (e.g., warm data HM) are not differentiated and are both represented by "H." Third stored data is cold data and is represented by "C." As shown in Figure 7A , an SLC storage cell group functions as a write cache, with the cached data moved to a QLC storage cell group and erased. Each QLC storage cell group is divided into two parts: one part, consisting of first QLC storage cells, serves as usable capacity, and the other part, consisting of second QLC storage cells, serves as redundant capacity. Figure 7B illustrates the media state of non-volatile memory 203 during a read cache process. In Figure 7B , the first stored data is hot data, designated "HS"; the second stored data is warm data, designated "HM"; and the third stored data is cold data, designated "C." As shown in Figure 7B , using SLC storage cells to store hot data facilitates fast reads. On the other hand, as shown in FIG7B , a small number of redundant flash memory cells are reserved in the redundant capacity as the first redundant capacity for bad block replacement. The remaining storage capacity in the redundant capacity is used as the second redundant capacity, and data is written using the aforementioned non-balanced write and read method. Specifically, the upper two bits are used to write two bits of data to be written, while the lower two bits are used to write two bits of preset padding data. Simultaneously, a portion of the capacity equivalent to the second redundant capacity is used to store warm data. Data is written using the aforementioned non-balanced write and read method. Specifically, the QLC storage cells containing the warm data are read sequentially, and a group of 4-bit data is divided into two groups of 2-bit data. Two bits of preset padding data are appended to each group of 2-bit data to form a group of 4-bit data, which is then written to a cell of a QLC storage cell. This ensures that when a QLC storage cell group (for example, group A) is fully written with data, its data is adjusted and then written to the other two QLC storage cell groups. Furthermore, after writing each data group to a first QLC storage cell, the process may also include erasing the data in the first QLC storage cell where the second data is stored.For example, after the data in group A is moved, the data on it is erased and group A is recycled to free up space. The remaining capacity is used to store cold data, maintaining the read latency of the QLC storage unit. For example, Figure 8 illustrates data transfer in accordance with an embodiment of the present disclosure. As shown in Figure 8, a large page (super page) is used as a read unit. A read unit then contains two QLC pages, such as QLC page A and QLC page B. For each cell in QLC page A, the upper two bits of data are read and padded with the lower two bits of preset padding data, forming four bits of data that are then transferred to one read unit. Similarly, for each cell in QLC page B, the upper two bits of data are read and padded with the lower two bits of preset padding data, forming four bits of data that are then transferred to another read unit. As can be seen, based on the unbalanced write and read scheme of the embodiment of the present disclosure, each read still obtains data from a QLC page, ensuring the atomic read and concurrent read performance of the original data placement. The embodiments of the present disclosure can be applied to the storage device 300 shown in Figure 3 . Figure 9 is a flow chart of a data processing method provided by the embodiments of the present disclosure, which can be applied to the controller 201 of the storage device 300. Specifically, the data processing method can be implemented by the controller 201 of the storage device 200. As shown in Figures 3 and 9 , the data processing method may include the following: Step S901: Receiving data to be written to the storage device 300. The storage device 300 may be provided with a host interface for receiving data to be written input by a host user. The data to be written is data that needs to be written to the storage device for persistence. When the storage device 300 is installed in an electronic device (host), the host interface can serve as an interface between the storage device and the electronic device, enabling interactive operations such as reading and writing data on the storage device 300. The host interface can be internally connected to the controller 201. During the corresponding data writing process, the host interface transmits the data to be written, provided by the storage engine on the electronic device, to the controller 201. For example, when any application or electronic device transmits data to be written to the storage device 300, the controller 201 receives the data to be written and implements the following write operation for the data to be written. Step S902: Cache the data to be written to the volatile memory 302.For example, after receiving the data to be written, the controller 201 may write the data to be written into the volatile memory 302 for caching and provide feedback to the host indicating that the data has been written successfully, thereby preventing the host from experiencing write latency. Step S903: If the volatile memory 302 cache is full and there is uncached data to be written, the uncached data to be written is cached in the SLC storage cell group of the non-volatile memory 203. In other words, the volatile memory 302 and the SLC storage cell group of the non-volatile memory 203 can function as parallel write caches. Data to be written is preferentially cached in the volatile memory 202 (path A in FIG3 ). If the volatile memory 202 encounters a capacity bottleneck or a throughput bottleneck, causing the cache to be saturated, the data to be written is cached in the SLC storage cell group (path B in FIG3 ). The step of caching the data to be written in the SLC storage cell group of the non-volatile memory 203 can be seen in step S402 of the above embodiment and will not be repeated here. Step S904: The data to be written cached in the volatile memory 302 is written to the QLC storage cell group of the non-volatile memory 203. Under the control of the controller 201, the data to be written is preferentially cached in the volatile memory 202 (path A in FIG3 ) and then asynchronously written to the QLC storage cell group for persistence (path C in FIG3 ). Step S905: The data to be written cached in the SLC storage cell group is written to the QLC storage cell group. When a capacity bottleneck or throughput bottleneck occurs in the volatile memory 202, causing the volatile memory 202 to enter a cache saturation state, the data to be written is cached in the SLC storage cell group (path B in FIG3 ). The data written to the SLC storage cell group is temporarily stored in the SLC storage cell group until the SLC storage cell group is full. At this point, the backend asynchronously initiates a write operation from the SLC storage cell group to the QLC storage cell group, thereby persisting the data to be written in the QLC storage cell group. Step S905 can be implemented in the same or similar manner as step S403 in the above embodiment and will not be further described here. It should be noted that steps S904 and S905 can be executed concurrently, and the order of execution is not limited in this embodiment.Based on the solution of the embodiments of the present disclosure, when the volatile memory 302 within the storage device 300 encounters a capacity or throughput bottleneck, to match front-end write performance, in addition to the volatile memory 302 serving as a write cache, the SLC storage units of the non-volatile memory 203 are added as parallel write caches. This eliminates limitations imposed by the storage device's DRAM capacity, bandwidth, and power-loss protection, thereby improving the write performance of the QLC SSD. Furthermore, the embodiments of the present disclosure utilize the characteristics of QLC NAND media, allowing areas configured as SLC storage units to continue functioning as SLC write caches, thus avoiding the loss of lifespan caused by mode switching. Furthermore, for the non-volatile memory 203 as a whole, the data write mode remains unchanged, thus having no impact on the lifespan of the QLC NAND media. The areas of the SLC storage units can subsequently continue to function as QLC areas for reading and writing stored data. For example, FIG10 is an application example diagram of the data processing method provided by an embodiment of the present disclosure. As shown in FIG10 , after the host-side write traffic data begins to enter the storage device 200, the storage device 300 receives the user write data (i.e., data to be written) and preferentially places it into the volatile memory 302 (e.g., a DRAM write cache). A write success message is returned to the host. The backend asynchronously writes the data in the DRAM write cache to the QLC storage cell group after format integration. When a capacity bottleneck or a throughput bottleneck occurs, causing the volatile memory 202 to enter a cache saturation state, a switch is made to a parallel mode in which the DRAM and SLC storage cells are parallel write caches. Data outside the DRAM is cached from the controller 201 to the SLC storage cell group, and a write success message is returned to the host. The data written to the SLC storage cell group is temporarily stored in an area of ​​the SLC storage cell group until one SLC storage cell group is full. Then, a noisy copy is performed from the SLC storage cell group to the QLC storage cell group. After the data in one SLC storage cell group is copied, the SLC storage cell group in which all data has been copied is erased. Release (return) it to the SLC resource pool. It will be appreciated that, optionally, the method of the embodiment of the present disclosure may further include: in response to the data to be written cached in the SLC storage cell group being written to the QLC storage cell group, erasing the data to be written cached in the SLC storage cell group. For specific implementations, please refer to the relevant description of the above embodiment. Optionally, the method of the embodiment of the present disclosure may further include: in response to the data to be written in the SLC storage cell group being written to the QLC storage cell group, updating the data refresh time for the QLC storage cell group. For specific implementations, please refer to the relevant description of the above embodiment.Furthermore, the technical solutions of the embodiments of the present disclosure can also employ solutions that asymmetric data writes to and reads from QLC storage cells, a convertible MLC read cache based on redundant capacity, and a non-convertible SLC read cache. For specific implementations, please refer to the relevant descriptions of the aforementioned embodiments. In the embodiments of the present disclosure, the SLC configured within the non-volatile memory 203 (QLC NAND media) serves as a write cache, overcoming the capacity limitations of volatile memory caches such as DRAM and leveraging the high concurrency throughput advantages of NAND to overcome the bandwidth bottleneck of the DRAM controller. Furthermore, the non-volatility of SLC eliminates the power-failure protection required for corresponding volatile memory capacities. This eliminates the limitations of storage devices' DRAM capacity, bandwidth, and power-failure protection, improving the write performance of QLC SSDs and narrowing the performance gap between QLC SSDs and TLC SSDs. This enables QLC SSDs to be used in a wider range of application scenarios, reducing costs through scale. Furthermore, the technical solutions of the disclosed embodiments integrate SLC and QLC data retention management, enabling asynchronous, noisy data migration from SLC storage cell groups to QLC storage cell groups without requiring a controller. This achieves high-throughput, user-imperceptible asynchronous data migration and background refresh. Furthermore, based on the asymmetric design of data writes to and reads from QLC storage cells, a small amount of redundant capacity beyond the bad block management reserve can be reused. This significantly improves cache hit rates through a low-latency, large-capacity, two-bit read cache without impacting media lifespan. Using existing hardware, firmware and algorithm design improves the read and write performance of QLC SSDs. Corresponding to the application scenario and method of the method provided in the embodiments of the present disclosure, the embodiments of the present disclosure further provide a data processing device. The data processing device can be applied to a controller 201 of a storage device. The storage device also includes a non-volatile memory connected to the controller. The non-volatile memory includes an SLC storage cell group and a QLC storage cell group. The data processing device includes: a receiving module for receiving to-be-written data transmitted to the storage device; a cache control module for caching the to-be-written data in the SLC storage cell group; and a write control module for writing the to-be-written data cached in the SLC storage cell group into the QLC storage cell group.In one embodiment, a QLC storage cell group includes multiple QLC storage cells, and a cache control module is specifically configured to: read N data pages from an SLC storage cell group; and write the read N data pages into N / 4 QLC storage cells, where N is a positive integer greater than or equal to 1. In one embodiment, the cache control module is further configured to, in response to the presence of an invalid data block in the N read data pages, update the mapping relationship between the logical block addresses and physical block addresses of valid data blocks in the N read data pages, and sequentially write the valid data blocks into the N / 4 QLC storage cells. In one embodiment, the device further includes an erase module configured to, in response to data to be written cached in the SLC storage cell group being written into the QLC storage cell group, erase the data to be written cached in the SLC storage cell group. In one embodiment, the device further includes an update module configured to, in response to data to be written in the SLC storage cell group being written into the QLC storage cell group, update the data refresh time for the QLC storage cell group. In one embodiment, a QLC storage cell group includes multiple QLC storage cells. Two bits of to-be-written data are written into the upper two bits of the QLC storage cells, and two bits of preset padding data are written into the lower two bits of the QLC storage cells. In one embodiment, the device further includes a read control module configured to read data from the upper two bits of the QLC storage cells each time. In one embodiment, the stored data of the non-volatile memory is divided into first stored data, second stored data, and third stored data based on access frequency, from high to low. The QLC storage cell group includes a first QLC storage cell serving as usable capacity and a second QLC storage cell serving as redundant capacity. The SLC storage cell group is configured to store the first stored data, and the first QLC storage cell is configured to store the second and third stored data. In one embodiment, the device further includes a copy control module configured to: read four bits of data from the first QLC storage cell where the second stored data is located; convert the read data into two data groups, wherein the upper two bits of data in each data group are derived from the read data, and the lower two bits of data in each data group are derived from the preset padding data; and write one data group into one first QLC storage cell. In one embodiment, the copy control module is further configured to erase data in the first QLC storage unit where the second storage data is located.In one embodiment, the storage device further includes a volatile memory connected to the controller. The cache control module is further configured to cache the data to be written in the SLC storage cell group before writing it to the QLC storage cell. If the volatile memory cache is full and there is uncached data to be written, the uncached data to be written is cached in the SLC storage cell group. The write control module is further configured to write the data to be written cached in the volatile memory to the QLC storage cell group. The functions of each module in each apparatus of the disclosed embodiments can be found in the corresponding descriptions of the above-described methods, and they have corresponding beneficial effects, which are not further described here. The disclosed embodiments also provide an electronic device comprising a storage device in any of the above-described embodiments, such as storage device 200 or storage device 300. The storage device may be one or multiple, and the multiple storage devices may operate on the same or different principles, which is not limited in the disclosed embodiments. When the electronic device is used in different systems or fields, other components of the electronic device may vary. The other components of the electronic device of the above-described embodiments may adopt various technical solutions currently or in the future known to persons of ordinary skill in the art, and are not described in detail here. The above embodiments can be implemented in whole or in part via software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. A computer program product comprises one or more computer instructions. When the computer program instructions are loaded and executed on a computer, they fully or partially generate the processes or functions according to the present disclosure. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. Throughout this specification, references to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present disclosure. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and assemble the different embodiments or examples, and features of different embodiments or examples, described in this specification, without conflict. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.Thus, features defined as "first" or "second" may explicitly or implicitly include at least one of these features. In the description of this disclosure, "plurality" means two or more, unless otherwise specifically defined. Any process or method described in a flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a specific logical function or process step. Furthermore, the scope of the preferred embodiments of this disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions substantially simultaneously or in reverse order depending on the functions involved. The logic and / or steps described in a flowchart or otherwise herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or for use in conjunction with such an instruction execution system, apparatus, or device. It should be understood that various aspects of the present disclosure may be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods may be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above-described embodiments may be performed by a program instructing the relevant hardware. This program may be stored in a computer-readable storage medium. When executed, this program includes one or a combination of the steps of the method embodiments. Furthermore, the functional units in the various embodiments of the present disclosure may be integrated into a single processing module, each unit may exist physically separately, or two or more units may be integrated into a single module. These integrated modules may be implemented in either hardware or software functional modules. If these integrated modules are implemented as software functional modules and sold or used as standalone products, they may also be stored in a computer-readable storage medium. This storage medium may be a read-only memory, a magnetic disk, or an optical disk. The above are merely exemplary embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can readily conceive of various modifications or substitutions within the technical scope of the present disclosure, and such modifications or substitutions are intended to fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope of protection of the claims.Industrial Applicability: The solution provided by the embodiments of the present disclosure can use the SLC storage cells configured within the QLC NAND media as a write cache. This overcomes the capacity limitations of volatile memory caches such as dynamic random access memory, exploits the high concurrent throughput advantages of NAND flash memory, and overcomes the bandwidth bottleneck of the DRAM controller. Furthermore, the non-volatile nature of SLC eliminates the power-loss protection required for corresponding volatile memory capacity. This eliminates the limitations of DRAM capacity, bandwidth, and power-loss protection on storage devices, thereby improving the write performance of QLC solid-state drives and enabling QLC solid-state drives to be used in a wider range of application scenarios to reduce costs at scale.

Claims

Claims 1. A data processing method, applied to a controller of a storage device, wherein the storage device includes a non-volatile memory connected to the controller, the non-volatile memory including a single-layer SLC memory cell group and a quad-layer QLC memory cell group, the method comprising: receiving data to be written transmitted to the storage device; caching the data to be written into the SLC storage unit group; The data to be written cached in the SLC storage unit group is written into the QLC storage unit group.

2. The method according to claim 1, wherein: The QLC storage cell group includes a plurality of QLC storage cells, and writing the to-be-written data cached in the SLC storage cell group into the QLC storage cell group includes: reading N data pages from the SLC storage cell group; and writing the read N data pages into N / 4 of the QLC storage cells; wherein N is a positive integer and is greater than or equal to 1.

3. The method according to claim 2, wherein: Writing the read N data pages into N / 4 of the QLC storage cells includes: in response to a failed data block existing in the read N data pages, updating a mapping relationship between logical block addresses and physical block addresses of valid data blocks in the read N data pages; and writing the valid data blocks into the N / 4 of the QLC storage cells in sequence based on the updated mapping relationship.

4. The method according to claim 1, further comprising: In response to writing the to-be-written data cached in the SLC storage unit group into the QLC storage unit group, the to-be-written data cached in the SLC storage unit group is erased.

5. The method according to claim 1, further comprising: In response to writing the to-be-written data in the SLC storage cell group into the QLC storage cell group, a data refresh time of the QLC storage cell group is updated.

6. The method according to claim 1, wherein: The QLC storage cell group includes a plurality of QLC storage cells, wherein the upper two-bit data bits of the QLC storage cells are used to write two bits of data to be written, and the lower two-bit data bits of the QLC storage cells are used to write two bits of preset filling data.

7. The method according to claim 6, further comprising: The data in the upper two bits are read from the QLC storage unit each time.

8. The method according to claim 1 , wherein the storage data of the non-volatile memory is divided into first storage data, second storage data, and third storage data according to access frequency from high to low, the QLC storage cell group includes a first QLC storage cell used as usable capacity and a second QLC storage cell used as redundant capacity, the SLC storage cell group is used to store the first storage data, and the first QLC storage cell is used to store the second storage data and the third storage data.

9. The method according to claim 8, further comprising: Reading four bits of data from the first QLC storage unit where the second stored data is located; converting the read four bits of data into two four-bit data groups, wherein: The high-order two bits of data of each of the four-bit data groups come from the read four-bit data, and the low-order two bits of data of each data group come from preset padding data; and each data group is written into a corresponding first QLC storage unit.

10. The method according to claim 9, further comprising: Erasing the four bits of data in the first QLC storage unit where the second storage data is located.

11. The method according to any one of claims 1 to 10, wherein The storage device includes a volatile memory connected to the controller. Before writing the to-be-written data cached in the SLC storage cell group into the QLC storage cell, the method further includes: caching the to-be-written data in the volatile memory; and if the volatile memory cache is saturated and there is uncached data to be written, caching the uncached data to be written in the SLC storage cell group.

12. The method according to claim 11, further comprising: The data to be written cached in the volatile memory is written into the QLC storage unit group.

13. A storage device comprising a controller and a non-volatile memory connected to the controller, the non-volatile memory comprising an SLC storage cell group and a QLC storage cell group, the controller being configured to implement the method according to any one of claims 1 to 10.

14. The storage device according to claim 13, further comprising a volatile memory connected to the controller, wherein the controller is further configured to implement the method according to claim 11 or 12.

15. An electronic device comprising the storage device according to claim 13 or 14.

16. A computer program product comprising: A computer program, wherein when executed by a processor, the computer program implements the method according to any one of claims 1 to 10.

17. A computer program product comprising: A non-volatile computer-readable storage medium storing a computer program, wherein the computer program implements the method according to any one of claims 1 to 10 when executed by a processor.

18. A computer program, wherein When the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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