Sample-and-hold circuit and analog-to-digital conversion device

Abstract

A sample-and-hold circuit (1) is configured such that a plurality of sample-and-hold paths (11-1)-(11-N) to which a high-frequency signal is applied are connected in parallel, and an output circuit (12) that outputs the sum of signals outputted from the plurality of sample-and-hold paths (11-1)-(11-N) is provided therein. The sample-and-hold path (11-n) (n = 1, ..., N) of the sample-and-hold circuit (1) is provided with a switching element (11a-n) to one end of which the high-frequency signal is applied, and a capacitor (11b-n) one end of which is connected to the other end of the switching element (11a-n) and the other end of which is grounded. The switching elements (11a-n) provided in the plurality of sample-and-hold paths (11-1)-(11-n) are configured such that switching is controlled according to local signals having phases different from each other.

Description

Sample and hold circuit and analog-to-digital conversion device

[0001] The present disclosure relates to a sample-and-hold circuit and an analog-to-digital conversion device.

[0002] There is a sample-and-hold circuit that converts a high-frequency signal (hereinafter referred to as an "RF signal") into an intermediate frequency signal (hereinafter referred to as an "IF signal"). For example, Patent Document 1 discloses an example of such a sample-and-hold circuit that includes a switching element to one end of which the high-frequency signal is applied, and a capacitor having one end connected to the other end of the switching element and the other end grounded, and in which the opening and closing of the switching element is controlled in accordance with a local signal.

[0003] Japanese Utility Model Application Publication No. 57-166202

[0004] The sample-and-hold circuit disclosed in Patent Document 1 can improve the quantization accuracy of the IF signal by increasing the frequency of the local signal, but has the problem that increasing the frequency of the local signal increases phase noise, thereby degrading the signal-to-noise ratio of the IF signal.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a sample-and-hold circuit that can improve the quantization accuracy of an IF signal without increasing the frequency of the local signal.

[0006] A sample and hold circuit according to the present disclosure includes a plurality of sample and hold paths connected in parallel to receive a high-frequency signal, and an output circuit that outputs the sum of the signals output from the plurality of sample and hold paths. Each sample and hold path of the sample and hold circuit includes a switching element to which the high-frequency signal is received at one end, and a capacitor having one end connected to the other end of the switching element and the other end grounded, and the switching elements of the plurality of sample and hold paths are controlled to open or close in accordance with local signals that are out of phase with each other.

[0007] According to the present disclosure, it is possible to improve the quantization accuracy of the IF signal without increasing the frequency of the local signal.

[0008] 1 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to a first embodiment. FIG. 2 is an explanatory diagram showing the signal waveforms of an RF signal, an IF signal, and an LO signal when N=4. FIG. 3 is an explanatory diagram showing a desired signal included in an IF signal output from the sample-and-hold circuit disclosed in Patent Document 1 when the frequency of the RF signal is 16.1 GHz, and LO spurious and aliased spurious included in the IF signal. FIG. 4 is an explanatory diagram showing a desired signal included in an IF signal output from the sample-and-hold circuit 1 shown in FIG. 1 when N=4 and the frequency of the RF signal is 16.1 GHz, and LO spurious and aliased spurious included in the IF signal. FIG. 5 is an explanatory diagram showing the relative signal-to-noise ratio of an IF signal when N=1, 2, or 4 and the frequency of the LO signal is 4 GHz. FIG. 6 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to a second embodiment. FIG. 7 is an explanatory diagram showing the signal waveforms of an RF signal, an IF signal, and an LO signal when N=4. 7 is an explanatory diagram showing the maximum change in gain and the minimum noise in the analog-to-digital conversion device shown in FIG. 1 and the maximum change in gain and the minimum noise in the analog-to-digital conversion device shown in FIG. 6 .

[0009] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0010] First Embodiment Fig. 1 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to a first embodiment. The analog-to-digital conversion device shown in Fig. 1 comprises a sample-and-hold circuit 1 and an analog-to-digital converter (hereinafter referred to as "AD converter") 2. The sample-and-hold circuit 1 converts a high-frequency signal (hereinafter referred to as "RF signal") into an intermediate frequency signal (hereinafter referred to as "IF signal") and outputs the IF signal to the AD converter 2. The AD converter 2 converts the IF signal output from the sample-and-hold circuit 1 from an analog signal to a digital signal.

[0011] The sample and hold circuit 1 includes N sample and hold paths 11-1 to 11-N and an output circuit 12 that outputs the sum of the signals output from the sample and hold paths 11-1 to 11-N as an IF signal to the AD converter 2. N is an integer equal to or greater than 2. FIG. 1 shows an example where N=4. The N sample and hold paths 11-1 to 11-N are connected in parallel and are supplied with the same RF signal. Each sample and hold path 11-n (n=1, ..., N) includes a switching element 11a-n and a capacitor 11b-n.

[0012] The switching elements 11a-n (n=1, . . . , N) are realized by, for example, transistors. An RF signal is applied to one end of the switching elements 11a-n. The other end of the switching elements 11a-n is connected to one end of a capacitor 11b-n and to an input end of an adder 12a (described later) in the output circuit 12. The N switching elements 11a-1 to 11a-N are controlled to open and close in accordance with local signals (hereinafter referred to as "LO signals") that are out of phase with one another.

[0013] One end of the capacitor 11b-n (n = 1, ..., N) is connected to the other end of the switching element 11a-n and the input end of the adder 12a. The other end of the capacitor 11b-n is grounded. When the switching element 11a-n is in the closed state, the capacitor 11b-n is charged by the RF signal that has passed through the switching element 11a-n. When the switching element 11a-n is in the open state, the capacitor 11b-n discharges its electric charge.

[0014] The output circuit 12 includes an adder 12a. The input terminal of the adder 12a is connected to the other terminals of the switching elements 11a-n (n=1, . . . , N) and one terminal of the capacitor 11b-n. The output terminal of the adder 12a is connected to the AD converter 2. The adder 12a adds the voltages at one terminal of the N capacitors 11b-1 to 11b-N and outputs the sum of the voltages to the AD converter 2.

[0015] Next, the operation of the analog-to-digital conversion device shown in Fig. 1 will be described. Of the LO signals that control the opening and closing of N switching elements 11a-1 to 11a-N, the phase difference between adjacent LO signals is 2π / N, and each LO signal has a duty of 1 / N. For example, if N=4, the LO signal that controls the switching element 11a-1 (hereinafter referred to as "LO １ signal") that controls the switching element 11a-2, and an LO signal (hereinafter referred to as "LO ２ The phase difference between the LO signal and the ２ signal and an LO signal (hereinafter referred to as "LO") that controls the switching element 11a-3. ３ The phase difference between the LO signal and the LO signal is 2π / N. ３ signal and an LO signal (hereinafter referred to as "LO") that controls the switching element 11a-4. ４ The phase difference between the LO signal and the ４ Signal and LO １ The phase difference between the LO signal and the LO signal is 2π / N. １ Signal ~ LO ４ The signal has a duty of 25 (=1 / N=1 / 4×100)%.

[0016] Specifically, LO １ When the phase of the signal is used as a reference, for example, LO １ If the signal phase is 0 degrees, LO ２ The signal phase is 90 degrees, LO ３ The signal phase is 180 degrees, LO ４ The phase of the signal is 270 degrees. The period during which the switching elements 11a-n (n=1, . . . , N) are in the open state is one-fourth of the total period. １ During the period when the switching element 11a-1 is in the open state due to the signal, the switching elements 11a-2, 11a-3, and 11a-4 are in the closed state, and the LO ２ During the period when the switching element 11a-2 is in the open state due to the signal, the switching elements 11a-1, 11a-3, and 11a-4 are in the closed state. ３During the period when the switching element 11a-3 is in the open state due to the signal, the switching elements 11a-1, 11a-2, and 11a-4 are in the closed state, and the LO ４ During the period in which the switching element 11a-4 is in the open state due to the signal, the switching elements 11a-1, 11a-2, and 11a-3 are in the closed state.

[0017] 2A and 2B are explanatory diagrams showing the signal waveforms of the RF signal, the IF signal, and the LO signal when N=4. ｎ During the period when the switching elements 11a-n (n=1, ..., 4) are in the closed state by the signal, a charge corresponding to the voltage of the RF signal is stored in the capacitor 11b-n. During the period when the switching elements 11a-n are in the closed state, the voltage at one end of the capacitor 11b-n follows the voltage of the RF signal. This mode in which the voltage at one end of the capacitor 11b-n follows the voltage of the RF signal is called the sample mode. After that, LO ｎ When a signal causes switching element 11a-n to transition to the open state, the voltage at one end of capacitor 11b-n is fixed according to the charge stored in switching element 11a-n immediately before the switching element 11a-n transitions to the open state. In other words, the voltage of the RF signal immediately before the switching element 11a-n transitions to the open state is held by capacitor 11b-n, and the voltage at one end of capacitor 11b-n is fixed to the voltage of the RF signal immediately before the switching element 11a-n transitions to the open state. This mode in which the voltage at one end of capacitor 11b-n is fixed to the voltage of the RF signal immediately before the switching element 11a-n transitions to the open state is called a hold mode. Therefore, during the period in which switching element 11a-n is in the closed state, the voltage of the RF signal is applied to the input end of adder 12a, and during the period in which switching element 11a-n is in the open state, the voltage of the RF signal immediately before the switching element 11a-n transitions to the open state is applied to the input end of adder 12a.

[0018] During a period in which switching element 11a-1 is in an open state, the voltage held by capacitor 11a-1, the voltage of the RF signal that has passed through switching element 11a-2, the voltage of the RF signal that has passed through switching element 11a-3, and the voltage of the RF signal that has passed through switching element 11a-4 are applied to the input terminal of adder 12a. During a period in which switching element 11a-2 is in an open state, the voltage of the RF signal that has passed through switching element 11a-1, the voltage held by capacitor 11b-2, the voltage of the RF signal that has passed through switching element 11a-3, and the voltage of the RF signal that has passed through switching element 11a-4 are applied to the input terminal of adder 12a. During a period in which switching element 11a-3 is in an open state, the voltage of the RF signal that has passed through switching element 11a-1, the voltage of the RF signal that has passed through switching element 11a-2, the voltage held by capacitor 11b-3, and the voltage of the RF signal that has passed through switching element 11a-4 are applied to the input terminal of adder 12a. During the period when switching element 11a-4 is in the open state, the voltage of the RF signal that has passed through switching element 11a-1, the voltage of the RF signal that has passed through switching element 11a-2, the voltage of the RF signal that has passed through switching element 11a-3, and the voltage held by capacitor 11b-4 are applied to the input terminal of adder 12a.

[0019] Therefore, the input terminal of the adder 12a is applied with a voltage maintained by a capacitor having one end connected to the other end of any one of the switching elements 11a-1 to 11a-4 that is in an open state, and the voltage of the RF signal that has passed through each of the three switching elements that are in a closed state. The adder 12a adds the four applied voltages. As shown in FIG. 2, the adder 12a outputs the result of the voltage addition to the AD converter 2 as an IF signal. In the example of FIG. 2, the frequency of the IF signal is one-fourth the frequency of the RF signal.

[0020] The AD converter 2 acquires the IF signal from the sample and hold circuit 1. The AD converter 2 converts the IF signal from an analog signal to a digital signal and outputs the digital signal to, for example, a receiver (not shown). The signal waveform of the IF signal output from the sample and hold circuit 1 to the AD converter 2 differs from the signal waveform of the IF signal output from the sample and hold circuit of Patent Document 1 when the frequency of the local signal is multiplied by N. Even if the waveform of the IF signal output from the sample and hold circuit 1 differs from the signal waveform of the IF signal output from the sample and hold circuit of Patent Document 1, the AD converter 2 can convert the analog signal into a digital signal using the same AD conversion process.

[0021] Fig. 3 is an explanatory diagram showing a desired signal included in an IF signal output from the sample-and-hold circuit disclosed in Patent Document 1 when the frequency of the RF signal is 16.1 GHz, and LO spurious and alias spurious included in the IF signal. Fig. 4 is an explanatory diagram showing a desired signal included in an IF signal output from the sample-and-hold circuit 1 shown in Fig. 1 when N = 4 and the frequency of the RF signal is 16.1 GHz. In Figs. 3 and 4, the horizontal axis represents the frequency [GHz] of the IF signal, and the vertical axis represents the power [dBm] of the IF signal. In the case of the sample-and-hold circuit disclosed in Patent Document 1, as shown in Fig. 3, large LO spurious and large alias spurious are generated at 4 GHz, 8 GHz, 12 GHz, 16 GHz, and 20 GHz in addition to the desired signal. In the case of the sample-and-hold circuit 1 shown in FIG. 1, as shown in FIG. 4, the LO spurious and aliasing spurious are reduced compared to the sample-and-hold circuit disclosed in Patent Document 1.

[0022] FIG. 5 is an explanatory diagram showing the relative signal-to-noise ratio (hereinafter referred to as "relative SN") of the IF signal when N=1, 2, or 4 and the frequency of the LO signal is 4 GHz. FIG. 5 shows that when N=1, the relative SN deteriorates as the frequency of the RF signal increases. FIG. 5 shows that when N=2, the deterioration of the relative SN is suppressed compared to when N=1. FIG. 5 shows that when N=4, the deterioration of the relative SN is suppressed compared to when N=2. When the frequency of the RF signal is RF, the frequency of the LO signal is LO, and the number of sample-and-hold paths 11 is N, a high relative SN can be obtained if the sample-and-hold circuit 1 includes as many sample-and-hold paths 11 as N such that the frequency RF of the RF signal satisfies the following equation (1): LO×N<RF<LO×(N+1) (1)

[0023] In the first embodiment described above, the sample-and-hold circuit 1 is configured such that a plurality of sample-and-hold paths 11-1 to 11-N, each receiving a high-frequency signal, are connected in parallel, and the sample-and-hold circuit 1 includes an output circuit 12 that outputs the sum of the signals output from the plurality of sample-and-hold paths 11-1 to 11-N. Each of the sample-and-hold paths 11-n (n = 1, ..., N) of the sample-and-hold circuit 1 includes a switching element 11a-n, one end of which receives a high-frequency signal, and a capacitor 11b-n, one end of which is connected to the other end of the switching element 11a-n and the other end of which is grounded. The switching elements 11a-n of the plurality of sample-and-hold paths 11-1 to 11-N are configured so that their switching operations are controlled in accordance with local signals that are out of phase with each other. Therefore, the sample-and-hold circuit 1 can improve the quantization accuracy of the IF signal without increasing the frequency of the local signal.

[0024] Second Embodiment In a second embodiment, a sample-and-hold circuit 1 in which an output circuit 12 includes a plurality of common-drain transistors 12b-1 to 12b-N and a constant current source 12c will be described.

[0025] 6 is a configuration diagram showing an analog-to-digital conversion device including a sample-and-hold circuit 1 according to the second embodiment. The output circuit 12 includes drain-grounded transistors 12b-1 to 12b-N and a constant current source 12c. An example where N=4 is shown in FIG.

[0026] The common-drain transistors 12b-n (n=1, . . . , N) are source follower circuits. The gate terminals of the common-drain transistors 12b-n are connected to the other end of the switching elements 11a-n and one end of the capacitors 11b-n. The source terminals of the common-drain transistors 12b-n are connected to the constant current source 12c. The drain terminals of the common-drain transistors 12b-n are grounded.

[0027] The constant current source 12c is realized by, for example, a current mirror circuit, and supplies a constant current to the source terminals of the common-drain transistors 12b-1 to 12b-N.

[0028] Next, the operation of the analog-to-digital converter shown in Fig. 6 will be described. Except for the common-drain transistors 12b-n (n = 1, ..., N) and the constant current source 12c, the analog-to-digital converter is the same as that shown in Fig. 1. Therefore, only the operation of the common-drain transistors 12b-n and the constant current source 12c will be described here.

[0029] 1, the output circuit 12 is realized by an adder 12a. Therefore, when the sample-and-hold path 11-n is in the hold mode, the charge stored in the capacitor 11b-n may leak to other sample-and-hold paths via the adder 12a. The leaking of charge to other sample-and-hold paths causes degradation of the signal-to-noise ratio (SN) of the IF signal.

[0030] The constant current source 12c supplies a constant current to the source terminals of the grounded-drain transistors 12b-1 to 12b-N. When the voltage of the RF signal that has passed through the switching element 11a-n or the voltage held by the capacitor 11b-n is applied to the gate terminal of the grounded-drain transistor 12b-n, the grounded-drain transistor 12b-n outputs the voltage applied to the gate terminal to the source terminal. On the other hand, the grounded-drain transistor 12b-n does not output the voltage of the source terminal to the gate terminal. Therefore, when the sample-and-hold path 11-n is in the hold mode, there is almost no possibility that the charge stored in the capacitor 11b-n will leak to other sample-and-hold paths via the grounded-drain transistor 12b-n, thereby degrading the signal-to-noise ratio of the IF signal. FIG. 7 is an explanatory diagram showing the signal waveforms of the RF signal, the IF signal, and the LO signal when N=4.

[0031] As is clear from a comparison of Fig. 7 and Fig. 2, the analog-to-digital conversion device shown in Fig. 6 has reduced waveform distortion of the IF signal compared to the analog-to-digital conversion device shown in Fig. 1. Therefore, the analog-to-digital conversion device shown in Fig. 6 has an improved SN ratio of the IF signal compared to the analog-to-digital conversion device shown in Fig. 1.

[0032] Fig. 8 is an explanatory diagram showing the maximum change gain and minimum noise in the analog-digital conversion device shown in Fig. 1 and the maximum change gain and minimum noise in the analog-digital conversion device shown in Fig. 6. Fig. 8 shows that the maximum change gain of the analog-digital conversion device shown in Fig. 6 is improved compared to the maximum change gain of the analog-digital conversion device shown in Fig. 1, and the minimum noise of the analog-digital conversion device shown in Fig. 6 is lower than the minimum noise of the analog-digital conversion device shown in Fig. 1.

[0033] In the second embodiment described above, the sample and hold circuit 1 shown in Fig. 6 is configured so that the output circuit 12 includes a plurality of common-drain transistors 12b-1 to 12b-N, each having a gate terminal connected to one end of each of the capacitors 11b-n and a grounded drain terminal, and a constant current source 12c that supplies a constant current to the source terminals of the plurality of common-drain transistors 12b-1 to 12b-N. Therefore, the sample and hold circuit 1 shown in Fig. 6 can improve the quantization accuracy of the IF signal without increasing the frequency of the local signal, and can also improve the SNR of the IF signal more than the sample and hold circuit 1 shown in Fig. 1.

[0034] 6, the sample-and-hold path 11-n includes a capacitor 11b-n. However, this is merely an example, and instead of the capacitor 11b-n, the parasitic capacitance of the common-drain transistor 12b-n may serve as the capacitor 11b-n.

[0035] 6, the output circuit 12 includes a plurality of common-drain transistors 12b-1 to 12b-N. However, this is merely an example, and the output circuit 12 may use, for example, common-source transistors instead of the common-drain transistors 12b-n.

[0036] In addition, the present disclosure allows for free combination of the respective embodiments, modification of any of the components of the respective embodiments, or omission of any of the components of the respective embodiments.

[0037] The present disclosure is suitable for sample-and-hold circuits and analog-to-digital conversion devices.

[0038] 1 sample and hold circuit, 2 AD converter, 11-1 to 11-4 sample and hold paths, 11a-1 to 11a-4 switching elements, 11b-1 to 11b-4 capacitors, 12 output circuit, 12a adder, 12b-1 to 12b-4 drain-grounded transistors, 12c constant current source.

Claims

1. A sample and hold circuit comprising: a plurality of sample and hold paths to which a high frequency signal is applied connected in parallel; and an output circuit that outputs the sum of the signals output from said plurality of sample and hold paths; each sample and hold path comprising: a switching element to one end of which the high frequency signal is applied; and a capacitor having one end connected to the other end of said switching element and the other end grounded; and the switching elements of said plurality of sample and hold paths are controlled to open and close in accordance with local signals having mutually different phases.

2. The sample-and-hold circuit according to claim 1, wherein the output circuit includes an adder that adds the voltages at one end of the plurality of capacitors and outputs the result of the addition of the voltages.

3. The sample-and-hold circuit according to claim 1, wherein the output circuit comprises a plurality of drain-grounded transistors, each having a gate terminal connected to one end of the capacitor and a drain terminal grounded, and a constant current source that supplies a constant current to the source terminals of the plurality of drain-grounded transistors.

4. The sample-and-hold circuit according to claim 1, characterized in that, when the frequency of the high-frequency signal is RF, the frequency of the local signal is LO, and the number of sample-and-hold paths is N, the number of sample-and-hold paths satisfies LO×N<RF<LO×(N+1).

5. A sample-and-hold circuit according to claim 4, characterized in that, among a plurality of local signals that control the opening and closing of each switching element, the phase difference between local signals that are adjacent in phase is 2π / N, and each local signal has a duty of 1 / N.

6. An analog-to-digital conversion device comprising: a sample-and-hold circuit according to any one of claims 1 to 5; and an analog-to-digital converter that converts the signal output from said sample-and-hold circuit from an analog signal to a digital signal.

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