Method for manufacturing semiconductor module, and semiconductor module

Abstract

This method for manufacturing a semiconductor module including a semiconductor element comprises: a first bonding step of bonding a component to a support substrate; a second bonding step of bonding the support substrate to a heat dissipation member by means of a bonding layer with a pressure lower than that of the first bonding step; and a molding step of forming a sealing resin covering the semiconductor element. The component and the heat dissipation member are bonded on the opposite sides to each other with respect to the support substrate in the thickness direction of the support substrate. The second bonding step is performed after the first bonding step. The molding step is performed after the second bonding step.

Description

Semiconductor module manufacturing method and semiconductor module

[0001] The present disclosure relates to a method for manufacturing a semiconductor module and a semiconductor module.

[0002] Conventionally, semiconductor devices incorporating semiconductor elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) have been widely known. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in Patent Document 1 includes a substrate (a heat sink in Patent Document 1) on which the semiconductor elements are mounted, a sealing resin (a sealing body in Patent Document 1) that covers a portion of the substrate and the semiconductor elements, and a heat dissipation member (a heat dissipation fin in Patent Document 1) that faces the substrate. The sealing resin is attached to the heat dissipation member via screws. This improves the heat dissipation performance of the semiconductor device.

[0003] In addition to the semiconductor device disclosed in Patent Document 1, a semiconductor device in which a substrate is bonded to a heat dissipation member via a bonding layer is also considered. In such a semiconductor device, the work of attaching a sealing resin to a heat dissipation member is not required. However, when attempting to bond the substrate to the heat dissipation member after forming the sealing resin, there is a concern that the sealing resin may lose its shape if the temperature at which the bonding layer is formed is relatively high.

[0004] International Publication No. 2019 / 239997

[0005] [Summary] An object of the present disclosure is to provide an improved semiconductor module compared to conventional semiconductor modules. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor module (and a manufacturing method thereof) that can better maintain the shape of the sealing resin.

[0006] A manufacturing method for a semiconductor module provided by a first aspect of the present disclosure is a manufacturing method for a semiconductor module including a semiconductor element, comprising: a first bonding process for bonding a component to a support substrate; a second bonding process for bonding the support substrate to a heat dissipation member using a bonding layer at a pressure lower than that of the first bonding process; and a molding process for forming a sealing resin that covers the semiconductor element, wherein the component and the heat dissipation member are bonded on opposite sides of the support substrate in the thickness direction of the support substrate, and the second bonding process is performed after the first bonding process, and the molding process is performed after the second bonding process.

[0007] A semiconductor module provided by a second aspect of the present disclosure comprises a semiconductor element, a support substrate to which the semiconductor element is bonded and which supports the semiconductor element, a sealing resin covering the semiconductor element, a heat dissipation member to which the support substrate is bonded, a bonding layer which bonds the heat dissipation member and the support substrate, and a power terminal electrically connected to the semiconductor element, wherein the semiconductor element and the heat dissipation member are bonded on opposite sides of the support substrate in the thickness direction, the sealing resin has a resin back surface in contact with the heat dissipation member and a resin main surface facing the opposite side to the resin back surface in the thickness direction, a side of the bonding layer facing in a direction perpendicular to the thickness direction is covered with the sealing resin, and the power terminal is exposed at the resin main surface.

[0008] FIG. 1 is a perspective view showing a semiconductor module according to a first embodiment. FIG. 2 is a view of the perspective view of FIG. 1 , with the sealing resin of each semiconductor package omitted. FIG. 3 is a perspective view (different from FIG. 1 ) showing a semiconductor module according to the first embodiment. FIG. 4 is a plan view showing a semiconductor module according to the first embodiment. FIG. 5 is a front view showing a semiconductor module according to the first embodiment. FIG. 6 is a bottom view showing a semiconductor module according to the first embodiment. FIG. 7 is a rear view showing a semiconductor module according to the first embodiment. FIG. 8 is a left side view showing a semiconductor module according to the first embodiment. FIG. 9 is a partially enlarged plan view of a portion of FIG. 4 . FIG. 10 is a view of FIG. 9 , with multiple power terminals omitted. FIG. 11 is a view of FIG. 9 , with the heat dissipation member omitted and the sealing resin shown in imaginary lines. FIG. 12 is a view of FIG. 11 , with the multiple power terminals omitted. FIG. 13 is a view of FIG. 12 , with one of two conductive members and the sealing resin omitted. FIG. 14 is a diagram of FIG. 13 with the other of the two conductive members omitted. FIG. 15 is a bottom view showing one of the multiple semiconductor packages of the semiconductor module according to the first embodiment. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 11. FIG. 17 is a partially enlarged cross-sectional view of FIG. 16. FIG. 18 is a partially enlarged cross-sectional view of FIG. 16 (a portion different from FIG. 17). FIG. 19 is a partially enlarged cross-sectional view of FIG. 16 (a portion different from FIG. 17 and FIG. 18). FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 11. FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 11. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 11. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 11. FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 11. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 11. Fig. 26 is a flowchart showing a method for manufacturing a semiconductor module according to the first embodiment. Fig. 27 is a cross-sectional view showing a step (element bonding step) of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to the cross section of Fig. 25. Fig. 28 is a cross-sectional view showing a step (support substrate bonding step) of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to the cross section of Fig. 25.29 is a cross-sectional view showing a step (conductive member joining step, sleeve joining step, and thermistor joining step) of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 30 is a cross-sectional view showing a step (molding step) of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 31 is a plan view showing a step (molding step) of the method for manufacturing the semiconductor module according to the first embodiment. FIG. 32 is a cross-sectional view showing a step (molding step) of the method for manufacturing the semiconductor module according to the first embodiment, and corresponds to the cross section of FIG. 25 . FIG. 33 is a flowchart showing another example of the method for manufacturing the semiconductor module according to the first embodiment. FIG. 34 is a front view showing a power conversion unit including the semiconductor module according to the first embodiment. FIG. 35 is an enlarged cross-sectional view of a main part of the power conversion unit shown in FIG. 34 . FIG. 36 is a front view showing another example of the configuration of the power conversion unit including the semiconductor module according to the first embodiment. FIG. 37 is a schematic diagram of a vehicle including a power conversion unit including the semiconductor module according to the first embodiment. FIG. 38 is a bottom view showing a semiconductor module according to a first modified example of the first embodiment. FIG. 39 is a front view showing a semiconductor module according to a second modified example of the first embodiment. FIG. 40 is a plan view showing a semiconductor module according to the second embodiment. FIG. 41 is a cross-sectional view showing the semiconductor module shown in FIG. 40 , corresponding to the cross section of FIG. 20 . FIG. 42 is a front view showing a semiconductor module according to the third embodiment. FIG. 43 is a cross-sectional view showing a semiconductor module according to a modified example of the third embodiment, corresponding to the cross section of FIG. 25 . FIG. 44 is a plan view showing a semiconductor module according to the fourth embodiment. FIG. 45 is a cross-sectional view showing another configuration example (first modified example) of the semiconductor package, corresponding to the cross section of FIG. 20 . FIG. 46 is a cross-sectional view showing the semiconductor package shown in FIG. 45 , corresponding to the cross section of FIG. 25 . FIG. 47 is a cross-sectional view showing another configuration example (second modified example) of the semiconductor package, corresponding to the cross section of FIG. 20 . FIG. 48 is a cross-sectional view showing another configuration example (third modified example) of the semiconductor package, corresponding to the cross section of FIG. 20 . FIG. 49 is a plan view showing another configuration example (fourth modified example) of the semiconductor package.Fig. 50 is a perspective view showing another configuration example (fifth modification) of the semiconductor package. Fig. 51 is a plan view showing the semiconductor package shown in Fig. 50, with the sealing resin shown by imaginary lines. Fig. 52 is a cross-sectional view taken along line LII-LII in Fig. 51.

[0009] DETAILED DESCRIPTION A preferred embodiment of the semiconductor module of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant description will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps part of object B." "Object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." "A surface A faces in a certain direction B (one side or the other side of a certain direction B)" does not necessarily mean that surface A is at a 90° angle with respect to direction B, but also includes surface A being tilted relative to direction B. "A surface A is perpendicular to surface B" does not necessarily mean that surface A is at a 90° angle with respect to surface B, but also includes surface A being tilted relative to surface B, unless otherwise specified. Unless otherwise specified, the phrase "an object A (surface A) is parallel to an object B (surface B)" is not limited to a strict definition, and includes cases where an object A (surface A) is tilted relative to an object B (surface B) (for example, a slight deviation due to a manufacturing error).

[0011] 1 to 25 show a semiconductor module A10 according to a first embodiment. The semiconductor module A10 includes three semiconductor packages B10 and a heat dissipation member C10. The semiconductor module A10 is used, for example, in an inverter for driving a three-phase AC motor, but the use of the semiconductor module A10 is not limited to this.

[0012] For ease of explanation, reference will be made to the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of the semiconductor module A10. "Planar view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. Terms such as "above," "below," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0013] The three semiconductor packages B10 are each bonded to a heat dissipation member C10. In a plan view, the heat dissipation member C10 has a rectangular shape with the first direction x as its longitudinal direction. The plan view shape of the heat dissipation member C10 is not limited to the example shown. The three semiconductor packages B10 are each arranged on the heat dissipation member C10 along the first direction x. A detailed configuration example of each semiconductor package B10 will be described later. In the semiconductor module A10, the number of semiconductor packages B10 is not limited to three, and may be one or more.

[0014] The heat dissipation member C10 supports the multiple semiconductor packages B10. The heat dissipation member C10 is, for example, a heat sink. Most of the heat dissipation member C10 is located below the multiple semiconductor packages B10 in the thickness direction z (on the z1 side). The heat dissipation member C10 faces the bottom surface (the surface facing the z1 side in the thickness direction z) of each of the multiple semiconductor packages B10. The material of the heat dissipation member C10 includes, for example, aluminum. The material is not limited to aluminum, and may be other metal materials or resin materials (preferably those with good thermal conductivity). The heat dissipation member C10 includes a housing 70, an inlet portion 72, an outlet portion 73, and a heat dissipation portion 75.

[0015] The housing 70 is box-shaped and has a hollow structure. As shown in Figures 16 and 20 to 25, the housing 70 includes a hollow portion 701. The hollow portion 701 is located inside the housing 70. The housing 70 includes a top plate 71 and a case portion 74.

[0016] The top plate 71 has a flat plate shape. The top plate 71 has, for example, a rectangular shape in a plan view. The shape of the top plate 71 in a plan view is not limited in any way. The plurality of semiconductor packages B10 are mounted on the top plate 71. The plurality of semiconductor packages B10 are arranged on the top plate 71 along the first direction x. The top plate 71 faces the bottom surface of each of the plurality of semiconductor packages B10.

[0017] The top plate 71 has a main surface 71a and a back surface 71b. As shown in Figures 5, 7, and 8, the main surface 71a and the back surface 71b are spaced apart in the thickness direction z. The main surface 71a and the back surface 71b face opposite each other in the thickness direction z. The main surface 71a faces upward in the thickness direction z, and the back surface 71b faces downward in the thickness direction z. The main surface 71a faces the multiple semiconductor packages B10. Each of the multiple semiconductor packages B10 is bonded to the main surface 71a.

[0018] The top plate 71 includes a main portion 711 and an outer peripheral portion 712. The main portion 711 overlaps each of the multiple semiconductor packages B10 in a plan view. The multiple semiconductor packages B10 are bonded to the main portion 711. In this embodiment, the main portion 711 is rectangular in a plan view. The outer peripheral portion 712 surrounds the periphery of the main portion 711 in a plan view. The outer peripheral portion 712 forms a ring shape surrounding the main portion 711 in a plan view of the top plate 71. The outer peripheral portion 712 is sandwiched by a mold (mold M10 described below) used to form the sealing resin 50. The outer peripheral portion 712 is located outside the multiple semiconductor packages B10 in a plan view. As shown in FIG. 6 , the outer peripheral portion 712 has multiple through holes 712a formed therein. The multiple through holes 712a penetrate the top plate 71 (the outer peripheral portion 712) in the thickness direction z. Each of the plurality of through holes 712a can be used as a mounting hole when mounting the semiconductor module A10 to a housing (frame, etc.) of an electronic device or an electric vehicle, or as a positioning hole for a mold M10 described later.

[0019] The case portion 74 has a bottomed, hollow rectangular parallelepiped shape. The case portion 74 is attached to the back surface 71b. In the illustrated example, the periphery of the case portion 74 in a plan view is enclosed within the periphery of the top plate 71 in a plan view. The surface of the case portion 74 on the z2 side in the thickness direction z is open. The top plate 71 closes the opening on the z2 side in the thickness direction z of the case portion 74. The case portion 74 has a bottom plate and a frame plate interposed between the bottom plate and the top plate 71 and having an annular shape when viewed in the thickness direction z. In the case portion 74, the bottom plate and the frame plate are integrally formed, but may be separate bodies. The top plate 71 and the case portion 74 define a hollow portion 701 inside the housing 70. The case portion 74 is hermetically joined to the top plate 71 with a joining material (not shown). The case portion 74 may also be joined to the top plate 71 by welding.

[0020] The inlet portion 72 and the outlet portion 73 are each connected to the hollow portion 701. In the illustrated example, the inlet portion 72 and the outlet portion 73 are located on opposite sides of the hollow portion 701 in the first direction x. The arrangement of the inlet portion 72 and the outlet portion 73 may be opposite to that shown in the illustrated example. The inlet portion 72 and the outlet portion 73 are each cylindrical. The heat dissipation member C10 is configured so that a fluid (e.g., a refrigerant) flows from the inlet portion 72 through the hollow portion 701 to the outlet portion 73. Thus, the inlet portion 72 and the outlet portion 73 are inlet and outlet ports for the fluid into the hollow portion 701. In the illustrated example, the openings of the inlet portion 72 and the outlet portion 73 face the first direction x. The number, shape, and arrangement of the inlet portions 72 and the number, shape, and arrangement of the outlet portions 73 are not limited to those shown in the illustrated example. For example, the openings of the inlet portion 72 and the outlet portion 73 are not limited to those facing sideways (first direction x), but may face upward or downward in the thickness direction z.

[0021] As shown in Figures 3 and 5, the heat dissipation section 75 protrudes in the thickness direction z from the back surface 71b of the top plate 71. The heat dissipation section 75 is located on the opposite side of the top plate 71 from each semiconductor package B10 in the thickness direction z. The heat dissipation section 75 is contained in the hollow section 701. When the heat dissipation section 75 comes into contact with the fluid flowing through the hollow section 701, heat is transferred from the heat dissipation section 75 to the fluid. The heat dissipation section 75 is formed integrally with the top plate 71, but may be formed separately.

[0022] The heat dissipation unit 75 includes a plurality of heat dissipation fins 751. The plurality of heat dissipation fins 751 contact the rear surface 71b. The plurality of heat dissipation fins 751 extend downward in the thickness direction z from the rear surface 71b. In this embodiment, the plurality of heat dissipation fins 751 are pin fins and rod-shaped metal bodies. The plurality of heat dissipation fins 751 are spaced apart from one another in a direction perpendicular to the thickness direction z. In the illustrated example (e.g., FIG. 6 ), each heat dissipation fin 751 is circular in plan view. The planar shape of each heat dissipation fin 751 may not be circular, but may be elliptical, polygonal (triangle, rectangle, rhombus, hexagon, etc.), Y-shaped, X-shaped, or the like. In the example shown in FIG. 6 , the plurality of heat dissipation fins 751 are arranged in a face-centered rectangular lattice pattern of a two-dimensional Bravais lattice in plan view. However, they may be arranged in a square lattice pattern, a rectangular lattice pattern, a diagonal lattice pattern, or a hexagonal lattice pattern. The plurality of heat dissipation fins 751 are arranged in three regions corresponding to the three semiconductor packages B10, but they do not have to be arranged in such a manner. The plurality of heat dissipation fins 751 are not limited to pin fins, and may be plate fins or corrugated fins.

[0023] In the illustrated example, a gap ΔG (see FIG. 16 ) is provided between the tips (lower edges in the thickness direction z) of the multiple heat dissipation fins 751 and the bottom plate of the case portion 74, but this gap ΔG is not necessary. However, because manufacturing errors of the multiple heat dissipation fins 751 can cause differences in the lengths of the multiple heat dissipation fins 751, it is preferable to provide the gap ΔG in order to properly seal the boundary between the top plate 71 and the case portion 74. In the illustrated example, the multiple heat dissipation fins 751 (heat dissipation portion 75) are connected to (the back surface 71 b of) the top plate 71. However, unlike this example, the multiple heat dissipation fins 751 (heat dissipation portion 75) may be connected to the case portion 74. For example, when the multiple heat dissipation fins 751 are connected to the bottom plate of the case portion 74, the multiple heat dissipation fins 751 each extend upward in the thickness direction z from the upper surface (the surface facing upward in the thickness direction z) of the bottom plate.

[0024] Next, a detailed configuration example of each semiconductor package B10 will be described. As shown in Figures 9 to 25, each of the multiple semiconductor packages B10 includes a support substrate 10, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, two conductive members 31 and 32, multiple connecting members 41 to 45, a sealing resin 50, and two signal boards 601 and 602. The multiple connecting members 41 to 45 are not shown in Figure 2. In the following description, the support substrate 10, multiple power terminals 15, 16, and 17, multiple signal terminals 19, multiple semiconductor elements 21 and 22, two conductive members 31 and 32, multiple connecting members 41 to 45, a sealing resin 50, and two signal boards 601 and 602 are common to each semiconductor package B10 unless otherwise specified. The plurality of signal terminals 19 includes a plurality of signal terminals 191 , 192 , 193 , 194 , 196 , and 197 .

[0025] Each semiconductor package B10 converts a DC power supply voltage applied to power terminals 15 and 16 into an AC voltage using multiple semiconductor elements 21 and 22. The converted AC voltage is input from power terminal 17 to a power supply target such as a motor.

[0026] As shown in FIGS. 13 and 14 , the support substrate 10 supports a plurality of semiconductor elements 21 and 22 in the thickness direction z. The support substrate 10 is, for example, an active metal brazing (AMB) substrate. Alternatively, the support substrate 10 may be a direct copper bonding (DCB) substrate. The support substrate 10 includes an insulating substrate 11, a main surface metal layer 12, and a back surface metal layer 13. In this embodiment, the support substrate 10 is covered with a sealing resin 50.

[0027] As shown in Figures 16 and 20 to 25, the insulating substrate 11 is interposed between the main surface metal layer 12 and the back surface metal layer 13 in the thickness direction z. The insulating substrate 11 supports a plurality of semiconductor elements 21 and a plurality of semiconductor elements 22 via the main surface metal layer 12. The insulating substrate 11 includes a material with relatively high thermal conductivity. The insulating substrate 11 is made of ceramics including aluminum nitride (AlN), for example. The insulating substrate 11 may include an insulating resin sheet in addition to ceramics.

[0028] The insulating substrate 11 has a substrate main surface 11a and a substrate back surface 11b. As shown in Figures 16 and 20 to 25, the substrate main surface 11a and the substrate back surface 11b are spaced apart in the thickness direction z. The substrate main surface 11a and the substrate back surface 11b face opposite each other in the thickness direction z. The substrate main surface 11a faces upward in the thickness direction z, and the substrate back surface 11b faces downward in the thickness direction z. The substrate main surface 11a faces the multiple semiconductor elements 21 and the multiple semiconductor elements 22.

[0029] As shown in Figures 16 and 20 to 25, the main surface metal layer 12 is located above the insulating substrate 11 in the thickness direction z. The main surface metal layer 12 is in contact with and bonded to the substrate main surface 11a. The main surface metal layer 12 contains copper (Cu), but may contain other metals. In a plan view, the main surface metal layer 12 is surrounded by the periphery of the insulating substrate 11. As shown in Figure 14, the main surface metal layer 12 includes a conductor portion 121, a conductor portion 122, and two conductor portions 123. The conductor portion 121, the conductor portion 122, and the two conductor portions 123 are spaced apart from each other.

[0030] The conductor portion 121 and the conductor portion 122 are spaced apart in the second direction y. The conductor portion 121 and the conductor portion 122 are aligned in the second direction y. The two conductor portions 123 are respectively arranged near two corners on one side (y2 side) of the four corners of the support substrate 10 in a plan view in the second direction y. The two conductor portions 123 are located on the opposite side of the conductor portion 121 in the second direction y, sandwiching a part of the conductor portion 122 (a partition portion 1221 described below). The dimension of the conductor portion 121 in the thickness direction z, the dimension of the conductor portion 122 in the thickness direction z, and the dimensions of the two conductor portions 123 in the thickness direction z are all the same.

[0031] The conductor portion 121 is located on the other side (y1 side) in the second direction y with respect to the conductor portion 122. The conductor portion 121 is located closer to the power terminal 17 in the second direction y than the conductor portion 122. The conductor portion 121 has, for example, a rectangular shape in a plan view, but the shape of the conductor portion 121 in a plan view is not limited in any way. A plurality of semiconductor elements 21 and a signal substrate 601 are joined to the conductor portion 121.

[0032] The conductor portion 121 has a conductor principal surface 121a. As shown in FIG. 20 and other figures, the conductor principal surface 121a faces upward in the thickness direction z. The conductor principal surface 121a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 121a is flat and parallel to the substrate principal surface 11a. The conductor principal surface 121a faces the multiple semiconductor elements 21.

[0033] As shown in Figures 12 to 14, the conductor portion 121 includes two exposed regions 121b. For ease of understanding, the two exposed regions 121b are depicted as dots in Figures 12 to 14. Each of the two exposed regions 121b is exposed from the upper surface of the sealing resin 50 (the resin main surface 51 described below). As shown in Figure 12, the two exposed regions 121b are arranged near the edge of the conductor main surface 121a on the y1 side in the second direction y. The two exposed regions 121b are located closer to the y1 side of the semiconductor element 21 in the second direction y. The two exposed regions 121b are located on both sides of the signal substrate 602 in the first direction x, sandwiching the signal substrate 602 therebetween.

[0034] The conductor portion 122 is located on one side (y2 side) of the conductor portion 121 in the second direction y. The conductor portion 122 includes two partition portions 1221, 1222. A plurality of semiconductor elements 22 are joined to the partition portion 1221. The partition portion 1222 is located on the opposite side of the conductor portion 121 in the second direction y with respect to the partition portion 1221. The partition portion 1222 is located closer to the power terminal 15 than the partition portion 1221. The partition portion 1222 is connected to one side (y2 side) of the partition portion 1221 in the second direction y. The dimension of the partition portion 1221 in the first direction x is the same as the dimension of the conductor portion 121 in the first direction x. The dimension of the partition portion 1222 in the first direction x is smaller than the dimension of the partition portion 1221 in the first direction x.

[0035] The conductor portion 122 has a conductor principal surface 122a. As shown in FIG. 20 and other figures, the conductor principal surface 122a faces upward in the thickness direction z. The conductor principal surface 122a faces the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 122a is flat and parallel to the substrate principal surface 11a. The conductor principal surface 122a faces the multiple semiconductor elements 22.

[0036] As shown in Figures 12 to 14, the conductor principal surface 122a includes two exposed regions 122b. For ease of understanding, the two exposed regions 122b are depicted as dots in Figures 12 to 14. Each of the two exposed regions 122b is exposed from the upper surface of the sealing resin 50 (a resin principal surface 51 described below). As shown in Figure 12, the two exposed regions 122b are disposed near the edge of the conductor principal surface 122a on the y2 side in the second direction y. The two exposed regions 122b are located on the opposite side of the signal substrate 601 from the multiple semiconductor elements 22 in the second direction y.

[0037] The two conductor portions 123 are located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 as the reference. The two conductor portions 123 are located closer to the power terminal 16 than the conductor portion 121 in the second direction y. The two conductor portions 123 are located on opposite sides of the partition portion 1222 in the first direction x. The power terminal 16 and the conductive member 32 are respectively joined to the two conductor portions 123.

[0038] Each of the two conductor portions 123 has a conductor principal surface 123a. As shown in Figure 20 and other figures, the conductor principal surface 123a of each conductor portion 123 faces upward in the thickness direction z. The conductor principal surface 123a of each conductor portion 123 faces in the same direction as the substrate principal surface 11a. In the illustrated example, the conductor principal surface 123a of each conductor portion 123 is flat and parallel to the substrate principal surface 11a.

[0039] As shown in Figures 12 to 14, each of the conductor principal surfaces 123a of the two conductor portions 123 includes an exposed region 123b. For ease of understanding, the two exposed regions 123b are depicted as dots in Figures 12 to 14. The exposed region 123b of each conductor portion 123 is exposed from the upper surface of the sealing resin 50 (the resin principal surface 51 described below). In each conductor portion 123, the exposed region 123b is located near the edge of the conductor principal surface 123a on the y2 side in the second direction y, as shown in Figure 12. In each conductor portion 123, the exposed region 123b is located on the y2 side in the second direction y of the conductor principal surface 123a to which the conductive member 32 is joined.

[0040] As shown in Figures 16 and 20 to 25, the back surface metal layer 13 is located below (on the z1 side of) the insulating substrate 11 in the thickness direction z. The back surface metal layer 13 is in contact with and bonded to the substrate back surface 11b. The composition of the back surface metal layer 13 includes copper (Cu), similar to the main surface metal layer 12, but may be other metals. Unlike this example, the composition of the back surface metal layer 13 may be different from that of the main surface metal layer 12. In the illustrated example, the back surface metal layer 13 is rectangular in plan view. The back surface metal layer 13 is surrounded by the periphery of the insulating substrate 11 in plan view.

[0041] The main surface metal layer 12 and the back surface metal layer 13 are metal bodies individually bonded to both sides of the insulating substrate 11 in the thickness direction z. In the main surface metal layer 12, the metal body is divided into multiple conductor portions 121, 122, and 123 by patterning. That is, the conductor portions 121, 122, and two conductor portions 123 are patterns of metal bodies formed on the substrate main surface 11a of the insulating substrate 11. In an example where the support substrate 10 is an AMB substrate, the main surface metal layer 12 and the back surface metal layer 13 are each bonded by an active metal bonding method. In contrast to this example, in an example where the support substrate 10 is a DCB substrate, the main surface metal layer 12 and the back surface metal layer 13 are each bonded to the insulating substrate 11 by a direct bonding method.

[0042] As shown in Figures 16 to 25, each semiconductor package B10 further includes a bonding layer 109. The bonding layer 109 bonds the back metal layer 13 (support substrate 10) and the heat dissipation member C10. The bonding layer 109 is interposed between the lower surface of the back metal layer 13 and the main surface 71a of the top plate 71. The bonding layer 109 may be conductive or non-conductive, and may be, for example, solder. Alternatively, the bonding layer 109 may be a sintered body of metal particles that can be formed with low pressure. Here, "low pressure" refers to a pressure that is lower than the pressure required to form a sintered body of metal particles formed with pressure. This low pressure also includes "no pressure," which means that no external force is applied. Hereinafter, a sintered body of metal particles that is formed with pressure may be referred to as a "pressurized metal sintered body," and a sintered body of metal particles that can be formed with low pressure may be referred to as a "low-pressure metal sintered body." The bonding layer 109 preferably has high thermal conductivity. 15 and 19 , the periphery of the bonding layer 109 in plan view is covered with the sealing resin 50. Therefore, in plan view, the bonding layer 109 is enclosed within the periphery of the sealing resin 50. The lower surface of the bonding layer 109 (the surface facing downward in the thickness direction z) is flush with the lower surface of the sealing resin 50 (a resin rear surface 52 described below).

[0043] The plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 may be other transistors such as insulated gate bipolar transistors (IGBTs) and bipolar transistors, or diodes. In this embodiment, the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are each n-channel MOSFETs with a vertical structure.

[0044] The plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 each include a compound semiconductor substrate. The composition of the compound semiconductor substrate includes silicon (Si), a wide bandgap semiconductor with a wider bandgap than Si, or an ultra-wide bandgap semiconductor with an even wider bandgap than the wide bandgap semiconductor. Wide bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Ultra-wide bandgap semiconductors include, but are not limited to, gallium oxide (GaO), diamond, and aluminum nitride (AlN). In this embodiment, the composition of each compound semiconductor substrate of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 includes SiC. The types and compositions of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 are not limited to being the same, and may be different.

[0045] 14 and 17 , the semiconductor elements 21 are mounted on the conductor portion 121. The semiconductor elements 21 are arranged along the first direction x. In the illustrated example, each semiconductor package B10 includes six semiconductor elements 21, but the number of semiconductor elements 21 is not limited to six and can be changed as appropriate depending on the specifications of the semiconductor module A10 (each semiconductor package B10).

[0046] 17 , each of the multiple semiconductor elements 21 has an element main surface 21a and an element back surface 21b. The element main surface 21a and the element back surface 21b are spaced apart in the thickness direction z. The element main surface 21a and the element back surface 21b face opposite each other in the thickness direction z. The element main surface 21a faces upward in the thickness direction z, and the element back surface 21b faces downward in the thickness direction z. The element main surface 21a faces in the same direction as the substrate main surface 11a in the thickness direction z. The element back surface 21b faces the support substrate 10.

[0047] Each of the semiconductor elements 21 has a back surface electrode 211 and a plurality of principal surface electrodes 212, 213, and 214. The back surface electrode 211 and the plurality of principal surface electrodes 212, 213, and 214 described below are common to all the semiconductor elements 21 unless otherwise specified.

[0048] As shown in FIG. 17 , the back surface electrode 211 is disposed on the element back surface 21b and exposed thereon. As shown in FIGS. 14 and 17 , the plurality of principal surface electrodes 212, 213, and 214 are disposed on the element main surface 21a and exposed thereon. In the illustrated example, the principal surface electrode 212 is divided into two regions in a plan view. The two regions are aligned in the first direction x. Unlike this example, the principal surface electrode 212 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 213 in a plan view is smaller than the area of ​​the principal surface electrode 212 in a plan view. The two principal surface electrodes 214 are disposed on either side of the principal surface electrode 213 in the first direction x, sandwiching the principal surface electrode 213 therebetween. Unlike the illustrated example, each semiconductor element 21 may include only one of the two principal surface electrodes 214 or may include neither of the two principal surface electrodes 214 .

[0049] Each semiconductor element 21 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 213. The operation of each semiconductor element 21 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 211 and the principal surface electrode 212 are conductive, and in the OFF state, the back surface electrode 211 and the principal surface electrode 212 are non-conductive. In each semiconductor element 21, the back surface electrode 211 and the principal surface electrode 212 are conductive in response to a drive signal input to the principal surface electrode 213. The two principal surface electrodes 214 are short-circuited to the principal surface electrode 212 inside each semiconductor element 21. In this example, the potential of each of the two principal surface electrodes 214 is equal to the potential of the principal surface electrode 212. In an example where each semiconductor element 21 is a MOSFET, the back surface electrode 211 is a drain electrode, the main surface electrode 212 is a source electrode, the main surface electrode 213 is a gate electrode, and each main surface electrode 214 is a source sense electrode.

[0050] The semiconductor module A10 further includes a plurality of conductive bonding layers 219. As shown in FIG. 17 , each of the plurality of semiconductor elements 21 is bonded to the conductor 121 by a corresponding one of the plurality of conductive bonding layers 219. Each of the plurality of conductive bonding layers 219 is interposed between the back electrode 211 of the corresponding semiconductor element 21 and the conductor 121, thereby providing electrical continuity therebetween. For example, each conductive bonding layer 219 is intended to electrically connect the back electrode 211 of the corresponding semiconductor element 21 to the conductor 121 by solid-state diffusion bonding (hereinafter referred to as "full-surface diffusion bonding") using an insert metal. This insert metal includes a base layer containing, for example, aluminum (Al) and metal layers containing, for example, silver (Ag) formed on both sides of the base layer in the thickness direction z. The compositions of the base layer and the metal layers are not limited to these examples. The conductive bonding layer 219 has a structure in which metal layers on both sides of the base layer in the thickness direction z are individually solid-phase diffusion bonded to the back electrode 211 and the conductor 121 of the semiconductor element 21. In a configuration in which each metal layer of the insert metal contains Ag, a metal layer containing, for example, Ag may be formed on the surface of the back electrode 211 and the conductor 121. Each conductive bonding layer 219 may contain, for example, the above-mentioned pressurized metal sintered compact. Alternatively, each conductive bonding layer 219 may be, for example, solder.

[0051] 14 and other figures, the semiconductor elements 22 are mounted on the partition portions 1221 of the conductor portion 122. The semiconductor elements 22 are arranged along the first direction x. In the illustrated example, each semiconductor package B10 includes six semiconductor elements 22, but the number of semiconductor elements 22 is not limited to six and can be changed as appropriate depending on the specifications of the semiconductor module A10 (each semiconductor package B10).

[0052] 18 , each of the multiple semiconductor elements 22 has an element main surface 22 a and an element back surface 22 b. The element main surface 22 a and the element back surface 22 b are spaced apart in the thickness direction z. The element main surface 22 a and the element back surface 22 b face opposite each other in the thickness direction z. The element main surface 22 a faces upward in the thickness direction z, and the element back surface 22 b faces downward in the thickness direction z. The element main surface 22 a faces the same direction as the substrate main surface 11 a in the thickness direction z. The element back surface 22 b faces the support substrate 10.

[0053] Each of the semiconductor elements 22 has a back surface electrode 221 and a plurality of principal surface electrodes 222, 223, and 224. The back surface electrode 221 and the plurality of principal surface electrodes 222, 223, and 224 described below are common to all the semiconductor elements 22 unless otherwise specified.

[0054] As shown in FIG. 18 , the back surface electrode 221 is disposed on the element back surface 22b and exposed thereon. As shown in FIGS. 14 and 18 , the plurality of principal surface electrodes 222, 223, and 224 are disposed on the element main surface 22a and exposed thereon. In the illustrated example, the principal surface electrode 222 is divided into two regions in a plan view. The two regions are aligned in the first direction x. Unlike this example, the principal surface electrode 222 may be divided into three or more regions, or may be a single region without being divided. The area of ​​the principal surface electrode 223 in a plan view is smaller than the area of ​​the principal surface electrode 222 in a plan view. The two principal surface electrodes 224 are disposed on either side of the principal surface electrode 223 in the first direction x, sandwiching the principal surface electrode 223 therebetween. Unlike the illustrated example, each semiconductor element 22 may include only one of the two principal surface electrodes 224 or may include neither of the two principal surface electrodes 224 .

[0055] Each semiconductor element 22 is switched between an ON state and an OFF state by a drive signal input to the principal surface electrode 223. The operation of each semiconductor element 22 alternately switching between the ON state and the OFF state is called a switching operation. In the ON state, the back surface electrode 221 and the principal surface electrode 222 are conductive, and in the OFF state, the back surface electrode 221 and the principal surface electrode 222 are non-conductive. In each semiconductor element 22, the back surface electrode 221 and the principal surface electrode 222 are conductive in response to a drive signal input to the principal surface electrode 223. The two principal surface electrodes 224 are short-circuited to the principal surface electrode 222 inside each semiconductor element 22. In this example, the potential of each of the two principal surface electrodes 224 is equal to the potential of the principal surface electrode 222. In an example in which each semiconductor element 22 is a MOSFET, the back surface electrode 221 is a drain electrode, the main surface electrode 222 is a source electrode, the main surface electrode 223 is a gate electrode, and each main surface electrode 224 is a source sense electrode.

[0056] The semiconductor module A10 further includes a plurality of conductive bonding layers 229. As shown in FIG. 18 , each of the plurality of semiconductor elements 22 is bonded to the conductor portion 122 (partition portion 1221) by a corresponding one of the plurality of conductive bonding layers 229. Each of the plurality of conductive bonding layers 229 is interposed between the back electrode 221 of the corresponding semiconductor element 22 and the conductor portion 122, thereby establishing electrical continuity therebetween. For example, like each of the conductive bonding layers 219, each conductive bonding layer 229 is intended to electrically connect the back electrode 221 of the corresponding semiconductor element 22 to the conductor portion 122 by solid-state diffusion bonding (full-surface diffusion bonding) using an insert metal. This insert metal includes a base layer containing, for example, aluminum (Al) and a metal layer containing, for example, silver (Ag) formed on both sides of the base layer in the thickness direction z. The compositions of the base layer and the metal layer are not limited to these examples. The conductive bonding layer 229 has a structure in which metal layers on both sides of the base layer in the thickness direction z are individually solid-phase diffusion bonded to the back electrode 221 and the conductor 122 of the semiconductor element 22. In a configuration in which each metal layer of the insert metal contains Ag, a metal layer containing, for example, Ag may be formed on the surface of the back electrode 221 and the conductor 122. Each conductive bonding layer 229 may contain, for example, the above-mentioned pressurized metal sintered compact. Alternatively, each conductive bonding layer 229 may be, for example, solder.

[0057] In the semiconductor module A10, the back electrodes 211 (drain electrodes) of the multiple semiconductor elements 21 are electrically connected, and the main surface electrodes 212 (source electrodes) are electrically connected. That is, the multiple semiconductor elements 21 are electrically connected in parallel with each other. In the multiple semiconductor elements 22, the back electrodes 221 (drain electrodes) of the multiple semiconductor elements 22 are electrically connected, and the main surface electrodes 222 (source electrodes) of the multiple semiconductor elements 22 are electrically connected. That is, the multiple semiconductor elements 22 are electrically connected in parallel with each other. In the semiconductor module A10, the back electrodes 211 (drain electrodes) of the multiple semiconductor elements 21 are electrically connected to the main surface electrodes 222 (source electrodes) of the multiple semiconductor elements 22. That is, the multiple semiconductor elements 21 and the multiple semiconductor elements 22 are connected in series. The semiconductor module A10 configures a half-bridge circuit in which the multiple semiconductor elements 22 form an upper arm circuit and the multiple semiconductor elements 21 form a lower arm circuit.

[0058] As shown in FIGS. 9 to 12 and 14 to 25 , the sealing resin 50 covers the semiconductor elements 21, portions of the two conductor portions 123, and the insulating substrate 11. Furthermore, the sealing resin 50 covers portions of the conductor portion 121, portions of the conductor portion 122, the semiconductor elements 22, the two conductive members 31, 32, the connecting members 41 to 45, the two signal boards 601, 602, and portions of the signal terminals 19 (the signal terminals 191 to 194, 196, and 197 described below). In this embodiment, the power terminals 15, 16, and 17 are disposed outside the sealing resin 50. The sealing resin 50 has electrical insulation properties. The sealing resin 50 contains, for example, a black epoxy resin. The sealing resin 50 is formed, for example, by molding. In the illustrated example, the periphery of the sealing resin 50 in plan view is enclosed within the periphery of the heat dissipation member C10 (top plate 71) in plan view. The sealing resin 50 has a resin main surface 51, a resin back surface 52, and multiple resin side surfaces 531 to 534.

[0059] As shown in FIGS. 16 and 20 to 25, the resin main surface 51 and the resin back surface 52 are spaced apart in the thickness direction z. The resin main surface 51 and the resin back surface 52 face opposite each other in the thickness direction z. The resin main surface 51 faces upward in the thickness direction z, and the resin back surface 52 faces downward in the thickness direction z. The resin main surface 51 faces the same direction in the thickness direction z as the substrate main surface 11a, the element main surface 21a, and the element main surface 22a. Each of the signal terminals 19 protrudes upward in the thickness direction z from the resin main surface 51. As shown in FIGS. 15, 16, and 20 to 25, the lower surface of the bonding layer 109 is exposed from the resin back surface 52. As shown in FIG. 15, the resin back surface 52 has a rectangular ring shape surrounding the bonding layer 109 in a plan view.

[0060] Each of the multiple resin side surfaces 531 to 534 is connected to the resin main surface 51. As shown in FIGS. 9 and 16 , the pair of resin side surfaces 531, 532 are spaced apart in the second direction y. The resin side surface 531 faces one side of the second direction y (the y2 side), and the resin side surface 532 faces the other side of the second direction y (the y1 side). Each of the pair of resin side surfaces 531, 532 extends in the first direction x. In the illustrated example, the pair of resin side surfaces 531, 532 are connected to the resin main surface 51 as well as the resin back surface 52. As shown in FIGS. 9 and 20 to 25 , the pair of resin side surfaces 533, 534 are spaced apart in the first direction x. The resin side surface 533 faces one side of the first direction x (the x2 side), and the resin side surface 534 faces the other side of the first direction x (the x1 side). 15 to 17, each of the pair of resin side surfaces 533 and 534 is connected to the resin main surface 51 as well as the resin rear surface 52.

[0061] The sealing resin 50 has a main surface opening 56. The main surface opening 56 is formed in the resin main surface 51. As shown in Fig. 10 , the main surface opening 56 exposes a portion of the main surface metal layer 12 from the resin main surface 51. The main surface opening 56 includes two openings 561, two openings 562, and two openings 563.

[0062] Each of the two openings 561 overlaps the conductor portion 121 in a planar view. As shown in FIG. 12 and other figures, the two openings 561 individually expose two different regions (two exposed regions 121b) of the conductor principal surface 121a of the conductor portion 121. The two openings 561 expose the two exposed regions 121b from the resin principal surface 51. A power terminal 17 is inserted into each of the two openings 561. The two openings 561 are aligned in the first direction x. In the illustrated example, the two openings 561 are arranged on both sides of the signal terminals 191, 193, and 197 in the first direction x. Each of the two openings 561 has a rectangular shape in a planar view. The long sides of each of the two openings 561 extend in the first direction x and the short sides extend in the second direction y. Unlike this example, each of the two openings 561 may have a short side in the first direction x and a long side in the second direction y. The planar shape of each of the two openings 561 is not limited to a rectangle. In the illustrated example (for example, FIGS. 20 and 25 ), each of the two openings 561 is tapered. In this example, the cross section of each opening 561 perpendicular to the thickness direction z gradually becomes smaller in the thickness direction z from the resin main surface 51 toward the conductor portion 121. Unlike this example, each opening 561 does not need to be tapered.

[0063] Each of the two openings 562 overlaps the conductor portion 122 in a planar view. As shown in FIG. 12 and other figures, the two openings 562 individually expose two different regions (two exposed regions 122b) of the conductor principal surface 122a of the conductor portion 122. The two openings 562 expose the two exposed regions 122b from the resin principal surface 51. A power terminal 15 is inserted into each of the two openings 562. The two openings 562 are aligned in the first direction x. Each of the two openings 562 has a rectangular shape in a planar view. Each of the two openings 562 has a long side extending in the second direction y and a short side extending in the first direction x. Unlike this example, each of the two openings 562 may have a short side extending in the second direction y and a long side extending in the first direction x. The planar view shape of each of the two openings 562 is not limited to a rectangle. In the illustrated example (e.g., FIG. 21 ), each of the two openings 562 is tapered. In this example, the cross section of each opening 562 perpendicular to the thickness direction z gradually decreases in size from the resin main surface 51 toward the conductor portion 122. Unlike this example, each opening 562 does not need to be tapered.

[0064] The two openings 563 overlap the two conductor portions 123, respectively, in a plan view. As shown in FIG. 12 and other figures, the two openings 563 each expose a portion (exposed region 123b) of the conductor principal surface 123a of the corresponding conductor portion 123. Each of the two openings 563 exposes the exposed region 123b of the corresponding conductor portion 123 from the resin principal surface 51. A power terminal 16 is inserted through each of the two openings 563. The two openings 563 are aligned in the first direction x. The two openings 563 are arranged on both sides of the two openings 562 in the first direction x. Each of the two openings 563 has a rectangular shape in a plan view. The long side of each of the two openings 563 is in the second direction y and the short side is in the first direction x. Unlike this example, the short side of each of the two openings 563 may be in the second direction y and the long side is in the first direction x. The planar shape of each of the two openings 563 is not limited to a rectangle. In the illustrated example (e.g., FIGS. 20 and 21 ), each of the two openings 563 is tapered. In this example, the cross section of each opening 563 perpendicular to the thickness direction z gradually becomes smaller as it approaches the conductor portion 123 from the resin main surface 51 in the thickness direction z. Unlike this example, each opening 563 does not need to be tapered.

[0065] In this embodiment, each opening 561 of each semiconductor package B10 is surrounded by the resin main surface 51 (i.e., the top surface of the sealing resin 50) in a plan view. This configuration increases the creepage distance between the conductor 121 exposed through each opening 561 and the heat dissipation member C10, ensuring a moderate dielectric strength voltage. In this embodiment, each opening 562 of each semiconductor package B10 is surrounded by the resin main surface 51 (i.e., the top surface of the sealing resin 50) in a plan view. This configuration increases the creepage distance between the conductor 122 exposed through each opening 562 and the heat dissipation member C10, ensuring a moderate dielectric strength voltage. In this embodiment, each opening 563 of each semiconductor package B10 is surrounded by the resin main surface 51 (i.e., the top surface of the sealing resin 50) in a plan view. This configuration increases the creepage distance between the conductor 123 exposed through each opening 563 and the heat dissipation member C10, ensuring a moderate dielectric strength voltage. That is, in each semiconductor package B10, the main surface opening 56 is surrounded by the resin main surface 51 (i.e., the top surface of the sealing resin 50) in a plan view. This increases the creepage distance along the sealing resin 50 between the main surface metal layer 12 and the heat dissipation member C10 in each semiconductor package B10, thereby ensuring an appropriate dielectric strength.

[0066] 9, 10, 16, and 25, the resin main surface 51 has a recess 571 and two recesses 572. As shown in these figures, the recess 571 and the two recesses 572 are each recessed downward in the thickness direction z from the resin main surface 51. In a plan view, the recess 571 and the two recesses 572 are each interposed between the main surface opening 56 and any one of the plurality of signal terminals 19.

[0067] In a plan view, the recess 571 is disposed between the two openings 562 and 563 and the plurality of signal terminals 192, 194, and 196. In a plan view, the recess 571 has a strip shape extending in the first direction x. In the illustrated example, the recess 571 extends from the resin side surface 533 to the resin side surface 534.

[0068] One of the two recesses 572 is located between one of the two openings 561 and the plurality of signal terminals 191, 193, and 197. The other of the two recesses 572 is located between the other of the two openings 561 and the plurality of signal terminals 191, 193, and 197. Each of the two recesses 572 has a strip shape extending in the second direction y in plan view.

[0069] Each of the plurality of power terminals 15, 16, and 17 is electrically connected to one of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22. A current corresponding to the power before or after conversion by the switching operations of the plurality of semiconductor elements 21 and the plurality of semiconductor elements 22 flows through each of the plurality of power terminals 15, 16, and 17.

[0070] The power terminal 15 is joined to the conductor portion 122 (partition portion 1222). This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 15 is inserted through the two openings 562 and joined to the two exposed regions 122b of the conductor portion 122, respectively. The power terminal 15 is electrically connected to the back electrodes 221 (drain electrodes of the upper arm circuits) of the multiple semiconductor elements 22 via the conductor portion 122. The power terminal 15 is a P terminal (positive terminal) to which a DC power supply voltage to be converted into power is applied. As shown in FIG. 11 and other figures, the power terminal 15 is located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 (part of the conductor portion 122) sandwiched therebetween. As shown in FIG. 11, the power terminal 15 is located on the opposite side of the multiple semiconductor elements 21 in the second direction y, with the multiple semiconductor elements 22 sandwiched therebetween.

[0071] As shown in FIGS. 9, 11, 21, and the like, the power terminal 15 includes two joining portions 151, a suspension portion 152, and an extension portion 153.

[0072] The two joints 151 are each individually joined to a portion of the conductor principal surface 122a of the conductor portion 122 (specifically, the two exposed regions 122b). The two joints 151 are each individually housed in the two openings 562. Therefore, the peripheries of the two joints 151 are each enclosed within the peripheries of the corresponding openings 562 in a plan view.

[0073] The suspension portion 152 connects two joint portions 151. In the illustrated example, the suspension portion 152 extends in the first direction x from each joint portion 151. In a plan view, the suspension portion 152 has a strip shape extending in the first direction x. Most of the suspension portion 152 is located above each joint portion 151 in the thickness direction z. Most of the suspension portion 152 is located above the resin main surface 51 in the thickness direction z. The end of the suspension portion 152 on the side connected to each joint portion 151 is bent downward in the thickness direction z and inserted into the corresponding opening 562.

[0074] The extension portion 153 protrudes from the suspension portion 152 to one side in the second direction y (y2 side). The extension portion 153 causes a part of the power terminal 15 to protrude from the power terminal 16 in a plan view.

[0075] The power terminal 16 is joined to a corresponding one of the two conductor portions 123. This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 16 is inserted through the two openings 563 and joined to the exposed regions 123b of the two conductor portions 123. Each of the two power terminals 16 is electrically connected to the principal surface electrodes 212 (source electrodes of the lower arm circuits) of the multiple semiconductor elements 21 via the corresponding conductor portion 123 and the conductive member 32. The power terminal 16 is an N-terminal (negative terminal) to which a DC power supply voltage to be converted is applied. As shown in FIG. 11 and other figures, the power terminal 16 is located on the opposite side of the conductor portion 121 in the second direction y, with the partition portion 1221 (part of the conductor portion 122) sandwiched therebetween. As shown in FIG. 11 , the power terminal 16 is located on the opposite side of the semiconductor elements 21 in the second direction y, with the semiconductor elements 22 sandwiched therebetween.

[0076] As shown in FIGS. 9, 11, and 21, the power terminal 16 includes two joining portions 161 and a suspension portion 162.

[0077] The two joint portions 161 are individually joined to portions (specifically, exposed regions 123b) of the conductor principal surfaces 123a of the two conductor portions 123. The two joint portions 161 are individually housed in the two openings 563. Thus, the peripheries of the two joint portions 161 are respectively contained within the peripheries of the corresponding openings 563 in a plan view.

[0078] The suspension portion 162 connects two joint portions 161. In the illustrated example, the suspension portion 162 extends from each joint portion 161 in the first direction x. In a plan view, the suspension portion 162 has a strip shape extending in the first direction x. Most of the suspension portion 162 is located above each joint portion 161 in the thickness direction z. The end of the suspension portion 162 that connects to each joint portion 161 is bent downward in the thickness direction z and inserted into the corresponding opening 563. In the illustrated example, most of the suspension portion 162 is located above the suspension portion 152 (power terminal 15) in the thickness direction z. Most of the suspension portion 162 is located above the resin main surface 51 in the thickness direction z. In a plan view, the suspension portion 152 completely overlaps the suspension portion 162.

[0079] The power terminal 17 is joined to the conductor portion 121. This joining is performed, for example, by laser welding. Alternatively, any joining method capable of electrical connection, such as ultrasonic joining or joining using a conductive adhesive, may be appropriately employed. The power terminal 17 is inserted through the two openings 561 and joined to the two exposed regions 121b of the conductor portion 121, respectively. The power terminal 17 is electrically connected to the back electrodes 211 (drain electrodes of the lower arm circuit) of the multiple semiconductor elements 21 via the conductor portion 121, and is electrically connected to the main surface electrodes 222 (source electrodes of the upper arm circuit) of the multiple semiconductor elements 22 via the conductor portion 121 and the conductive member 31. AC power converted by the multiple semiconductor elements 21 and the multiple semiconductor elements 22 is output from the power terminal 17. In other words, the power terminal 17 is an output terminal for the AC power. As shown in FIG. 11 , the power terminal 17 is located on the opposite side of the multiple semiconductor elements 22 from the multiple semiconductor elements 21 in the second direction y.

[0080] As shown in FIGS. 9, 11, 25, and the like, the power terminal 17 includes two joining portions 171 and a suspension portion 172.

[0081] The two joint portions 171 are individually joined to parts of the conductor principal surface 121a (specifically, the two exposed regions 121b) of the conductor portion 121. The two joint portions 171 are individually housed in the two openings 561. Thus, the peripheries of the two joint portions 171 are respectively contained within the peripheries of the corresponding openings 561 in a plan view.

[0082] The suspension portion 172 connects the two joint portions 171. In the illustrated example, the suspension portion 172 extends a short distance from each joint portion 171 along the second direction y and then bends in the first direction x. More specifically, in a plan view, the suspension portion 172 extends from one of the two joint portions 171 (e.g., the joint portion 171 on the x1 side in the first direction x) along the second direction y (e.g., the y1 side) and bends in the first direction x (e.g., the x2 side). Then, it bends in the second direction y (e.g., the y2 side) and connects to the other of the two joint portions 171 (e.g., the joint portion 171 on the x2 side in the first direction x). With this configuration, the strip-shaped portion of the suspension portion 172 extending along the first direction x is located outside the sealing resin 50 in a plan view. Most of the suspension portion 172 is strip-shaped and extends in the first direction x in a plan view. Most of this suspension portion 172 is located above each joint 171 in the thickness direction z. Most of this suspension portion 172 is located above each resin main surface 51 in the thickness direction z. The end of the suspension portion 172 that is connected to each joint 171 is bent downward in the thickness direction z and inserted into the corresponding opening 561.

[0083] The shapes of the multiple power terminals 15, 16, and 17 are not limited to the above example and can be modified as appropriate depending on the specifications of each semiconductor package B10. For example, in the power terminal 15, the two joint portions 151 do not have to be connected by the suspension portion 152. In this example, each semiconductor package B10 includes two power terminals 15. This configuration can also be similarly modified for the other power terminals 16 and 17.

[0084] The pair of signal boards 601, 602 constitute part of the conductive paths between the multiple signal terminals 19 and the multiple semiconductor elements 21 and the multiple semiconductor elements 22. As shown in FIGS. 13 and 14 , the signal board 601 is located on the y1 side of the multiple semiconductor elements 21 in the second direction y. As shown in FIGS. 16 and 25 , the signal board 601 is bonded to the conductor portion 121. As shown in FIGS. 13 and 14 , the signal board 602 is located on the y2 side of the multiple semiconductor elements 22 in the second direction y. As shown in FIGS. 16 and 22 , the signal board 602 is bonded to the conductor portion 122. In the illustrated example, the signal board 602 is bonded so as to overlap the boundary between the two partition portions 1221, 1222 in a plan view. Each of the pair of signal boards 601, 602 is, for example, a DCB board or an AMB board. Unlike this example, each of the pair of signal boards 601, 602 may be a printed circuit board.

[0085] Each of the pair of signal substrates 601, 602 has an insulating layer 61, a wiring layer 62, a metal layer 63, and a plurality of sleeves 64. Each of the pair of signal substrates 601, 602 is covered with a sealing resin 50 except for a portion of each of the plurality of sleeves 64. Unless otherwise specified, the insulating layer 61, the wiring layer 62, the metal layer 63, and the plurality of sleeves 64 described below are common to each of the pair of signal substrates 601, 602.

[0086] The insulating layer 61 is interposed between the wiring layer 62 and the metal layer 63 in the thickness direction z. The insulating layer 61 may be made of, for example, ceramics. Alternatively, the insulating layer 61 may be made of an insulating resin sheet.

[0087] 22 and 25, the wiring layer 62 is located above the insulating layer 61 in the thickness direction z. The composition of the wiring layer 62 is not limited in any way, but may include copper. As shown in FIG. 14, the wiring layer 62 includes a plurality of wiring portions 621 to 624. The plurality of wiring portions 621 to 624 are spaced apart from one another. The planar shape, arrangement, size, and the like of each of the wiring portions 621 to 624 are not limited to the examples shown in the drawings.

[0088] As shown in FIGS. 22 and 25 , the metal layer 63 is located on the opposite side of the wiring layer 62 in the thickness direction z, with the insulating layer 61 sandwiched therebetween. The composition of the metal layer 63 is not limited in any way, but may include copper. The metal layer 63 of the signal substrate 601 is bonded to the conductor portion 121 by an adhesive layer (not shown). The metal layer 63 of the signal substrate 602 is bonded to the conductor portion 122 by an adhesive layer (not shown). These adhesive layers are made of a material that may or may not be conductive. These adhesive layers may be, for example, solder. In this embodiment, the adhesive layer bonding the metal layer 63 of the signal substrate 601 to the conductor portion 121 and the adhesive layer bonding the metal layer 63 of the signal substrate 602 to the conductor portion 122 may be, like the conductive bonding layers 219 and 229, for example, by the above-mentioned full-surface diffusion bonding, or may include a pressurized metal sintered body.

[0089] 16 , 22 , and 25 , each of the multiple sleeves 64 is bonded to the wiring layer 62 by a conductive bonding layer (e.g., solder) not shown. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the thickness direction z. One end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z1 side in the thickness direction z) is conductively bonded to the wiring layer 62. As shown in FIGS. 16 , 22 , and 25 , the other end of each of the multiple sleeves 64 in the thickness direction z (an edge on the z2 side in the thickness direction z) is exposed from the sealing resin 50.

[0090] As shown in FIG. 14 , the thermistor 23 is conductively connected to the wiring portion 623 of the signal substrate 601 and the wiring portion 624 of the signal substrate 601. The thermistor 23 is, for example, an NTC (Negative Temperature Coefficient) thermistor. An NTC thermistor has a characteristic in which its resistance decreases gradually with increasing temperature. The thermistor 23 is used as a temperature detection sensor for the semiconductor module A10. The thermistor 23 is connected by, for example, solder. Alternatively, the thermistor 23 may include a low-pressure sintered metal compact.

[0091] Each of the signal terminals 19 (signal terminals 191 to 194, 196, and 197) is formed by a metal pin and extends in the thickness direction z. The signal terminals 19 protrude from the sealing resin 50 (a resin main surface 51, described below). The signal terminals 19 (signal terminals 191 to 194, 196, and 197) are individually press-fitted into the sleeves 64 of the pair of signal boards 601 and 602. As a result, each of the signal terminals 19 is supported by one of the sleeves 64 and is electrically connected to one of the wiring layers 62 of the pair of signal boards 601 and 602. The signal terminals 191 to 194 and 196 are electrically connected to one of the semiconductor elements 21 and the semiconductor elements 22. The two signal terminals 197 are not electrically connected (non-conductive) to either the semiconductor elements 21 or the semiconductor elements 22, but are electrically connected to the thermistor 23.

[0092] 14 , the signal terminal 191 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal substrate 601. The signal terminal 191 is electrically connected to each of the main surface electrodes 213 of the plurality of semiconductor elements 21. A drive signal for driving each semiconductor element 21 is input to the signal terminal 191 (a gate voltage is applied).

[0093] 14 , the signal terminal 192 is press-fitted into the sleeve 64 joined to the wiring portion 621 of the signal board 602. As a result, the signal terminal 192 is supported by the sleeve 64 and is electrically connected to the wiring portion 621 of the signal board 602. The signal terminal 192 is electrically connected to each of the main surface electrodes 223 of the plurality of semiconductor elements 22. A drive signal for driving each semiconductor element 22 is input to the signal terminal 192 (a gate voltage is applied).

[0094] 14 , the signal terminal 193 is located next to the signal terminal 191 in the first direction x. As shown in FIG. 14 , the signal terminal 193 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 601. As a result, the signal terminal 193 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 601. The signal terminal 193 is electrically connected to the main surface electrodes 214 of the multiple semiconductor elements 21. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 214 of the multiple semiconductor elements 21 is applied to the signal terminal 193.

[0095] 14 , the signal terminal 194 is located next to the signal terminal 192 in the first direction x. As shown in FIG. 14 , the signal terminal 194 is press-fitted into the sleeve 64 joined to the wiring portion 622 of the signal substrate 602. As a result, the signal terminal 194 is supported by the sleeve 64 and is electrically connected to the wiring portion 622 of the signal substrate 602. The signal terminal 194 is electrically connected to the main surface electrodes 224 of the multiple semiconductor elements 22. A voltage corresponding to the maximum current among the currents flowing through the main surface electrodes 224 of the multiple semiconductor elements 22 is applied to the signal terminal 194.

[0096] As shown in Fig. 14 , the signal terminal 196 is located on the opposite side of the signal terminal 192 in the first direction x, with the signal terminal 194 sandwiched therebetween. As shown in Fig. 14 , the signal terminal 196 is press-fitted into the sleeve 64 joined to the wiring portion 623 of the signal board 602. As a result, the signal terminal 196 is supported by the sleeve 64 and is electrically connected to the wiring portion 623 of the signal board 602. The signal terminal 196 is electrically connected to the conductor portion 122. A voltage equivalent to the DC power input to the power terminal 15 is applied to the signal terminal 196.

[0097] 14 , the pair of signal terminals 197 are located on the opposite side of the signal terminal 191 in the first direction x with the signal terminal 193 sandwiched therebetween, and the pair of signal terminals 197 are adjacent to each other in the first direction x. As shown in FIG. 14 , the pair of signal terminals 197 are individually press-fitted into a pair of sleeves 64 joined to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601, respectively. As a result, the pair of signal terminals 197 are individually supported by the pair of sleeves 64 and are individually conducted to the wiring portion 623 of the signal board 601 and the wiring portion 624 of the signal board 601. The pair of signal terminals 197 are conducted to the thermistor 23.

[0098] Each of the plurality of connection members 41 to 45 electrically connects parts spaced apart from one another. Each of the plurality of connection members 41 to 45 is, for example, a bonding wire. Unlike this example, each of the plurality of connection members 41 to 45 may be a metal plate material. Each of the plurality of connection members 41 to 45 contains gold (Au). Each of the plurality of connection members 41 to 45 may contain copper or aluminum. The plurality of connection members 41 to 45 are omitted from FIGS. 2 and 16.

[0099] 14 , each of the plurality of connection members 41 is conductively joined to the corresponding main surface electrode 213 of the semiconductor element 21 and the wiring portion 621 of the signal substrate 601. As a result, the signal terminal 191 is conductively connected to the main surface electrodes 213 of the plurality of semiconductor elements 21.

[0100] 14 , each of the plurality of connection members 42 is conductively joined to the corresponding main surface electrode 223 of the semiconductor element 22 and the wiring portion 621 of the signal substrate 602. As a result, the signal terminal 192 is conductively connected to the main surface electrodes 223 of the plurality of semiconductor elements 22.

[0101] 14 , each of the plurality of connection members 43 is conductively joined to the corresponding main surface electrode 214 of the semiconductor element 21 and to the wiring portion 622 of the signal substrate 601. This allows the signal terminal 193 to be conductively connected to the main surface electrodes 214 of the plurality of semiconductor elements 21. When each semiconductor element 21 does not include either of the two main surface electrodes 214, each of the plurality of connection members 43 is joined to the main surface electrode 212 of the corresponding semiconductor element 21.

[0102] 14 , each of the plurality of connection members 44 is conductively joined to the corresponding main surface electrode 224 of the semiconductor element 22 and the wiring portion 622 of the signal substrate 602. This allows the signal terminal 194 to be conductively connected to the main surface electrodes 224 of the plurality of semiconductor elements 22. When each semiconductor element 22 does not include either of the two main surface electrodes 224, each of the plurality of connection members 44 is joined to the main surface electrode 222 of the corresponding semiconductor element 22.

[0103] 14 , the connection member 45 is electrically connected to the wiring portion 623 of the signal substrate 602 and the conductor portion 122 (partition portion 1222). As a result, the signal terminal 196 is electrically connected to the back surface electrodes 221 of the plurality of semiconductor elements 22 via the conductor portion 122.

[0104] As shown in FIG. 13 and other figures, the conductive member 31 is bonded to the main surface electrodes 222 of the plurality of semiconductor elements 22 and the conductor portion 121 of the support substrate 10. The main surface electrodes 222 of the plurality of semiconductor elements 22 are electrically connected to the conductor portion 121 via the conductive member 31. The conductive member 31 may contain copper. The conductive member 31 is a metal clip. As shown in FIG. 13 and other figures, the conductive member 31 has a main body portion 311 and a plurality of joint portions 312, 313.

[0105] The main body portion 311 forms a main part of the conductive member 31. As shown in FIG. 13 , the main body portion 311 extends in the first direction x. As shown in FIG. 13 , the main body portion 311 straddles the conductor portion 121 and the conductor portion 122. As shown in FIG. 13 , a plurality of through holes 311 a are formed in the main body portion 311. The plurality of through holes 311 a penetrate the main body portion 311 in the thickness direction z. The plurality of through holes 311 a overlap between the conductor portion 121 and the conductor portion 122 in a plan view. This allows the sealing resin 50 to flow smoothly downward in the thickness direction z of the main body portion 311 when forming the sealing resin 50.

[0106] As shown in FIG. 13 , the multiple bonding portions 312 are individually bonded to the principal surface electrodes 222 of the multiple semiconductor elements 22. Each of the multiple bonding portions 312 faces one of the principal surface electrodes 222 of the multiple semiconductor elements 22. In a plan view, each bonding portion 312 extends from the main body portion 311 toward the y2 side in the second direction y. In the illustrated example, the multiple bonding portions 312 are bifurcated from the main body portion 311, but they do not have to be bifurcated. The tip of each bonding portion 312 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 312 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each bonding portion 312, which is located at a different position in the thickness direction z, to the main body portion 311.

[0107] 13 , the multiple joints 313 are joined to the conductor portion 121. The multiple joints 313 face the conductor portion 121. In a plan view, each joint 313 extends from the main body portion 311 to the y1 side in the second direction y. The tip of each joint 313 (the end opposite to the side connected to the main body portion 311) is located below the main body portion 311 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each joint 313 (the end connected to the main body portion 311) is bent in the thickness direction z so as to connect the tip of each joint 313, which is located at a different position in the thickness direction z, to the main body portion 311.

[0108] 18 , the semiconductor module A10 further includes a conductive bonding layer 33. The conductive bonding layer 33 is interposed between the main surface electrodes 222 of the plurality of semiconductor elements 22 and the plurality of bonding portions 312. The conductive bonding layer 33 conductively bonds the main surface electrodes 222 of the plurality of semiconductor elements 22 to the plurality of bonding portions 312. The conductive bonding layer 33 is, for example, solder. Alternatively, the conductive bonding layer 33 may include a low-pressure metal sintered body.

[0109] 17, the semiconductor module A10 further includes a conductive bonding layer 34. The conductive bonding layer 34 is interposed between the conductor portion 121 and the joint portion 313. The conductive bonding layer 34 conductively bonds the conductor portion 121 and the joint portion 313. The conductive bonding layer 34 is, for example, solder. Alternatively, the conductive bonding layer 34 may include a low-pressure sintered metal compact.

[0110] As shown in FIG. 12 , the conductive member 32 is conductively bonded to the principal surface electrodes 212 of the plurality of semiconductor elements 21 and the two conductor portions 123 of the support substrate 10. As a result, the principal surface electrodes 212 of the plurality of semiconductor elements 21 are electrically connected to each of the two conductor portions 123 via the conductive member 32. As described above, the power terminals 16 are respectively bonded to the two conductor portions 123, and therefore the principal surface electrodes 212 of the plurality of semiconductor elements 21 are electrically connected to the power terminals 16. The composition of the conductive member 32 may include copper, for example. The conductive member 32 is a metal clip. As shown in FIG. 12 and other figures, the conductive member 32 includes two main body portions 321, a plurality of joint portions 322, an intermediate portion 323, and a plurality of joint portions 324.

[0111] As shown in FIG. 12 , the two main bodies 321 are spaced apart from each other in the first direction x. The two main bodies 321 extend in the second direction y. As shown in FIG. 20 and other figures, the two main bodies 321 are arranged parallel to the conductor principal surface 121 a of the conductor portion 121, the conductor principal surface 122 a of the conductor portion 122, and the conductor principal surface 123 a of each conductor portion 123. In the thickness direction z, the two main bodies 321 are farther from the main surface metal layer 12 (the conductor portion 121, the conductor portion 122, and the two conductor portions 123) than the main body 311 of the conductive member 31. Each of the two main bodies 321 intersects the conductor portion 122 (the partition portion 1221) in a plan view. That is, each of the two main bodies 321 extends from one edge to the other edge of the partition portion 1221 of the conductor portion 122 in the second direction y in a plan view. Both surfaces of the two main body portions 321 in the thickness direction z are covered with sealing resin 50 .

[0112] The intermediate portion 323 is located between the two main body portions 321 in the first direction x. The intermediate portion 323 extends in the first direction x from each of the two main body portions 321. As can be seen from FIG. 12 , the intermediate portion 323 overlaps some of the multiple joint portions 312 of the conductive member 31 in a planar view. The intermediate portion 323 straddles the two conductor portions 121, 122 in a planar view. The intermediate portion 323 has multiple through holes 323a. The multiple through holes 323a penetrate the intermediate portion 323 in the thickness direction z. The multiple through holes 323a are arranged along the first direction x. Each of the multiple through holes 323a overlaps between the two conductor portions 121, 122 in a planar view.

[0113] 12 and 24 , the multiple bonding portions 322 are individually bonded to the principal surface electrodes 212 of the multiple semiconductor elements 21. Each of the multiple bonding portions 322 faces one of the principal surface electrodes 212 of the multiple semiconductor elements 21. In a plan view, the multiple bonding portions 322 extend in the first direction x from the multiple intermediate portions 323. The tip of each bonding portion 322 (the end opposite to the side connected to the intermediate portion 323) is located below the intermediate portion 323 in the thickness direction z (on the z1 side in the thickness direction z). The base end of each bonding portion 322 (the end connected to the intermediate portion 323) is bent in the thickness direction z so as to connect the tip of each bonding portion 322 and each intermediate portion 323, which are located at different positions in the thickness direction z.

[0114] 12 and 22 , the pair of joints 324 are individually joined to the conductors 123. The joining is, for example, solder joining. Alternatively, joining using a pressurized or low-pressure metal sintered body, joining by laser welding, or ultrasonic joining may be used. Each of the pair of joints 324 faces a corresponding one of the two conductors 123. Each of the pair of joints 324 is joined to the corresponding conductor 123 on the y1 side in the second direction y relative to the exposed region 123b.

[0115] 17 , the semiconductor module A10 further includes a conductive bonding layer 35. The conductive bonding layer 35 is interposed between the main surface electrodes 212 of the plurality of semiconductor elements 21 and the plurality of bonding portions 322. The conductive bonding layer 35 conductively bonds the main surface electrodes 212 of the semiconductor elements 21 to the plurality of bonding portions 322. The conductive bonding layer 35 is, for example, solder. Alternatively, the conductive bonding layer 35 may include a low-pressure metal sintered body.

[0116] The shapes of the two conductive members 31, 32 are not limited to the illustrated example. The conductive member 31 may be any member that electrically connects the conductor portion 121 to each of the main surface electrodes 222 of the plurality of semiconductor elements 22. The conductive member 32 may be any member that electrically connects the two conductor portions 123 to each of the main surface electrodes 212 of the plurality of semiconductor elements 21.

[0117] First Embodiment: Manufacturing Method of Semiconductor Module A10: Next, a manufacturing method of the semiconductor module A10 will be described with reference to FIGS. 26 to 32. FIG. 26 is a flowchart showing an example of a manufacturing method of the semiconductor module A10. FIGS. 27 to 30 and 32 are cross-sectional views showing one step of the manufacturing method of the semiconductor module A10. Each cross section in FIGS. 27 to 30 and 32 corresponds to the cross-sectional position in FIG. 25. FIG. 31 is a plan view showing one step of the manufacturing method of the semiconductor module A10.

[0118] As shown in FIG. 26, the manufacturing method of the semiconductor module A10 according to this embodiment includes a substrate preparation step S101, an element bonding step S102, a signal substrate bonding step S103, a support substrate bonding step S104, a conductive member bonding step S105, a sleeve bonding step S106, a thermistor bonding step S107, a wire bonding step S108, a molding step S109, and a terminal connection step S110.

[0119] In the substrate preparation step S101, a support substrate 10 including an insulating substrate 11, a main surface metal layer 12, and a back surface metal layer 13 is prepared. In this embodiment, three support substrates 10 are prepared. The three prepared support substrates 10 are placed on, for example, a work table H1, as shown in Fig. 27. The work table H1 may be a transport device (for example, a belt conveyor or a transport robot) or may be desk-shaped.

[0120] In the element bonding step S102, as shown in FIG. 27 , a plurality of semiconductor elements 21 are mounted on the conductor portion 121 of each support substrate 10, and a plurality of semiconductor elements 22 are mounted on the conductor portion 122. For example, each of the plurality of semiconductor elements 21 is bonded to the conductor principal surface 121 a of the conductor portion 121 by a conductive bonding layer 219, and each of the plurality of semiconductor elements 22 is bonded to the conductor principal surface 122 a of the conductor portion 122 (partition portion 1221) by a conductive bonding layer 229. These bonding processes are performed, for example, by the full-surface diffusion bonding described above. In this full-surface diffusion bonding, the aforementioned insert metal is sandwiched between each semiconductor element 21 and the conductor portion 121, and pressure (see arrows in FIG. 27 ) is applied to each semiconductor element 21 from above in the thickness direction z toward the work table H1. The aforementioned insert metal is sandwiched between each semiconductor element 22 and the conductor portion 122, and pressure is applied to each semiconductor element 22 from above in the thickness direction z toward the workbench H1. As a result, the metal layers on both sides of the base layer of each insert metal in the thickness direction z are solid-phase diffusion bonded to the back electrode 211 and conductor portion 121 of each semiconductor element 21, or to the back electrode 221 and conductor portion 122 of each semiconductor element 22, respectively, thereby forming each insert metal into the conductive bonding layer 219, 229. That is, each semiconductor element 21 is conductively bonded to the conductor portion 121 by the conductive bonding layer 219, and each semiconductor element 22 is conductively bonded to the conductor portion 122 by the conductive bonding layer 229. Alternatively, the bonding between each semiconductor element 21 and the conductor portion 121 or the bonding between each semiconductor element 22 and the conductor portion 122 may be performed using a pressurized metal sintered body (a sintered body of metal particles formed by pressure). Full-surface diffusion bonding differs from bonding using a pressurized metal sintered body in that it uses the aforementioned insert metal. In bonding using a pressurized metal sintered body, a conductive bonding layer 219 is sandwiched between each semiconductor element 21 and the conductor portion 121, and pressure (see arrows in FIG. 27 ) is applied to each semiconductor element 21 from above in the thickness direction z toward the work table H1 to bond the metal particles of the conductive bonding layer 219. The same applies to bonding each semiconductor element 22 and the conductor portion 122 using a conductive bonding layer 229. As described above, a moderate amount of pressure is required in the process of bonding each semiconductor element 21, 22 to the support substrate 10 (element bonding process S102). In this embodiment, the element bonding process S102 is an example of a "first bonding process."

[0121] In the signal substrate bonding process S103, the two signal substrates 601, 602 are bonded to corresponding ones of the two conductor portions 121, 122 of each support substrate 10. This bonding is, for example, solder bonding, but may also be full-surface diffusion bonding (solid-phase diffusion bonding using an insert metal) or bonding using a pressurized metal sintered body. When the signal substrates 601, 602 are bonded to the corresponding support substrate 10 by full-surface diffusion bonding or bonding using a pressurized metal sintered body in the signal substrate bonding process S103, the signal substrate bonding process S103 is an example of a "first bonding process."

[0122] In the support substrate bonding process S104, as shown in FIG. 28 , each of the multiple support substrates 10 is bonded to the heat dissipation member C10. For example, the backside metal layer 13 of the support substrate 10 is bonded to the main surface 71a of the top plate 71 of the heat dissipation member C10 using a bonding layer 109. This bonding is performed using a method that allows bonding at a lower pressure than in the element bonding process S102. That is, this bonding is performed using a method that allows bonding at a lower pressure than full-surface diffusion bonding and bonding using a pressurized metal sintered body. For example, this bonding is performed using solder as the bonding layer 109. In the support substrate bonding process S104, the bonding layer 109 is formed by melting solder by reflow and then solidifying the solder. The temperature at which the bonding layer 109 is formed (i.e., the bonding temperature between each support substrate 10 and the heat dissipation member C10 using the bonding layer 109) is, for example, approximately 260°C. As described above, the step of bonding each support substrate 10 to the top plate 71 of the heat dissipation member C10 (support substrate bonding step S104) does not require any particular pressure (however, pressure sufficient to fix each support substrate 10 and the heat dissipation member C10 may be applied to suppress vibration of these). In this embodiment, the support substrate bonding step S104 is an example of a "second bonding step." The bonding layer 109 is not limited to solder as long as it can be bonded at a lower pressure than in the element bonding step S102, and may be, for example, a low-pressure metal sintered body (a sintered body of metal particles that can be formed at a low pressure).

[0123] In the conductive member bonding process S105, for each support substrate 10, conductive members 31 are bonded to the plurality of semiconductor elements 22 and conductor portions 121, and then conductive members 32 are bonded to the plurality of semiconductor elements 21 and two conductor portions 123. In the sleeve bonding process S106, for each support substrate 10, multiple sleeves 64 are bonded to the wiring layers 62 of the pair of signal substrates 601, 602 with a conductive adhesive (not shown). In the thermistor bonding process S107, for each support substrate 10, a thermistor 23 is mounted on the signal substrate 601. For example, the thermistor 23 is arranged so as to straddle two wiring portions 623, 624 of the signal substrate 601, and the two wiring portions 623, 624 of the signal substrate 601 are electrically connected to the thermistor 23 with a conductive adhesive (not shown). The signal substrate bonding step S103, the conductive member bonding step S105, the sleeve bonding step S106, and the thermistor bonding step S107 result in the state shown in Fig. 29. In this embodiment, the conductive member bonding step S105, the sleeve bonding step S106, and the thermistor bonding step S107 are performed by a method that allows bonding at a lower pressure than the element bonding step S102 (for example, solder bonding or bonding using a low-pressure metal sintered body), similar to the support substrate bonding step S104.

[0124] In the wire bonding step S108, a plurality of connection members 41 to 45 are formed on each support substrate 10. In an example in which the plurality of connection members 41 to 45 are bonding wires, in the wire bonding step S108, the connection members 41 to 45 are formed sequentially by ball bonding using a capillary. The order in which the plurality of connection members 41 to 45 are formed is not limited in any way. Alternatively, the connection members 41 to 45 may be formed sequentially by wedge bonding using a wedge tool. In this embodiment, the pressure applied in the wire bonding step S108 is lower than the pressure applied in the element bonding step S102. Here, if the pressure applied in the wire bonding step S108 is higher than the pressure applied in the element bonding step S102, the wire bonding step S108 is performed before the support substrate bonding step S104.

[0125] In the molding process S109, the sealing resin 50 is formed by, for example, molding. In the molding process S109, a mold M10 shown in FIG. 30 is used. The mold M10 includes an upper mold 81 and a lower mold 82. In the molding process S109, the main surface 71a and the back surface 71b of the top plate 71 are sandwiched between the upper mold 81 and the lower mold 82, respectively, in the thickness direction z.

[0126] The upper mold 81 presses the outer periphery 712 of the top plate 71 against the main surface 71a of the top plate 71 from above in the thickness direction z (the z2 side). As shown in FIG. 30 , a recess 811 is formed in the upper mold 81. When the upper mold 81 presses the top plate 71 from above in the thickness direction z, the recess 811 and the main surface 71a form a resin inlet cavity 801. The resin inlet cavity 801 is a void for forming the sealing resin 50. In the molding process S109, the material for the sealing resin 50 is injected into the resin inlet cavity 801 and cured. A plurality of protrusions 812 are formed in the recess 811. The plurality of protrusions 812 include one for forming the main surface opening 56, one for forming the plurality of recesses 571 and 572, and one for exposing the upper surfaces of the plurality of sleeves 64 (for forming the insertion holes 58 described below).

[0127] The lower mold 82 presses the outer periphery 712 of the top plate 71 against the back surface 71b of the top plate 71 from below in the thickness direction z (z1 side). As shown in Figure 30, a recess 821 is formed in the lower mold 82. When the lower mold 82 presses the top plate 71 from below in the thickness direction z, an avoidance cavity 802 is secured by the recess 821 and the back surface 71b. The avoidance cavity 802 is a gap for accommodating the case portion 74. In other words, the case portion 74 is accommodated in the recess 821.

[0128] The molding process S109 forms the sealing resin 50 shown in FIGS. 31 and 32 . The sealing resin 50 is formed on the main surface 71 a of the top plate 71 of the heat dissipation member C10 and covers the bonding layer 109 along with the support substrate 10 (and each component supported by the support substrate 10). The resin rear surface 52 of the sealing resin 50 contacts the main surface 71 a along with the underside of the bonding layer 109. As can be seen from FIGS. 30 to 32 , the sealing resin 50 formed by the molding process S109 has a main surface opening 56 (a plurality of openings 561, 562, 563) and a plurality of recesses 571, 572 formed in the resin main surface 51. As shown in FIGS. 31 and 32 , the sealing resin 50 formed by the molding process S109 has a plurality of through holes 58 formed in the resin main surface 51. The plurality of through holes 58 individually overlap with a plurality of sleeves 64 in a plan view. Each of the plurality of insertion holes 58 exposes an upper surface of the corresponding sleeve 64. The temperature at which the sealing resin 50 is formed in the molding step S109 is, for example, about 180° C. Therefore, the temperature at which the sealing resin 50 is formed is lower than the temperature at which the bonding layer 109 is formed.

[0129] In the terminal connecting step S110, a plurality of power terminals 15, 16, 17 and a plurality of signal terminals 19 are connected. As shown in Fig. 26 , the terminal connecting step S110 includes a power terminal connecting step S1101 and a signal terminal connecting step S1102. The order of the power terminal connecting step S1101 and the signal terminal connecting step S1102 is not particularly limited.

[0130] In the power terminal connecting step S1101, the power terminal 15 is inserted through each of the two openings 562 and joined to a portion of the conductor principal surface 122a (each exposed region 122b) of the conductor portion 122 that is exposed through the two openings 562. The power terminal 16 is inserted through each of the two openings 563 and joined to a portion of the conductor principal surface 123a (each exposed region 123b) of the conductor portion 123 that is exposed through the two openings 563. The power terminal 17 is inserted through each of the two openings 561 and joined to a portion of the conductor principal surface 121a (each exposed region 121b) of the conductor portion 121 that is exposed through the two openings 561. The power terminals 15, 16, and 17 are joined by, for example, laser welding. Alternatively, ultrasonic bonding or other joining methods may be used. This electrically connects the power terminals 15, 16, and 17 to the multiple semiconductor elements 21 and the multiple semiconductor elements 22.

[0131] In the signal terminal connecting step S1102, each signal terminal 19 is press-fitted into a corresponding one of the plurality of sleeves 64. In the signal terminal connecting step, the plurality of signal terminals 19 are individually inserted into the plurality of insertion holes 58, and each signal terminal 19 is press-fitted into the sleeve 64 exposed from the inserted insertion hole 58. In this way, each signal terminal 19 is electrically connected to any one of the plurality of semiconductor elements 21, the plurality of semiconductor elements 22, and thermistor 23.

[0132] The semiconductor module A10 shown in FIGS. 1 to 25 can be manufactured through the above steps. The manufacturing method for the semiconductor module A10 shown in FIG. 26 is merely an example and is not limited thereto. For example, the timing of the support substrate bonding step S104 is not limited as long as it is performed between the element bonding step S102 and the molding step S109. As an example, as shown in FIG. 33, the support substrate bonding step S104 may be performed between the wire bonding step S108 and the molding step S109. In the manufacturing method for the semiconductor module A10, the order of the signal substrate bonding step S103, the conductive member bonding step S105, the sleeve bonding step S106, the thermistor bonding step S107, and the wire bonding step S108 may be changed as appropriate. However, the element bonding step S102 must be performed before both the conductive member bonding step S105 and the wire bonding step S108, and the signal substrate bonding step S103 must be performed before the sleeve bonding step S106. In the manufacturing method of the semiconductor module A10, the respective bonding steps performed in the signal substrate bonding step S103, the conductive member bonding step S105, the sleeve bonding step S106, and the thermistor bonding step S107 may be performed by solder bonding, pressurized metal sintering, full-surface diffusion bonding, or ultrasonic bonding if performed before the support substrate bonding step S104, whereas if performed after the support substrate bonding step S104, they are performed by a method that allows bonding at a lower pressure than the element bonding step S102 (for example, solder bonding or bonding using a low-pressure metal sintering).

[0133] First embodiment: power conversion unit U10: Next, a power conversion unit U10 including a semiconductor module A10 will be described with reference to Fig. 34. The power conversion unit U10 includes the semiconductor module A10 and a control board E1.

[0134] As shown in FIG. 34 , the control substrate E1 is provided in common for the three semiconductor packages B10. Alternatively, multiple control substrates E1 may be provided individually for each of the three semiconductor packages B10. As can be seen from FIG. 34 , the signal terminals 19 of the three semiconductor packages B10 are inserted into the control substrate E1. The control substrate E1 is electrically connected to each of the signal terminals 19. The control substrate E1 includes, for example, a control circuit that controls the operation of the semiconductor elements 21 and 22 of the three semiconductor packages B10. In an example in which the semiconductor elements 21 and 22 are MOSFETs or IGBTs, the control substrate E1 is a gate driver. The control substrate E1 faces the upper surface (resin main surface 51) of the sealing resin 50 of each of the three semiconductor packages B10. The control substrate E1 is located on the opposite side of the three semiconductor packages B10 from the top plate 71 of the heat dissipation member C10. In a plan view, the control substrate E1 overlaps the sealing resin 50 of each of the three semiconductor packages B10. The control substrate E1 is held at a certain distance in the thickness direction z by a plurality of pedestals (not shown). The plurality of pedestals may be provided, for example, on the main surface 71 a of the top plate 71 of the heat dissipation member C10.

[0135] As shown in FIG. 35 , the control board E1 has a base material 91, main wiring 92, back wiring 93, and internal wiring 94. The base material 91 has a plurality of through holes 911 that penetrate in the thickness direction z. The main wiring 92 is formed on the upper surface of the base material 91 (the surface facing the z1 side in the thickness direction z). The back wiring 93 is formed on the lower surface of the base material 91 (the surface facing the z2 side in the thickness direction z). The internal wiring 94 is disposed on the inner surfaces of the plurality of through holes 911. The internal wiring 94 is connected to the main wiring 92 and the back wiring 93. The main wiring 92 forms a path for mutual conduction between the back wiring 93 and the internal wiring 94 and circuits provided on the control board E1.

[0136] Each signal terminal 19 of the three semiconductor packages B10 is inserted into a corresponding one of the multiple through holes 911 of the control board E1. Fig. 35 shows a state in which the signal terminal 19 of any one of the three semiconductor packages B10 is inserted into the through hole 911 of the base material 91. As can be seen from Fig. 35, each signal terminal 19 of the three semiconductor packages B10 is inserted into the through hole 911 of the base material 91.

[0137] As shown in Fig. 35 , each signal terminal 19 includes a tip portion 190. The tip portion 190 is an end portion of each signal terminal 19 that is far from the sealing resin 50. The tip portion 190 has a bulging portion 190A. As shown in Fig. 35 , the bulging portion 190A bulges out in a direction perpendicular to the thickness direction z in the signal terminal 19. In the illustrated example (e.g., Fig. 5 ), the bulging portion 190A of each signal terminal 19 is located higher in the thickness direction z than any of the multiple power terminals 15, 16, and 17.

[0138] As shown in FIG. 35 , the bulging portion 190A of each signal terminal 19 is press-fitted into one of the through-holes 911 of the control board E1. As a result, the internal wiring 94 arranged in one of the through-holes 911 is pressed against the bulging portion 190A of the signal terminal 19 inserted into that through-hole 911. Therefore, each signal terminal 19 is press-fitted into the through-hole 911 in the thickness direction z, thereby providing electrical continuity with the control board E1 (its control circuit). The control board E1 is supported by each signal terminal 19 by press-fitting each signal terminal 19 into a corresponding one of the through-holes 911. As can be seen from this configuration, the control board E1 is attached to the tip portion 190 of each signal terminal 19. Alternatively, each signal terminal 19 may not include a bulging portion 190A. That is, each signal terminal 19 may be a straight pin with no change in thickness. In this case, each signal terminal 19 is inserted into a through-hole 911 and then soldered to the control board E1.

[0139] The configuration of the power conversion unit U10 is not limited to the example shown in FIG. 34 . FIG. 36 shows a power conversion unit U11 according to a modified example. In the power conversion unit U11, the control board E1 includes two circuit boards E11 and E12. The two circuit boards E11 and E12 are spaced apart in the thickness direction z. The control board E1 of the power conversion unit U11 includes a plurality of interconnecting wires 96. The two circuit boards E11 and E12 are electrically connected to each other via the interconnecting wires 96. The configuration of the interconnecting wires 96 is not limited in any way, but may be configured as follows, for example. Each interconnecting wire 96 includes a plurality of connection pins provided on the circuit board E11 and a connector provided on the circuit board E12. In each interconnecting wire 96, the plurality of connection pins are connected to the connector, thereby electrically connecting the circuit board E11 and the circuit board E12. The power conversion unit U11 includes a plurality of positioning pins 97. Each positioning pin 97 is interposed between the two circuit boards E11 and E12. Each positioning pin 97 determines the position of the circuit board E12 relative to the circuit board E11 and is used to support the circuit board E12.

[0140] First Embodiment: Vehicle F1: Next, a vehicle F1 equipped with a semiconductor module A10 will be described with reference to FIG. 37. The vehicle F1 is, for example, an electric vehicle (EV). In FIG. 37, the semiconductor module A10 is described as being equipped in the vehicle F1 as the power conversion unit U10, but the semiconductor module A10 may also be equipped in the vehicle F1 as the semiconductor module A10. In this case, a control board E1 is separately provided in the vehicle F1.

[0141] As shown in Fig. 37, the vehicle F1 includes an on-board charger F11, a storage battery F12, and a drive system F13. The on-board charger F11 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger F11 via a wired connection. The on-board charger F11 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger F11 is stepped up by the converter and then supplied to the storage battery F12. The stepped-up voltage is, for example, 600 V.

[0142] The drive system F13 drives the vehicle F1. The drive system F13 includes an inverter F131 and a drive source F132. The power conversion unit U10 (semiconductor module A10) constitutes part of the inverter F131. Power stored in the storage battery F12 is supplied to the inverter F131. The power supplied from the storage battery F12 to the inverter F131 is DC power. Alternatively, unlike the power system shown in FIG. 37 , a step-up DC-DC converter may be further provided between the storage battery F12 and the inverter F131. The inverter F131 converts DC power into AC power. The inverter F131, including the power conversion unit U10 (semiconductor module A10), is electrically connected to the drive source F132. The drive source F132 includes an AC motor and a transmission. When AC power converted by the inverter F131 is supplied to the drive source F132, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle F1. This drives the vehicle F1. To drive the vehicle F1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the power conversion unit U10 (semiconductor module A10) in the inverter F131 is necessary to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0143] The functions and effects of the semiconductor module A10 and the method for manufacturing the semiconductor module A10 are as follows.

[0144] The manufacturing method for the semiconductor module A10 includes a second bonding step of bonding the support substrate 10 to the heat dissipation member C10 with the bonding layer 109 and a molding step S109 of forming the sealing resin 50 that covers each of the semiconductor elements 21 and 22. In this embodiment, the second bonding step is, for example, the support substrate bonding step S104. The molding step S109 is performed after the support substrate bonding step S104. With this configuration, when the molding step S109 is performed, the support substrate bonding step S104 has already been completed. Therefore, the semiconductor module A10 being manufactured after the molding step S109 is not placed in an environment with a temperature higher than the temperature at which the sealing resin 50 is formed. Therefore, the manufacturing method for the semiconductor module A10, in which the support substrate 10 is bonded to the heat dissipation member C10, can better maintain the shape of the sealing resin 50.

[0145] The manufacturing method for the semiconductor module A10 includes a first bonding step of bonding components to the support substrate 10 and a second bonding step of bonding the support substrate 10 to the heat dissipation member C10 using a bonding layer 109. In this embodiment, the first bonding step is, for example, an element bonding step S102 of bonding each semiconductor element 21, 22 as a component to the support substrate 10. The second bonding step is, for example, a support substrate bonding step S104. The second bonding step (e.g., the support substrate bonding step S104) uses a lower pressure than the first bonding step (e.g., the element bonding step S102), and the second bonding step is performed after the first bonding step. This configuration allows the first bonding step, which requires a higher pressure than the second bonding step, to be performed before the second bonding step. This allows each component to be bonded using a bonding method requiring a higher pressure before bonding the support substrate 10 to the heat dissipation member C10. Therefore, the manufacturing method for the semiconductor module A10 reduces the pressure applied to the heat dissipation member C10. For example, in the semiconductor module A10, by reducing the pressure applied to the heat dissipation member C10, it is possible to reduce deformation of the case portion 74 and the heat dissipation portion 75 (the plurality of heat dissipation fins 751).

[0146] According to the manufacturing method of the semiconductor module A10, the support substrate bonding step S104 (second bonding step) is performed after the element bonding step S102 (first bonding step). Therefore, when the element bonding step S102 is performed, the support substrates 10 are not bonded to the heat dissipation member C10. Therefore, in the element bonding step S102, pressure can be applied to the conductive bonding layers 219, 229 from below in the thickness direction z through the support substrate 10. This means that the semiconductor elements 21, 22 can be bonded to the support substrate 10 using a bonding method requiring high pressure, such as the full-surface diffusion bonding (solid-phase diffusion bonding using an insert metal), bonding using a pressurized metal sintered body, or ultrasonic bonding. Therefore, the manufacturing method of the semiconductor module A10 can increase the bonding strength between the semiconductor elements 21, 22 and the support substrate 10 using the conductive bonding layers 219, 229. This means that the manufacturing method of the semiconductor module A10 can prevent the semiconductor elements 21, 22 from peeling off from the support substrate 10.

[0147] In the manufacturing method of the semiconductor module A10, the support substrate bonding step S104 bonds the support substrate 10 and the heat dissipation member C10 with the bonding layer 109 at a lower pressure than the element bonding step S102. This configuration allows the support substrate 10 to be bonded to the heat dissipation member C10 without applying a large pressure to the bonding layer 109. In particular, in the semiconductor module A10, the heat dissipation member C10 has a housing 70 having a hollow portion 701. In this configuration, the hollow portion 701 makes it difficult to apply pressure to the bonding layer 109 from below in the thickness direction z through the heat dissipation member C10. In other words, bonding between the support substrate 10 and the heat dissipation member C10 using a pressurized metal sintered body, the above-mentioned full-surface diffusion bonding, or ultrasonic bonding is difficult. Therefore, in the manufacturing method of the semiconductor module A10, the support substrate 10 can be bonded to the heat dissipation member C10 having the hollow portion 701 via the bonding layer 109.

[0148] In the manufacturing method of the semiconductor module A10, solder bonding is performed in the support substrate bonding step S104. With this configuration, the support substrate bonding step S104 can be performed at a lower pressure than when the element bonding step S102 is performed by the above-mentioned full-surface diffusion bonding, bonding using a pressurized metal sintered body, ultrasonic bonding, etc. In other words, the second bonding step (support substrate bonding step S104) can be performed at a lower pressure than the first bonding step (element bonding step S102).

[0149] In the manufacturing method of the semiconductor module A10, the temperature at which the sealing resin 50 is formed in the molding step S109 is lower than the temperature at which the bonding layer 109 is formed in the support substrate bonding step S104. This configuration can prevent the bonding layer 109 from melting when the sealing resin 50 is formed.

[0150] In the semiconductor module A10, the side surface of the bonding layer 109 facing in a direction perpendicular to the thickness direction z is covered with the sealing resin 50. This configuration can increase the bonding strength between the support substrate 10 and the heat dissipation member C10 by the bonding layer 109. In other words, the manufacturing method for the semiconductor module A10 can prevent the support substrate 10 from peeling off from the heat dissipation member C10.

[0151] In the semiconductor module A10, the power terminals 15, 16, and 17 are exposed at the resin main surface 51. Alternatively, the power terminals 15, 16, and 17 may be configured to protrude from one of the resin side surfaces 531 to 534. In this case, the sealing resin 50 is formed after the power terminals 15, 16, and 17 are bonded to the support substrate 10. In other words, the molding step S109 is performed after the power terminal connection step S1101. However, in this configuration, regions above and below the power terminals 15, 16, and 17 in the thickness direction z may be formed where the sealing resin 50 is difficult to form properly. In contrast, in the manufacturing method for the semiconductor module A10, the power terminal connection step S1101 is performed after the molding step S109. As a result, the power terminals 15, 16, and 17 are not present when the sealing resin 50 is formed, allowing the sealing resin 50 to be formed properly. Therefore, in the semiconductor module A10, a configuration in which each power terminal 15, 16, 17 is exposed on the resin main surface 51 is a preferable structure when performing the power terminal connection process S1101 after the molding process S109, compared to a configuration in which each power terminal 15, 16, 17 protrudes from one of the multiple resin side surfaces 531 to 534.

[0152] The semiconductor module A10 includes a semiconductor element 21, an insulating substrate 11, a conductor portion 123, and a sealing resin 50. The conductor portion 123 has a conductor principal surface 123a and is electrically connected to the semiconductor element 21. The insulating substrate 11 is located inward from the periphery of the sealing resin 50 in the thickness direction z. The sealing resin 50 has a resin principal surface 51 and a principal surface opening 56 formed in the resin principal surface 51. The principal surface opening 56 includes an opening 563 that exposes a portion of the conductor principal surface 123a from the resin principal surface 51. With this configuration, the conductor principal surface 123a (the conductor portion 123) is exposed from the resin principal surface 51 of the sealing resin 50 through the opening 563, making it possible to electrically connect a power terminal 16 to the conductor portion 123 after the sealing resin 50 is formed. In other words, the semiconductor module A10 allows for the placement of a power terminal for handling power supply voltage after the sealing resin 50 is formed.

[0153] In the molding step S109 in the manufacturing method of the semiconductor module A10, a main surface opening 56 is formed in the resin main surface 51 to expose a portion of the support substrate 10 (e.g., a portion of the conductor main surface 121a, a portion of the conductor main surface 122a, and a portion of the conductor main surface 123a). With this configuration, the power terminal connecting step S1101 (a step of connecting the power terminals 15, 16, and 17 from the main surface opening 56 and electrically connecting each of the power terminals 15, 16, and 17 to one of the semiconductor elements 21 and 22) can be performed after the molding step S109. In other words, the manufacturing method of the semiconductor module A10 allows the power terminals (the power terminals 15, 16, and 17) that handle the power supply voltage to be arranged after the sealing resin 50 is formed.

[0154] In the semiconductor module A10, the opening 563 is rectangular in shape with its longer side extending in the second direction y as viewed in the thickness direction z. In the semiconductor module A10, the power terminal 16 includes a joint 161 and a suspension 162. The joint 161 is a portion joined to the exposed region 123b (the region of the conductor principal surface 123a exposed through the opening 563). The suspension 162 is a portion extending from the joint 161 as viewed in the thickness direction z. The suspension 162 extends from the joint 161 in the first direction x as viewed in the thickness direction z. In this configuration, the opening 563 is rectangular in shape with its shorter side extending in the direction (first direction x) in which the suspension 162 extends from the joint 161. In other words, the longer side of the opening 563 is in the direction (second direction y) perpendicular to the direction (first direction x) in which the suspension 162 extends from the joint 161. This configuration allows the size (width) of the power terminal 16 to be increased in the direction perpendicular to the direction of current flow, which means that the cross-sectional area of ​​the power terminal 16 can be increased relative to the flow of current, thereby reducing the wiring resistance of the power terminal 16.

[0155] The semiconductor module A10 includes an insulating substrate 11, conductor portions 121 and 123, and a conductive member 32. The conductor portions 121 and 123 are bonded to the main surface 11a of the insulating substrate 11. The semiconductor element 21 is mounted on the conductor portion 121. The conductor portion 123 is spaced from the conductor portion 121. The conductive member 32 is bonded to a main surface electrode 212 of the semiconductor element 21. The conductive member 32 is electrically connected to the conductor portion 123 and supported by the conductor portion 123. With this configuration, heat generated by the semiconductor element 21 is transferred to the conductive member 32. Furthermore, the conductive member 32 generates heat due to parasitic resistance (wiring resistance) when a current flows through it. The heat transferred to or generated by the conductive member 32 is then transferred to the conductor portion 123 and dissipated to the outside of the semiconductor module A10 via the insulating substrate 11. Therefore, the semiconductor module A10 can improve the heat dissipation performance of heat that may accumulate in the conductive member 32 by dissipating heat through the conductor 123. That is, the semiconductor module A10 can improve the heat dissipation performance. In particular, in the semiconductor module A10, some of the multiple heat dissipation fins 751 are arranged below each conductor 123 in the thickness direction z. This can improve the heat dissipation performance of each conductor 123. That is, the semiconductor module A10 can further improve the heat dissipation performance of heat that may accumulate in the conductive member 32.

[0156] In the semiconductor module A10, the conductive member 32 forms a path through which a main current flows. The main current refers to a current corresponding to the power before or after conversion by the switching operations of the multiple semiconductor elements 21 and the multiple semiconductor elements 22. In this configuration, a large current flows through the conductive member 32, which can lead to increased heat generation due to the parasitic resistance (wiring resistance) of the conductive member 32. This means that the amount of heat that can accumulate in the conductive member 32 can be large. Therefore, improving the heat dissipation performance of the conductive member 32 is important for improving the heat dissipation performance of the semiconductor module A10. In particular, the main body 321 of the conductive member 32 is strip-shaped extending in the second direction y and has a small cross-sectional area relative to the main current. Therefore, the parasitic resistance of the main body 321 is large, and self-heat generation in the main body 321 can also be large. In other words, improving the heat dissipation performance of the conductive member 32 is particularly important in the semiconductor module A10. Therefore, in the semiconductor module A10, as described above, the heat dissipation properties of the conductive member 32 are improved by connecting the conductive member 32 to the conductor portion 123. In other words, the semiconductor module A10 has a preferable structure for improving the heat dissipation properties of the semiconductor module A10.

[0157] In the semiconductor module A10, the opening 561 is rectangular with its longer side extending in the first direction x as viewed in the thickness direction z. In the semiconductor module A10, the power terminal 17 includes a joint 171 and a suspension 172. The joint 171 is a portion joined to the exposed region 121b (a region of the conductor principal surface 121a exposed through the opening 561). The suspension 172 is a portion extending from the joint 171 as viewed in the thickness direction z. An end of the suspension 172 connected to the joint 171 extends from the joint 171 in the second direction y as viewed in the thickness direction z. In this configuration, the opening 561 is rectangular with its shorter side extending in the direction in which the suspension 172 extends from the joint 171 (the second direction y). That is, the long side of the opening 561 is in a direction (first direction x) perpendicular to the direction (second direction y) in which the suspension portion 172 extends from the joint portion 171. With this configuration, the size (width) of the power terminal 17 can be increased in the direction perpendicular to the direction of current flow. In other words, the cross-sectional area of ​​the power terminal 17 can be increased relative to the flowing current, thereby reducing the wiring resistance of the power terminal 17.

[0158] In the semiconductor module A10, the opening 562 is rectangular in shape with its longer side extending in the second direction y as viewed in the thickness direction z. In the semiconductor module A10, the power terminal 15 includes a joint 151 and a suspension 152. The joint 151 is a portion joined to the exposed region 122b (a region of the conductor principal surface 122a exposed through the opening 562). The suspension 152 is a portion extending from the joint 151 as viewed in the thickness direction z. An end of the suspension 152 connected to the joint 151 extends from the joint 151 in the first direction x as viewed in the thickness direction z. In this configuration, the opening 562 is rectangular in shape with its shorter side extending in the direction in which the suspension 152 extends from the joint 151 (first direction x). That is, the long side of the opening 562 is in a direction (second direction y) perpendicular to the direction (first direction x) in which the suspension portion 152 extends from the joint portion 151. With this configuration, the size (width) of the power terminal 15 can be increased in the direction perpendicular to the direction of current flow. In other words, the cross-sectional area of ​​the power terminal 15 can be increased relative to the flowing current, thereby reducing the wiring resistance of the power terminal 15.

[0159] The semiconductor module A10 includes two conductor portions 123. In the semiconductor module A10, the main surface opening 56 includes two openings 563, which expose the two conductor portions 123 from the resin main surface 51. In the semiconductor module A10, the main surface opening 56 includes two openings 562. The two openings 562 are aligned in the first direction x between the two openings 563. Unlike this configuration, it is possible to connect the two openings 563 to form a single opening. However, if the two openings 563 are connected to form a single opening, regions on both sides of the single opening in the second direction y may be created where it is difficult to properly form the sealing resin 50. In contrast, if two openings 563 are provided, a flow path for the sealing resin 50 can be secured between the two openings 563. In other words, the semiconductor module A10 has a structure that is preferable for properly forming the sealing resin 50.

[0160] In the semiconductor module A10, the resin main surface 51 has a recess 571 recessed downward in the thickness direction z from the resin main surface 51. In a plan view, the recess 571 is located between the two openings 562 and 563 and the multiple signal terminals 192, 194, and 196. This configuration increases the creepage distance along the resin main surface 51 between the signal terminals 192, 194, and 196 and the power terminals 15 inserted through the two openings 562 and the power terminals 16 inserted through the two openings 563. In other words, the semiconductor module A10 can reduce unintended short circuits between the multiple signal terminals 192, 194, and 196 and the two power terminals 15 and 16.

[0161] In the semiconductor module A10, the resin main surface 51 has two recesses 572 that are recessed downward in the thickness direction z from the resin main surface 51. Each of the two recesses 572 is located between the corresponding opening 561 and the multiple signal terminals 191, 193, and 197. This configuration increases the creepage distance along the resin main surface 51 between the signal terminals 191, 193, and 197 and the power terminals 17 inserted through the two openings 561. In other words, the semiconductor module A10 can reduce unintended short circuits between the multiple signal terminals 191, 193, and 197 and the power terminals 17.

[0162] In the power terminal connection step S1101 of the manufacturing method for the semiconductor module A10, the power terminals 15, 16, and 17 are joined to the corresponding conductors 121, 122, and 123, for example, by laser welding. Alternatively, the power terminals 15, 16, and 17 may be joined to the corresponding conductors 121, 122, and 123 by soldering, for example. However, in the manufacturing method for the semiconductor module A10, the terminal connection step S110 is performed after the molding step S109. Therefore, soldering may result in a higher temperature environment than the temperature at which the encapsulating resin 50 is formed. On the other hand, when the power terminals 15, 16, and 17 are joined by laser welding, heating is localized and short, minimizing the thermal impact on the surrounding area. Therefore, thermal deformation of the encapsulating resin 50 can be suppressed. In other words, the manufacturing method for the semiconductor module A10 allows the encapsulating resin 50 to maintain its shape better.

[0163] In the molding step S109 of the manufacturing method of the semiconductor module A10, insertion holes 58 are formed in the sealing resin 50. With this configuration, the signal terminal connecting step S1102 (a step of connecting each signal terminal 19 through the insertion holes 58 and electrically connecting each signal terminal 19 to one of the semiconductor elements 21, 22) can be performed after the molding step S109. That is, in the manufacturing method of the semiconductor module A10, each signal terminal 19 can be arranged after the sealing resin 50 is formed.

[0164] In the semiconductor module A10, the periphery of the sealing resin 50 in a plan view is enclosed within the periphery of the heat dissipation member C10 in a plan view. That is, the entire sealing resin 50 is located above the heat dissipation member C10 in the thickness direction z. This configuration allows the volume of the sealing resin 50 to be reduced, thereby reducing the cost of the semiconductor module A10.

[0165] Other embodiments and modifications of the semiconductor module A10 of the present disclosure will be described below. The configurations of the components in the embodiments and modifications can be combined with each other to the extent that no technical contradictions arise.

[0166] 38 shows a semiconductor module A11 according to a first modification of the first embodiment. The semiconductor module A11 differs from the semiconductor module A10 in the configuration of the heat dissipation member C10. Specifically, the housing 70 of the heat dissipation member C10 of the semiconductor module A11 includes a plurality of case portions 74.

[0167] In the illustrated example, the housing 70 includes three case portions 74. The three case portions 74 are provided individually for the three semiconductor packages B10. The three case portions 74 are located below the corresponding semiconductor packages B10 in the thickness direction z. Each of the three case portions 74 houses a plurality of heat dissipation fins 751 arranged in three separate regions. Each of the three case portions 74 is connected to one inlet portion 72 and one outlet portion 73. Therefore, the heat dissipation member C10 of the semiconductor module A11 includes three inlet portions 72 and three outlet portions 73.

[0168] In the semiconductor module A11, the cooling efficiency of each semiconductor package B10 can be made uniform compared to the semiconductor module A10.

[0169] 39 shows a semiconductor module A12 according to a second modification of the first embodiment. The semiconductor module A12 differs from the semiconductor module A10 in the following respect: the heat dissipation member C10 includes a base 76 instead of the housing 70.

[0170] The base 76 is configured similarly to the top plate 71 in the semiconductor module A10. The heat dissipation section 75 (multiple heat dissipation fins 751) is connected to the base 76. The base 76 has a main surface 76a and a back surface 76b that are spaced apart in the thickness direction z. The main surface 76a faces upward in the thickness direction z, and the back surface 76b faces downward in the thickness direction z. The multiple heat dissipation fins 751 extend downward in the thickness direction z from the back surface 76b. In the housing 70 of the semiconductor module A12, the heat dissipation section 75 (multiple heat dissipation fins 751) is exposed to the outside.

[0171] The semiconductor modules A11 and A12 according to the above-described modifications also achieve the same effects as the semiconductor module A10. As can be seen from the semiconductor modules A11 and A12 according to the above-described modifications, the configuration of the heat dissipation member C10 in the semiconductor modules of the present disclosure is not limited in any way. For example, in a configuration different from that of the semiconductor module A12, the heat dissipation member C10 may not include the heat dissipation portion 75 (plurality of heat dissipation fins 751) and may be composed of only the plate-shaped base 76.

[0172] 40 and 41 show a semiconductor module A20 according to a second embodiment. The semiconductor module A20 differs from the semiconductor module A10 in the following respect. That is, each sealing resin 50 protrudes in the second direction y beyond the top plate 71 of the heat dissipation member C10 in a plan view. The semiconductor modules A10 and A20 have different structures, but share the same manufacturing method (each step).

[0173] In the semiconductor module A20, the two resin side surfaces 531, 532 of each semiconductor package B10 are each located outward from the top plate 71 in a plan view. As shown in FIG. 41 , both side surfaces of the top plate 71 in the second direction y are covered with the sealing resin 50. In the illustrated example, the back surface 71b of the top plate 71 and the resin back surface 52 are flush with each other. Unlike this example, the resin back surface 52 of the sealing resin 50 of each semiconductor package B10 may be positioned so as to overlap the top plate 71 (between the main surface 71a and the back surface 71b) when viewed in the second direction y.

[0174] In the semiconductor module A20, as in the semiconductor module A10, the shape of the sealing resin 50 can be maintained more favorably. Additionally, the semiconductor module A20 (and its manufacturing method) has a common configuration with the semiconductor module A10 (and its manufacturing method), and thus achieves the same effects as the semiconductor module A10 (and its manufacturing method). For example, in the semiconductor module A20, as in the semiconductor module A10, the support substrate 10 can be bonded to the heat dissipation member C10 having a hollow portion 701 via a bonding layer 109. In the semiconductor module A20, as in the semiconductor module A10, the bonding strength between the support substrate 10 and the heat dissipation member C10 due to the bonding layer 109 can be increased, thereby preventing the support substrate 10 from peeling off from the heat dissipation member C10.

[0175] In the semiconductor module A20, compared to the semiconductor module A10, both side surfaces of the top plate 71 in the second direction y are covered with the sealing resin 50. With this configuration, the contact area between the sealing resin 50 and the heat dissipation member C10 (top plate 71) can be increased, and therefore, peeling of each semiconductor package B10 from the heat dissipation member C10 can be suppressed.

[0176] Third Embodiment: Figure 42 shows a semiconductor module A30 according to a third embodiment. The semiconductor module A30 differs from the semiconductor module A10 in the following respect: a plurality of support substrates 10 (and a plurality of semiconductor elements 21, 22, etc. mounted on each support substrate 10) are covered with a single sealing resin 50. The semiconductor modules A10 and A30 have different structures, but share the same manufacturing method (each step).

[0177] In the semiconductor module A30, a plurality of semiconductor elements 21, 22, etc. are mounted on each of a plurality of support substrates 10, and the above-mentioned half-bridge circuit is configured on each of the plurality of support substrates 10. In other words, in the semiconductor module A30, a plurality of half-bridge circuits are covered with a single sealing resin 50. In the illustrated example, three support substrates 10 are provided, but the number of support substrates 10 may be one. In this case, a plurality of main surface metal layers 12 are bonded to the substrate main surface 11a of the common insulating substrate 11, and three half-bridge circuits are formed on each main surface metal layer 12.

[0178] In the semiconductor module A30, like the semiconductor module A10, the shape of the sealing resin 50 can be maintained more favorably. Additionally, the semiconductor module A30 (and its manufacturing method) has a common configuration with the semiconductor modules A10 and A20 (and their manufacturing methods), and thus achieves the same effects as the semiconductor modules A10 and A20 (and their manufacturing methods). For example, in the semiconductor module A30, like the semiconductor module A10, the support substrate 10 can be bonded to the heat dissipation member C10 having a hollow portion 701 via a bonding layer 109. In the semiconductor module A30, like the semiconductor module A10, the bonding layer 109 can increase the bonding strength between the support substrate 10 and the heat dissipation member C10, thereby preventing the support substrate 10 from peeling off from the heat dissipation member C10.

[0179] As can be seen from the semiconductor module A30, the semiconductor module of the present disclosure is not limited to a configuration in which multiple half-bridge circuits (such as multiple support substrates 10 and multiple semiconductor elements 21, 22 arranged on each of the multiple support substrates 10) are individually covered with the sealing resin 50, but also includes a configuration in which multiple half-bridge circuits are covered with a single sealing resin 50. However, considering the difference in thermal expansion coefficient between the heat dissipation member C10 and the sealing resin 50, a configuration in which multiple half-bridge circuits are individually covered with multiple sealing resins 50 is preferable.

[0180] 43 shows a semiconductor module A31 according to a modification of the third embodiment. The semiconductor module A31 differs from the semiconductor module A30 in the following respect: the sealing resin 50 protrudes in the first direction x beyond the top plate 71 of the heat dissipation member C10.

[0181] In the semiconductor module A31, two resin side surfaces 533, 534 of the sealing resin 50 are each located outward from the top plate 71. As shown in FIG. 43 , both side surfaces of the top plate 71 in the first direction x are covered with the sealing resin 50. In the illustrated example, the back surface 71b of the top plate 71 and the resin back surface 52 are flush with each other. Unlike this example, the resin back surface 52 may be located so as to overlap the top plate 71 when viewed in the first direction x.

[0182] The semiconductor module A31 also achieves the same effects as the semiconductor module A30. Furthermore, in the semiconductor module A31, compared to the semiconductor module A30, both side surfaces of the top plate 71 in the first direction x are covered with the sealing resin 50. This configuration increases the contact area between the sealing resin 50 and the heat dissipation member C10 (top plate 71), thereby preventing the semiconductor package B10 from peeling off from the heat dissipation member C10.

[0183] Fourth Embodiment: Figure 44 shows a semiconductor module A40 according to a fourth embodiment. The semiconductor module A40 differs from the semiconductor module A10 in the following respect: four semiconductor packages B10 are bonded to a heat dissipation member C10. The semiconductor modules A10 and A40 have different structures, but share the same manufacturing method (each step).

[0184] In the illustrated example, the four semiconductor packages B10 are arranged in two rows and two columns in the first direction x and the second direction y in a plan view. In the illustrated example, the semiconductor packages B10 on the y1 side in the second direction y are bonded to the heat dissipation member C10 in a position inverted from the semiconductor packages B10 on the y2 side in the second direction y in a plan view. In this configuration, the power terminals 17 of the semiconductor packages B10 are arranged close to each other. Alternatively, the semiconductor packages B10 on the y1 side in the second direction y and the semiconductor packages B10 on the y2 side in the second direction y may be arranged so that the power terminals 15, 16 are close to each other. Alternatively, the semiconductor packages B10 on the y1 side in the second direction y and the semiconductor packages B10 on the y2 side in the second direction y do not need to be inverted from each other.

[0185] In the semiconductor module A40, as in the semiconductor module A10, the shape of the sealing resin 50 can be more properly maintained. Furthermore, the semiconductor module A40 (and its manufacturing method) has a common configuration with the semiconductor modules A10, A20, and A30 (and their manufacturing methods), and thus achieves the same effects as the semiconductor modules A10, A20, and A30 (and their manufacturing methods). For example, in the semiconductor module A40, as in the semiconductor module A10, the support substrate 10 can be bonded to the heat dissipation member C10 having a hollow portion 701 via a bonding layer 109. In the semiconductor module A40, as in the semiconductor module A10, the bonding layer 109 can increase the bonding strength between the support substrate 10 and the heat dissipation member C10, thereby preventing the support substrate 10 from peeling off from the heat dissipation member C10.

[0186] As can be seen from the semiconductor module A40, in the semiconductor module of the present disclosure, there is no limitation on the number of semiconductor packages B10 for one heat dissipation member C10. For example, in the semiconductor module of the present disclosure, one semiconductor package B10 or multiple semiconductor packages B10 may be provided for one heat dissipation member C10.

[0187] In the first to fourth embodiments (including their modified examples), the configuration of each semiconductor package B10 is not limited to the above example. Other configuration examples of each semiconductor package in the semiconductor module of the present disclosure (each semiconductor package B11 to B15) will be described below.

[0188] 45 and 46 show a semiconductor package B11 according to a first modified example. The semiconductor package B11 differs from the semiconductor package B10 in the following respects. First, the resin main surface 51 of the sealing resin 50 has a protrusion 573 instead of a recess 571. Second, the resin main surface 51 of the sealing resin 50 has two protrusions 574 instead of two recesses 572.

[0189] The protrusion 573 and the two protrusions 574 each protrude upward in the thickness direction z from the resin main surface 51. In plan view, the protrusion 573 and the two protrusions 574 are each interposed between the main surface opening 56 and one of the multiple signal terminals 19. Like the recess 571, the protrusion 573 is located between the two openings 562 and 563 and the multiple signal terminals 192, 194, and 196 in plan view. Like one of the two recesses 572, one of the two protrusions 574 is located between one of the two openings 561 and the multiple signal terminals 191, 193, and 197. Like the other of the two recesses 572, the other of the two protrusions 574 is located between the other of the two openings 561 and the multiple signal terminals 191, 193, and 197.

[0190] In each semiconductor package B11, a protrusion 573, instead of the recess 571, can increase the creepage distance along the resin main surface 51 between the multiple signal terminals 192, 194, 196 and the power terminal 15 inserted into the two openings 562 and the power terminal 16 inserted into the two openings 563. In each semiconductor package B11, a protrusion 574, instead of the recess 572, can increase the creepage distance along the resin main surface 51 between the multiple signal terminals 191, 193, 197 and the power terminal 17 inserted into the two openings 561.

[0191] 47 shows a semiconductor package B12 according to a second modified example. The semiconductor package B12 differs from the semiconductor package B10 in the following respects. First, the sealing resin 50 has a recess 521 recessed in the thickness direction z from the resin rear surface 52. Second, the top plate 71 (heat dissipation member C10) has a protrusion 715 protruding in the thickness direction z from the main surface 71 a.

[0192] The protrusions 715 are fitted into the recesses 521. At least one recess 521 and one protrusion 715 are arranged around the periphery of the support substrate 10 in a plan view. The number of recesses 521 and protrusions 715 is not limited in any way. In the semiconductor package B12, the sealing resin 50 exhibits an anchoring effect with respect to the top plate 71 (heat dissipation member C10). This makes it possible to prevent the sealing resin 50 from peeling off from the main surface 71 a.

[0193] 48 shows a semiconductor package B13 according to a third modified example. The semiconductor package B13 differs from the semiconductor package B12 in the following respects. First, the top plate 71 (heat dissipation member C10) has a recess 716 recessed from the main surface 71a in the thickness direction z, instead of the protrusion 715. Second, the sealing resin 50 has a protrusion 522 protruding from the resin back surface 52 in the thickness direction z, instead of the recess 521.

[0194] The protrusion 522 is fitted into the recess 716. In the semiconductor package B13, as in the semiconductor package B12, the sealing resin 50 exhibits an anchoring effect with respect to the top plate 71 (heat dissipation member C10), thereby preventing the sealing resin 50 from peeling off from the main surface 71 a.

[0195] 49 shows a semiconductor package B14 according to a fourth modification. The semiconductor package B14 differs from the semiconductor package B10 in the following respect: the number and positions of the plurality of signal terminals 19 are different. In the semiconductor package B14, the arrangement, number, size, shape, etc. of each component of the semiconductor package can be appropriately changed according to the arrangement of the plurality of signal terminals 19.

[0196] 49 , in the semiconductor package B14, the multiple signal terminals 19 are arranged at the end closer to the power terminal 17 in the second direction y, but are not arranged at the end closer to the two power terminals 15, 16. Unlike this example, the multiple signal terminals 19 may not be arranged at the end closer to the power terminal 17 in the second direction y, but may be arranged at the end closer to the two power terminals 15, 16. In the illustrated example, the semiconductor package B14 includes four signal terminals 19. The four signal terminals 19 are, for example, signal terminals 191 to 194, but are not limited to this combination.

[0197] 50 to 52 show a semiconductor package B15 according to a fifth modification. The semiconductor package B15 differs from the semiconductor package B10 in the configuration of the multiple power terminals 15, 16, and 17. The semiconductor package B15 includes one power terminal 15, two power terminals 16, and two power terminals 17. These power terminals 15, 16, and 17 are formed from blocks of metal (e.g., copper).

[0198] The power terminal 15 is joined to the conductor portion 122 inside the sealing resin 50. The power terminal 15 is exposed from the resin main surface 51 of the sealing resin 50. In a plan view, the power terminal 15 is surrounded by the periphery of the sealing resin 50 and is located inward from the periphery of the resin main surface 51. The power terminal 15 has a connection surface 155 exposed from the sealing resin 50. The connection surface 155 faces the same side as the main surface 71a of the top plate 71 of the heat dissipation member C10 in the thickness direction z. The power terminal 15 is exposed from an opening 562 in the sealing resin 50.

[0199] The two power terminals 16 are individually bonded to two conductor portions 123 inside the sealing resin 50. Each of the two power terminals 16 is exposed from the resin main surface 51 of the sealing resin 50. In a plan view, each of the two power terminals 16 is surrounded by the periphery of the sealing resin 50 and is located inward from the periphery of the resin main surface 51. Each of the two power terminals 16 has a connection surface 165 exposed from the sealing resin 50. The connection surface 165 faces the same side as the main surface 71a of the top plate 71 of the heat dissipation member C10 in the thickness direction z. The connection surfaces 165 of the two power terminals 16 are individually exposed from two openings 563 in the sealing resin 50. In the example shown in FIG. 52 , the joint portion 324 of the conductive member 32 is bonded to the corresponding power terminal 16 via a conductive bonding layer 39. The conductive bonding layer 39 is, for example, solder. Unlike this example, the joint portion 324 of the conductive member 32 may be joined to the corresponding conductor portion 123 .

[0200] Each of the two power terminals 17 is joined to the conductor portion 121 inside the sealing resin 50. Each of the two power terminals 17 is exposed from the resin main surface 51 of the sealing resin 50. In a plan view, each of the two power terminals 17 is surrounded by the periphery of the sealing resin 50 and is located inward from the periphery of the resin main surface 51. Each of the two power terminals 17 has a connection surface 175 exposed from the sealing resin 50. The connection surface 175 faces the same side as the main surface 71a of the top plate 71 of the heat dissipation member C10 in the thickness direction z. The connection surfaces 175 of the two power terminals 17 are individually exposed from two openings 561 in the sealing resin 50.

[0201] The semiconductor packages B11 to B15 described above can be applied to any of the semiconductor modules A10, A20, A30, and A40 according to the first to fourth embodiments (including their modifications). Therefore, in the semiconductor module of the present disclosure, the configuration of the semiconductor package is not limited in any way.

[0202] The semiconductor module and the method for manufacturing the semiconductor module according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor module according to the present disclosure and the specific processing of each step of the method for manufacturing the semiconductor module according to the present disclosure can be freely designed in various ways. For example, the present disclosure includes the embodiments described in the following appendices. Appendix 1. A manufacturing method for a semiconductor module (A10) including semiconductor elements (21, 22), the manufacturing method comprising: a first bonding step (S102) of bonding a component to a support substrate (10); a second bonding step (S104) of bonding the support substrate (10) to a heat dissipation member (C10) with a bonding layer (109) at a pressure lower than that in the first bonding step (S102); and a molding step (S109) of forming a sealing resin (50) that covers the semiconductor elements (21, 22), wherein the component and the heat dissipation member (C10) are bonded to opposite sides of the support substrate (10) in the thickness direction (z) of the support substrate (10), the second bonding step (S104) being performed after the first bonding step (S102), and the molding step (S109) being performed after the second bonding step (S104). A method for manufacturing a semiconductor module (A10) according to Appendix 1, wherein the component includes the semiconductor elements (21, 22). Appendix 3. A method for manufacturing a semiconductor module (A10) according to Appendix 2, wherein the support substrate (10) includes an insulating substrate (11) having a substrate main surface (11a) facing the semiconductor elements (21, 22) in the thickness direction (z), and a main surface metal layer (12) formed on the substrate main surface (11a), and wherein the first bonding step bonds the semiconductor elements (21, 22) to the main surface metal layer (12). Appendix 4. A method for manufacturing a semiconductor module (A10) according to Appendix 3, wherein the first bonding step bonds the semiconductor elements (21, 22) to the main surface metal layer (12) by solid-state diffusion bonding. Appendix 4-1. The method for manufacturing a semiconductor module described in Appendix 3, wherein in the first bonding step (S102), bonding of the semiconductor element (21, 22) and the main surface metal layer (12) is performed by sintering metal particles.Supplementary Note 5. The method for manufacturing a semiconductor module (A10) according to Supplementary Note 3, wherein the insulating substrate (11) has a substrate back surface (11b) facing opposite to the substrate main surface (11a) in the thickness direction (z), the support substrate (10) includes a back surface metal layer (13) formed on the substrate back surface (11b), and in the second bonding step (S104), the back surface metal layer (13) is bonded to the heat dissipation member (C10) by the bonding layer (109). Supplementary Note 6. The method for manufacturing a semiconductor module (A10) according to Supplementary Note 5, wherein the bonding layer (109) is solder, and in the second bonding step (S104), the support substrate (10) and the heat dissipation member (C10) are bonded by solder bonding. Supplementary Note 7. A method for manufacturing a semiconductor module (A10) according to any one of Supplementary Note 3 to Supplementary Note 6, wherein in the molding step (S109), the bonding layer (109) together with the semiconductor elements (21, 22) are covered with the sealing resin (50), and the sealing resin (50) is brought into contact with the heat dissipation member (C10). Supplementary Note 8. A method for manufacturing a semiconductor module according to Supplementary Note 7, wherein the sealing resin (50) has a resin back surface (52) in contact with the heat dissipation member (C10) and a resin main surface (51) facing the opposite side to the resin back surface (52) in the thickness direction (z). Supplementary Note 9. The method for manufacturing a semiconductor module (A10) described in Appendix 8 further includes, after the molding step (S109), a power terminal connecting step (S1101) for electrically connecting power terminals (15, 16, 17) to the semiconductor elements (21, 22), wherein a main surface opening (56) for exposing a portion of the main surface metal layer (12) is formed in the resin main surface (51), and in the power terminal connecting step (S1101), the power terminals (15, 16, 17) are connected to the main surface metal layer (12) exposed from the main surface opening (56), thereby electrically connecting the power terminals (15, 16, 17) to the semiconductor elements (21, 22).Supplementary Note 10. The method for manufacturing a semiconductor module according to Supplementary Note 8 or Supplementary Note 9, further comprising a signal terminal connecting step (S1102) of electrically connecting signal terminals (19) to the semiconductor elements (21, 22) after the molding step (109), wherein insertion holes (58) are formed in the resin main surface (51), and in the signal terminal connecting step (S1102), the signal terminals (19) are inserted into the insertion holes (58) to electrically connect the signal terminals (19) to the semiconductor elements (21, 22). Supplementary Note 11. The method for manufacturing a semiconductor module (A10) according to any of Supplementary Note 1 to Supplementary Note 10, further comprising a signal terminal connecting step (S1102) of electrically connecting signal terminals (19) to the semiconductor elements (21, 22) after the molding step (109), wherein insertion holes (58) are formed in the resin main surface (51), and in the signal terminal connecting step (S1102), the signal terminals (19) are inserted into the insertion holes (58) to electrically connect the signal terminals (19) to the semiconductor elements (21, 22). Supplementary Note 11-1. The manufacturing method of the semiconductor module (A10) according to Appendix 11, wherein the hollow portion (701) overlaps the bonding layer (109) when viewed in the thickness direction (z).Supplementary Note 12. The manufacturing method of the semiconductor module (A10) according to Appendix 11, wherein the housing (70) includes a top plate portion (71) to which the support substrate (10) is bonded, and the heat dissipation member (C10) includes a heat dissipation portion (75) extending from the top plate portion (71) in the thickness direction (z) and contained in the hollow portion (701).Supplementary Note 13. A semiconductor device comprising: semiconductor elements (21, 22); a support substrate (10) to which the semiconductor elements (21, 22) are bonded and which supports the semiconductor elements (21, 22); a sealing resin (50) covering the semiconductor elements (21, 22); a heat dissipation member (C10) to which the support substrate (10) is bonded; a bonding layer (109) which bonds the heat dissipation member (C10) and the support substrate (10); and power terminals (15, 16, 17) electrically connected to the semiconductor elements (21, 22), wherein the semiconductor elements (21, 22) and the heat dissipation member (C10) are bonded on opposite sides of the support substrate (10) in the thickness direction (z) of the support substrate (10), The semiconductor module (A10) includes a resin back surface (52) in contact with the heat dissipation member (C10) and a resin main surface (51) facing the opposite side to the resin back surface (52) in the thickness direction (z), a side surface of the bonding layer (109) facing a direction perpendicular to the thickness direction (z) is covered with the sealing resin, and the power terminals (15, 16, 17) are exposed at the resin main surface (51). The semiconductor module (A10) according to Appendix 13, wherein the support substrate (10) includes an insulating substrate (11) having a substrate main surface (11a) facing the semiconductor elements (21, 22) in the thickness direction (z), and a main surface metal layer (12) formed on the substrate main surface (11a), the resin main surface (51) has a main surface opening (56) that exposes a portion of the main surface metal layer (12), and the power terminals (15, 16, 17) are inserted through the main surface opening (56). Appendix 13-2. The semiconductor module (A10) according to Appendix 13-1, wherein the main surface opening (56) is surrounded by the resin main surface (51) when viewed in the thickness direction (z). Appendix 14. A semiconductor module (A10) described in Appendix 13, wherein the periphery of the sealing resin (50) as viewed in the thickness direction (z) is enclosed within the periphery of the heat dissipation member (C10) as viewed in the thickness direction (z).Supplementary Note 15. The semiconductor module (A10) according to Supplementary Note 13 or Supplementary Note 14, wherein the heat dissipation member (C10) has a housing (70) having a hollow portion (701), and an inlet portion (72) and an outlet portion (73) that are connected to the hollow portion (701) and serve as an inlet and outlet for a fluid into the hollow portion (701). Supplementary Note 15-1. The semiconductor module (A10) according to Supplementary Note 15, wherein the hollow portion (701) overlaps the bonding layer (109) when viewed in the thickness direction (z). Supplementary Note 16. The semiconductor module (10) according to Supplementary Note 15, wherein the housing (70) includes a top plate portion (71) to which the support substrate (10) is bonded, and the heat dissipation member (C10) includes a heat dissipation portion (75) that extends from the top plate portion (71) in the thickness direction (z) and is contained in the hollow portion (701). Appendix 17. The semiconductor module (A10) according to any one of Appendixes 13 to 16, further comprising signal terminals (19) electrically connected to the semiconductor elements (21, 22), the signal terminals (19) protruding from the resin main surface (51). Appendix 17-1. The semiconductor module (A10) according to any one of Appendixes 13 to 17, Appendix 13-1, Appendix 13-2, and Appendix 15-1, wherein the semiconductor elements (21, 22) include a semiconductor substrate. Appendix 17-2. The semiconductor module (A10) according to Appendix 17-1, wherein the semiconductor substrate includes silicon, a wide bandgap semiconductor having a wider bandgap than silicon (e.g., silicon carbide or gallium nitride), or an ultra-wide bandgap semiconductor having a wider bandgap than a wide bandgap semiconductor (e.g., gallium oxide, diamond, aluminum nitride). Appendix 17-3. A power conversion unit (U10, U11) further comprising: a semiconductor module (A10) according to any one of Supplementary Notes 13 to 17, Supplementary Notes 13-1, 13-2, Supplementary Notes 15-1, Supplementary Notes 17-1, and Supplementary Notes 17-2; and a control board (E1) for driving the semiconductor elements (21, 22).Supplementary Note 17-4. A vehicle (F1) comprising: a semiconductor module (A10) according to any one of Supplementary Note 13 to Supplementary Note 17, Supplementary Note 13-1, Supplementary Note 13-2, Supplementary Note 15-1, Supplementary Note 17-1, and Supplementary Note 17-2; and a drive source (F132), wherein the semiconductor module is electrically connected to the drive source (F132).

[0203] A10, A11, A12, A20, A30, A31, A40: Semiconductor module B10 to B15: Semiconductor package 10: Support substrate 109: Bonding layer 11: Insulating substrate 11a: Substrate main surface 11b: Substrate back surface 12: Main surface metal layer 121: Conductor portion 121a: Conductor main surface 121b: Exposed area 122: Conductor portion 122a: Conductor main surface 122b: Exposed area 1221, 1222: Partition portion 123: Conductor portion 123a: Conductor main surface 123b: Exposed area 13: Back surface metal layer 15: Power terminal 151: Bonding portion 152: Suspension portion 153: Extension portion 155: Connection surface 16: Power terminal 161: Bonding portion 162: Suspension portion 165: Connection surface 17: Power terminal 171: Bonding portion 172: Suspension portion 175: Connection surface 19: Signal terminal 191 to 194, 196, 197: Signal terminal 190: Tip portion 190A: Bulging portion 21: Semiconductor element 21a: Element main surface 21b: Element back surface 211: Back electrode 212, 213, 214: Principal surface electrode 219: Conductive bonding layer 22: Semiconductor element 22a: Element main surface 22b: Element back surface 221: Back electrode 222, 223, 224: Principal surface electrode 229: Conductive bonding layer 23: Thermistor 31: Conductive member 311: Main body portion 311a: Through hole 312: Bonding portion 313: Bonding portion 32: Conductive member 321: Main body portion 322: Bonding portion 323: Intermediate portion 323a: Through hole 324: Joint portion 33 to 35, 39: Conductive joining layer 41 to 45: Connection member 50: Sealing resin 51: Resin main surface 52: Resin back surface 521: Recess 522: Protrusion 531 to 534: Resin side surface 56: Main surface opening 561, 562, 563: Opening 571, 572: Recess 573,574: Convex portion 58: Insertion hole 601: Signal board 602: Signal board 61: Insulating layer 62: Wiring layer 621 to 624: Wiring portion 63: Metal layer 64: Sleeve 70: Housing 701: Hollow portion 71: Top plate 71a: Main surface 71b: Back surface 711: Main portion 712: Outer periphery 712a: Through hole 715: Protrusion 716: Recess 72: Inflow portion 73: Outflow portion 74: Case portion 75: Heat dissipation portion 751: Heat dissipation fin 76: Base portion 76a: Main surface 76b: Back surface 801: Resin inflow cavity 802: Avoidance cavity 81: Upper mold 811: Recess 812: Protrusion 82: Lower mold 821: Recess 91: Base material 911: Through hole 92: Main wiring 93: Back wiring 94: Internal wiring 96: Connecting wiring 97: Positioning pin C10: Heat dissipation member E1: Control board E11, E12: Circuit board F1: Vehicle F11: On-board charger F12: Storage battery F13: Drive system F131: Inverter F132: Drive source H1: Workbench M10: Mold S101: Board preparation process S102: Element bonding process S103: Signal board bonding process S104: Support board bonding process S105: Conductive member bonding process S106: Sleeve bonding process S107: Thermistor bonding process S108: Wire bonding process S109: Molding process S110: Terminal connection process S1101: Power terminal connection process S1102: Signal terminal connection process U10, U11: Power conversion unit,

Claims

1. A method for manufacturing a semiconductor module including a semiconductor element, comprising: a first bonding process for bonding a component to a support substrate; a second bonding process for bonding the support substrate to a heat dissipation member using a bonding layer at a pressure lower than that of the first bonding process; and a molding process for forming a sealing resin that covers the semiconductor element, wherein the component and the heat dissipation member are bonded on opposite sides of the support substrate in the thickness direction of the support substrate, the second bonding process being performed after the first bonding process, and the molding process being performed after the second bonding process.

2. The method for manufacturing a semiconductor module according to claim 1, wherein the component includes the semiconductor element.

3. The method for manufacturing a semiconductor module according to claim 2, wherein the support substrate includes an insulating substrate having a substrate main surface facing the semiconductor element in the thickness direction, and a main surface metal layer formed on the substrate main surface, and the first bonding step bonds the semiconductor element to the main surface metal layer.

4. The method for manufacturing a semiconductor module according to claim 3, wherein in the first bonding step, the semiconductor element and the main surface metal layer are bonded by solid-state diffusion bonding.

5. The method for manufacturing a semiconductor module described in claim 3, wherein the insulating substrate has a substrate back surface facing opposite the substrate main surface in the thickness direction, the support substrate includes a back surface metal layer formed on the substrate back surface, and in the second bonding step, the back surface metal layer is bonded to the heat dissipation member by the bonding layer.

6. The method for manufacturing a semiconductor module according to claim 5, wherein the bonding layer is solder, and in the second bonding step, the support substrate and the heat dissipation member are bonded by solder bonding.

7. A method for manufacturing a semiconductor module according to any one of claims 3 to 6, wherein in the molding step, the bonding layer as well as the semiconductor element are covered with the sealing resin, and the sealing resin is brought into contact with the heat dissipation member.

8. The method for manufacturing a semiconductor module according to claim 7, wherein the sealing resin has a resin back surface that contacts the heat dissipation member and a resin main surface that faces the opposite side to the resin back surface in the thickness direction.

9. A method for manufacturing a semiconductor module as described in claim 8, further comprising, after the molding step, a power terminal connecting step of electrically connecting a power terminal to the semiconductor element, wherein a main surface opening is formed in the resin main surface to expose a portion of the main surface metal layer, and in the power terminal connecting step, the power terminal is connected to the main surface metal layer exposed from the main surface opening, thereby electrically connecting the power terminal to the semiconductor element.

10. A method for manufacturing a semiconductor module as described in claim 8 or claim 9, further comprising a signal terminal connecting step of electrically connecting a signal terminal to the semiconductor element after the molding step, wherein insertion holes are formed in the main surface of the resin, and in the signal terminal connecting step, the signal terminal is inserted into the insertion hole to electrically connect the signal terminal to the semiconductor element.

11. A method for manufacturing a semiconductor module as described in any one of claims 1 to 10, wherein the heat dissipation member has a housing having a hollow portion, and an inlet portion and an outlet portion that are connected to the hollow portion and serve as an inlet and outlet for a fluid into the hollow portion.

12. A method for manufacturing a semiconductor module as described in claim 11, wherein the housing includes a top plate portion to which the support substrate is joined, and the heat dissipation member includes a heat dissipation portion extending from the top plate portion in the thickness direction and contained within the hollow portion.

13. A semiconductor module comprising: a semiconductor element; a support substrate to which the semiconductor element is bonded and which supports the semiconductor element; a sealing resin covering the semiconductor element; a heat dissipation member to which the support substrate is bonded; a bonding layer bonding the heat dissipation member and the support substrate; and a power terminal electrically connected to the semiconductor element, wherein the semiconductor element and the heat dissipation member are bonded on opposite sides of the support substrate in the thickness direction of the support substrate, the sealing resin has a resin back surface in contact with the heat dissipation member and a resin main surface facing opposite the resin back surface in the thickness direction, a side surface of the bonding layer facing in a direction perpendicular to the thickness direction is covered with the sealing resin, and the power terminal is exposed at the resin main surface.

14. The semiconductor module according to claim 13, wherein the periphery of the sealing resin as viewed in the thickness direction is enclosed within the periphery of the heat dissipation member as viewed in the thickness direction.

15. A semiconductor module according to claim 13 or claim 14, wherein the heat dissipation member has a housing having a hollow portion, and an inlet portion and an outlet portion that are connected to the hollow portion and serve as an inlet and outlet for a fluid to enter and exit the hollow portion.

16. The semiconductor module according to claim 15, wherein the housing includes a top plate portion to which the support substrate is joined, and the heat dissipation member includes a heat dissipation portion extending from the top plate portion in the thickness direction and contained within the hollow portion.

17. A semiconductor module according to any one of claims 13 to 16, further comprising signal terminals electrically connected to said semiconductor element, said signal terminals protruding from said main surface of said resin.

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