High power diamond transistors with electrical and optical gate control

Abstract

A semiconductor and method for making and operating the same includes diamond layers including a p type layer, a drain electrode coupled to the p type layer and a drift layer adjacent to the p type layer. An n type layer has a first surface disposed adjacent to the drift layer. The n type diamond layer has a trench and a second surface opposite the drift layer and an edge surface forming the trench. A gate electrode is coupled to the n type diamond layer. A conducting channel includes a first portion disposed on the second surface of the n type layer and a second portion disposed on the edge surface, the conducting channel electrically coupled to the drift layer. A source electrode is coupled to the conducting channel. A dielectric layer is disposed on the first portion of the conducting channel and the second portion of the conducting channel.

Description

HIGH POWER DIAMOND TRANSISTORS WITH ELECTRICAL AND OPTICAL GATE CONTROLCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 562,289, filed on March 7, 2024. The entire disclosure of the above application is incorporated herein by reference.TECHNICAL FIELD

[0002] The present disclosure relates generally to high power semiconductors and, more specifically, to high power semiconductor that is both optically and electrically controlled.BACKGROUND

[0003] This section provides background information related to the present disclosure which is not necessarily prior art.

[0004] There is a pressing need to upgrade and modernize the Nation’s power grid to improve efficiency and resiliency and reduce network congestion. Grid modernization requires the research and development of power electronics (PE) components, systems and grid integration, and the benefits of such a system are enormous. A 2018 ARPA-E GENI pilot study concludes that commercialization of PE systems in the grid can pay for themselves through efficiency gains and cost savings in three years. Further the wide scale commercial adoption requires scaling to higher voltages and higher powers than are currently feasible.

[0005] Ultrawide band gap (UWBG) semiconductors can be a key part of revolutionizing power converter technologies, i.e., the inverters and rectifiers that form the heart of power distribution systems. Diamond is the ultimate UWBG semiconductors, and it has a fundamental advantage over silicon and other semiconductors because it can switch enormous amounts of power in a given fast pulse. This advantage brings about new challenges however because fast, high power switching can make the device more susceptible to electromagnetic interference (EMI). As power electronics increase in power and switching speed, EMI has become a greater challenge and the EMI generated by the rapid switching can have parasitic effects on the power system componentry.SUMMARY

[0006] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0007] In accordance with the present invention, an electronic apparatus includes a diamond substrate, a nitrogen-doped layer, a dielectric layer and gates. In another aspect, an electronic power switching apparatus includes conductive gate electrodes, a nitrogen-doped diamond layer located on a boron-doped diamond layer, and a light source configured to lock the apparatus into a power on or off mode. A further aspect of an electronic power switching apparatus includes a nitrogen-doped diamond layer and a light source configured to modulate a power conducting channel. Yet another aspect provides an electronic power switching apparatus which includes a diamond substrate having a nitrogen-doped layer located on a boron-doped layer, and photons changing the charge and associated voltage in the nitrogen-doped layer that modulates the electrons (or holes) in a channel or area of the diamond substrate between conductive and insulating states.

[0008] An aspect of an electronic power switching apparatus includes a diamond substrate having a nitrogen-doped layer located on a boron-doped layer, and photons cause a change in the electron charge in the nitrogen-doped layer to change the number of holes in a channel or area of the diamond substrate, between adjacent gate and dielectric layers on one side, and the nitrogen- doped layer on the other side. A method of switching an electronic component uses light (with or without an optional supply voltage) to modulate a power conducting gate or channel in a diamond substrate between a nitrogen-doped diamond layer and a dielectric layer. In another aspect, a power switching apparatus and method have a >10 kHz switching speed and are unaffected by EMI.

[0009] The present diamond-based electronic apparatus may be a transistor or diode. Moreover, the present diamond-based electronic apparatus is ideally suited for handling high voltage (>3 kV) power grid switching, which is achieved much faster, more efficiently and in a smaller size, than would be obtained with conventional devices. The present apparatus is also beneficially unaffected by EMI.

[0010] In one aspect of the disclosure, a semiconductor includes diamond layers including a p type layer, a drain electrode coupled to the p type layer and a drift layer adjacent to the p type layer. An n type layer comprising a first surface disposed adjacent to the drift layer. The n type diamond layer comprising a trench and a second surface opposite the drift layer and an edge surface forming the trench. A gate electrode is coupled to the n type diamond layer. A conducting channel includes a first portion disposed on the second surface of the n type layer and a secondportion disposed on the edge surface, the conducting channel electrically coupled to the drift layer. A source electrode is coupled to the conducting channel. A dielectric layer is disposed on the first portion of the conducting channel and the second portion of the conducting channel.

[0011] In another aspect of the disclosure, A method of forming a semiconductor includes epitaxially forming a drift layer on a p+ boron doped layer, etching a first trench into the drift layer, epitaxially forming an n-doped layer in the first trench, forming a conducting channel partially around the n-doped layer, coupling a drain electrode on the p+ boron doped layer, coupling a first gate to the coupling to the n-doped layer, coupling a source electrode to the conducting channel, and coupling a second gate electrode to a dielectric layer at the conducting channel.

[0012] In yet another aspect of the disclosure, a method of controlling a semiconductor includes applying a voltage across a nitrogen doped diamond layer from a gate electrode separated from the nitrogen-doped diamond layer by a conducting channel, applying an optical signal to the nitrogen-doped diamond layer, changing a conductivity state of the nitrogen-doped diamond layer and, when the optical signal is removed, causing the conductivity state to remain locked until the optical signal is re-applied and the voltage is changed on the first gate.

[0013] Further advantages and benefits of the present apparatus will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0015] Fig. 1 is a cross sectional view of a semiconductor formed according to the present disclosure.

[0016] Fig. 2 is a plot doping level and energies of diamond.

[0017] Fig 3A is a plot of resistance voltage versus breakdown voltage at room temperature.

[0018] Fig. 3B is a plot of resistance voltage versus breakdown voltage at a temperature of 450K .

[0019] Fig. 4 is a diagram showing part of the process for forming the semiconductor of Fig-1-

[0020] Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.DETAILED DESCRIPTION

[0021] Referring now to Figure 1, a semiconductor device 10 such as an electronic FET apparatus is illustrated having a drain 12. The drain 12 is formed from a metallic conductor. The method for forming the semiconductor 10 is provided in greater detail below. An epitaxially grown p+heavily doped diamond layer 14 (p type diamond layer) is coupled to the drain 12. In one example, the p+layer is heavily doped with boron. A p" lightly doped diamond referred to as drift layer 16 is epitaxially grown on the p+layer 14. The doping on the drift layer 16 is less than the doping on the layer 14. An n-type doped layer 18 is epitaxially grown on the p" layer 16. The doping may be composed of nitrogen. As will be described below, the drift layer 16 may ultimately be etched so that areas or conducting channel 20 of the p" layer is adjacent a bottom surface 18 A. The layer 18 also has a top surface 18B and an edge 18C that extends between the bottom surface 18A and the top side 18B. The conducting channel 20 may be referred to as a conducting layer as it selectively conducts holes toward the drift layer, the layer 14 and the drainl2. The channel 20 may be formed of p doped material such as boron or may be a hydrogen terminated layer to form a conducting channel on the upper surface thereof. The conducting channel 20 may be formed partially around the layer 18. In this example, a first portion 20A of the conducting channel 20 is adjacent to the top surface 18A of the doped diamond layer 18. A second portion 20B of the conducting channel 20 extends adjacent to the edge surface 18C and between the first portion 20A and the drift layer 16. A dielectric layer 30 is deposited on the first portion 20A, the second portion 20B and an upper surface 16A of the drift layer 16. A gate or metallic gate electrode 32 extends in a general U-shape into a trench 22 on the dielectric layer 30. The dielectric layer 30 separates gate 32 from the channel 20B.

[0022] The trench 22 is located between the portions of the layer 18. That is, the conducting channel 20 is positioned adjacent to the edges 18C of the doped layer 18. The facing inside edges 18C of the layer 18 with the conducting channels 20 therebetween have the generally U-shaped dielectric insulator layer 30 thereon. The dielectric layer 30 is an insulator layer such as aluminum oxide or the like, extending along the gap between source pads 36 disposed on the first portion 20A of the conducting channels 20. The dielectric layer is also disposed on a portion of the exposed drift layer at the trench 22. The gate electrode 32 is a generally U-shaped and electrically conductive, primary metallic gate layer located upon the dielectric insulator layer 30 also between source electrodes 36. A secondary or “optical-control” gate 40 is electrically coupledto accessible portions of the layer 18. Source electrodes 36 are coupled to the p- drift layer at laterally opposite ends of the dielectric layer 30. A photonic light source 42, such as a laser or LED, selectively emits light photons (an optical signal) into the n-type (nitrogen) doped layer 18 to change the conductivity of the layer 18. While the light is shown shining on the top of the device 10, the light from the photonic source 42 may be positioned to shine from the sides or from below as long as it couples into layer 18 and travels therethrough. Therefore, the switching mode of the p" conducting channels 20 on either side of the trench 22 may be optically controlled. When in a conductive mode or state, the channels 20 allow transmission of the electrical current from the source 36 to the drain 12. In one configuration, the photonic light emission to the n type diamond layer 18 and simultaneous voltage supply through the gate 40, causes the nitrogen-doped diamond layer 18 to change the conductivity state or condition of the conducting channel 20, and causes the state of the conducting channel 20 to remain locked in that state or condition when the light is removed, until the light is re-emitted so that the conductivity remains locked independent of the voltage to the gate electrode. When light is reapplied to layer 18 and voltage to gate 40 is changed, a change of the conductivity state or condition of the channel 20 (such as, from power on to off and then from power off to on) occurs, where on means current flowing from the source electrode 36 to the drain electrode 12 and off means current is prevented from source electrode 36 to the drain electrode 12. In another configuration, this mode switching and locking are performed with only the photonic light emissions. The structure of the semiconductor in this example is disposed around the trench 22 whereby there in one gate 40 and one source gate 36 are used even though two appear in Fig. 1.

[0023] The present disclosure capitalizes on the superb high power switching capabilities of Ultra-Wide Band Gap (UWBG) diamond power electronics, and incorporates sophisticated, light activated switching control to further revolutionize the technology for real electrical grid applications. A solution to the EMI interference problem by switching the electronics not by using electrical means but by using a light source, which is resilient to EMI.

[0024] Referring now to Fig. 2, a feature of diamond is that, while conductive p-type diamond is relatively easy to achieve with controlled boron doping levels from 1015cm'3to >1O20cm'3, n-type diamond is more difficult and suffers from low conductivity. In diamond, the dopant activation energies are 0.36eV for boron, 0.6eV for phosphorus and 1.7 eV for nitrogen 2. In the case of nitrogen doping the donor level is so deep that the charge state of the donor atoms is “frozen” at normal operating temperatures. However, the number of nitrogen donors ionized can be changed by optical excitation with light of photon energy greater than 1.7 eV. Nitrogen doped diamond with sub-bandgap excitation has shown photo-active behavior in photoconductiveswitching tests. This has been used as an advantage to make a non-volatile switch where the switches ON / OFF states can be set with optical excitation of the nitrogen donors.

[0025] Based on this phenomenon of a non-volatile charge state of nitrogen doped diamond, the proposed diamond semiconductor 10, a transistor in this example, has a dual gate structure. Gate 32 is a metal electrode, and the other gate is the charge state of the non-volatile nitrogen-doped (N-doped) layer 18 that is optically controlled. The charge state of the N-doped diamond layer 18 is set to either have a positive charge when a positive voltage is applied to the “Optical-Control” terminal or gate 40 and light is used to excite electrons from the nitrogen donors, or alternatively if the light is on and a negative voltage is applied to the “Optical Control” terminal or gate 40, the charge state is neutral via electrons filling the positive donor states. The design in Fig. 1 can be such that the channel is conducting only if both the non-volatile region 18 and the metal gate 32 are set so that the transistor is on.

[0026] The conducting channel 20 in this case could be either a conduction layer of p-type diamond FET or a Hydrogen transfer-doped FET. The optical switching rate alone is estimated below to achieve the 1-100 kHz switching rate. However, by first setting the optical state gate 40 followed by the metal gate 32, the electrical signal to the metal gate 32 of the transistor allows fast switching.

[0027] A first fundamental question is how fast the optical state of the non-volatile FI- doped layer 18 can be switched. The optical excitation of electrons from the N-donors needs photon energies greater than 1.7 eV. It should also be noted that the thermal excitation of electrons is very low at anticipated operating temperatures because of the 1.7 eV donor activation energy, which gives the non-volatile nature of the N-doped diamond regions. To estimate the switching time of the non-volatile layer 18, how many electrons are created per unit time by a given light intensity and how long the electrons exist may be considered. Stated differently, can the electrons flow through the nitrogen doped layer 18 to the optical-control contact 40 during their lifetime in the conduction band. For nitrogen doping in the few- 10 ppm range the absorption coefficient of green light is ~10 cm'1and the lifetime of electrons in the conduction band is 0.1-1 nsec. If the optical control signals are 10’ s volts and the distance across the non-volatile layer 18 is at most a few micrometers, then the electric field is ~ 105V / cm and the time for electrons to cross the region is less than 0.1 nsec. Hence, most electrons excited to the conduction band can be moved in and out of the non-volatile region during their lifetime.

[0028] The next estimate is how much light is needed to activate a sufficient number of electrons. By assuming an optical absorption coefficient of 10 cm'1and a thickness of the N-doped layer of 1 pm, about 0.1% of the light is absorbed. An estimate of the switching speed possiblefor different light levels is shown in Table 1. This estimate is based on considering the charge (number of electrons) that needs to be created to change the voltage (charge) of the non-volatile region according to Q=CV where C is the capacitance of switching the charge state of the nitrogen doped region. By assuming a depletion layer thickness of the N-doped region and the p- drift layer junction of d=500 nm where the capacitance is C=s*A / d with a being the permittivity of diamond, the estimate is C / A~lxlO'8F / cm2. Assuming an optical control voltage of V=50 V, then Q=CV= C*50V=5xl(F7C / cm2which is 3xl012electrons / cm2. For a N-doped region at a level of a few ppm (N=1017-1018cm'3) the number of dopant sites in a 1 pm thick layer is ~ few xlO13dopants / cm2so achieving 3x1012electrons / cm2requires ~ 10% of the dopants be optically activated.

[0029] Now, assuming that one free electron is created for each photon absorbed, the photons that are absorbed needs to be 3xl012photons / cm2. The power level of light to do this versus time is shown below for the cases of the light spread over 1 cm2and 1 mm2. The efficiency =0.001 assumes an optical absorption coefficient of a=10 cm'1and the N-doped regions are 1 pm thick. As seen in Table 1 for a 1 mm2device the light lower level for switching at 10- 100 kHz is 20-200 mW.

[0030] Table 1: Switching time (frequency) versus light power.

[0031] The relationship of current flow (on resistance) and breakdown voltage is explored. The forward current flow in Fig. 1 as described above can be done with either a conducting channel that is a p-type doped channel where the voltage at the gate 32 controls the depletion of the conducting channel 20, or the conducting channel 20 that is a two-dimensional hole gas (2DHG) formed by hydrogen surface doping for transfer doping. The transfer doping approach gives the highest flows in the channel region. The primary origin of the on-resistance for high voltage transistors (that need a thick p- drift layer with low doping) will be the drift layer in either of the p-channel or 2DHG channel cases.

[0032] Vertical FETs based on the transfer-doped 2DHG have been demonstrated. A fabricated vertical hole-conducting FETs with a 2DHG layer has been used. In one design a channel region was used that is a 2DHG layer and then the higher voltage is achieved with a p- drift layer. A forward current of 700 A / cm2and a breakdown voltage of 580 V was achieved. The basic challenges are to have a 2DHG with a high carrier concentration and good mobility by designing the N-doped layer so that the voltage variation of gate 32 allows channel pinch-off and high forward currents, and undoped layer and drift layer doping and doping profile to control the electric field to achieve a high breakdown voltage.

[0033] As noted above the current control is possible using a 2DHG or p-channel gate control structure, however for higher breakdown voltage devices the dominant resistance for high voltage devices is the p- drift layer. In particular the higher voltages are possible because of a lowly doped thick p- drift layer. For voltages of 3.3kV-10kV the boron acceptor dopant concentration may be 1015-1016cm'3and the theoretical on-resistance is 50-200 mQ-cm2for the temperature range 300-450K as shown in Figs. 3A and 3B. Estimates of the normalized power loss versus temperature at an operating temperature of 150-175°C are that the power loss in the diamond drift layer is 60-80% lower than other unipolar semiconductor devices like SiC and GaN.

[0034] Another challenge with diamond unipolar devices is that the number of holes in the drift layer at starting temperatures of room temperature or below is small. Specifically, at room temperature the number of holes may only be 1% of the boron acceptor concentration. When the transistor turns-on, the two current flow mechanisms are normal ohmic conduction across the drift layer and space charge limited current (SCLC) across the drift layer. If the number of free carriers for ohmic conduction is too low, then the SCLC will dominate as the forward voltage between the source and drain increases. As an example, consider a 10 kV drift layer with a thickness of 20 pm designed so that the maximum electric field is 5 x 106V / cm. A space charge limited current density of 100 A / cm2flows with a voltage of ~40V assuming a mobility of 1000 cm2 / V-sec. This will lead to a short period of high power dissipation (voltage times current) of 4 kW / cm2that will heat the diamond die and increase the hole concentration from the boron acceptors ionizing as the temperature goes up. Once the acceptors are ionized and hole concentration increases the operating forward voltage will drop back to 1- few volts for the current density of 100 A / cm2. With diamond SCLC is a viable way to start conduction at low temperatures because the mobility of the carriers (1000-2000 V / cm2-sec) is high in diamond drift layers.

[0035] Further, non-volatile switching behavior is used to make the diamond transistor switches more resilient to EMI interference. Specifically, the charge state of a nitrogen doped diamond region acts as the second gate to a transistor and to change the charge state both light anda voltage (higher in magnitude than typical threshold voltage values) are required, which improves EMI tolerance.

[0036] The design of diamond diodes and transistors for switching in the 10-100 kHz range with power ranges >100 kW with a focus on the 3.3-10 kV range for individual diodes and transistors is set forth. The diodes and transistors address the need for switching devices and / or modules which will be used to realize building blocks of the control infrastructure for the future grid. Diamond due to its high electric field breakdown and high mobility allows for lower on- resistance for DC current flow and lower capacitance in switching, both of which results in an improvement of efficiency over the state of the art. The basic EMI concept is that if the device is in an OFF state by optical control, the input of voltage spikes (noise) on the electrical gate does not turn the device on.

[0037] A disruptive innovation relative to standard all electrically-controlled transistors is the use of the deep donor level of nitrogen in diamond to allow a non-volatile charge region to be created in diamond. This non-volatile charge state can be used to control a conducting channel of a FET transistors such that the transistor can be both electrically controlled with rapid current, or voltage slew rates while also allow the transistor to be much more EMI tolerant once in the OFF optical set state. The combination of a fast, high power FET that can have an EMI-tolerant ON / OFF state is a new innovation that can lead to other device architectures with such capability.

[0038] The transistor can be designed so that the optically controlled gate either locks the transistor in to an OFF state regardless of the electrical signal applied to the gate, or the optical control is set so that the electrically controlled gate controls the transistor drain current flow. The structure provides for more EMI tolerance via the lock-OFF mode. Also, the on mode with electrical control provides the high switching slew rates.

[0039] Alternatively, the semiconductor of the present example can be design and operated so the electrical signal is fixed, and the device is under optical control for even more EMI tolerance (or stacking of transistors in series for high voltage under optical control).

[0040] The optical activation in this structure is to change the charge state (essentially the voltage) of a “gate region” that controls the flow of the current from the source to the drain. This requires less light power than alternative approaches where the light absorbed creates the carriers that flow from the source to the drain. Due to the lower light levels needed, sub-bandgap excitation of carriers from dopants levels is a viable alternative for controlling the charge state of the optical gate.

[0041] Referring now to Fig. 4, the specific epitaxial stack growth and device fabrication process to construct the trench structure with embedded n-type regions is set forth. The simplifiedprocess flow is illustrated, which shows the basic process steps but omits the steps involving photoresist deposition and patterning, for space considerations. The final dielectric deposition and metal deposition steps will be done to realize the structure in Fig. 1.

[0042] The process begins with doping a diamond layer to form a p+ diamond layer 14. The drift layer 16 is formed epitaxially. The drift layer 16 is diamond and is a p- doped drift layer. A hard mask 410 is applied to the drift layer 14. A trench 412 is etched in the drift layer 16. The n-type diamond layer 18 is epitaxially grown in the trench for 18. Excess diamond layer 18’ is also epitaxially grown on the mask 410. The mask 410 and excess diamond layer 18’ is etched to form a planar raised surface 414. A p- layer 416 is grown epitaxially on the surface 414, A hard mark 418 is applied to the p- layer 416. The hard mask 418 is etched to form an opening 420. The opening is less than the width of the P- layer that is between the ends of n-doped diamond layer. Thereafter, a portion of the p-layer is etched to form the trench 22 which is bounded be the conducting channel 20. Portion 20B bounds the trench while 20A is adjacent to the n-doped layer 18.

[0043] The mask 418 is removed. Thereafter, the dielectric layer 30 is applied to the conducting channel 20. The gate 32 is applied thereover. The source electrode 36 is applied to the conducting channel 20. The “optical-control” gate 40 is applied to the n-doped layer 18. As well, the metal drain 12 may be applied to the p+ layer 14.

[0044] An alternative approach would be to utilize a surface conductive, H-terminated layer as the 2DHG instead of bulk conduction through the p conducting channel under the gatedrift layer.

[0045] Example embodiments are provided so that this disclosure will be thorough and will fully convey the scope to those who are skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In some example embodiments, well-known processes, well-known device structures, and well- known technologies are not described in detail.

[0046] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a,” "an," and "the" may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and / orcomponents, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.

[0047] When an element or layer is referred to as being "on," “engaged to,” "connected to," or "coupled to" another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," “directly engaged to,” "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

[0049] Spatially relative terms, such as “inner,” “outer,” "beneath," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Claims

CLAIMSWhat is claimed is:

1. A semiconductor device comprising: a p type diamond layer; a drain electrode coupled to a first side of the p type diamond layer; a drift layer adjacent to the p type diamond layer; an n type diamond layer comprising a first surface disposed adjacent to the drift layer, said n type diamond layer further comprising a trench, said n type diamond layer further comprising a second surface opposite the drift layer and an edge surface forming the trench; a first gate coupled to the n type diamond layer; a conducting channel comprising a first portion disposed on the second surface of the n type diamond layer and a second portion disposed on the edge surface, the conducting channel electrically coupled to the drift layer; a source electrode coupled to the conducting channel; a dielectric layer disposed on the first portion of the conducting channel and the second portion of the conducting channel; and a second gate disposed on the dielectric opposite the conducting channel.

2. The semiconductor device of claim 1 wherein the conducting channel comprises a boron doped layer.

3. The semiconductor device of claim 1 wherein the conducting channel is doped with boron with concentrations between 1015cm'3and IO20cm'3.

4. The semiconductor device of claim 1 wherein the conducting channel is doped with boron with concentrations between 1015- 1016cm'3.

5. The semiconductor device of claim 1 wherein the conducting channel comprises a hydrogen terminated layer.

6. The semiconductor device of claim 1 wherein the p type diamond layer comprises a p+ type layer.

7. The semiconductor device of claim 1 wherein the drift layer comprises a p- layer.

8. The semiconductor device of claim 1 wherein the dielectric layer disposed on a surface of the drift layer.

9. The semiconductor device of claim 1 wherein the second gate is disposed between the source electrode and the trench.

10. The semiconductor of claim 9 wherein the second gate on the dielectric layer and the first gate connected to the n type layer controls the conducting of the conducting channel.

11. The semiconductor of claim 10 further comprising a photonic source coupling light into the n type diamond layer.

12. The semiconductor of claim 11 wherein the photonic source comprises a laser or LED.

13. A method of forming a semiconductor device comprising: epitaxially forming a drift layer on a p+ boron doped layer; etching a first trench into the drift layer; epitaxially forming an n-doped layer in the first trench; forming a conducting channel partially around the n-doped layer; coupling a drain electrode on the p+ boron doped layer; coupling a first gate electrode to the n-doped layer; coupling a source electrode to the conducting channel; and coupling a second gate electrode to a dielectric layer at the conducting channel.

14. The method of claim 13 wherein forming the conducting channel comprises forming the conducting channel on a top surface and an edge surface of the n-doped layer.

15. The method of claim 14 wherein forming the conducting channel comprises forming a trench.

16. The method of claim 13 wherein after forming the trench applying the dielectric layer within the trench and on a top surface of the conducting channel.

17. A method of controlling a semiconductor device comprising: providing a first gate electrode coupled to a nitrogen-doped diamond layer; applying a voltage across the nitrogen doped diamond layer from a second gate electrode separated from the nitrogen-doped diamond layer by a conducting channel; applying an optical signal to the nitrogen-doped diamond layer; changing a conductivity state of the nitrogen-doped diamond layer by applying a voltage to the first gate coupled to the nitrogen-doped layer; and when the optical signal is removed, causing the conductivity state to remain locked until the optical signal is re-applied, and a different voltage is applied to the first gate electrode coupled to the nitrogen-doped layer.

18. The method of claim 17 wherein after causing the conductivity to remain locked switching the conductivity state when the optical signal is applied to the nitrogen-doped diamond layer while apply a voltage to the first gate coupled to the nitrogen-doped layer.

19. The method of claim 18 wherein switching the conductivity state comprises switching from power on to power off, or from power off to power on.

20. The method of claim 19 wherein causing the conductivity state to remain locked comprises causing the conductivity state to remain locked independent of a voltage change to the second gate electrode.

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