Display substrate and display apparatus

Abstract

A display substrate and a display apparatus, the display substrate comprising a display area (AA) and a border area (BB) located on at least one side of the display area (AA). The border area (BB) is provided with a first power line (VSS) and at least one gate driving circuit (10). Different types of gate driving circuits (10) are sequentially arranged in a direction from the display area (AA) to the border area (BB), and a plurality of gate driving circuits (10) of the same type are arranged in a direction of extension of the border area (BB). The first power line (VSS) comprises a plurality of branch structures, and the plurality of branch structures are arranged in the direction from the display area (AA) to the border area (BB) and extend in the direction of extension of the border area (BB). In a direction perpendicular to the plane on which the display substrate is located, the plurality of branch structures are located on the side of the gate driving circuits (10) away from the substrate, and the orthographic projections of at least part of the branch structures on the substrate at least partially overlap the orthographic projections of at least some types of the gate driving circuits (10) on the substrate.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The subject matter of the present text is outlined in this summary. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the display substrate provided by the embodiments of the present disclosure includes a display area and a frame area on at least one side of the display area, the frame area is provided with a first power supply line and at least one gate drive circuit, different types of gate drive circuits are arranged in sequence along a direction from the display area to the frame area, and multiple gate drive circuits of the same type are arranged along an extension direction of the frame area; the first power supply line includes multiple branch structures, which are arranged in sequence along the direction from the display area to the frame area and extend along the extension direction of the frame area.

[0006] In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a substrate, the multiple branch structures are located on a side of the gate drive circuit away from the substrate, and the orthographic projection of at least part of the branch structures on the substrate at least partially overlaps the orthographic projection of at least part of the gate drive circuits of the same type on the substrate.

[0007] In an exemplary embodiment, the types of the at least one gate drive circuit include a first gate drive circuit, and the multiple branch structures include a first branch structure.

[0008] A projection of the first branch structure on the substrate at least partially overlaps with a projection of the first gate driving circuit on the substrate.

[0009] In an example embodiment, the first gate driving circuit comprises a plurality of transistors, the plurality of transistors comprising an output transistor, and a projection of the output transistor in the first gate driving circuit on the substrate at least partially overlaps with a projection of the first branch structure on the substrate.

[0010] In an example embodiment, a projection of an output transistor in the first gate driving circuit on the substrate is within a range of a projection of the first branch structure on the substrate.

[0011] In an example embodiment, the display region comprises a plurality of rows of sub-pixels, the sub-pixels comprising at least a pixel driving circuit, the pixel driving circuit comprising at least one first type of low-temperature polysilicon transistor, the first gate driving circuit being electrically connected to a control electrode of the at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels, and configured to provide a scanning signal to the at least one first type of low-temperature polysilicon transistor in the at least one row of sub-pixels.

[0012] In an example embodiment, the at least one first type of low-temperature polysilicon transistor comprises a data writing transistor and an initialization transistor.

[0013] In an example embodiment, the at least one type of gate driving circuit further comprises a second gate driving circuit and a third gate driving circuit, and the plurality of branch structures further comprises a second branch structure and a third branch structure.

[0014] In a direction in which the display region points to the frame region, the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit are arranged in sequence, and the first branch structure, the second branch structure, and the third branch structure are arranged in sequence, a projection of the second branch structure on the substrate is located between a projection of the second gate driving circuit on the substrate and a projection of the third driving circuit on the substrate, and a projection of the third branch structure on the substrate is located on a side of a projection of the third gate driving circuit on the substrate away from a projection of the second gate driving circuit on the substrate.

[0015] In an exemplary embodiment, the display region comprises a plurality of rows of sub-pixels, the sub-pixels comprising at least pixel driving circuitry, the pixel driving circuitry comprising at least one oxide transistor, the second gate driving circuit is electrically connected to the control electrode of the at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scan signal to the at least one oxide transistor in the at least one row of sub-pixels.

[0016] In an exemplary embodiment, the pixel driving circuitry further comprises at least one low-temperature polysilicon transistor of a second type, the third gate driving circuit is electrically connected to the control electrode of the at least one low-temperature polysilicon transistor of a second type in at least one row of sub-pixels, and is configured to provide a scan signal to the at least one low-temperature polysilicon transistor of a second type in the at least one row of sub-pixels.

[0017] In an exemplary embodiment, the at least one oxide transistor comprises a compensation transistor, and the at least one low-temperature polysilicon transistor of a second type comprises a light-emitting transistor.

[0018] In an exemplary embodiment, in a direction parallel to the plane on which the display substrate lies, the frame region is located at the periphery of the display region, in a first direction, the gate driving circuit and the first power supply line are located in the frame region on both sides of the display region, in a second direction, the frame region on one side of the display region is provided with a binding region, and the first direction intersects the second direction; the display substrate is symmetrical with respect to a first center line, and the first center line is a center line of the display substrate extending in the second direction.

[0019] In an exemplary embodiment, in the frame region on the same side of the display region in the first direction, the first stage to the last stage of the plurality of gate driving circuits of the same type are arranged in order in the direction in which the display region points to the binding region, and at least part of the signal lines in the last stage of at least two gate driving circuits share a signal line on the side close to the binding region.

[0020] In an exemplary embodiment, in the frame region on the same side of the display region in the first direction, the plurality of gate driving circuits comprise a second gate driving circuit and a third gate driving circuit, and in the direction in which the display region points to the frame region, the second gate driving circuit and the third gate driving circuit are arranged in order.

[0021] The last stage of the second gate driving circuit and at least part of the signal lines in the last stage of the third gate driving circuit share a signal line on the side close to the binding region.

[0022] In an exemplary embodiment, the at least part of the signal lines include clock signal lines; the third gate drive circuit includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line in the frame area on the same side of the display area along the first direction; and the second gate drive circuit includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line.

[0023] On the side close to the binding area, the first clock signal line shares one clock signal line with the fifth clock signal line, the second clock signal line shares one clock signal line with the sixth clock signal line, the third clock signal line shares one clock signal line with the seventh clock signal line, and the fourth clock signal line shares one clock signal line with the eighth clock signal line.

[0024] In an exemplary embodiment, the at least part of the signal lines include high-voltage power supply lines and low-voltage power supply lines; the third gate drive circuit includes a first high-voltage power supply line, a second high-voltage power supply line, a first low-voltage power supply line, and a second low-voltage power supply line in the frame area on the same side of the display area along the first direction; and the second gate drive circuit includes a third high-voltage power supply line, a fourth high-voltage power supply line, a third low-voltage power supply line, and a fourth low-voltage power supply line.

[0025] On the side close to the binding area, the first high-voltage power supply line shares one high-voltage signal line with the third high-voltage power supply line, the second high-voltage power supply line shares one high-voltage signal line with the fourth high-voltage power supply line, the first low-voltage power supply line shares one low-voltage signal line with the third low-voltage power supply line, and the second low-voltage power supply line shares one low-voltage signal line with the fourth low-voltage power supply line.

[0026] In an exemplary embodiment, the frame area includes a first frame area and a second frame area on both sides of the display area along a second direction, a third frame area and a fourth frame area on both sides of the display area along a first direction, a first corner area connecting the first frame area and the third frame area, a second corner area connecting the third frame area and the second frame area, a third corner area connecting the second frame area and the fourth frame area, and a fourth corner area connecting the fourth frame area and the first frame area.

[0027] The gate driving circuit and the first power supply line are located in the third and fourth frame regions, the first power supply line and the gate driving circuit located in the third frame region extend to the first and second corner regions, the first power supply line and the gate driving circuit located in the fourth frame region extend to the third and fourth corner regions, and the third and fourth frame regions are symmetrical relative to the first middle line.

[0028] In an example embodiment, the binding region is located in the first frame region.

[0029] In the third frame region, at least part of the signal lines in the last stage of at least two gate driving circuits share one signal line at one end of the first corner region close to the binding region.

[0030] In the fourth frame region, at least part of the signal lines in the last stage of at least two gate driving circuits share one signal line at one end of the fourth corner region close to the binding region.

[0031] In an example embodiment, the branch structure includes a first end and a second end, the first end of the plurality of branch structures extends to the frame region where the binding region is located, and the second end of the plurality of branch structures extends to the frame region on the side of the display region away from the binding region.

[0032] In the plurality of branch structures located on the same side of the display region in the first direction, the first end of the plurality of branch structures is connected as a connection end in the frame region where the binding region is located, or the second end of the plurality of branch structures is connected as a connection end in the frame region on the side of the display region away from the binding region.

[0033] In an example embodiment, the display substrate further includes a first power supply line collection line, the first power supply line collection line is located in the frame region where the binding region is located, or is located in the frame region on the side of the display region away from the binding region; the plurality of branch structures include a first branch structure, a second branch structure and a third branch structure arranged in sequence, in the first direction on the same side of the display region and in the direction of the display region pointing to the frame region.

[0034] In the direction perpendicular to the plane where the display substrate is located, the first power supply line collection line is located between the substrate and the first power supply line, the first power supply line collection line has an overlapping region with the connection end of the third branch structure in the orthographic projection on the substrate, and the connection ends of the first and second branch structures are connected with the connection end of the third branch structure.

[0035] In an example embodiment, the bus of the first power line and the third branch structure are directly connected in the overlapping area to form a double-layer structure.

[0036] In an example embodiment, the display substrate further comprises an auxiliary structure of the third branch structure, the third branch structure and the auxiliary structure of the third branch structure have an overlapping area in the orthographic projection on the base, and the third branch structure and the auxiliary structure of the third branch structure are directly connected in the overlapping area.

[0037] The first branch structure, the second branch structure, and the third branch structure are located in a second source-drain metal layer, the bus of the first power line and the auxiliary structure of the third branch structure are located in a first source-drain metal layer, and the auxiliary structure of the third branch structure and the bus of the first power line form an integrated structure.

[0038] In an example embodiment, the display substrate further comprises an anti-static circuit, the connection end portion of the first branch structure is provided with a first bending structure bent away from the display area, the connection end portion of the second branch structure is provided with a second bending structure bent away from the display area, and the first bending structure and the second bending structure are arranged in sequence in a frame area on the same side of the display area in a direction in which the display area points to the frame area.

[0039] In the first direction, the anti-static circuit is located between the first bending structure and the second bending structure, and in the second direction, the anti-static circuit is located between the connection end portion of the first branch structure and the connection end portion of the third branch structure.

[0040] In an example embodiment, in a direction perpendicular to the plane on which the display substrate is located, an anode conductive layer and a cathode layer are sequentially arranged on a side of the first power line away from the base, the anode conductive layer comprises a plurality of transfer electrodes, the orthographic projection of the plurality of transfer electrodes on the base at least partially overlaps the orthographic projection of the cathode layer and the plurality of branch structures on the base, the plurality of branch structures of the first power line are electrically connected to the plurality of transfer electrodes through a plurality of connection vias, and the cathode layer is connected to the plurality of transfer electrodes.

[0041] In an example embodiment, the plurality of branch structures comprise a first branch structure, a second branch structure, and a third branch structure, the plurality of transfer electrodes comprise a first transfer electrode, a second transfer electrode, and a third transfer electrode, and the plurality of connection vias comprise a first connection via, a second connection via, and a third connection via.

[0042] A normal projection of the first connection via on the substrate at least partially overlaps with a normal projection of the first branch structure and the first transfer electrode on the substrate, a normal projection of the second connection via on the substrate at least partially overlaps with a normal projection of the second branch structure and the second transfer electrode on the substrate, and a normal projection of the third connection via on the substrate at least partially overlaps with a normal projection of the third branch structure and the third transfer electrode on the substrate.

[0043] In an exemplary embodiment, the gate drive circuit includes a plurality of transistors and at least one capacitor, and includes, in a direction perpendicular to a plane on which the display substrate is located, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer which are sequentially arranged on the substrate.

[0044] The semiconductor layer includes an active layer of the plurality of transistors in the at least one gate drive circuit.

[0045] The first conductive layer includes a control electrode of the plurality of transistors in the at least one gate drive circuit and a first plate of the at least one capacitor.

[0046] The second conductive layer includes a second plate of the at least one capacitor in the at least one gate drive circuit.

[0047] The third conductive layer includes a first electrode and a second electrode of the plurality of transistors in the at least one gate drive circuit.

[0048] The fourth conductive layer includes a plurality of branch structures of the first power supply line.

[0049] In a second aspect, the embodiments of the present disclosure further provide a display device including the display substrate described in any of the above embodiments.

[0050] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0051] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, but do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of each component in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0052] FIG. 1 shows a structural schematic diagram of a display device provided by an embodiment of the present disclosure;

[0053] FIG. 2 shows a structural schematic diagram of a display device provided by an embodiment of the present disclosure;

[0054] Fig. 3 shows a partial cross-sectional structure of a display area of a display substrate according to an embodiment of the present disclosure;

[0055] Fig. 4 shows an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0056] Fig. 5 shows an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0057] Fig. 6 shows a structure of a display device according to an embodiment of the present disclosure;

[0058] Fig. 7 shows a structure of a display substrate according to an embodiment of the present disclosure;

[0059] Fig. 8 shows a structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0060] Fig. 9 shows a structure of a binding area according to an exemplary embodiment of the present disclosure;

[0061] Fig. 10 shows a structure of a display substrate after bending of a binding area according to an exemplary embodiment of the present disclosure;

[0062] Fig. 11a shows an equivalent circuit diagram of a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0063] Fig. 11b shows a plan structure of a first gate driving circuit according to an exemplary embodiment of the present disclosure;

[0064] Fig. 12a shows an equivalent circuit diagram of a second gate driving circuit according to an exemplary embodiment of the present disclosure;

[0065] Fig. 12b shows a plan structure of a second gate driving circuit according to an exemplary embodiment of the present disclosure;

[0066] Fig. 13a shows an equivalent circuit diagram of a third gate driving circuit according to an exemplary embodiment of the present disclosure;

[0067] Fig. 13b shows a plan structure of a third gate driving circuit according to an exemplary embodiment of the present disclosure;

[0068] Fig. 14a shows an enlarged structure of a third frame area according to an exemplary embodiment of the present disclosure;

[0069] Fig. 14b shows an enlarged structure of a third frame area according to an exemplary embodiment of the present disclosure;

[0070] Fig. 14c shows an enlarged structure of a third frame area according to an exemplary embodiment of the present disclosure;

[0071] FIG. 15a is a schematic view of an enlarged structure of a third bezel region according to an exemplary embodiment of the present disclosure;

[0072] FIG. 15b is a schematic view of a structure after forming an active layer in the third bezel region according to an exemplary embodiment of the present disclosure;

[0073] FIG. 15c is a schematic view of a structure after forming a first conductive layer in the third bezel region according to an exemplary embodiment of the present disclosure;

[0074] FIG. 15d is a schematic view of a structure after forming a second conductive layer in the third bezel region according to an exemplary embodiment of the present disclosure;

[0075] FIG. 15e is a schematic view of a structure after forming a third conductive layer in the third bezel region according to an exemplary embodiment of the present disclosure;

[0076] FIG. 15f is a schematic view of a structure after forming a fourth conductive layer in the third bezel region according to an exemplary embodiment of the present disclosure;

[0077] FIG. 16 is a schematic view of an enlarged structure of a first bezel region according to an exemplary embodiment of the present disclosure;

[0078] FIG. 17 is a schematic view of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It should be readily understood by those skilled in the art that the embodiments and features thereof can be changed or substituted without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. Embodiments and features of the present disclosure can be combined with each other as long as they are not inconsistent with each other.

[0080] In the drawings, the size, the thickness, or the region of one or more constituent elements, or the layer can be exaggerated for clarity in some cases. Therefore, one embodiment of the present disclosure should not be interpreted as being limited to the drawing. The size, the shape, and the relative arrangement of one or more constituent elements in the drawings are schematically shown, and therefore, the present disclosure is not limited to the drawings.

[0081] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to limit the numbers in the specification. In the present disclosure, "a plurality of" means two or more.

[0082] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or locational relationship are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation of this specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is changed as appropriate according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0083] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the situation.

[0084] In this specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to a region where current mainly flows.

[0085] In this specification, the first electrode can be a drain, and the second electrode can be a source, or the first electrode can be a source, and the second electrode can be a drain. In addition, the gate can also be referred to as the control electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source" and "drain" are sometimes exchanged with each other. Therefore, in this specification, "source" and "drain" can be exchanged with each other. In the embodiments of the present disclosure, the gate can be referred to as the control electrode.

[0086] In this specification, "electrically connected" includes the case where the components are connected through an element having some electrical effect. The element having some electrical effect is not particularly limited as long as it can transmit an electrical signal between the connected components. Examples of the element having some electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like.

[0087] In the present specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0088] In the present specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly so, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, etc. There can be some small deformations due to tolerances, such as a fillet, an arc edge, and a deformation, etc.

[0089] In the present specification, "about", "approximately", refer to not strictly limited boundaries, and allow for a range of process and measurement errors. In the present disclosure, "approximately the same" refers to a case in which the values differ by 10% or less.

[0090] In the present specification, A extending along a direction of B refers to A can include a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction of B, and the length of the main portion extending along the direction of B is greater than the length of the secondary portion extending along other directions. In the present specification, "A extends along the direction of B" refers to "the main portion of A extends along the direction of B".

[0091] In the present specification, "A and B are in the same layer structure" refers to A and B are formed at the same time by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A contains the orthographic projection of B" refers to the orthographic projection of B falls within the orthographic projection of A, or the orthographic projection of A covers the orthographic projection of B.

[0092] FIG. 1 is a schematic diagram of an outer shape of a display device, which is a rectangular rounded shape. The display device can include a display substrate. In some examples, the display substrate can be a closed polygon including linear sides, a circle or an ellipse including curved sides, or a semi-circle or a semi-ellipse including linear sides and curved sides, etc. In some examples, when the substrate substrate has linear sides, at least some of the corners of the substrate substrate can be curved. When the substrate substrate has a rectangular shape, the portions where the adjacent linear sides meet each other can be replaced with a curve having a predetermined curvature. Among them, the curvature can be set according to the different positions of the curve. For example, the curvature can be changed according to the position where the curve starts, the length of the curve, etc.

[0093] In some examples, as shown in FIG. 1, the display substrate can include a display area AA and a peripheral area BB located at the periphery of the display area. In some examples, the display area AA can include a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) oppositely arranged in the first direction X. Adjacent edges can be connected by an arc-shaped chamfer to form a chamfered quadrilateral shape. In some examples, the peripheral area BB can include a first frame (lower frame) B1 and a second frame (upper frame) B2 oppositely arranged in the second direction Y, and a third frame (left frame) B3 and a fourth frame (right frame) B4 oppositely arranged in the first direction X. The first frame B1 communicates with the third frame B3 and the fourth frame B4, and the second frame B2 communicates with the third frame B3 and the fourth frame B4.

[0094] In some examples, as shown in FIG. 1, the display area AA includes a plurality of sub-pixels PX, a plurality of gate lines G, and a plurality of data lines D. The plurality of gate lines G can extend along the first direction X, and the plurality of data lines D can extend along the second direction Y. The orthogonal projections of the plurality of gate lines G and the plurality of data lines D on the substrate substrate intersect to form a plurality of sub-pixel regions, with one sub-pixel PX arranged in each sub-pixel region. The plurality of data lines D are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines D can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines G are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines G can be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals can include scan signals and light emission control signals.

[0095] In some examples, as shown in FIG. 1, the first direction X can be the extension direction (row direction) of the gate lines G in the display area, and the second direction Y can be the extension direction (column direction) of the data lines D in the display area. The first direction X and the second direction Y can be perpendicular to each other.

[0096] In some examples, one pixel unit of the display area AA can include three sub-pixels, which are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. However, the present embodiment is not limited thereto. In some examples, one pixel unit can include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively.

[0097] In some examples, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal. When one pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner; when one pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner. However, the present embodiment is not limited thereto.

[0098] In some examples, the sub-pixel can include a pixel circuit and a light emitting element connected with the pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor, for example, the pixel circuit can be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0099] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected with the corresponding pixel circuit. However, the present embodiments are not limited thereto.

[0100] FIG. 2 is a structural schematic diagram of a display device. In some examples, as shown in FIG. 2, the display device can include a timing controller 201, a data driver 202, a scan driving circuit 203, a light emitting driving circuit 204, and a display substrate 205. In some examples, the display area of the display substrate 205 can include a plurality of sub-pixels PX arranged regularly. The scan driving circuit 203 can be configured to provide a scan signal to the sub-pixels PX along a scan line; the data driver 202 can be configured to provide a data voltage to the sub-pixels PX along a data line; the light emitting driving circuit 204 can be configured to provide a light emitting control signal to the sub-pixels PX along a light emitting control line; and the timing controller 201 can be configured to control the scan driving circuit 203, the light emitting driving circuit 204, and the data driver 202.

[0101] In some examples, the timing controller 201 can provide grayscale values and control signals suitable for the specifications of the data driver 202 to the data driver 202; the timing controller 201 can provide a scan clock signal, a scan start signal, and the like suitable for the specifications of the scan driving circuit 203 to the scan driving circuit 203; the timing controller 201 can provide a light emission clock signal, a light emission start signal, and the like suitable for the specifications of the light emission driving circuit 204 to the light emission driving circuit 204. The data driver 202 can generate data voltages to be provided to the data lines D1 to Dn using the grayscale values and the control signals received from the timing controller 201. For example, the data driver 202 can sample the grayscale values using the clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of sub-pixel behaviors. The scan driving circuit 203 can generate scan signals to be provided to the scan lines S1 to Sm by the scan clock signal, the scan start signal, and the like received from the timing controller 201. For example, the scan driving circuit 203 can sequentially provide scan signals having on-pulse to the scan lines. In some examples, the scan driving circuit 203 can include a shift register, and can generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the scan clock signal. The light emission driving circuit 204 can generate light emission control signals to be provided to the light emission control lines E1 to Eo by the light emission clock signal, the light emission start signal, and the like received from the timing controller 201. For example, the light emission driving circuit 204 can sequentially provide the light emission start signal having an off-pulse to the light emission control lines. The light emission driving circuit 204 can include a shift register to generate the light emission control signals in a manner that sequentially transfers the light emission start signal provided in the form of an off-pulse to a next stage circuit under the control of the light emission clock signal. Here, n, m, and o are all natural numbers.

[0102] In some examples, the scan driving circuit and the light emission driving circuit can be directly disposed on the display substrate. For example, the scan driving circuit can be disposed on the third bezel of the display substrate, and the light emission driving circuit can be disposed on the fourth bezel of the display substrate; or, the scan driving circuit and the light emission driving circuit can be disposed on both the third bezel and the fourth bezel of the display substrate. In some examples, the scan driving circuit and the light emission driving circuit can be formed together with the sub-pixels in a process of forming the sub-pixels.

[0103] In some examples, the data driver can be disposed on a separate chip or printed circuit board to be connected to the sub-pixels through signal access pins on the display substrate. For example, the data driver can be formed by chip on glass, chip on plastic, chip on film, etc. to be disposed on the first bezel of the display substrate to be connected to the signal access pins. The timing controller can be disposed separately from the data driver or integrally with the data driver. However, the present embodiments are not limited thereto. In some examples, the data driver can be directly disposed on the display substrate.

[0104] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base 101, and an encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the base 101. In some possible implementation manners, the display substrate can include other film layers, such as a spacer, etc., which are not limited in the present disclosure.

[0105] In the example implementation, the base 101 can be a flexible base or a rigid base. The driving circuit layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 103 can include an anode 301, an organic light-emitting layer 302, and a cathode 303, the anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302, the organic light-emitting layer 302 emits light of a corresponding color under the driving of the anode 301 and the cathode 303. The encapsulation layer 104 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together, the first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic material, the second encapsulation layer 402 can be made of organic material, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external water vapor from entering the light-emitting structure layer 103.

[0106] In exemplary embodiments, the organic light-emitting layer 302 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In exemplary embodiments, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0107] In exemplary embodiments, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in FIG. 4, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit can be connected with 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, emitting signal line E, initial signal line INIT, second power supply line VDD, and first power supply line VSS).

[0108] In exemplary embodiments, the pixel driving circuit can include a first node N1, a second node N2, and a third node N3. The first node N1 is connected with the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected with the second electrode of the first transistor T1, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected with the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0109] In exemplary embodiments, the first terminal of the storage capacitor C is connected with the second power supply line VDD, and the second terminal of the storage capacitor C is connected with the second node N2, i.e., the second terminal of the storage capacitor C is connected with the control electrode of the third transistor T3.

[0110] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the amount of charge of the control electrode of the third transistor T3.

[0111] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0112] The control electrode of the third transistor T3 is connected to the second node N2, i.e., the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the second power supply line VDD and the first power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0113] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, etc., and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit.

[0114] The control electrode of the fifth transistor T5 is connected to the emission signal line E, the first electrode of the fifth transistor T5 is connected to the second power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When an on-level emission signal is applied to the emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the second power supply line VDD and the first power supply line VSS.

[0115] The control electrode of the seventh transistor T7 is connected with the first scan signal line S1, the first electrode of the seventh transistor T7 is connected with the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light emitting device. When the turn-on level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device, so as to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0116] In the exemplary embodiments, the second electrode of the light emitting device is connected with the first power supply line VSS, the signal of the first power supply line VSS is a low level signal, and the signal of the second power supply line VDD is a high level signal continuously provided. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row, i.e., for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row is the same signal line as the first scan signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0117] In the exemplary embodiments, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E and the initial signal line INIT extend along the horizontal direction, and the first power supply line VSS, the second power supply line VDD and the data signal line D extend along the vertical direction.

[0118] In the exemplary embodiments, the light emitting device can be an organic electroluminescence diode (OLED) including a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked.

[0119] In an example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors (as shown in FIG. 4) or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors. As shown in FIG. 5, which is an equivalent circuit schematic diagram of a pixel driving circuit, in FIG. 5, the second transistor T2 is an N-type transistor (i.e., an oxide thin film transistor), the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors (i.e., low-temperature poly-silicon thin film transistors), the active layer of the low-temperature poly-silicon thin film transistor adopts low-temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low-temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of both and can achieve low-frequency driving, reduce power consumption, and improve display quality. As shown in FIG. 5, the pixel driving circuit can include 8 transistors (the first transistor T1 to the eighth transistor T8) and 1 storage capacitor C, and can be connected with 10 signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, an emission signal line E, an initial signal line INIT, a third initial signal line INIT3, a second power supply line VDD, and a first power supply line VSS). Compared with FIG. 4, the difference of FIG. 5 is that the eighth transistor T8, the third initial signal line INIT3, the third scan signal line S3, and the fourth scan signal line S4 are added, the third scan signal line S3 is connected with the control electrode of the second transistor T2, and the fourth scan signal line S4 is connected with the control electrode of the fourth transistor T4; the second transistor T2 is an N-type transistor, the first scan signal line S1 is further connected with the control electrode of the eighth transistor T8, the first electrode of the eighth transistor T8 is connected with the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected with the first node N; the first electrode of the first transistor T1 is connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected with the third node N3.

[0120] In an example embodiment, the first initial signal line INIT1 and the second initial signal line INIT2 in FIG. 4 and FIG. 5 can share one initial signal line INIT.

[0121] In some examples, the second power line VDD can be configured to provide a constant second voltage signal to the pixel circuit, the first power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal can be greater than the second voltage signal. The first scan line S1 can be configured to provide a first scan signal to the pixel circuit, the second scan line S2 can be configured to provide a second scan signal to the pixel circuit, the third scan line S3 can be configured to provide a third scan signal to the pixel circuit, the fourth scan line S4 can be configured to provide a fourth scan signal to the pixel circuit, the data line D can be configured to provide a data signal to the pixel circuit, and the light-emitting control line E can be configured to provide a light-emitting control signal to the pixel circuit.

[0122] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, which can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0123] An arc edge design can be adopted on a large-size display panel, which can maximize the display area in the display screen and achieve an extremely narrow frame. The GOA is rotated together with the layout of the pixel circuit, as shown in FIG. 6, which is a structural schematic diagram of a display device. The display device can include a display panel, and the display panel can include a display substrate. The display substrate can include a display area AA and a frame area BB around the display area. The display area AA can include at least one corner area, and the frame area BB can include at least one corner area, and the at least one corner area of the display area AA and the at least one corner area of the frame area BB correspond. A plurality of sub-pixels PX are located in the display area AA. At least part of the sub-pixels PX in the plurality of sub-pixels PX are located in the at least one corner area of the display area AA and are arranged in a stepped manner. A plurality of driving circuits 10 can be arranged in the at least one corner area of the frame area BB. The driving circuit 10 can be a gate driver on array (GOA) circuit. The GOA circuit can be a gate driving circuit. The gate driving circuit is configured to provide a gate driving signal (for example, the gate driving signal can be a signal provided to the first scan line S1, the second scan line S2, and the light-emitting control line E in FIG. 4) to the sub-pixel PX in the display area AA.

[0124] In some example embodiments, as shown in FIG. 6, the bezel area BB can further include: a first bezel area B1 and a second bezel area B2 located on both sides of the display area AA along the second direction Y, a third bezel area B3 and a fourth bezel area B4 located on both sides of the display area AA along the first direction X; at least one corner area of the bezel area BB can include: a first corner area C1 connecting the first bezel area B1 and the third bezel area B3, a second corner area C2 connecting the third bezel area B3 and the second bezel area B2, a third corner area C3 connecting the second bezel area B2 and the fourth bezel area B4, and a fourth corner area C4 connecting the fourth bezel area B4 and the first bezel area B1.

[0125] In some example embodiments, as shown in FIG. 6, the plurality of drive circuits 10 can be located in the third bezel area B3, the fourth bezel area B4, the first corner area C1, the second corner area C2, the third corner area C3, and the fourth corner area C4.

[0126] In some example embodiments, as shown in FIG. 6, the bezel area BB can further be provided with a first power line VSS, which can be located on the side of the GOA circuit away from the display area AA along the first direction X, for example, in the third bezel area B3 and the fourth bezel area B4. The cathode of the light emitting element EL is usually provided as a common electrode layer, and the first power line VSS is provided to supply a second voltage signal to the common electrode layer, and the common electrode layer provides the second voltage signal to the plurality of light emitting elements EL. Since the display panel usually does not provide the first power line VSS in the corner (rounded corner) area.

[0127] In order to better meet people's needs for various functions and better screen experience (for example, a display screen with an ultra-high screen ratio), the display screen design with a narrow bezel has gradually become the mainstream form of display devices. However, the layout of some signal lines and circuits in the display panel in some implementations makes it impossible for the display panel to achieve a narrow bezel, or in the case of a narrow bezel area BB, the width of the signal traces located in the bezel area BB is small, and there is a technical problem of signal trace burn. For example, in the structure shown in FIG. 6, the first power line VSS is arranged on the side of the GOA circuit 10 away from the display area AA, that is, in the third bezel area B3, the first power line VSS and the GOA circuit 10 are arranged along the first direction X in sequence; in the fourth bezel area B4, the GOA circuit 10 and the first power line VSS are arranged along the first direction X in sequence. In the structure with a narrow bezel, the dimensions of the third bezel area B3 and the fourth bezel area B4 along the first direction X are limited, and the dimension (i.e. width) of the first power line VSS along the first direction X is small, which causes the technical problem of burn due to the small width of the first power line VSS.

[0128] The display substrate provided by the embodiments of the present disclosure can include a display area and a frame area on at least one side of the display area, the frame area is provided with a first power supply line and at least one kind of gate drive circuit, different kinds of gate drive circuits are arranged in sequence along the direction in which the display area points to the frame area, and multiple gate drive circuits of the same kind are arranged along the extension direction of the frame area; the first power supply line can include multiple branch structures, the multiple branch structures are arranged in sequence along the direction in which the display area points to the frame area and extend along the extension direction of the frame area.

[0129] In the direction perpendicular to the plane where the display substrate is located, the display substrate can include a substrate, and the multiple branch structures are located on the side of the gate drive circuit away from the substrate, and the orthographic projection of at least part of the branch structures on the substrate at least partially overlaps the orthographic projection of at least part of the gate drive circuits on the substrate.

[0130] The display substrate provided by the embodiments of the present disclosure can include a display area and a frame area on at least one side of the display area, the frame area is provided with a first power supply line and at least one kind of gate drive circuit, different kinds of gate drive circuits are arranged in sequence along the direction in which the display area points to the frame area, and multiple gate drive circuits of the same kind are arranged along the extension direction of the frame area; the first power supply line can include multiple branch structures, the multiple branch structures are arranged in sequence along the direction in which the display area points to the frame area and extend along the extension direction of the frame area.

[0131] As shown in FIGS. 7 and 8, in the display substrate provided by the embodiments of the present disclosure, in the direction parallel to the plane where the display substrate is located, the display substrate can include a display area AA and a frame area BB on at least one side of the display area AA, the frame area BB can be provided with a first power supply line VSS and at least one kind of gate drive circuit 10, different kinds of gate drive circuits 10 are arranged in sequence along the direction in which the display area AA points to the frame area BB, and multiple gate drive circuits 10 of the same kind are arranged along the extension direction of the frame area BB; the first power supply line VSS can include multiple branch structures, the multiple branch structures are arranged in sequence along the direction in which the display area AA points to the frame area BB and extend along the extension direction of the frame area BB.

[0132] In the direction perpendicular to the plane where the display substrate is located, the display substrate can include a substrate, and the multiple branch structures are located on the side of the gate drive circuit 10 away from the substrate, and the orthographic projection of at least part of the branch structures on the substrate at least partially overlaps the orthographic projection of at least part of the gate drive circuits 10 on the substrate.

[0133] In the example embodiment, the kind of the at least one kind of gate drive circuit can include a first gate drive circuit 10P, and the multiple branch structures can include a first branch structure VSS1; the orthographic projection of the first branch structure VSS1 on the substrate at least partially overlaps the orthographic projection of the first gate drive circuit 10P on the substrate.

[0134] In an example embodiment, the first gate drive circuit 10P can include a plurality of transistors, the plurality of transistors can include an output transistor, and a positive projection of the first branch structure VSS1 on the base can at least partially overlap with a positive projection of the output transistor in the first gate drive circuit 10P on the base. In an example embodiment, the positive projection of the output transistor in the first gate drive circuit 10P on the base can be located within the range of the positive projection of the first branch structure VSS1 on the base.

[0135] In an example embodiment, the display area AA can include a plurality of rows of sub-pixels, the sub-pixels at least including pixel drive circuits, the pixel drive circuits can include at least one first type of low-temperature polysilicon transistor, the first gate drive circuit 10P can be electrically connected to a control electrode of the at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels, and be configured to provide a scanning signal to the at least one first type of low-temperature polysilicon transistor in the at least one row of sub-pixels.

[0136] In an example embodiment, the at least one first type of low-temperature polysilicon transistor can include a data writing transistor and an initialization transistor. As shown in FIG. 5, the data writing transistor can include the fourth transistor T4 (i.e., the fourth transistor T4 can serve as the data writing transistor), and the initialization transistor can include the first transistor T1, the seventh transistor T7, and the eighth transistor T8 (i.e., the first transistor T1, the seventh transistor T7, and the eighth transistor T8 can serve as the initialization transistor).

[0137] In an example embodiment, the types of the at least one gate drive circuit can further include a second gate drive circuit 10N and a third gate drive circuit 10EM, and the plurality of branch structures can further include a second branch structure VSS2 and a third branch structure VSS3.

[0138] In the direction in which the display area AA points to the frame area BB, the first gate drive circuit 10P, the second gate drive circuit 10N, and the third gate drive circuit 10EM are arranged in sequence, the first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 are arranged in sequence, a positive projection of the second branch structure VSS2 on the base is located between a positive projection of the second gate drive circuit 10N on the base and a positive projection of the third drive circuit on the base, and a positive projection of the third branch structure VSS3 on the base is located on a side of the third gate drive circuit 10EM on the base away from the positive projection of the second gate drive circuit 10N on the base.

[0139] In an example embodiment, the pixel driving circuit can include at least one oxide transistor, the second gate driving circuit 10N is electrically connected to the control electrode of the at least one oxide transistor in the at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one oxide transistor in the at least one row of sub-pixels.

[0140] In an example embodiment, the pixel driving circuit can further include at least one second type of low-temperature polysilicon transistor, the third gate driving circuit 10EM is electrically connected to the control electrode of the at least one second type of low-temperature polysilicon transistor in the at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one second type of low-temperature polysilicon transistor in the at least one row of sub-pixels.

[0141] In an example embodiment, the at least one oxide transistor includes a compensation transistor, and the at least one second type of low-temperature polysilicon transistor includes a light-emitting transistor. As shown in FIG. 5, the compensation transistor can include the second transistor T2, i.e., the second transistor T2 can serve as the compensation transistor, and the light-emitting transistor can include the fifth transistor T5 and the sixth transistor T6, i.e., the fifth transistor T5 and the sixth transistor T6 can serve as the light-emitting transistor.

[0142] In an example embodiment, in a direction parallel to the plane on which the display substrate lies, the frame area BB can be located at the periphery of the display area AA, in the first direction X, the gate driving circuit 10 and the first power supply line VSS can be located in the frame area BB on both sides of the display area AA, in the second direction Y, the frame area BB on one side of the display area AA is provided with a binding area 63, and the first direction X intersects the second direction Y; the display substrate can be symmetrical with respect to the first middle line Q-Q, and the first middle line Q-Q is a middle line of the display substrate extending in the second direction Y.

[0143] In an example embodiment, in the frame area BB on the same side of the display area AA in the first direction X, the first stage 10-1 to the last stage 10-N of the multiple gate driving circuits 10 of the same type are arranged in sequence in the direction in which the display area AA points to the binding area 63, and at least part of the signal lines in the last stage of the at least two gate driving circuits 10 share a signal line on the side close to the binding area. As shown in FIG. 8, the first stage 10P-1 to the last stage 10P-N of the multiple first gate driving circuits 10P are arranged in sequence in the direction in which the display area AA points to the binding area 63.

[0144] In the exemplary embodiments, in the frame region BB on the same side of the display region AA in the first direction X, the plurality of gate drive circuits 10 can include a second gate drive circuit 10N and a third gate drive circuit 10EM, and the second gate drive circuit 10N and the third gate drive circuit 10EM are arranged in sequence in the direction in which the display region AA points to the frame region BB.

[0145] At least part of the signal lines in the last stage of the second gate drive circuit 10N and the last stage of the third gate drive circuit 10EM share a signal line on the side close to the binding region.

[0146] In the exemplary embodiments, as shown in FIG. 8, the first stage 10N-1 to the last stage 10P-N of the plurality of second gate drive circuits 10N are arranged in sequence in the direction in which the display region AA points to the binding region 63, and the first stage 10EM-1 to the last stage 10EM-N of the plurality of third gate drive circuits 10EM are arranged in sequence in the direction in which the display region AA points to the binding region 63.

[0147] In the exemplary embodiments, as shown in FIGS. 14a to 14c, in the direction perpendicular to the plane on which the display substrate lies, the anode conductive layer, the cathode layer VSS0 are sequentially arranged on the side of the first power supply line VSS away from the base, the anode conductive layer can include a plurality of transfer electrodes ZM, the orthogonal projection of the plurality of transfer electrodes ZM on the base at least partially overlaps the orthogonal projection of the cathode layer VSS0 and the plurality of branch structures on the base, the plurality of branch structures of the first power supply line VSS are electrically connected to the plurality of transfer electrodes ZM through the plurality of connection vias Vm, and the cathode layer VSS0 is connected (for example, directly connected, lap joint connected) to the plurality of transfer electrodes.

[0148] In the exemplary embodiments, the plurality of branch structures can include a first branch structure VSS1, a second branch structure VSS2 and a third branch structure VSS3, the plurality of transfer electrodes ZM can include a first transfer electrode ZM1, a second transfer electrode ZM2 and a third transfer electrode ZM3, and the plurality of connection vias Vm can include a first connection via Vm1, a second connection via Vm2 and a third connection via Vm3.

[0149] The orthogonal projection of the first connection via Vm1 on the base at least partially overlaps the orthogonal projection of the first branch structure VSS1 and the first transfer electrode ZM on the base, the orthogonal projection of the second connection via Vm2 on the base at least partially overlaps the orthogonal projection of the second branch structure VSS2 and the second transfer electrode ZM on the base, and the orthogonal projection of the third connection via Vm3 on the base at least partially overlaps the orthogonal projection of the third branch structure VSS3 and the third transfer electrode ZM3 on the base.

[0150] In an exemplary embodiment, the gate driving circuit 10 can include a plurality of transistors and at least one capacitor, and include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially disposed on a base, in a direction perpendicular to a plane on which the display substrate is disposed;

[0151] The semiconductor layer can include at least one of an active layer of the plurality of transistors in the gate driving circuit 10;

[0152] The first conductive layer can include at least one of a control electrode of the plurality of transistors in the gate driving circuit 10 and a first electrode plate of the at least one capacitor;

[0153] The second conductive layer can include at least one of a second electrode plate of the at least one capacitor in the gate driving circuit 10;

[0154] The third conductive layer can include at least one of a first electrode and a second electrode of the plurality of transistors in the gate driving circuit 10;

[0155] The fourth conductive layer can include a plurality of branch structures of the first power line VSS.

[0156] The technical solutions of the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0157] As shown in FIGS. 7 and 8, the display substrate can include a display area AA and a bezel area BB located at a periphery of the display area AA, and the bezel area BB can include a first bezel area B1 and a second bezel area B2 located at both sides of the display area AA in a second direction Y, a third bezel area B3 and a fourth bezel area B4 located at both sides of the display area AA in a first direction X, and at least one corner area; the at least one corner area of the bezel area BB can include a first corner area C1 connecting the first bezel area B1 and the third bezel area B3, a second corner area C2 connecting the third bezel area B3 and the second bezel area B2, a third corner area C3 connecting the second bezel area B2 and the fourth bezel area B4, and a fourth corner area C4 connecting the fourth bezel area B4 and the first bezel area B1.

[0158] As shown in FIG. 8, the display substrate can further include a binding area 63 located at one side of the display area AA, and the binding area 63 can be located in the first bezel area B1. In a direction perpendicular to the plane on which the display substrate is located, the display area AA can include a substrate and a plurality of sub-pixels PX disposed on the substrate, the plurality of sub-pixels PX can form a plurality of rows and a plurality of columns, the sub-pixels PX can include a pixel driving circuit and a light emitting device, the binding area 63 can include a binding circuit for connecting a signal line to an external driving device, the third bezel area B3 and the fourth bezel area B4 can include a gate driving circuit 10 and a first power line VSS for transmitting a voltage signal to the plurality of sub-pixels. In an exemplary embodiment, the first power line VSS and the gate driving circuit 10 located in the third bezel area B3 can extend to the first corner area C1 and the second corner area C2, and the first power line VSS and the gate driving circuit 10 located in the fourth bezel area B4 can extend to the third corner area C3 and the fourth corner area C4, and the third bezel area B3 and the fourth bezel area B4 are symmetrical with respect to the first middle line Q-Q.

[0159] FIG. 9 is an enlarged structural schematic view of the first bezel area B1 in FIG. 8. As shown in FIGS. 8 and 9, in a plane parallel to the display substrate, the first bezel area B1 can include, in order along a direction away from the display area AA, a first fan-out region 61, a bending region 62, a second fan-out region 631, and a binding region 63; the binding region 63 can include, in order along a direction away from the bending region 62 of the second fan-out region 631, a driving chip region 632 and a binding electrode region 633. The first fan-out region 61 can include data fan-out lines, a second power line, and a first power line VSS, the data fan-out lines being located in a middle portion of the first fan-out region 61 and including a plurality of data connection lines configured to connect data lines of the display area AA in a fan-out manner, the second power line being configured to connect a high-voltage power line (VDD) of the display area AA, and the first power line being a low-voltage power line (VSS) located in the third bezel area B3 and the fourth bezel area B4. The bending region 62 can include a composite insulating layer provided with a groove and configured to bend the binding region 63 to a back surface of the display area AA. The second fan-out region 631 includes a plurality of data connection lines led out in a fan-out manner. The driving chip region 632 can be provided with an integrated circuit (IC) 70 configured to be connected to the plurality of data connection lines. The binding electrode region 633 includes a plurality of bonding pads configured to be connected to a flexible printed circuit (FPC) 80 in a binding manner. In an exemplary embodiment, the integrated circuit (IC) 400 can be connected to the driving chip region 205 in a binding manner, and the flexible printed circuit (FPC) 80 can be connected to the binding electrode region 633 in a binding manner. In an exemplary embodiment, the integrated circuit 70 can generate a driving signal required for driving a sub-pixel and can provide the driving signal to the sub-pixel PX located in the display area AA. For example, the driving signal can be a data signal for controlling the luminance of the sub-pixel. In an exemplary embodiment, the binding electrode region 632 can be provided with a pad (PAD) including a plurality of pins (PIN), and the flexible printed circuit 80 can be connected to the pad in a binding manner.

[0160] In an exemplary embodiment, as shown in FIG. 10, the bending region 62 can invert the surface of the binding region 63, i.e., the surface of the binding region 63 facing upward can be converted to face downward through the bending of the bending region 62. In an exemplary embodiment, when the bending region 62 is bent, the binding region 63 can overlap the display area AA in a display panel thickness direction.

[0161] In an example embodiment, for a large-size display substrate, a plurality of data driving ICs and a plurality of FPCs can be provided, and the plurality of FPCs are respectively bound to the plurality of data driving ICs, for example, four data driving ICs can be provided and bound to four FPCs, and the embodiments of the present disclosure are not limited to four ICs and four FPCs, for example, two data driving ICs and two FPCs can be provided. In the embodiments of the present disclosure, the number of data driving ICs and FPCs can be set according to the size of the display substrate and the need for function, which is not limited herein.

[0162] As shown in FIGS. 7 and 8, in the plane parallel to the display substrate, in the direction pointing from the display area AA to the third frame area B3, the gate driving circuit 10 in the third frame area B3 can include the first gate driving circuit 10P, the second gate driving circuit 10N and the third gate driving circuit 10EM arranged in sequence; in the direction pointing from the display area AA to the fourth frame area B4, the gate driving circuit 10 in the fourth frame area B4 can include the first gate driving circuit 10P, the second gate driving circuit 10N and the third gate driving circuit 10EM arranged in sequence.

[0163] In an example embodiment, the first gate driving circuit 10P can be configured to provide a scanning signal to at least part of the low-temperature polysilicon transistors of at least one row of sub-pixel circuits, the second gate driving circuit 10N can be configured to provide a scanning signal to at least one oxide transistor in at least one row of sub-pixels, and the third gate driving circuit 10EM can be configured to provide a scanning signal to at least one light-emitting control transistor in at least one row of sub-pixels. Taking the pixel driving circuit shown in FIG. 5 as an example: the first gate driving circuit 10P can be configured to provide a scanning signal to the first transistor T1, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 of at least one row of sub-pixel circuits, i.e., the first gate driving circuit 10P can include three types, the first gate driving circuit 10P of the first type can be configured to provide a first scanning signal to the first scanning signal line S1, the first gate driving circuit 10P of the second type can be configured to provide a second scanning signal to the second scanning signal line S2, and the first gate driving circuit 10P of the third type can be configured to provide a fourth scanning signal to the fourth scanning signal line S4; the second gate driving circuit 10N can be configured to provide a third scanning signal to the third scanning signal line S3; and the third gate driving circuit 10EM can be configured to provide a light-emitting control signal to the light-emitting signal line E.

[0164] In an example embodiment, as shown in FIGS. 7 and 8, the first power supply line VSS can be disposed in the third and fourth bezel regions B3 and B4, and in a direction in which the display region AA points to the bezel region BB, the first power supply line VSS can include a plurality of branch structures arranged in sequence, first ends of the plurality of branch structures can extend to the first bezel region B1, and second ends of the plurality of branch structures can extend to the second bezel region B2. The first ends of the plurality of branch structures can be electrically connected to each other in the first bezel region B1, or the second ends of the plurality of branch structures can be electrically connected to each other in the second bezel region B2.

[0165] In an example embodiment, the first power supply line VSS can include a first branch structure VSS1, a second branch structure VSS2, and a third branch structure VSS3, and in a direction in which the display region AA points to the bezel region BB, the first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 can be arranged in sequence. The first branch structure VSS1 can at least partially overlap the at least partial projection of the first gate driving circuit 10P on the base.

[0166] As shown in FIG. 11a, it is an equivalent circuit diagram of a first gate drive circuit 10P, and as shown in FIG. 11b, it is a plane structure schematic diagram of the first gate drive circuit 10P. The first gate drive circuit 10P can be a 9T3C structure, that is, the first gate drive circuit 10P can include nine transistors and three capacitors. The nine transistors can include a first transistor T101 to a ninth transistor T109, and the three capacitors can include a first capacitor C11 to a third capacitor C13. The circuit connection relationship of the first gate drive circuit 10P is as follows: the control electrode of the first transistor T101 is connected with a clock signal line CK, the first electrode of the first transistor T101 is connected with a first initial signal line STV1, and the second electrode of the first transistor T101 is connected with a first node N11; the control electrode of the second transistor T102 is connected with a third node N13, the first electrode of the second transistor T102 is connected with a second node N12, and the second electrode of the second transistor T102 is connected with a fourth node N14; the control electrode of the third transistor T103 is connected with a seventh node N17, the first electrode of the third transistor T103 is connected with a low-voltage power supply line VGL, and the second electrode of the third transistor T103 is connected with the second node N12; the control electrode of the fourth transistor T104 is connected with the second node N12, the first electrode of the fourth transistor T104 is connected with a high-voltage power supply line VGH, and the second electrode of the fourth transistor T104 is connected with a first output end OUT1; the control electrode of the fifth transistor T105 is connected with a fifth node N15; the first electrode of the fifth transistor T105 is connected with a clock signal line CB, and the second electrode of the fifth transistor T105 is connected with the first output end OUT1; the control electrode of the sixth transistor T106 is connected with the second node N12, the first electrode of the sixth transistor T106 is connected with a sixth node N16, and the second electrode of the sixth transistor T106 is connected with the fourth node N14; the control electrode of the seventh transistor T107 is connected with the third node N13, the first electrode of the seventh transistor T107 is connected with the high-voltage power supply line VGH, and the second electrode of the seventh transistor T107 is connected with the seventh node N17; the control electrode of the eighth transistor T108 is connected with the low-voltage power supply line VGL, the first electrode of the eighth transistor T108 is connected with the first node N11, and the second electrode of the eighth transistor T108 is connected with the fifth node N15; the control electrode of the ninth transistor T109 is connected with the clock signal line CB, the first electrode of the ninth transistor T109 is connected with the first node N11, and the second electrode of the ninth transistor T109 is connected with the sixth node N16; one of the plates of the first capacitor C11 is connected with the first output end OUT1, and the other plate is connected with the fifth node N15; one of the plates of the second capacitor C12 is connected with the high-voltage power supply line VGH, and the other plate is connected with the second node N12; one of the plates of the third capacitor C13 is connected with the low-voltage power supply line VGL, and the other plate is connected with the seventh node N17.

[0167] As shown in FIG. 12a, it is an equivalent circuit diagram of a second gate drive circuit 10N, and as shown in FIG. 12b, it is a plane structure schematic diagram of the second gate drive circuit 10N. The second gate drive circuit 10N can be a 16T3C structure, that is, the second gate drive circuit 10N can include sixteen transistors and three capacitors. The sixteen transistors can include a first transistor T201 to a sixteenth transistor T216, and the three capacitors can include a first capacitor C21 to a third capacitor C23. The circuit connection relationship of the second gate drive circuit 10N is as follows: the control electrode of the first transistor T201 is connected with a fifth clock signal line CK5, the first electrode of the first transistor T201 is connected with a second initial signal line STV2, and the second electrode of the first transistor T201 is connected with a first node N21; the control electrode of the second transistor T202 is connected with the first node N21, the first electrode of the second transistor T202 is connected with a seventh clock signal line CK7, and the second electrode of the second transistor T202 is connected with a second node N22; the control electrode of the third transistor T203 is connected with the fifth clock signal line CK5, the first electrode of the third transistor T203 is connected with a second low-voltage power supply line VGL2, and the second electrode of the third transistor T203 is connected with the second node N22; the control electrode of the fourth transistor T204 is connected with a ninth node N29, the first electrode of the fourth transistor T204 is connected with a sixth clock signal line N26, and the second electrode of the fourth transistor T204 is connected with a fifth node N25; the control electrode of the fifth transistor T205 is connected with the second node N22, the first electrode of the fifth transistor T205 is connected with a third high-voltage power supply line VGH3, and the second electrode of the fifth transistor T205 is connected with the fifth node N25; the control electrode of the sixth transistor T206 is connected with a sixth node N26, the first electrode of the sixth transistor T206 is connected with an eighth clock signal line CK8, and the second electrode of the sixth transistor T206 is connected with a third node N23; the control electrode of the seventh transistor T207 is connected with the eighth clock signal line CK8, the first electrode of the seventh transistor T207 is connected with the third node N23, and the second electrode of the seventh transistor T207 is connected with a fourth node N24; the control electrode of the eighth transistor T208 is connected with the first node N21, the first electrode of the eighth transistor T208 is connected with a fourth high-voltage power supply line VGH4, and the second electrode of the eighth transistor T208 is connected with the fourth node N24; the control electrode of the ninth transistor T209 is connected with the fourth node N24, the first electrode of the ninth transistor T209 is connected with the fourth high-voltage power supply line VGH4, and the second electrode of the ninth transistor T209 is connected with a second output end OUT2; the control electrode of the tenth transistor T210 is connected with a seventh node N27, the first electrode of the tenth transistor T210 is connected with a third low-voltage power supply line VGL3, and the second electrode of the tenth transistor T210 is connected with the second output end OUT2;The control electrode of the eleventh transistor T211 is connected with the fourth low-voltage power supply line VGL4, the first electrode of the eleventh transistor T211 is connected with the second node N22, and the second electrode of the eleventh transistor T211 is connected with the sixth node N26; the control electrode of the twelfth transistor T212 is connected with the fourth low-voltage power supply line VGL4, the first electrode of the twelfth transistor T212 is connected with the first node N21, and the second electrode of the twelfth transistor T212 is connected with the seventh node N27; the control electrode of the thirteenth transistor T213 is connected with the power supply line VEL, the first electrode of the thirteenth transistor T213 is connected with the fourth high-voltage power supply line VGH4, and the second electrode of the thirteenth transistor T213 is connected with the first node N21; the control electrode of the fourteenth transistor T214 is connected with the fifth clock signal line CK5, the first electrode of the fourteenth transistor T214 is connected with the second initial signal line STV2, and the second electrode of the fourteenth transistor T214 is connected with the eighth node N28; the control electrode of the fifteenth transistor T215 is connected with the fourth low-voltage power supply line VGL4, the first electrode of the fifteenth transistor T215 is connected with the eighth node N28, and the second electrode of the fifteenth transistor T215 is connected with the ninth node N29; the control electrode and the first electrode of the sixteenth transistor T216 are both connected with the ninth node N29, and the second electrode of the sixteenth transistor T216 is connected with the seventh node N27; one of the electrodes of the first capacitor C21 is connected with the third node N23, and the other electrode is connected with the sixth node N26; one of the electrodes of the second capacitor C22 is connected with the fourth high-voltage power supply line VGH4, and the other electrode is connected with the fourth node N24; one of the electrodes of the third capacitor C23 is connected with the fifth node N25, and the other electrode is connected with the ninth node N29.

[0168] As shown in FIG. 13a, it is an equivalent circuit diagram of a third gate drive circuit 10EM, and as shown in FIG. 13b, it is a plane structure schematic diagram of the third gate drive circuit 10EM. The third gate drive circuit 10EM can be a 12T3C structure, that is, the third gate drive circuit 10EM can include twelve transistors and three capacitors. The twelve transistors can include a first transistor T301 to a twelfth transistor T312, and the three capacitors can include a first capacitor C31 to a third capacitor C33. The connection relationship of the third gate drive circuit 10EM is as follows: the control electrode of the first transistor T301 is connected with a first clock signal line CK1, the first electrode of the first transistor T301 is connected with a third initial signal line STV3, and the second electrode of the first transistor T301 is connected with a first node N31; the control electrode of the second transistor T302 is connected with the first node N31, the first electrode of the second transistor T302 is connected with a third clock signal line CK3, and the second electrode of the second transistor T302 is connected with a second node N32; the control electrode of the third transistor T303 is connected with the first clock signal line CK1, the first electrode of the third transistor T303 is connected with a second low-voltage power supply line VGL2, and the second electrode of the third transistor T303 is connected with the second node N32; the control electrode of the fourth transistor T304 is connected with a seventh node N37, the first electrode of the fourth transistor T304 is connected with the second clock signal line N32, and the second electrode of the fourth transistor T304 is connected with a fifth node N35; the control electrode of the fifth transistor T305 is connected with the second node N32, the first electrode of the fifth transistor T305 is connected with a second high-voltage power supply line VGH1, and the second electrode of the fifth transistor T305 is connected with the fifth node N35; the control electrode of the sixth transistor T306 is connected with a sixth node N36, the first electrode of the sixth transistor T306 is connected with a fourth clock signal line CK4, and the second electrode of the sixth transistor T306 is connected with a third node N33; the control electrode of the seventh transistor T307 is connected with the fourth clock signal line CK4, the first electrode of the seventh transistor T307 is connected with the third node N33, and the second electrode of the seventh transistor T307 is connected with a fourth node N34; the control electrode of the eighth transistor T308 is connected with the first node N31, the first electrode of the eighth transistor T308 is connected with a first high-voltage power supply line VGH2, and the second electrode of the eighth transistor T308 is connected with the fourth node N34; the control electrode of the ninth transistor T309 is connected with the fourth node N34, the first electrode of the ninth transistor T309 is connected with the second high-voltage power supply line VGH2, and the second electrode of the ninth transistor T309 is connected with a third output end OUT3; the control electrode of the tenth transistor T310 is connected with the seventh node N37, the first electrode of the tenth transistor T310 is connected with a first low-voltage power supply line VGL1, and the second electrode of the tenth transistor T310 is connected with the third output end OUT3;The control electrode of the eleventh transistor T311 is connected with the second low-voltage power supply line VGL2, the first electrode of the eleventh transistor T311 is connected with the second node N32, and the second electrode of the eleventh transistor T311 is connected with the sixth node N36; the control electrode of the twelfth transistor T312 is connected with the second low-voltage power supply line VGL2, the first electrode of the twelfth transistor T312 is connected with the first node N31, and the second electrode of the twelfth transistor T312 is connected with the seventh node N37; one of the plates of the first capacitor C31 is connected with the third node N33, and the other plate is connected with the sixth node N36; one of the plates of the second capacitor C32 is connected with the second high-voltage power supply line VGH2, and the other plate is connected with the fourth node N34; one of the plates of the third capacitor C33 is connected with the fifth node N35, and the other plate is connected with the seventh node N37.

[0169] In the example embodiment, the second gate driving circuit 10N is not limited to the 16T3C structure, for example, a 9T3C structure or a 12T3C structure can be adopted; the third gate driving circuit 10EM is not limited to the 12T3C structure, for example, a 9T3C structure or a 16T3C structure can be adopted. In the example embodiment, as shown in FIG. 14a, the first gate driving circuit 10P, the second gate driving circuit 10N, and the third gate driving circuit 10EM can be arranged in sequence along the direction from the display area AA to the frame area BB, the output transistor in the first gate driving circuit 10P can include a fourth transistor T104 and a fifth transistor T105, the fourth transistor T104 and the fifth transistor T105 can be arranged in sequence along the second direction Y, and the fourth transistor T104 and the fifth transistor T105 can be located on the side of the second gate driving circuit 10N away from the third gate driving circuit 10EM, i.e., the fourth transistor T104 and the fifth transistor T105 can be located on the side close to the display area AA.

[0170] In an example embodiment, the display substrate can include, in a direction perpendicular to a plane on which the display substrate lies, a base and, in order, a semiconductor layer, a first conductive (GATE1) layer, a second conductive (GATE2) layer, a third conductive (SD1) layer, and a fourth conductive (SD2) layer. In an example embodiment, a first insulating layer is provided between the active layer and the first conductive layer, a second insulating layer is provided between the first conductive layer and the second conductive layer, a third insulating layer is provided between the second conductive layer and the third conductive layer, a fourth insulating layer and a first planarization layer (the fourth insulating layer is between the third conductive layer and the first planarization layer, and the first planarization layer is between the fourth insulating layer and the fourth conductive layer) are provided between the third conductive layer and the fourth conductive layer, and a second planarization layer is provided between the fourth conductive layer and a fifth conductive layer. In an example embodiment, on a side of the fourth conductive layer away from the base in a direction perpendicular to a plane on which the display substrate lies, the display area AA can further include, in order, a fifth conductive layer (which can be referred to as an anode conductive layer and include a plurality of anodes 301), a pixel definition layer, an emission layer (for example, the organic emission layer 302 in FIG. 3), and a sixth conductive layer (which can be referred to as a cathode layer VSS0 and include the cathode 303 in FIG. 3), as shown in FIG. 14b, the anode conductive layer can include a plurality of transfer electrodes ZM, the plurality of transfer electrodes ZM have projections on the base that at least partially overlap the projection of the cathode layer VSS0 and the plurality of branch structures on the base, the plurality of transfer electrodes ZM can be electrically connected to the plurality of branch structures through a plurality of connection vias Vm, and the cathode layer VSS0 can extend to the frame area BB and be connected (for example, directly connected or overlapped) to the plurality of transfer electrodes ZM to achieve electrical connection between the plurality of branch structures (VSS1, VSS2, VSS3) of the first power supply line VSS and the cathode layer VSS0. For example, the second planarization layer (PLN2) can include a plurality of connection vias Vm, the plurality of connection vias Vm can include a first connection via Vm1, a second connection via Vm2, and a third connection via Vm2, the plurality of transfer electrodes ZM can include a first transfer electrode ZM1, a second transfer electrode ZM2, and a third transfer electrode ZM3, the projection of the first connection via Vm1 on the base at least partially overlaps the first branch structure VSS1 of the first power supply line VSS and the projection of the first transfer electrode ZM1 on the base, the projection of the second connection via Vm2 on the base at least partially overlaps the second branch structure VSS2 of the first power supply line VSS and the projection of the second transfer electrode ZM2 on the base, and the projection of the third connection via Vm3 on the base at least partially overlaps the third branch structure VSS3 of the first power supply line VSS and the projection of the third transfer electrode ZM3 on the base. In an example embodiment, the cathode layer VSS0 can be connected to the plurality of organic emission layers 302 in the display area AA.

[0171] In an example embodiment, the semiconductor layer can include: an active layer of the first transistor T101 to the ninth transistor T109 in the first gate drive circuit 10P, an active layer of the first transistor T201 to the sixteenth transistor T216 in the second gate drive circuit 10N, an active layer of the first transistor T301 to the twelfth transistor T212 in the third gate drive circuit 10EM; wherein the planar structure schematic diagram of the semiconductor layer of the first gate drive circuit 10P to the third gate drive circuit 10EM can be as shown in FIG. 15b.

[0172] The first conductive layer can include: a control electrode of the first transistor T101 to the ninth transistor T109 in the first gate drive circuit 10P, a control electrode of the first transistor T201 to the sixteenth transistor T216 in the second gate drive circuit 10N, a control electrode of the first transistor T301 to the twelfth transistor T212 in the third gate drive circuit 10EM, a first plate of the first capacitor C11 to the third capacitor C13 in the first gate drive circuit 10P, a first plate of the first capacitor C21 to the third capacitor C23 in the second gate drive circuit 10N, a first plate of the first capacitor C31 to the third capacitor C33 in the third gate drive circuit 10EM; wherein the planar structure schematic diagram of the first conductive layer of the first gate drive circuit 10P to the third gate drive circuit 10EM can be as shown in FIG. 15c, and the area of the first conductive layer overlapping with the active layer of the transistor can be used as the control electrode of the transistor.

[0173] The second conductive layer can include: a second plate of the first capacitor C11 to the third capacitor C13 in the first gate drive circuit 10P, a second plate of the first capacitor C21 to the third capacitor C23 in the second gate drive circuit 10N, a second plate of the first capacitor C31 to the third capacitor C33 in the third gate drive circuit 10EM, a second output terminal OUT2, a third output terminal OUT3; wherein the planar structure schematic diagram of the second conductive layer of the first gate drive circuit 10P to the third gate drive circuit 10EM can be as shown in FIG. 15d.

[0174] The third conductive layer can include: a first electrode and a second electrode of the first transistor T101 to the ninth transistor T109 in the first gate drive circuit 10P, a first electrode and a second electrode of the first transistor T201 to the sixteenth transistor T216 in the second gate drive circuit 10N, a first electrode and a second electrode of the first transistor T301 to the twelfth transistor T212 in the third gate drive circuit 10EM, a first output terminal OUT1, a first low-voltage power supply line VGL1 to a second low-voltage power supply line VGL2; wherein the planar structure schematic diagram of the third conductive layer of the first gate drive circuit 10P to the third gate drive circuit 10EM can be as shown in FIG. 15e.

[0175] The fourth conductive layer can include: a plurality of branch structures of the first power supply line VSS, the third low-voltage power supply line VGL3 to the fourth low-voltage power supply line VGL4, the first high-voltage power supply line VGJ1 to the fourth high-voltage power supply line VGH4, the first clock signal line CK1 to the eighth clock signal line CK8, the first initial signal line STV1 to the third initial signal line STV3, the low-voltage power supply line VGL and the high-voltage power supply line VGH. A planar structure diagram of the fourth conductive layer located in the frame region (for example, located in the third frame region B3) can be as shown in FIG. 15f.

[0176] In an example embodiment, the first output end OUT1 is configured to provide a scan signal to the P-type transistor (i.e., a low-temperature polysilicon transistor) shown in FIG. 4 or FIG. 5, for example, to provide a scan signal to the control electrode of the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 in FIG. 4, or to the control electrode of the first transistor T1, the control electrode of the fourth transistor T4, the control electrode of the seventh transistor T7, and the control electrode of the eighth transistor T8 in FIG. 5; the second output end OUT2 is configured to provide a scan signal to the N-type transistor (i.e., an oxide transistor) shown in FIG. 5, for example, to provide a scan signal to the control electrode of the second transistor T2 in FIG. 5; and the third output end OUT3 is configured to provide a scan signal to the light-emitting transistor shown in FIG. 4 or FIG. 5, for example, to provide a scan signal to the control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 in FIG. 5, or to the control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 in FIG. 4.

[0177] As shown in FIGS. 14-15f, the structure of the fourth frame region B4 can be symmetrically arranged with the structure of the third frame region B3 along the middle line of the display substrate in the second direction Y. As shown in FIGS. 7 and 14, the orthographic projection of the first branch structure VSS1 on the base can at least partially overlap the orthographic projection of the output transistor in the first gate drive circuit 10P on the base, for example, the orthographic projection of the output transistor (the fourth transistor T104 and the fifth transistor T105) in the first gate drive circuit 10P on the base can be located within the range of the orthographic projection of the first branch structure VSS1 on the base. The first branch structure VSS1 can shield the output transistor in the first gate drive circuit 10P, and can reduce the influence of the interference signal on the output transistor in the gate drive circuit 10P.

[0178] As shown in FIG. 7 and FIG. 14, in the direction in which the display region AA points to the frame region BB, the orthogonal projection of the second branch structure VSS2 on the substrate can be located between the orthogonal projection of the second gate driving circuit 10N on the substrate and the orthogonal projection of the third gate driving circuit 10EM on the substrate, and the orthogonal projection of the third branch structure VSS3 on the substrate can be located on the side of the orthogonal projection of the third gate driving circuit 10EM on the substrate away from the orthogonal projection of the second gate driving circuit 10N on the substrate.

[0179] In the example embodiment, the first power line VSS arranged as a plurality of branch structures can increase the width of the first power line VSS, and to some extent, can reduce the risk of burn caused by the first power line VSS being too narrow.

[0180] In the example embodiment, in the direction perpendicular to the plane on which the substrate lies, the first power line VSS can be located on the side of the gate driving circuit 10 away from the substrate. As shown in FIG. 14, the positions of the plurality of branch structures of the first power line VSS generally take into account the restrictions and shielding effects of other signal lines (such as the clock signal line CK and the power signal line VGL, VGH), for example, the first gate driving circuit 10P can adopt a 9T3C structure, and the first branch structure VSS1 of the first power line VSS can shield the output transistor in the first gate driving circuit 10P of the 9T3C structure, thereby playing a shielding role, and the second branch structure VSS2 can not overlap with the gate driving circuit 10 (avoiding other signal lines). The branch structures of the first power line VSS of the embodiments of the present disclosure can not be limited to the positional relationship of the plurality of branch structures of the first power line VSS shown in FIG. 7 and FIG. 14, and in the case of changes in the circuit structure of the gate driving circuit 10, the positions of the plurality of branch structures of the first power line VSS can change accordingly. The positions of the plurality of branch structures of the first power line VSS can take into account two factors: on the one hand, avoiding other signal lines to avoid shorting with other signal lines, and on the other hand, trying to completely shield the transistors in the corresponding gate driving circuit to play a shielding role.

[0181] In the exemplary embodiment, as shown in FIG. 14, the second branch structure VSS2 and the third branch structure VSS3 are limited in space due to other signal line traces, and do not cover any transistor (TFT) above, so that there is no overlap with the internal TFT tube, and no shielding effect is generated. However, the signal line distribution on the GOA of other products can be different, and the positions covered by the multiple branch structures of the first power line VSS can be different. If the branch structure of the first power line VSS covers the TFT tube of the effective GOA, in addition to considering that the space distribution meets the requirements, the covered TFT tube can also be completely blocked to play a shielding role. If the branch structure (trace) of the first power line VSS does not cover the TFT (transistor) of the effective GOA, only the requirement of meeting the space distribution needs to be considered.

[0182] In the exemplary embodiment, as shown in FIGS. 15a and 15b, the multiple branch structures of the first power line VSS are arranged on the side away from the substrate of the first gate driving circuit 10P (P-Gate GOA), the second gate driving circuit 10N (N-Gate GOA), and the third gate driving circuit 10EM (EM GOA). The multiple branch structures of the first power line VSS can be arranged on the side away from the substrate of the dummy GOA (which can be referred to as virtual GOA) corresponding to the gate driving circuit 10. The relative positions of the multiple branch structures of the first power line VSS and the dummy GOA (virtual GOA) and the relative positions of the corresponding effective GOA can be the same. Thus, the multiple branch structures (i.e., branch traces) of the first power line VSS are formed on the side away from the substrate in the GOA area. As shown in FIG. 15a, the upper half of the GOA is the effective GOA, and the lower half of the GOA is the dummy GOA. As shown in FIG. 15b, the poly layer in the effective GOA is completely connected, while the poly layer in the dummy GOA has been broken, disconnecting the channel layer of the transistor (TFT), and avoiding the conduction of the transistor in the dummy GOA (virtual GOA circuit). The multiple branch structures of the first power line VSS located in the third border area B3 and the fourth border area B4 extend from the second border area B2 to the pad area 633 of the one border area B1.

[0183] As shown in FIG. 15a and FIG. 15b, the display substrate can include a first dummy gate driving circuit D10P, a second dummy gate driving circuit D10N, and a third dummy gate driving circuit D10EM, wherein, in the arrangement direction of the first gate driving circuit 10P, the first dummy gate driving circuit D10P can be located on one side of one of the first gate driving circuits 10P; in the arrangement direction of the second gate driving circuit 10N, the second dummy gate driving circuit D10N can be located on one side of one of the second gate driving circuits 10N; in the arrangement direction of the third gate driving circuit 10EM, the third dummy gate driving circuit D10EM can be located on one side of one of the third gate driving circuits 10EM.

[0184] As shown in FIG. 15a, the orthographic projection of the first branch structure VSS1 on the substrate can at least partially overlap the orthographic projection of the output transistor in the first gate driving circuit 10P and the position of the output transistor in the first dummy gate driving circuit D10P on the substrate, for example, the orthographic projection of the output transistor (the fourth transistor T104 and the fifth transistor T105) in the first gate driving circuit 10P and the position of the output transistor (the position T104D of the fourth transistor T104 and the position T105D of the fifth transistor T105) in the first dummy gate driving circuit D10P on the substrate can be located within the range of the orthographic projection of the first branch structure VSS1 on the substrate.

[0185] As shown in FIG. 15a, in the direction in which the display area AA points to the frame area BB, the orthographic projection of the second branch structure VSS2 on the substrate can be located between the orthographic projection of the second dummy gate driving circuit D10N on the substrate and the orthographic projection of the third dummy gate driving circuit D10EM on the substrate, and the orthographic projection of the third branch structure VSS3 on the substrate can be located on the side of the orthographic projection of the third dummy gate driving circuit D10EM on the substrate away from the orthographic projection of the second dummy gate driving circuit D10N on the substrate.

[0186] As shown in FIG. 15b, in the dummy gate driving circuit, the active layer can be interrupted, and signal communication can be avoided, for example, the active layer in the transistor can be interrupted at the position of the channel region, and the transistor in the dummy gate driving circuit can be avoided from being turned on.

[0187] In an example embodiment, as shown in FIG. 7 and FIG. 16, the branch structure can include a first end portion (D11, D21, D31) and a second end portion (D12, D22, D32), the first end portions of the plurality of branch structures can extend to the frame area where the binding area 63 is located (for example, the frame area where the binding area 63 is located can be the first frame area B1), and the second end portions of the plurality of branch structures can extend to the frame area on the side of the display area AA away from the binding area 63; for example, the first end portions of the plurality of branch structures can extend to the first frame area B1, and the second end portions of the plurality of branch structures can extend to the second frame area B2. Among the plurality of branch structures located on the same side of the display area AA in the first direction, the first end portions of the plurality of branch structures can be connected as the connection end portions in the frame area where the binding area 63 is located (for example, the frame area where the binding area 63 is located can be the first frame area B1), or the second end portions of the plurality of branch structures can be connected as the connection end portions in the frame area on the side of the display area AA away from the binding area 63.

[0188] In an example embodiment, as shown in FIG. 16, the display substrate can further include a bus VSSL of the first power supply line VSS, the bus VSSL of the first power supply line can be located in the frame area where the binding area 63 is located (for example, the frame area where the binding area 63 is located can be the first frame area B1), or in the frame area on the side of the display area AA away from the binding area 63 (for example, the second frame area B2); in the first direction X, on the same side of the display area AA, in the direction of the display area AA pointing to the frame area BB, the first branch structure VSS1, the second branch structure VSS2 and the third branch structure VSS3 are arranged in sequence.

[0189] In the direction perpendicular to the plane where the display substrate is located, the bus VSSL of the first power supply line VSS is located between the substrate and the first power supply line VSS, the bus VSSL of the first power supply line has an overlapping area with the connection end portion (for example, D31) of the third branch structure VSS3 in the orthographic projection of the substrate on the substrate, and the connection end portions of the first branch structure VSS1 and the second branch structure VSS2 are connected with the connection end portion of the third branch structure.

[0190] In an example embodiment, the bus VSSL of the first power supply line and the third branch structure VSS3 are connected in the overlapping area to form a double-layer structure, which increases the thickness of the first power supply line VSS and reduces the impedance and voltage drop. In an example embodiment, the bus VSSL of the first power supply line and the connection end portion (D31) of the third branch structure VSS3 can be electrically connected with the driving chip IC through the binding area 63.

[0191] In the example embodiment, the display substrate can further include a third branch structure auxiliary structure VSS31, the third branch structure VSS3 and the third branch structure auxiliary structure VSS31 have an overlapping area in the orthographic projection of the third branch structure VSS3 on the substrate, and the third branch structure VSS3 and the third branch structure auxiliary structure VSS31 are directly connected in the overlapping area, so as to reduce the voltage drop and impedance of the third branch structure VSS3.

[0192] In the example embodiment, as shown in FIG. 16, the branch structure of the first power supply line VSS can be located on the side of the gate driving circuit 10 (GOA circuit) away from the substrate, the first branch structure VSS1, the second branch structure VSS2, and the third branch structure VSS3 can be located on the second source-drain metal layer (SD2) on the side of the gate driving circuit 10 away from the substrate, the collection line VSSL of the first power supply line and the third branch structure auxiliary structure VSS31 can be located on the first source-drain metal layer (SD1), and the third branch structure auxiliary structure VSS31 and the collection line VSSL of the first power supply line can be an integrated structure. In the frame area (for example, the first frame area B1) where the binding area 63 is located, the collection line VSSL of the first power supply line and the third branch structure VSS3 at least partially overlap in the orthographic projection of the third branch structure VSS3 on the substrate, and the collection line VSSL of the first power supply line located on the first source-drain metal layer SD1 and the third branch structure VSS3 located on the second source-drain metal layer SD2 can form a double-layer structure, so as to reduce the impedance and voltage drop.

[0193] In the example embodiment, as shown in FIG. 16, the display substrate can further include an anti-static circuit ESD, the connection end of the first branch structure VSS1 is provided with a first bending structure Z1 bent in a direction away from the display area AA, the connection end of the second branch structure VSS2 is provided with a second bending structure Z2 bent in a direction away from the display area AA, and the first bending structure Z1 and the second bending structure Z2 are arranged in sequence in the direction of the display area AA pointing to the frame area BB on the same side frame area BB of the display area AA; for example, in the third frame area B3, the first bending structure Z1 and the second bending structure Z2 can be arranged in sequence in the direction of the display area AA pointing to the third frame area B3.

[0194] In the first direction X, the anti-static circuit ESD can be located between the first bending structure Z1 and the second bending structure Z2, and in the second direction Y, the anti-static circuit ESD can be located between the connection end of the first branch structure VSS1 and the connection end of the third branch structure VSS3.

[0195] In an exemplary embodiment, as shown in FIG. 16, the interval area of the plurality of branch structures of the first power supply line VSS in the first border area B1 (lower border area) can be provided with an anti-static circuit ESD (i.e. other TFT devices such as ESD can be placed in the space between the plurality of branch structures), which improves the space utilization and widens the width of VSS as a whole. As shown in FIG. 16, in the first border area B1, in the first direction X, the anti-static circuit ESD can be located between the first branch structure VSS1 and the second branch structure VSS2, i.e. the anti-static circuit ESD can be provided between the plurality of branch structures of the first power supply line VSS at the confluence interface in the first border area B1. The plurality of branch structures of the first power supply line VSS of the embodiments of the present disclosure are not limited to be connected in the first border area B1, for example, the confluence bus VSSL of the first power supply line can be confluenced in the second border area B2 or other positions.

[0196] In an exemplary embodiment, as shown in FIG. 16, at least part of the signal lines in the last stage 10N-N of the second gate drive circuit 10N and the last stage 10EM-N of the third gate drive circuit 10EM can share a signal line at the corner area close to the binding area 63, which can provide more space for the first power supply line VSS on the one hand while ensuring signal sharing, and on the other hand, can reduce the border under the condition that the space occupied by the first power supply line VSS remains unchanged, so as to further narrow the border.

[0197] As shown in FIG. 7, FIG. 8 and FIG. 16, in the third border area B3, at least part of the signal lines in the last stage of at least two kinds of gate drive circuits 10 share a signal line at one end of the first corner area C1 close to the binding area 63; in the fourth border area B4, at least part of the signal lines in the last stage of at least two kinds of gate drive circuits 10 share a signal line at one end of the fourth corner area C4 close to the binding area 63.

[0198] As illustrated in FIG. 16, at least part of the signal lines can include clock signal lines, and the third gate driver circuit 10EM can include a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4, and the second gate driver circuit 10N can include a fifth clock signal line CK5, a sixth clock signal line CK6, a seventh clock signal line CK7, and an eighth clock signal line CK8, in the frame region BB on the same side as the display region AA in the first direction X. In a side close to the bonding region 63 (for example, the gate driver circuit 10 positioned in the third frame region B3 can be in the first corner region C1, and the gate driver circuit 10 positioned in the fourth frame region B4 can be in the fourth corner region C4), the first clock signal line CK1 can share one clock signal line with the fifth clock signal line CKV5, the second clock signal line CK2 can share one clock signal line with the fifth clock signal line CKV6, the third clock signal line CK3 can share one clock signal line with the seventh clock signal line CKV7, and the fourth clock signal line CK4 can share one clock signal line with the eighth clock signal line CKV8.

[0199] As illustrated in FIG. 16, at least part of the signal lines can include high-voltage power supply lines and low-voltage power supply lines, and the third gate driver circuit 10EM can include a first high-voltage power supply line VGH1, a second high-voltage power supply line VGH2, a first low-voltage power supply line VGL1, and a second low-voltage power supply line VGL2, and the second gate driver circuit 10N can include a third high-voltage power supply line VGH3, a fourth high-voltage power supply line VGH4, a third low-voltage power supply line VGL3, and a fourth low-voltage power supply line VGL4, and the first gate driver circuit 10P includes a low-voltage power supply line VGL in a side close to the second gate driver circuit 10N. In a side close to the bonding region 63 (for example, the gate driver circuit 10 positioned in the third frame region B3 can be in the first corner region C1, and the gate driver circuit 10 positioned in the fourth frame region B4 can be in the fourth corner region C4), the first high-voltage power supply line VGH1 can share one high-voltage signal line with the third high-voltage power supply line VGH3, the second high-voltage power supply line VGH2 can share one high-voltage signal line with the fourth high-voltage power supply line VGH4, the first low-voltage power supply line VGL1 can share one low-voltage signal line with the third low-voltage power supply line VGL3, the low-voltage power supply line VGL in the first gate driver circuit 10P can share one signal line with the third low-voltage power supply line VGL3 in the second gate driver circuit 10N, and the second low-voltage power supply line VGL2 can share one low-voltage signal line with the fourth low-voltage power supply line VGL4.

[0200] In the structure shown in FIG. 16, the CK1 / CK5, CK2 / CK6, CK3 / CK7, CK4 / CK8, VGH1 / VGH3, VGH2 / VGH4, VGL1 / VGL3, VGL2 / VGL4 signals are connected to the PAD area (i.e. the first border area B1 where the binding area 63 is located) two by two at the end of the lower rounded last stage GOA, which can provide more space for the VSS wire while ensuring signal sharing.

[0201] The display device provided by the present disclosure can include the display substrate of any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0202] The display substrate and the display device provided by the present embodiment can increase the width of the first power line and reduce the risk of burn caused by the small width of the first power line by arranging the plurality of branch structures of the first power line in the border area.

[0203] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0204] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0205] Although the embodiments disclosed by the present disclosure are as described above, the content described above is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising a display area and a frame area on at least one side of the display area in a direction parallel to a plane on which the display substrate is located, the frame area being provided with a first power supply line and at least one gate drive circuit, different types of gate drive circuits being arranged in sequence in a direction in which the display area points to the frame area, and a plurality of gate drive circuits of the same type being arranged in an extension direction of the frame area; the first power supply line comprises a plurality of branch structures arranged in sequence in the direction in which the display area points to the frame area and extending in the extension direction of the frame area; in a direction perpendicular to the plane on which the display substrate is located, the display substrate comprises a substrate, the plurality of branch structures being located on a side of the gate drive circuit away from the substrate, and a projection of at least part of the branch structures on the substrate at least partially overlaps a projection of at least part of the types of gate drive circuits on the substrate. The types of the at least one gate drive circuit comprise a first gate drive circuit, and the plurality of branch structures comprise a first branch structure. 2.The display substrate of claim 1, wherein, The projection of the first branch structure on the substrate at least partially overlaps the projection of the first gate drive circuit on the substrate. The first gate drive circuit comprises a plurality of transistors, the plurality of transistors comprising an output transistor, and the projection of the first branch structure on the substrate at least partially overlaps the projection of the output transistor in the first gate drive circuit on the substrate. 3.The display substrate of claim 2, wherein, The projection of the output transistor in the first gate drive circuit on the substrate is located within the range of the projection of the first branch structure on the substrate. 4.The display substrate of claim 3, wherein, The display area comprises a plurality of rows of sub-pixels, the sub-pixels comprising at least a pixel drive circuit, the pixel drive circuit comprising at least one first type of low-temperature polysilicon transistor, the first gate drive circuit being electrically connected to a control electrode of the at least one first type of low-temperature polysilicon transistor in at least one row of sub-pixels and configured to provide a scanning signal to the at least one first type of low-temperature polysilicon transistor in the at least one row of sub-pixels. 5.The display substrate according to any one of claims 2 to 4, wherein, The at least one first type of low-temperature polysilicon transistor comprises a data writing transistor and an initialization transistor. 6.The display substrate of claim 5, wherein, The types of the at least one gate drive circuit further comprise a second gate drive circuit and a third gate drive circuit, and the plurality of branch structures further comprise a second branch structure and a third branch structure. 7.The display substrate of claim 2, wherein, In the direction in which the display area points to the frame area, the first gate drive circuit, the second gate drive circuit and the third gate drive circuit are arranged in sequence, and the first branch structure, the second branch structure and the third branch structure are arranged in sequence, the projection of the second branch structure on the substrate is located between the projection of the second gate drive circuit on the substrate and the projection of the third drive circuit on the substrate, and the projection of the third branch structure on the substrate is located on a side of the projection of the third gate drive circuit on the substrate away from the projection of the second gate drive circuit on the substrate. ​ 8.The display substrate of claim 7, wherein, The display region includes multiple rows of sub-pixels, and the sub-pixels at least include pixel driving circuits, the pixel driving circuits include at least one oxide transistor, the second gate driving circuit is electrically connected to the control electrode of the at least one oxide transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one oxide transistor in the at least one row of sub-pixels. 9.The display substrate of claim 8, wherein, The pixel driving circuit further includes at least one second type of low-temperature polysilicon transistor, and the third gate driving circuit is electrically connected to the control electrode of the at least one second type of low-temperature polysilicon transistor in at least one row of sub-pixels, and is configured to provide a scanning signal to the at least one second type of low-temperature polysilicon transistor in the at least one row of sub-pixels. 10.The display substrate of claim 9, wherein, The at least one oxide transistor includes a compensation transistor, and the at least one second type of low-temperature polysilicon transistor includes a light-emitting transistor.

11. The display substrate according to any one of claims 1 to 4, 7 to 10, wherein, In a direction parallel to the plane on which the display substrate is located, the frame region is located at the periphery of the display region, in a first direction, the gate driving circuit and the first power supply line are located in the frame region on both sides of the display region, in a second direction, the frame region on one side of the display region is provided with a binding region, and the first direction intersects the second direction; the display substrate is symmetrical relative to a first center line, and the first center line is a center line of the display substrate extending in the second direction. 12.The display substrate of claim 11, wherein, In the frame region on the same side of the display region in the first direction, the first level to the last level of the multiple gate driving circuits of the same type are arranged in turn in the direction in which the display region points to the binding region, and at least part of the signal lines in the last level of the at least two gate driving circuits share one signal line on the side close to the binding region. 13.The display substrate of claim 12, wherein, In the frame region on the same side of the display region in the first direction, the multiple gate driving circuits include a second gate driving circuit and a third gate driving circuit, and the second gate driving circuit and the third gate driving circuit are arranged in turn in the direction in which the display region points to the frame region. The last level of the second gate driving circuit and at least part of the signal lines in the last level of the third gate driving circuit share one signal line on the side close to the binding region. 14.The display substrate of claim 13, wherein, The at least part of the signal lines include clock signal lines; in the frame region on the same side of the display region in the first direction, the third gate driving circuit includes a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; and the second gate driving circuit includes a fifth clock signal line, a sixth clock signal line, a seventh clock signal line and an eighth clock signal line. On the side close to the binding region, the first clock signal line and the fifth clock signal line share one clock signal line, the second clock signal line and the sixth clock signal line share one clock signal line, the third clock signal line and the seventh clock signal line share one clock signal line, and the fourth clock signal line and the eighth clock signal line share one clock signal line. 15.The display substrate of claim 13, wherein, The at least partial signal lines include a high-voltage power supply line and a low-voltage power supply line; in the third border area along the first direction on the same side of the display area, the third gate drive circuit includes a first high-voltage power supply line, a second high-voltage power supply line, a first low-voltage power supply line, and a second low-voltage power supply line; the second gate drive circuit includes a third high-voltage power supply line, a fourth high-voltage power supply line, a third low-voltage power supply line, and a fourth low-voltage power supply line; On one side close to the binding area, the first high-voltage power supply line shares a high-voltage signal line with the third high-voltage power supply line, the second high-voltage power supply line shares a high-voltage signal line with the fourth high-voltage power supply line, the first low-voltage power supply line shares a low-voltage signal line with the third low-voltage power supply line, and the second low-voltage power supply line shares a low-voltage signal line with the fourth low-voltage power supply line. 16.The display substrate of claim 12, wherein, The border area includes: a first border area and a second border area located on both sides of the display area along the second direction, a third border area and a fourth border area located on both sides of the display area along the first direction, a first corner area connecting the first border area and the third border area, a second corner area connecting the third border area and the second border area, a third corner area connecting the second border area and the fourth border area, and a fourth corner area connecting the fourth border area and the first border area; The gate drive circuit and the first power supply line are located in the third border area and the fourth border area, the first power supply line and the gate drive circuit located in the third border area extend to the first corner area and the second corner area, and the first power supply line and the gate drive circuit located in the fourth border area extend to the third corner area and the fourth corner area, and the third border area and the fourth border area are symmetrical relative to the first middle line. The binding area is located in the first border area; 17.The display substrate of claim 16, wherein, In the third border area, at least partial signal lines in the last stage of at least two kinds of gate drive circuits share a signal line at one end of the first corner area close to the binding area; In the fourth border area, at least partial signal lines in the last stage of at least two kinds of gate drive circuits share a signal line at one end of the fourth corner area close to the binding area. The branch structure includes a first end and a second end, the first end of the plurality of branch structures extends to the border area where the binding area is located, and the second end of the plurality of branch structures extends to the border area on the side of the display area away from the binding area; 18.The display substrate of claim 11, wherein, In the plurality of branch structures located on the same side of the display area along the first direction, the first end of the plurality of branch structures is connected as a connection end in the border area where the binding area is located, or the second end of the plurality of branch structures is connected as a connection end in the border area on the side of the display area away from the binding area. ​ 19. The display substrate according to claim 18, further comprising a first power line bus, the first power line bus being located in a frame region where the binding region is located, or in a frame region on a side of the display region away from the binding region; the plurality of branch structures comprise, in a direction along the display region pointing to the frame region, a first branch structure, a second branch structure and a third branch structure arranged in sequence on the same side of the display region in the first direction. In a direction perpendicular to a plane where the display substrate is located, the first power line bus is located between the base and the first power line, a projection of the first power line bus on the base and a projection of the connection end portion of the third branch structure on the base have an overlapping region, and the connection end portions of the first branch structure and the second branch structure are connected to the connection end portion of the third branch structure. 20.The display substrate of claim 19, wherein, The first power line bus and the third branch structure are directly connected in the overlapping region to form a double-layer structure.

21. The display substrate according to claim 20, further comprising an auxiliary structure of the third branch structure, a projection of the third branch structure on the base and a projection of the auxiliary structure of the third branch structure on the base have an overlapping region, and the third branch structure and the auxiliary structure of the third branch structure are directly connected in the overlapping region. The first branch structure, the second branch structure and the third branch structure are located in a second source-drain metal layer, and the first power line bus and the auxiliary structure of the third branch structure are located in a first source-drain metal layer. The auxiliary structure of the third branch structure and the first power line bus form an integral structure.

22. The display substrate according to claim 19, further comprising an anti-static circuit, the connection end portion of the first branch structure is provided with a first bending structure bent away from the display region, the connection end portion of the second branch structure is provided with a second bending structure bent away from the display region, and the first bending structure and the second bending structure are arranged in sequence in a direction along the display region pointing to the frame region in a frame region on the same side of the display region. In the first direction, the anti-static circuit is located between the first bending structure and the second bending structure, and in the second direction, the anti-static circuit is located between the connection end portion of the first branch structure and the connection end portion of the third branch structure. In a direction perpendicular to a plane where the display substrate is located, an anode conductive layer and a cathode layer are sequentially arranged on a side of the first power line away from the base, the anode conductive layer comprises a plurality of transfer electrodes, a projection of the plurality of transfer electrodes on the base and a projection of the cathode layer and the plurality of branch structures on the base at least partially overlap, the plurality of branch structures of the first power line are electrically connected to the plurality of transfer electrodes through a plurality of connection vias, and the cathode layer is connected to the plurality of transfer electrodes.

23. The display substrate of claim 1, wherein, ​ 24. The display substrate of claim 23, wherein, The plurality of branch structures include a first branch structure, a second branch structure and a third branch structure, and the plurality of transfer electrodes include a first transfer electrode, a second transfer electrode and a third transfer electrode, and the plurality of connection vias include a first connection via, a second connection via and a third connection via; A projection of the first connection via on the substrate at least partially overlaps with a projection of the first branch structure and the first transfer electrode on the substrate, a projection of the second connection via on the substrate at least partially overlaps with a projection of the second branch structure and the second transfer electrode on the substrate, and a projection of the third connection via on the substrate at least partially overlaps with a projection of the third branch structure and the third transfer electrode on the substrate. 25.The display substrate of claim 1, wherein, The gate drive circuit includes a plurality of transistors and at least one capacitor, and in a direction perpendicular to a plane in which the display substrate is located, includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially arranged on the substrate; The semiconductor layer includes an active layer of the plurality of transistors in the at least one gate drive circuit; The first conductive layer includes a control electrode of the plurality of transistors in the at least one gate drive circuit and a first electrode plate of the at least one capacitor; The second conductive layer includes a second electrode plate of the at least one capacitor in the at least one gate drive circuit; The third conductive layer includes a first electrode and a second electrode of the plurality of transistors in the at least one gate drive circuit; The fourth conductive layer includes the plurality of branch structures of the first power supply line.

26. A display device, comprising the display substrate according to any one of claims 1 to 25.

Images