Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises: a base and multiple light-emitting pixels located on the base. Each light-emitting pixel comprises multiple light-emitting sub-pixels; each light-emitting sub-pixel comprises a micro light-emitting device located in a corresponding region and a pixel driving circuit coupled to the micro light-emitting device by means of a circuit output point; and in a same light-emitting sub-pixel, the orthographic projections of the circuit output point and the micro light-emitting device on the base entirely fall within the range of the orthographic projection of the corresponding light-emitting sub-pixel on the base.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Micro Light-Emitting Diode (Micro LED) display products have developed rapidly in recent years due to their excellent picture quality and wide range of application scenarios.

[0003] When Micro LEDs are used in active-drive displays, to achieve higher screen brightness uniformity, power signals, such as VDD, typically use two layers of metal, distributed in a mesh pattern. Consequently, minimizing wiring power consumption while maintaining high pixel density becomes a pressing technical challenge.

[0004] Summary of the Invention

[0005] The present disclosure provides a display substrate and a display device, the specific solutions of which are as follows:

[0006] An embodiment of the present disclosure provides a display substrate, comprising:

[0007] a substrate and a plurality of light-emitting pixels located on the substrate;

[0008] Among them, each of the luminous pixels includes multiple luminous sub-pixels; each of the luminous sub-pixels includes a micro-luminous device located in a corresponding area and a pixel driving circuit coupled to the micro-luminous device through a circuit output point; within the same luminous sub-pixel, the circuit output point and the micro-luminous device are projected orthographically on the substrate, completely falling within the area of ​​the orthographic projection of the corresponding luminous sub-pixel on the substrate.

[0009] Optionally, in the embodiment of the present disclosure, it also includes a first high-potential routing line extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels, and a plurality of second high-potential routing lines extending in a direction parallel to the long axis of each of the light-emitting sub-pixels; each of the second high-potential routing lines is coupled to the first high-potential routing line through a corresponding first node, and the orthographic projection of the first node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

[0010] Optionally, in an embodiment of the present disclosure, within the same light-emitting sub-pixel, the display substrate further includes a first overlap portion and a second overlap portion, the pixel driving circuit is coupled to one end of the first overlap portion through the circuit output point, and the other end of the first overlap portion is coupled to the anode of the corresponding micro-light-emitting device through a second node and the second overlap portion; the orthographic projection of the second node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

[0011] Optionally, in an embodiment of the present disclosure, the pixel driving circuit includes an active layer, a first metal layer, a second metal layer and a third metal layer arranged in sequence away from the substrate; the first high potential wiring and the second overlapping portion are both arranged in the same layer and material as the third metal layer, and the second high potential wiring and the first overlapping portion are both arranged in the same layer and material as the second metal layer.

[0012] Optionally, in the embodiment of the present disclosure, it also includes a low-potential trace extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels; the low-potential trace is arranged in the same layer and material as the third metal layer, and the low-potential trace is respectively coupled to the cathode of each of the micro-light-emitting devices in the light-emitting pixels.

[0013] Optionally, in the embodiment of the present disclosure, a third high-potential routing is further included, extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels; the orthographic projection of the third high-potential routing on the substrate completely falls within the area of ​​the orthographic projection of the first high-potential routing on the substrate, and the third high-potential routing is coupled to the corresponding second high-potential routing through a third node, and the orthographic projection of the third node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

[0014] Optionally, in the embodiment of the present disclosure, a fourth metal layer is further included between the first metal layer and the second metal layer, and the third high potential trace is provided in the same layer and with the same material as the fourth metal layer.

[0015] Optionally, in the embodiment of the present disclosure, in each of the luminescent pixels, the long axis direction of each of the micro-luminescent devices is parallel to the long axis direction of each of the luminescent sub-pixels, and each of the micro-luminescent devices is extended along a direction perpendicular to the long axis direction of each of the luminescent sub-pixels.

[0016] Optionally, in the embodiment of the present disclosure, it also includes a flat layer and a first passivation layer arranged between the second metal layer and the third metal layer, and a second passivation layer arranged on the side of the third metal layer away from the substrate; the flat layer, the first passivation layer and the second passivation layer are arranged away from the substrate in sequence; and a plurality of exhaust holes are opened along the thickness direction of the first passivation layer and the second passivation layer.

[0017] Optionally, in the embodiment of the present disclosure, in the display area, the orthographic projection of each of the exhaust holes on the substrate and the orthographic projection of the third metal layer on the substrate do not overlap with each other.

[0018] Optionally, in the embodiment of the present disclosure, within the display area, an arrangement period of the plurality of exhaust holes is the same as an arrangement period of the plurality of light-emitting sub-pixels.

[0019] Optionally, in an embodiment of the present disclosure, it also includes a display area and a peripheral area arranged around the display area; within the peripheral area, the display substrate also includes a first lead and a second lead, the first lead includes a first part extending along a direction parallel to the long axis of the light-emitting sub-pixel, the second lead includes a second part extending along a direction parallel to the long axis of the light-emitting sub-pixel, the first part is coupled to the first high potential wiring, the second part is coupled to the low potential wiring, and the first part is coupled to the first constant power supply terminal, and the second part is coupled to the second constant power supply terminal.

[0020] Optionally, in the embodiment of the present disclosure, on the same side of the display substrate, the second portion is arranged on a side of the first portion away from the display area.

[0021] Optionally, in the embodiment of the present disclosure, along a direction parallel to the short axis of each of the light-emitting sub-pixels, an extension length of the first portion and the second portion is greater than an extension length of each of the light-emitting sub-pixels.

[0022] Optionally, in an embodiment of the present disclosure, a flat layer is arranged between the first part and the substrate, and the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the flat layer on the substrate, the orthographic projection of the first part on the substrate completely falls within the area of ​​the orthographic projection of the flat layer on the substrate, the first part is provided with at least one hollow structure, and the inorganic layer located on the side of the flat layer away from the substrate is provided with an exhaust hole corresponding to the at least one hollow structure.

[0023] Optionally, in an embodiment of the present disclosure, a flat layer is provided between the first portion and the low potential trace, and in the peripheral region, the flat layer is located in an area where the first portion and the low potential trace overlap.

[0024] Optionally, in an embodiment of the present disclosure, a flat layer extending from the display area to the peripheral area is further included, and the orthographic projections of the first part and the second part on the substrate completely fall within the area of ​​the orthographic projection of the flat layer on the substrate. The first part and the second part are both provided with at least one hollow structure, and the inorganic layer located on the side of the flat layer away from the substrate is provided with an exhaust hole corresponding to the at least one hollow structure.

[0025] Accordingly, an embodiment of the present disclosure provides a display device, comprising:

[0026] A display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a schematic diagram of one arrangement of micro LEDs within a pixel in the related art;

[0028] FIG2 is a schematic diagram of one arrangement of micro LEDs within a pixel in the related art;

[0029] FIG3 a is a schematic diagram of one arrangement of sub-pixels in the related art;

[0030] FIG3 b is a schematic diagram of one configuration of a micro LED in the related art;

[0031] FIG4 is a typical circuit of a current channel in a pixel driving circuit in the related art;

[0032] FIG5 is a schematic diagram of a power signal design when micro LEDs are arranged in the manner shown in FIG1 in the related art;

[0033] FIG6 is a schematic diagram of one power signal design when multiple micro LEDs share a common VSS in the exemplary embodiment shown in FIG5 ;

[0034] FIG7 is a schematic diagram of a layout structure based on the same power signal design concept as FIG5 and FIG6;

[0035] FIG8 is a partially enlarged version of FIG7 in which the third metal pattern is not shown;

[0036] FIG9 is an enlarged view of the first connection point and the second connection point of the third metal pattern shown in FIG7;

[0037] FIG10 is a schematic diagram of a top view of a display substrate provided in an embodiment of the present disclosure;

[0038] FIG11 is a schematic diagram showing a design of a power supply signal for any light-emitting pixel in FIG10 ;

[0039] FIG12 is a schematic cross-sectional view of one embodiment of the structure of FIG11 ;

[0040] FIG13 is a schematic diagram showing one design of a power supply signal for any light-emitting pixel in FIG10 ;

[0041] FIG14 is a schematic diagram of a cross-sectional structure of FIG13;

[0042] Figure 15 is a simplified diagram corresponding to Figure 13;

[0043] Figure 16 is the complete layout corresponding to Figure 13;

[0044] FIG17 is a schematic diagram of a partial structure of FIG16;

[0045] FIG18 is a layout diagram of the fourth metal layer in FIG16 ;

[0046] FIG19 is a layout after the third node is set based on FIG18;

[0047] FIG20 is a layout diagram after the second metal layer is completed based on FIG19;

[0048] FIG21 is a layout after the first node and the second node are set based on FIG20;

[0049] FIG22 is a layout diagram after the third metal layer is set based on FIG21;

[0050] FIG23 is a layout of the third metal layer in FIG22;

[0051] FIG24 is a window diagram of PVX2 on the third metal layer in FIG23;

[0052] FIG25 is a schematic diagram showing one design of signal lines in a peripheral area of ​​a display substrate provided by an embodiment of the present disclosure;

[0053] FIG26 is a schematic diagram showing one design of signal lines in a peripheral area of ​​a display substrate provided by an embodiment of the present disclosure;

[0054] FIG27 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure, wherein a peripheral area of ​​the display substrate is formed of a signal line with a hollow pattern and a third metal layer;

[0055] FIG28 is a schematic diagram showing one design of corresponding positions of the first portion and the second portion of the peripheral region of a display substrate provided by an embodiment of the present disclosure;

[0056] FIG29 is a schematic diagram showing one design of corresponding positions of a first portion and a second portion of a peripheral region of a display substrate provided by an embodiment of the present disclosure;

[0057] FIG. 30 is a schematic diagram showing one design of corresponding positions of the first portion and the second portion in the peripheral area of ​​FIG. 26 . DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0060] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0061] In related art, as shown in Figures 1 and 2 , when micro LEDs are used for active drive displays, the three colors of micro LEDs 01 (R, G, and B) can be arranged vertically within a pixel, as shown in Figure 1 , or horizontally, as shown in Figure 2 . It should be noted that in the arrangement shown in Figure 1 , the long axis of micro LED 01 is perpendicular to the long axis of sub-pixel 02; in the arrangement shown in Figure 2 , the long axis of micro LED 01 is parallel to the long axis of sub-pixel 02. The long axis directions of sub-pixel 02 and micro LED 01 are explained in conjunction with Figures 3a and 3b . In the exemplary embodiment shown in Figure 3a , the direction parallel to the long axis of sub-pixel 02 is indicated by arrow x; in the exemplary embodiment shown in Figure 3b , the direction parallel to the long axis of micro LED 01 is indicated by arrow y.

[0062] In specific implementations, to ensure the display performance of a micro LED 01 display product, it is typically necessary to drive and control the corresponding micro LED 01 through a pixel driver circuit. Figure 4 shows a typical circuit for the current path in the pixel driver circuit. This circuit includes at least a drive control transistor M1, and emission control transistors M2 and M3. The emission control transistor M2 is turned on by control terminal S1, and the emission control transistor M3 is turned on by control terminal S2. Furthermore, the circuit also includes the light-emitting device micro LED 01 and corresponding power supply signals VDD and VSS. The pixel circuit output point 03 is connected to the anode 09 of the micro LED 01, and reference numeral 010 represents the cathode of the micro LED 01.

[0063] To achieve higher screen brightness uniformity, power signal lines in micro LED displays, such as those used to transmit VDD signals (simplified as VDD signal lines for ease of description), typically utilize two layers of metal, distributed in a mesh pattern. To enable external power signals to be loaded into pixels, when micro LEDs 01 are arranged as shown in Figure 1 and the power signal is designed as shown in Figure 5, each pixel includes three sub-pixels 02, namely SP-1, SP-2, and SP-3. The pixel circuit output point 03 within each sub-pixel 02 is relatively uniform within the sub-pixel 02. However, multiple micro LEDs 01 are relatively positioned within a specific sub-pixel 02. Connections between each pixel circuit output point 03 and the corresponding micro LED 01 anode 09 require multiple wiring changes, and multiple first connection points 04 exist. This complex and diverse connection method is also known to occur. The wiring between the pixel circuit output point 03 and the corresponding anode 09 consumes significant power and results in voltage drop. Furthermore, the excessive number of wiring and vias between the two is detrimental to achieving high pixel density.

[0064] Still referring to the exemplary embodiment shown in Figure 5 , the first connection point 04 is used to achieve electrical continuity between the first metal 06 and the second metal 07, and the second connection point 05 is used to achieve electrical continuity between the second metal 07 and the third metal 08. It should be noted that the first metal 06, the second metal 07, and the third metal 08 are arranged in sequence away from the substrate. Furthermore, in a specific implementation, the second connection point 05 includes a first-type second connection point 051 and a second-type second connection point 052. For the VDD signal line, the first-type second connection point 051 is used to achieve electrical continuity between the VDD signal line formed by the third metal 08 and the VDD signal line formed by the second metal 07; the second-type second connection point 052 is used to achieve electrical continuity between the second metal 07 and the third metal 08 at the anode 09 of the micro LED 01. In the exemplary embodiment shown in Figure 5 , multiple micro LEDs 01 can share a signal line for transmitting the VSS signal (simplified as the VSS signal line for ease of description). Accordingly, a schematic diagram of the power supply signal design is shown in Figure 6 .

[0065] Still referring to the exemplary embodiment shown in FIG6 , a VSS signal line formed using the third metal 08 runs through the pixel along the long axis of the sub-pixel 02, and a VDD signal line formed using the third metal 08 also runs through the pixel along the long axis of the sub-pixel 02. In this case, the VDD signal line and the VSS signal line formed using the third metal 08 are generally concentrated above a certain sub-pixel 02, but not all sub-pixels 02, within the pixel. For example, the VDD signal line formed using the third metal 08 is concentrated above the sub-pixel 02 (SP-1), and the VSS signal line formed using the third metal 08 is concentrated above the sub-pixels 02 (SP-2 and SP-3). When the VDD signal lines form a mesh structure using the first metal 06 and the third metal 08, except for the sub-pixel 02 (SP-1) where the VDD signal line formed using the third metal 08 is concentrated, the VDD power supply signals within the other sub-pixels 02 (SP-2 and SP-3) can only be arranged using the first metal 06 and the second metal 07. Since the resistance of the first metal 06 and the second metal 07 is generally relatively large, there is a lot of power loss and voltage drop within them.

[0066] Continuing with the exemplary embodiments shown in Figures 5 and 6, Figure 7 shows a schematic diagram of a layout structure based on the same power signal design concept. Still referring to Figure 7, the first connection point 04 is covered by the third metal 08. Figure 8 is an enlarged portion of the layout diagram based on Figure 7, excluding the third metal 08 pattern. First connection point 04 enables electrical conduction between first metal 06 and second metal 07. In Figure 8, the arrow indicates that second metal 07 is connected to pixel circuit output point 03. Figure 9 is an enlarged layout diagram based on the third metal 08 pattern shown in Figure 7, showing the first connection point 04 and second connection point 05. In the exemplary embodiment shown in Figure 9, there are at least two first connection points 04 and one second connection point 05 between the anode 09 of micro LED 01 and the pixel circuit output point 03. It should be noted that in the exemplary embodiment shown in Figure 6, the three RGB micro LEDs 01 share the third metal 08 VSS signal line; in the exemplary embodiment shown in Figure 7, there are two third metal 08 VSS signal lines, namely VSS1 and VSS2.

[0067] In the exemplary embodiment shown in Figure 6, when the long axis of micro LED 01 is perpendicular to the long axis of sub-pixel 02, to enable external power signals to be loaded into the pixel, the VDD signal line formed by the third metal 08 needs to be transferred through the horizontally arranged VDD signal line formed by the first metal 06, and ultimately connected to the VDD signal line formed by the second metal 07 within each sub-pixel 02. As a result, the current used to transmit the VDD signal flows through the third metal 08, the second metal 07, and the first metal 06. Moreover, the VDD signal formed by the third metal 08 is mainly concentrated above one sub-pixel 02 (i.e., SP-1). For the other two sub-pixels 02 (SP-2 and SP-3), the current transmission path is longer, resulting in higher wiring power consumption. Furthermore, when the arrangement of micro LEDs 01 shown in FIG1 is employed, multiple micro LEDs 01 are relatively concentrated within a specific sub-pixel 02 (i.e., SP-2). Consequently, the wiring between the pixel circuit output point 03 of each sub-pixel 02 and the anode 09 of the corresponding micro LED 01 undergoes multiple changes, resulting in a complex conduction method that is not conducive to achieving a higher pixel density.

[0068] In view of this, embodiments of the present disclosure provide a display substrate and a display device for achieving a higher pixel density while taking into account a low-power design for wiring.

[0069] As shown in Figures 10 and 11, Figure 10 is a schematic diagram of a top view of a display substrate provided in an embodiment of the present disclosure, and Figure 11 is a schematic diagram of a design of a power supply signal for any light-emitting pixel 20 in Figure 10. Specifically, the display substrate provided in an embodiment of the present disclosure includes:

[0070] A substrate 10 and a plurality of light-emitting pixels 20 located on the substrate 10;

[0071] Among them, each of the light-emitting pixels 20 includes multiple light-emitting sub-pixels 200; each of the light-emitting sub-pixels 200 includes a micro-light-emitting device 201 located in a corresponding area and a pixel driving circuit 202 coupled to the micro-light-emitting device 201 through a circuit output point N; within the same light-emitting sub-pixel 200, the circuit output point N and the micro-light-emitting device 201 are projected orthographically on the substrate 10, completely falling within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel 20 on the substrate 10.

[0072] In a specific implementation, the display substrate includes a base 10 and a plurality of light-emitting pixels 20 located on the base 10. For example, the base 10 can be a rigid substrate or a flexible substrate, which is not limited here. For example, when the base 10 is a flexible substrate, the material of the flexible substrate can be polyimide film (PI) or polyethylene terephthalate (PET), etc., which is not limited here. The flexible substrate can have a structure including a single flexible base layer or a structure including multiple flexible base layers, such as a structure with two flexible base layers or a structure with three flexible base layers, which is not limited here. In addition, a support layer can be provided between two adjacent flexible base layers. Of course, the base 10 can also be provided according to actual application requirements, which is not limited here. In addition, the plurality of light-emitting pixels 20 located on the base 10 can be arranged in an array, wherein the specific number and specific arrangement of the plurality of light-emitting pixels 20 can be set according to actual application requirements and are not limited here.

[0073] Moreover, each luminous pixel 20 includes a plurality of luminous sub-pixels 200. Among them, the plurality of luminous sub-pixels 200 can be of the same color, or can include a plurality of different colors. Exemplarily, each luminous pixel 20 includes a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B), thereby ensuring the color display of the display substrate. Of course, the composition form of a single luminous pixel 20 can also be set according to actual application needs, which is not limited here. Each luminous sub-pixel 200 includes a micro-luminous device 201 located in the corresponding area and a pixel driving circuit 202 coupled to the micro-luminous device 201 through a circuit output point N (not shown in Figure 11). Exemplarily, the micro-luminous device 201 can be a Micro LED or a Mini LED, which is not limited here. It should be noted that not all luminous pixels 20 are shown in the figure.

[0074] Furthermore, within the same light-emitting sub-pixel 200, the orthographic projections of the circuit output point N and the micro-light-emitting device 201 on the substrate 10 completely fall within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10. This allows for effective connection between the pixel driver circuit 202 and the micro-light-emitting device 201, using fewer wires and vias, between the circuit output point N and the micro-light-emitting device 201 corresponding to each light-emitting sub-pixel 200. This simplifies the overall connection method, which can be made substantially the same, while reducing power consumption and ensuring a higher pixel density.

[0075] During the specific implementation process, within the same luminous pixel 20, the positions of the circuit output points corresponding to each luminous sub-pixel 200 within the corresponding luminous sub-pixel 200 can be set to be approximately the same, and each micro-luminous device 201 can also be evenly distributed within each luminous sub-pixel 200. In this way, it provides a guarantee for the subsequent simplification of the connection method between the pixel driving circuit 202 and the micro-luminous device 201.

[0076] It should be noted that the pixel driving circuit 202 can be any of a variety of forms, such as low-temperature polysilicon (LTPS), oxide, or low-temperature polycrystalline silicon oxide (LTPO). Of course, the specific structure of the pixel driving circuit 202 can also be set according to actual application needs and is not limited here. In the embodiment of the present disclosure, the display substrate also includes a first high-potential trace 61 (i.e., VDD made of the third metal layer) extending perpendicular to the long axis of each of the light-emitting sub-pixels 200, and a plurality of second high-potential traces 51 (i.e., VDD made of the second metal layer) extending parallel to the long axis of each of the light-emitting sub-pixels 200. Each of the second high-potential traces 51 is coupled to the first high-potential trace 61 via a corresponding first node n1 (i.e., a first-type second connection point 051), and the orthographic projection of the first node n1 on the substrate 10 completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10.

[0077] Still referring to the exemplary embodiment shown in FIG11 , the display panel further includes a first high-potential trace 61 and a plurality of second high-potential traces 51 , wherein the first high-potential trace 61 extends perpendicular to the long axis of each light-emitting sub-pixel 200 , and each second high-potential trace 51 extends parallel to the long axis of each light-emitting sub-pixel 200 . In practical applications, the first high-potential trace 61 and each second high-potential trace 51 can transmit the same high-potential signal (e.g., a VDD signal). Moreover, each second high-potential trace 51 is coupled to the first high-potential trace 61 via a corresponding first node n1 , thereby ensuring the effectiveness of high-potential signal transmission. In addition, the orthographic projection of each first node n1 on the substrate 10 completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10 . In this way, an effective connection between the first node n1 corresponding to each light-emitting sub-pixel 200 and the micro-light-emitting device 201 can be achieved through fewer wires and vias; the entire connection method is relatively simple, and each first node n1 can be set at approximately the same position of the corresponding light-emitting sub-pixel 200, and the corresponding connection method can be approximately the same. In this way, while reducing power consumption, it provides a guarantee for a higher pixel density.

[0078] It should be noted that the length direction of the pattern in the plan view corresponding to the light-emitting sub-pixel 200 can be regarded as the long axis direction of the light-emitting sub-pixel 200, and accordingly, the width direction of the pattern in the plan view corresponding to the light-emitting sub-pixel 200 can be regarded as the short axis direction of the light-emitting sub-pixel 200. The length direction of the micro-light-emitting device 201 in the plan view corresponding to the pattern can also be regarded as the long axis direction of the micro-light-emitting device 201, and accordingly, the width direction of the pattern in the plan view corresponding to the micro-light-emitting device 201 can be regarded as the short axis direction of the micro-light-emitting device 201.

[0079] In the embodiment of the present disclosure, within the same light-emitting sub-pixel 200, the display substrate further includes a first overlap portion 203 and a second overlap portion 204, the pixel driving circuit 202 is coupled to one end of the first overlap portion 203 through the circuit output point N, and the other end of the first overlap portion 203 is coupled to the anode 205 of the corresponding micro-light-emitting device 201 through the second node n2 and the second overlap portion 204; the orthographic projection of the second node n2 on the substrate 10 completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10.

[0080] Still referring to the exemplary embodiment shown in Figure 11, within the same light-emitting sub-pixel 200, the display substrate further includes a first overlapping portion 203 and a second overlapping portion 204. The pixel driving circuit 202 is coupled to one end of the first overlapping portion 203 via a circuit output point N, and the other end of the first overlapping portion 203 is coupled to the anode 205 of the corresponding micro-light-emitting device 201 via a second node n2 and the second overlapping portion 204. This ensures that the pixel driving circuit 202 effectively drives the micro-light-emitting device 201. For example, the first overlapping portion 203 can be provided on the same layer and material as the second high-potential trace 51, and the second overlapping portion 204 can be provided on the same layer and material as the first high-potential trace 61. Furthermore, the orthographic projection of the second node n2 on the substrate 10 completely falls within the orthographic projection area of ​​the corresponding light-emitting sub-pixel 200 on the substrate 10. In this way, within the same light-emitting pixel 20, an effective connection between the pixel driving circuit 202 and the anode 205 of the micro-light-emitting device 201 can be achieved through fewer leads and vias between the second node n2 corresponding to each light-emitting sub-pixel 200 and the anode 205 of the micro-light-emitting device 201; the second node n2 corresponding to each light-emitting sub-pixel 200 and the anode 205 of the micro-light-emitting device 201 can also be set at approximately the same position. The entire connection method is relatively simple, and the connection method can be made approximately the same, thereby reducing power consumption while providing a guarantee for a higher pixel density.

[0081] In the embodiment of the present disclosure, the pixel driving circuit 202 includes an active layer 30, a first metal layer 40, a second metal layer 50 and a third metal layer 60, which are arranged in sequence away from the substrate 10; the first high-potential wiring 61 and the second overlapping portion 204 are both arranged in the same layer and material as the third metal layer 60, and the second high-potential wiring 51 and the first overlapping portion 203 are both arranged in the same layer and material as the second metal layer 50.

[0082] Continuing with the exemplary embodiment shown in FIG11 , FIG12 is a schematic cross-sectional view of one embodiment of the structure of FIG11 , omitting the micro-luminescent device 201. Specifically, the pixel driving circuit 202 includes an active layer 30, a first metal layer 40, a second metal layer 50, and a third metal layer 60, disposed sequentially away from the substrate 10. For example, the material of the first metal layer 40 may be Mo; the material of the second metal layer 50 may be an alloy material containing aluminum with a relatively low resistivity, or a laminated metal containing aluminum, such as titanium-aluminum-titanium; and the material of the third metal layer 60 may be Cu. Of course, the materials of the first metal layer 40, the second metal layer 50, and the third metal layer 60 may also be selected based on actual application needs, and are not limited here. Furthermore, the first high-potential trace 61 and the second overlapping portion 204 are both provided on the same layer and made of the same material as the third metal layer 60, and the second high-potential trace 51 and the first overlapping portion 203 are both provided on the same layer and made of the same material as the second metal layer 50. In the actual manufacturing process, the third metal layer 60 can be used to form the first high-potential trace 61 and the second overlapping portion 204, and the second metal layer 50 can also be used to form the second high-potential trace 51 and the first overlapping portion 203, thereby improving the manufacturing efficiency of the display substrate. It should be noted that in the exemplary embodiment shown in Figure 12, the specific arrangement of the active layer 30, the first metal layer 40, the second metal layer 50, and the third metal layer 60, as well as other film layer structures, can be referred to the description of the relevant parts below and will not be described in detail here.

[0083] In the embodiment of the present disclosure, the display substrate also includes a low-potential trace 206 extending along a direction perpendicular to the long axis of each of the light-emitting sub-pixels 200; the low-potential trace 206 is arranged in the same layer and material as the third metal layer 60, and the low-potential trace 206 is respectively coupled to the cathode 207 of each of the micro-light-emitting devices 201 in the light-emitting pixel 20.

[0084] Still referring to the exemplary embodiment shown in FIG11 , the display substrate further includes a low-potential trace 206 extending perpendicularly to the long axis of each light-emitting sub-pixel 200. Exemplarily, the low-potential trace 206 is used to transmit a low-potential signal (e.g., a VSS signal). Furthermore, the low-potential trace 206 is provided on the same layer and made of the same material as the third metal layer 60. This means that the third metal layer 60 can be used to fabricate the low-potential trace 206, thereby improving the efficiency of fabricating the low-potential trace. Furthermore, the low-potential trace 206 is coupled to the cathode 207 of each micro-light-emitting device 201 in the light-emitting pixel 20. In this way, each micro-light-emitting device 201 can share the low-potential trace 204, thereby reducing the number of traces required and lowering trace power consumption. Thus, within each light-emitting pixel 20, the low-potential trace 206 can extend through each light-emitting sub-pixel 200 perpendicularly to its long axis. For the low-potential wiring 204, current can easily flow through each light-emitting sub-pixel 200, the entire current propagation path is shorter, the required wiring and the number of vias opened are smaller, a higher pixel density can be achieved, and the power consumption of the signal line is significantly reduced.

[0085] In the embodiment of the present disclosure, the display substrate also includes a third high potential trace 71 extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels 200; the orthographic projection of the third high potential trace 71 on the substrate 10 completely falls within the area of ​​the orthographic projection of the first high potential trace 61 on the substrate 10, and the third high potential trace 71 is coupled to the corresponding second high potential trace 51 through a third node n3, and the orthographic projection of the third node n3 on the substrate 10 completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10.

[0086] In one of the exemplary embodiments, as shown in FIG13 , there is shown a schematic diagram of one design of the power supply signal of the luminescent pixel 20 in the embodiment of the present disclosure. Specifically, the wiring used to transmit high-potential signals (e.g., VDD signals) in the display substrate includes not only a first high-potential wiring 61 and a second high-potential wiring 51, but also a third high-potential wiring 71, which is arranged to extend in a direction perpendicular to the long axis of each luminescent sub-pixel 200. In this way, within each luminescent pixel 20, the third high-potential wiring 71 can pass through each luminescent sub-pixel 200 in a direction perpendicular to the long axis of each luminescent sub-pixel 200. For high-potential signals, the current propagation path is increased, the voltage drop is reduced, and thus the wiring power consumption is reduced. In addition, the storage capacitor is also taken into account.

[0087] Furthermore, the orthographic projection of the third high-potential trace 71 on the substrate 10 completely falls within the orthographic projection of the first high-potential trace 61 on the substrate 10, facilitating conduction and connection between the third high-potential trace 71 and the first high-potential trace 61. The third high-potential trace 71 is coupled to the corresponding second high-potential trace 51 via the third node n3, and the orthographic projection of the third node n3 on the substrate 10 completely falls within the orthographic projection of the corresponding light-emitting sub-pixel 200 on the substrate 10. In this way, within the same light-emitting sub-pixel 200, effective connection between the third node n3 corresponding to each light-emitting sub-pixel 200 and the micro-light-emitting device 201 can be achieved using fewer wires and vias. Furthermore, the third node n3 corresponding to each light-emitting sub-pixel 200 can be positioned at substantially the same location, simplifying the overall connection method and ensuring a substantially consistent connection method. This reduces power consumption while ensuring a higher pixel density. It should be noted that, in the exemplary embodiment shown in FIG. 13 , the third node n3 may be a connection point where the third high potential trace 71 formed by the fourth metal layer 70 is electrically connected to the second high potential trace 51 formed by the second metal layer 50 .

[0088] In the embodiment of the present disclosure, the display substrate further includes a fourth metal layer 70 located between the first metal layer 40 and the second metal layer 50 , and the third high potential trace 71 is provided in the same layer and made of the same material as the fourth metal layer 70 .

[0089] Still referring to the exemplary embodiment shown in Figure 13 , Figure 14 is a schematic cross-sectional view of one embodiment of the structure of Figure 13 . Specifically, the display substrate further includes a fourth metal layer 70 positioned between the first metal layer 40 and the second metal layer 50 . Accordingly, the first metal layer 40, the fourth metal layer 70, the second metal layer 50, and the third metal layer 60 are sequentially arranged away from the substrate 10 . In the actual fabrication process, the third high-potential trace 71 can be provided in the same layer and material as the fourth metal layer 70 , thereby improving the fabrication efficiency of the third high-potential trace 71 .

[0090] In the embodiment of the present disclosure, in each of the light-emitting pixels 20, the long axis direction of each of the micro-light-emitting devices 201 is parallel to the long axis direction of each of the light-emitting sub-pixels 200, and each of the micro-light-emitting devices 201 is extended along a direction perpendicular to the long axis direction of each of the light-emitting sub-pixels 200.

[0091] Still referring to the exemplary embodiments shown in Figures 11 and 13 , within each luminescent pixel 20, the long axis direction of each micro-light-emitting device 201 is parallel to the long axis direction of each luminescent sub-pixel 200, and each micro-light-emitting device 201 extends perpendicular to the long axis direction of each luminescent sub-pixel 200. Accordingly, within each luminescent pixel 20, the micro-light-emitting devices 201 can be arranged as shown in Figure 2 . In actual applications, within each luminescent pixel 20, the micro-light-emitting devices 201 are evenly distributed within each luminescent sub-pixel 200, and there is only one micro-light-emitting device 201 in each luminescent sub-pixel 200. In this way, in the subsequent process, only one metal (exemplarily, the second metal layer 50) is required between each circuit output point N and the anode of the corresponding micro-light-emitting device 201, and the first metal layer 40 and the first connection point 04 are not required. The entire connection method is relatively simple and the connection method is relatively consistent. The lead power consumption and voltage reduction between the circuit output point N and the anode 205 of the corresponding micro-light-emitting device 201 are relatively small, which is conducive to achieving a higher pixel density.

[0092] It should be noted that in the aforementioned schematic diagram of the related power signal design, all signal lines except the first high-potential trace 61 and the low-potential trace 204 prepared using the third metal layer 60 are drawn using lines. In reality, all signal lines have a certain width in space. FIG15 shows a simplified version corresponding to FIG13 , and FIG16 shows a complete version corresponding to FIG13 . Still referring to the exemplary embodiment shown in FIG16 , only the second metal layer 50 exists between the circuit output point N and the corresponding anode 205, and the connection method is relatively simple. FIG17 shows a schematic diagram of the partial structure in FIG16 , in which the third high-potential trace 71 is connected to the corresponding second high-potential trace 51 via the third node n3, and the second high-potential trace 51 is connected to the first high-potential trace 61 via the first node n1. Moreover, the third high-potential trace 71 is entirely located at the bottom of the first high-potential trace 61.

[0093] Still referring to the exemplary embodiment shown in FIG16 , FIG18 shows the layout of the fourth metal layer 70, FIG19 shows the layout after the third node n3 is completed, FIG20 shows the layout after the second metal layer 50 is completed, FIG21 shows the layout after the first node n1 and the second node n2 are completed, FIG22 shows the layout after the third metal layer 60 is completed, FIG23 shows the layout of the third metal layer 60, and FIG24 shows a window diagram of PVX2 on the third metal layer 60, wherein the reference numeral Q indicates the window position on PVX2. It should be noted that there is no film material for preparing PVX2 at the window position of PVX2. For the specific structural setting of PVX2, please refer to the description of the relevant part below and will not be described in detail here.

[0094] Still combining with the exemplary embodiment shown in Figure 14, the display substrate further includes a planar layer 80 and a first passivation layer 90 arranged between the second metal layer 50 and the third metal layer 60, and a second passivation layer 91 arranged on the side of the third metal layer 60 away from the substrate 10; the planar layer 80, the first passivation layer 90 and the second passivation layer 91 are arranged away from the substrate 10 in sequence; and a plurality of exhaust holes 92 are opened along the thickness direction of the first passivation layer 90 and the second passivation layer 91.

[0095] For example, the first passivation layer 90 may be PVX1, and the second passivation layer 91 may be PVX2. The material of the first passivation layer 90 and the second passivation layer 91 may be at least one of SiOx and SiNx. Of course, the materials of the first passivation layer 90 and the second passivation layer 91 may also be set according to actual application needs, and are not limited here.

[0096] In a specific implementation, the third metal layer 60 can be made of copper, a metal with a low sheet resistance, thereby reducing the voltage drop of the power signal. In the actual preparation process of the driver backplane of the display substrate, in order to ensure the performance of the driver backplane, a post-baking process (hard bake) is required after the driver backplane is completed. This process has a high temperature, and the organic materials corresponding to the planarization layer 80 may emit gases during the post-baking process. However, the inorganic materials corresponding to the first passivation layer 90 and the second passivation layer 91 on top of the planarization layer 80, as well as the related metal film layers, are often relatively dense, which is not conducive to the emission of gases.

[0097] In the disclosed embodiment, multiple vent holes 92 are provided along the thickness direction of the first passivation layer 90 and the second passivation layer 91 to effectively exhaust gas, thereby ensuring the performance of the display substrate. Of course, the specific number of vent holes 92 can be set according to actual application needs and is not limited here.

[0098] It should be noted that, in addition to the relevant film layers mentioned above, other film layer structures may also be provided in the embodiments of the present disclosure. For example, still in combination with Figures 12 and 14, the display substrate further includes a buffer layer 93 provided between the base 10 and the active layer 30, a first gate insulating layer 94 provided between the first metal layer 40 and the active layer 30, a second gate insulating layer 95 provided between the first metal layer 40 and the fourth metal layer 70, and an interlayer insulating layer 96 provided between the fourth metal layer 70 and the second metal layer 50. Of course, other film layer structures may also be provided according to actual application needs, which is not limited here.

[0099] In the embodiment of the present disclosure, the exhaust hole 92 may be provided according to the following implementation manner, but is not limited thereto.

[0100] In one exemplary embodiment, in the display area A, the orthographic projection of each of the exhaust holes 92 on the substrate 10 and the orthographic projection of the third metal layer 60 on the substrate 10 do not overlap with each other.

[0101] Still referring to Figures 15, 16, 17, and 24, in the display area A of the display substrate, the orthographic projections of the exhaust holes 92 on the substrate 10 do not overlap with the orthographic projections of the third metal layer 60 on the substrate 10. For example, within each light-emitting sub-pixel 200, the exhaust holes 92 are typically located in the gaps of the third metal layer 60, while the third metal layer 60 is not hollowed out, thereby improving the uniformity of the panel's brightness.

[0102] In one exemplary embodiment, in the display area A, the arrangement period of the plurality of exhaust holes 92 is the same as the arrangement period of the plurality of light-emitting sub-pixels 200 .

[0103] Still referring to Figures 15, 16, 17, and 24, within display area A, the arrangement period of the multiple exhaust holes 92 is roughly the same as the arrangement period of the multiple light-emitting sub-pixels 200. For example, one exhaust hole 92 is provided within each sub-pixel, and the arrangement period of the multiple exhaust holes 92 in the display substrate is the same as the arrangement period of the corresponding multiple light-emitting sub-pixels 200. For another example, one exhaust hole 92 is provided within each light-emitting pixel 20, and the arrangement period of the multiple exhaust holes 92 in the display substrate is the same as the arrangement period of the corresponding multiple light-emitting pixels 20. In this way, the exhaust consistency of the display substrate is ensured, and the performance of the display substrate is improved.

[0104] In the embodiment of the present disclosure, as shown in conjunction with FIG. 25 and FIG. 26 , the display substrate includes a display area A and a peripheral area B disposed around the display area A. In the peripheral area B, the display substrate further includes a first lead 97 and a second lead 98. The first lead 97 includes a first portion 99 extending parallel to the long axis of the light-emitting sub-pixel 200, and the second lead 98 includes a second portion 100 extending parallel to the long axis of the light-emitting sub-pixel 200. The first portion 99 is coupled to the first high-potential trace 61, and the second portion 100 is coupled to the low-potential trace 206. The first portion 99 is configured to receive a signal from the first constant power supply terminal 101, and the second portion 100 is configured to receive a signal from the second constant power supply terminal 102. For example, the direction indicated by arrow X in the figure is parallel to the long axis of the light-emitting sub-pixel 200, and the direction indicated by arrow Y is perpendicular to the long axis of the light-emitting sub-pixel 200. Among them, the first constant power supply terminal 101 can be a constant power supply terminal for providing a high-potential signal, and the second constant power supply terminal 102 can be a constant power supply terminal for providing a low-potential signal. The specific values ​​of the high-potential signal and the low-potential signal can be set according to actual application needs and are not limited here.

[0105] It should be noted that, unless otherwise specified, the direction indicated by arrow X in the figures is parallel to the long axis of the light-emitting sub-pixel 200, and the direction indicated by arrow Y is perpendicular to the long axis of the light-emitting sub-pixel 200. In the disclosed embodiment, since the first high-potential trace 61 and the low-potential trace 206 formed by the third metal layer 60 extend in a direction perpendicular to the long axis of the light-emitting sub-pixel 200, VDD leads and VSS leads parallel to the long axis of the light-emitting sub-pixel 200 can be provided on the left and right sides of the periphery of the display area A (i.e., the peripheral area B), respectively. The first high-potential trace 61 perpendicular to the long axis of the light-emitting sub-pixel 200 can be connected together in multiple rows of light-emitting sub-pixels 200 via the VDD leads, and the low-potential trace 206 perpendicular to the long axis of the light-emitting sub-pixel 200 can be connected together in multiple rows of light-emitting sub-pixels 200 via the VSS leads.

[0106] Still referring to FIG. 25 and FIG. 26 , on the same side of the display substrate, the second portion 100 is disposed on a side of the first portion 99 facing away from the display area A.

[0107] For example, for a P-type driver backplane in a display substrate, the first constant power supply terminal 101 corresponding to the first high-potential trace 61 can be used as the common terminal of the pixel driver circuit 202. On the same side of the display substrate, the second portion 100 corresponding to the second lead 98 is disposed on the side of the first portion 99 corresponding to the first lead 97 facing away from the display area A. Correspondingly, the first portion 99 is disposed on the side of the second portion 100 closer to the display area A. In this way, in actual manufacturing, the layer switching of the first high-potential trace 61 can be minimized, thereby ensuring VDD voltage uniformity at all locations and improving the performance of the display substrate.

[0108] In one exemplary embodiment, along a direction parallel to the short axis of each light-emitting sub-pixel 200, the extension lengths of the first portion 99 and the second portion 100 are both greater than the extension length of the light-emitting sub-pixel 200. In a specific implementation, for a large-sized backplane, along a direction parallel to the short axis of each light-emitting sub-pixel 200, the extension lengths of the first portion 99 and the second portion 100 can be set to be greater than the extension length of the light-emitting sub-pixel 200, thereby achieving higher brightness uniformity and reducing signal line power consumption. The specific extension lengths of the first portion 99 and the second portion 100, as well as the specific extension lengths of the light-emitting sub-pixel 200, can be set according to actual application needs and are not limited here.

[0109] It should be noted that in the exemplary embodiment shown in FIG25 , relevant signal lines prepared by the second metal layer 50 can be provided; exemplarily, the display substrate further includes a shift register located in the peripheral area B (not shown in the figure), which is used to ensure the clock signal (e.g., ECK signal, ECB signal) of the shift register, the high-voltage signal VGH, the low-voltage signal VGL and other related signal lines corresponding to the clock signal (e.g., ECK signal, ECB signal) of the shift register. In order to reduce the coupling between the signal lines prepared by the second metal layer 50 and the signal lines prepared by the third metal layer 60, and to avoid the breakdown between different signals due to the large voltage difference between the two metal layers, thereby causing the failure of the relevant circuits of the display substrate. In the specific implementation process, when the signal lines prepared by the second metal layer 50 and the signal lines prepared by the third metal layer 60 with different functions overlap in the projection direction of the display substrate, in addition to the first passivation layer 90, a flat layer 80 is also provided between the two metal layers. The relevant settings can be shown in FIG14 .

[0110] In the embodiment of the present disclosure, the exhaust holes 92 in the peripheral area B may be designed according to the following embodiments, but are not limited thereto.

[0111] In one exemplary embodiment, when a flat layer 80 is present in the peripheral area B of the display substrate, it is necessary to provide vent holes 92 on the first passivation layer 90, the second passivation layer 91, and the third metal layer 60 on top of the flat layer 80. FIG27 is a schematic diagram of a structure in which a signal line prepared by the third metal layer 60 has a hollow pattern. When a hollow pattern design is adopted on part of the signal line prepared by the third metal layer 60, and the hollow pattern period is small, the resistance of the corresponding signal line will be significantly increased, and the power consumption on the signal line will increase. In addition, the voltage drop on the signal line will also increase, which is not conducive to achieving high brightness uniformity. To this end, in the specific implementation process, the flat layer 80 below the part of the signal line prepared by the third metal layer 60 can be removed. In this case, there is no need to perform a hollowing process on the signal line, and accordingly, there is no need to open a corresponding vent hole 92 on the signal line.

[0112] In one exemplary embodiment, a flat layer 80 is arranged between the first part 99 and the substrate 10, and the orthographic projection of the second part 100 on the substrate 10 does not overlap with the orthographic projection of the flat layer 80 on the substrate 10. The orthographic projection of the first part 99 on the substrate 10 completely falls within the area of ​​the orthographic projection of the flat layer 80 on the substrate 10. The first part 99 is provided with at least one hollow structure 103, and the inorganic layer located on the side of the flat layer 80 facing away from the substrate 10 is provided with an exhaust hole 92 corresponding to the at least one hollow structure 103.

[0113] Still referring to the exemplary embodiment shown in FIG. 25 , in peripheral area B, the flat layer 80 beneath the second lead 98 formed from the third metal layer 60 can be removed. Accordingly, there is no need to hollow out the second lead 98. In other words, there is no need to provide the corresponding vent holes 92 at the locations corresponding to the second lead 98. This reduces power loss on the signal lines corresponding to the second lead 98, improves brightness uniformity across the display substrate, and thus enhances the reliability of the display substrate.

[0114] As shown in FIG28 , the second lead 98 located on the outermost side of the display substrate has no hollow design above it. A flat layer 80 is provided between the first portion 99 and the substrate 10. At least one hollow structure 103 is provided on the first portion 99 corresponding to the first lead 97. Correspondingly, the first passivation layer 90 and the second passivation layer 91 located on the side of the flat layer 80 facing away from the substrate 10 are provided with vents 92 corresponding to the at least one hollow structure 103. The specific number and arrangement of the at least one hollow structure 103 can be set according to actual application needs and are not limited here. It should be noted that in the exemplary embodiment shown in FIG28 , the VSS signal line formed by the second metal layer 50 passes under the VDD signal line formed by the third metal layer 60, and the VSS signal line formed by the second metal layer 50 and the VSS signal line formed by the third metal layer 60 are electrically connected through the second connection point (i.e., the conduction point between the second metal layer 50 and the third metal layer 60).

[0115] As shown in FIG. 29 , a planar layer 80 is provided between the first portion 99 and the low potential trace 206 , and in the peripheral region B, the planar layer 80 is only located in the mutually overlapping region of the first portion 99 and the low potential trace 206 .

[0116] Still referring to the exemplary embodiment shown in FIG. 29 , in peripheral region B of the display substrate, planarization layer 80 is retained only above the VSS signal line formed from second metal layer 50 and passing beneath the VDD signal line formed from third metal layer 60. Planarization layer 80 is removed from other areas. In this exemplary embodiment, a hollowing design is not required above the VDD signal line formed from third metal layer 60.

[0117] Still referring to the exemplary embodiment shown in FIG26 , the display substrate further includes a planar layer 80 extending from the display area A to the peripheral area B. The orthographic projections of the first portion 99 and the second portion 100 on the substrate 10 completely fall within the area of ​​the orthographic projection of the planar layer 80 on the substrate 10. Both the first portion 99 and the second portion 100 are provided with at least one hollow structure 103. The inorganic layer located on the side of the planar layer 80 facing away from the substrate 10 is provided with vent holes 92 corresponding to the at least one hollow structure 103. In other words, the exemplary embodiment shown in FIG26 has a larger area for the planar layer 80 than the exemplary embodiment shown in FIG25 . Accordingly, in the peripheral area B, both the first portion 99 and the second portion 100 are provided with at least one hollow structure 103. Consequently, the first passivation layer 90 and the second passivation layer 91 located on the side of the planar layer 80 facing away from the substrate 10 are provided with vent holes 92 corresponding to the at least one hollow structure 103. FIG30 is a schematic diagram showing the arrangement structure of the relevant hollow structure 103 located in the peripheral area B in the exemplary embodiment shown in FIG26 .

[0118] Based on the same disclosed concept, an embodiment of the present disclosure further provides a display device, which includes the display substrate as described in any one of the above items.

[0119] Since the principle of solving the problem of the display device is similar to that of the aforementioned display substrate, the implementation of the display device can refer to the implementation of the aforementioned display substrate, and the repeated parts will not be repeated.

[0120] In specific implementations, the display device provided by the embodiments of the present disclosure can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0121] The embodiments of the present disclosure provide a display substrate and a display device, wherein the display substrate includes a substrate 10 and a plurality of light-emitting pixels 20 located on the substrate 10; each light-emitting pixel 20 includes a plurality of light-emitting sub-pixels 200, for example, each light-emitting pixel 20 includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, thereby ensuring color display of the display substrate; each light-emitting sub-pixel 200 includes a micro-light-emitting device 201 located in a corresponding area and a pixel driving circuit 202 coupled to the micro-light-emitting device 201 via a circuit output point N;

[0122] Furthermore, within the same luminescent pixel 20, the orthographic projections of the circuit output point N and the micro-luminescent device 201 on the substrate 10 completely fall within the orthographic projection area of ​​the corresponding luminescent sub-pixel 20 on the substrate 10. This allows for effective connections between the pixel driver circuit 202 and the micro-luminescent device 201, using fewer wires and vias, between the circuit output point N and the micro-luminescent device 201 corresponding to each luminescent sub-pixel 200. This simplifies the overall connection method, which can be made substantially the same, while reducing power consumption and ensuring a higher pixel density.

[0123] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0124] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display substrate, wherein: include: a substrate and a plurality of light-emitting pixels located on the substrate; Each of the light-emitting pixels includes a plurality of light-emitting sub-pixels; each of the light-emitting sub-pixels includes a micro-light-emitting device located in a corresponding area and a pixel driving circuit coupled to the micro-light-emitting device through a circuit output point; In the same light-emitting sub-pixel, the orthographic projections of the circuit output point and the micro-light-emitting device on the substrate completely fall within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

2. The display substrate according to claim 1, wherein It also includes a first high-potential routing line extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels, and a plurality of second high-potential routing lines extending in a direction parallel to the long axis of each of the light-emitting sub-pixels; each of the second high-potential routing lines is coupled to the first high-potential routing line through a corresponding first node, and the orthographic projection of the first node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

3. The display substrate according to claim 2, wherein: In the same light-emitting sub-pixel, the display substrate further includes a first overlap portion and a second overlap portion, the pixel driving circuit is coupled to one end of the first overlap portion through the circuit output point, and the other end of the first overlap portion is coupled to the anode of the corresponding micro-light-emitting device through a second node and the second overlap portion; the orthographic projection of the second node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

4. The display substrate according to claim 3, wherein: The pixel driving circuit includes an active layer, a first metal layer, a second metal layer and a third metal layer arranged in sequence away from the substrate; the first high-potential wiring and the second overlapping portion are both arranged in the same layer and material as the third metal layer, and the second high-potential wiring and the first overlapping portion are both arranged in the same layer and material as the second metal layer.

5. The display substrate according to claim 4, wherein: It also includes a low-potential trace extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels; the low-potential trace is arranged in the same layer and material as the third metal layer, and the low-potential trace is respectively coupled to the cathode of each of the micro-light-emitting devices in the light-emitting pixels.

6. The display substrate according to claim 5, wherein: It also includes a third high-potential routing extending in a direction perpendicular to the long axis of each of the light-emitting sub-pixels; the orthographic projection of the third high-potential routing on the substrate completely falls within the area of ​​the orthographic projection of the first high-potential routing on the substrate, and the third high-potential routing is coupled to the corresponding second high-potential routing through a third node (i.e., connection point 04), and the orthographic projection of the third node on the substrate completely falls within the area of ​​the orthographic projection of the corresponding light-emitting sub-pixel on the substrate.

7. The display substrate according to claim 6, wherein: It also includes a fourth metal layer located between the first metal layer and the second metal layer, and the third high potential wiring is provided in the same layer and made of the same material as the fourth metal layer.

8. The display substrate according to any one of claims 1 to 7, wherein: In each of the light-emitting pixels, the long axis direction of each of the micro-light-emitting devices is parallel to the long axis direction of each of the light-emitting sub-pixels, and each of the micro-light-emitting devices is extended along a direction perpendicular to the long axis direction of each of the light-emitting sub-pixels.

9. The display substrate according to any one of claims 5 to 7, wherein: It also includes a flat layer and a first passivation layer arranged between the second metal layer and the third metal layer, and a second passivation layer arranged on the side of the third metal layer away from the substrate; the flat layer, the first passivation layer and the second passivation layer are arranged away from the substrate in sequence; and a plurality of exhaust holes are opened along the thickness direction of the first passivation layer and the second passivation layer.

10. The display substrate according to claim 9, wherein: In the display area, an orthographic projection of each of the exhaust holes on the substrate does not overlap with an orthographic projection of the third metal layer on the substrate.

11. The display substrate according to claim 10, wherein: In the display area, an arrangement period of the plurality of exhaust holes is the same as an arrangement period of the plurality of light-emitting sub-pixels.

12. The display substrate according to any one of claims 5 to 7, 10 and 11, wherein: It also includes a display area and a peripheral area arranged around the display area; in the peripheral area, the display substrate also includes a first lead and a second lead, the first lead includes a first part extending along a direction parallel to the long axis of the light-emitting sub-pixel, the second lead includes a second part extending along a direction parallel to the long axis of the light-emitting sub-pixel, the first part is coupled to the first high potential wiring, the second part is coupled to the low potential wiring, and the first part is coupled to a first constant power supply terminal, and the second part is coupled to a second constant power supply terminal.

13. The display substrate according to claim 12, wherein: The second portion is arranged on a side of the first portion facing away from the display area on the same side of the display substrate.

14. The display substrate according to claim 13, wherein: Along a direction parallel to the short axis of each of the light-emitting sub-pixels, an extension length of the first portion and an extension length of the second portion are both greater than an extension length of each of the light-emitting sub-pixels.

15. The display substrate according to claim 12, wherein: A flat layer is arranged between the first part and the substrate, and the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the flat layer on the substrate. The orthographic projection of the first part on the substrate completely falls within the area of ​​the orthographic projection of the flat layer on the substrate. The first part is provided with at least one hollow structure, and the inorganic layer located on the side of the flat layer away from the substrate is provided with an exhaust hole corresponding to the at least one hollow structure.

16. The display substrate according to claim 12, wherein: A planar layer is provided between the first portion and the low-potential wiring, and in the peripheral region, the planar layer is located in a region where the first portion and the low-potential wiring overlap.

17. The display substrate according to claim 12, wherein: It also includes a flat layer extending from the display area to the peripheral area, and the orthographic projections of the first part and the second part on the substrate completely fall within the area of ​​the orthographic projection of the flat layer on the substrate. The first part and the second part are both provided with at least one hollow structure, and the inorganic layer located on the side of the flat layer away from the substrate is provided with an exhaust hole corresponding to the at least one hollow structure.

18. A display device, wherein: include: The display substrate according to any one of claims 1 to 17.

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