Memory fault handling method and apparatus, and computing device cluster

Abstract

A memory fault handling method, comprising: predicting in a memory a region that is at risk of faults, so as to obtain a first region; determining a usage type of the first region, wherein the usage type is a user-mode memory or a kernel-mode memory; when the usage type of the first region is the kernel-mode memory, using redundant resources in the memory to repair the first region; and when the usage type of the first region is the user-mode memory, using a second region in the memory to repair the first region, wherein the second region is a region that is not at risk of faults in the memory, and the second region does not belong to the redundant resources. In this way, on the basis of the usage of a risky region in a memory, redundant resources are selectively used for repair, such that redundant resources can be saved on to the greatest extent and the redundant resources are reserved for faults of a kernel-mode memory that have greater impact, thereby lowering the risk of system crashes.

Description

Memory fault processing method, device and computing device cluster

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 19, 2024, with application number 202410319801.8 and application name “A memory fault handling method, device and computing device cluster”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of information technology (IT), and in particular to a memory fault processing method, apparatus, and computing device cluster. Background Art

[0003] Memory is a key component in computer systems, typically composed of storage cells that store data and instructions. During computer system operation, memory cells may experience bit transitions due to hardware defects or electromagnetic interference. Some bits in a memory cell can be used to store data, while others can be used to store error checking and correcting (ECC) codes. When a single-bit transition occurs in a memory cell, the ECC mechanism can correct it, resulting in a correctable error (CE) failure. When multiple-bit transitions occur in a memory cell, the ECC mechanism can only detect the error but not correct it, resulting in an uncorrectable error (UCE) failure. When an UCE failure occurs in user-mode memory, it can cause an application crash, while if it occurs in kernel-mode memory, it can cause a system crash.

[0004] To improve memory availability, firmware such as the baseboard management controller (BMC) or basic input / output system (BIOS) can employ soft package post repair (sPPR) technology. When a memory cell failure is detected or predicted, redundant rows in memory are used to replace the failed row, ensuring memory availability. However, spPPR ​​resources are limited. Each bank group in memory has only one to three redundant rows, and allocating too many redundant rows can waste resources. Therefore, reducing the waste of redundant memory resources is a pressing technical issue. Summary of the Invention

[0005] The present application provides a memory fault handling method, apparatus, computing device cluster, computer storage medium, and computer product, which can reduce the waste of redundant resources in memory.

[0006] In a first aspect, the present application provides a memory fault handling method, comprising: predicting an area in memory at risk of failure to obtain a first area; determining a usage type of the first area, where the usage type is user-mode memory or kernel-mode memory; if the usage type of the first area is kernel-mode memory, repairing the first area using redundant resources in the memory; if the usage type of the first area is user-mode memory, repairing the first area using a second area in the memory, wherein the second area is an area in the memory that is not at risk of failure and is not a redundant resource. Exemplarily, the second area may be an idle memory area that is not at risk of failure.

[0007] Since data in user-mode memory is portable, while data in kernel-mode memory is not, kernel-mode memory failures can only be repaired using redundant resources, while user-mode memory failures can be repaired with or without redundant resources. User-mode memory accounts for the majority of memory failures. Using redundant resources to repair user-mode memory failures will likely consume all redundant resources, rendering kernel-mode memory failures unrepairable. However, the impact of user-mode memory failures is often minor, while the impact of kernel-mode memory failures is greater. Therefore, using redundant resources to repair user-mode memory failures is likely to cause system downtime when kernel-mode memory failures occur. Therefore, selectively using redundant resources for repairs based on the usage of risky areas in memory can maximize redundant resource conservation and reserve them for kernel-mode memory failures with greater impact, thereby reducing the risk of system downtime.

[0008] In one possible implementation, repairing a first region using redundant resources in memory includes: copying data stored in the first region to a first redundant space in the redundant resources; removing a mapping relationship between a physical address of the first region and a memory array address of the first region, where the memory array address includes one or more of a Rank address, a BankGroup address, a Bank address, a Row address, and a Column address; and establishing a mapping relationship between the physical address of the first region and the memory array address of the first redundant space. Thus, by changing the mapping relationship between the physical address of the first region and the memory array address of the memory region in the memory, repairing the first region using redundant resources in the memory is achieved.

[0009] In one possible implementation, after repairing the first region using redundant resources in the memory, the method further includes: when the first redundant space is released, releasing the mapping relationship between the physical address of the first region and the memory array address of the first redundant space; establishing a mapping relationship between the physical address of the first region and the memory array address of the first region, and isolating the first region. In this way, the replacement relationship between the first redundant space and the first region can be released, thereby releasing the first redundant space, that is, completing the release of redundant resources in the memory, so that the first redundant space can be used for other memory repairs. In addition, after releasing the replacement relationship between the first redundant space and the first region, the first region can be accessed. Since the first region is at risk of storage failure, in order to reduce the probability of memory failure, the first region can be isolated so that it will not be used again in the future.

[0010] In one possible implementation, before copying the data stored in the first region to the first redundant space in the redundant resources, the method further includes: interrupting read and write access to the first region through a hardware mechanism; and after establishing a mapping relationship between the physical address of the first region and the memory array address of the first redundant space, the method further includes: restoring read and write access to the first region. This prevents access to the first region during the data copy process, thereby preventing data copy errors.

[0011] In one possible implementation, repairing the first area using the second area in memory includes: removing the mapping relationship between the physical address of the first area and the virtual address of a target service, where the target service is a service related to data stored in the first area; copying the data stored in the first area to the second area; establishing a mapping relationship between the virtual address of the target service and the physical address of the second area; and isolating the first area. Thus, by changing the mapping relationship between the virtual address of the service and the physical address of the memory area in memory, the first area can be repaired using the non-risk area in memory.

[0012] In a possible implementation, the redundant resources include: redundant rows and / or redundant storage cells.

[0013] In one possible implementation, predicting areas in the memory with a risk of failure includes: obtaining historical failure information of the memory; and predicting areas in the memory with a risk of failure based on the historical failure information. Thus, prediction of risk areas in the memory is achieved.

[0014] In one possible implementation, determining the usage type of the first region includes: determining, based on the physical address of the first region, a first virtual address that has a mapping relationship with the physical address of the first region; determining the usage type of the first region as kernel-mode memory when the first virtual address is within the virtual address range of kernel space; and determining the usage type of the first region as user-mode memory when the first virtual address is within the virtual address range of user space. In this way, the usage type of the first region is determined using the physical address of the first region.

[0015] In a second aspect, the present application provides a memory fault handling device, comprising: a fault prediction module, a type detection module and a fault handling module. The fault prediction module is used to predict an area in the memory where there is a risk of failure to obtain a first area. The type detection module is used to determine the usage type of the first area, where the usage type is user-mode memory or kernel-mode memory. The fault handling module is used to repair the first area using redundant resources in the memory when the usage type of the first area is kernel-mode memory; and to repair the first area using a second area in the memory when the usage type of the first area is user-mode memory, wherein the second area is an area in the memory where there is no risk of failure and the second area is not a redundant resource.

[0016] In one possible implementation, when the fault handling module uses redundant resources in the memory to repair the first area, it is specifically used to: copy the data stored in the first area to the first redundant space in the redundant resources; release the mapping relationship between the physical address of the first area and the memory array address of the first area, wherein the memory array address includes: one or more of: Rank address, BankGroup address, Bank address, row address and column address; establish a mapping relationship between the physical address of the first area and the memory array address of the first redundant space.

[0017] In one possible implementation, after repairing the first area using redundant resources in the memory, the fault handling module is further used to: when the first redundant space is released, release the mapping relationship between the physical address of the first area and the memory array address of the first redundant space; establish a mapping relationship between the physical address of the first area and the memory array address of the first area, and isolate the first area.

[0018] In one possible implementation, before copying data stored in the first region to the first redundant space in the redundant resources, the fault handling module is further configured to: interrupt read and write access to the first region through a hardware mechanism. After establishing a mapping relationship between the physical address of the first region and the memory array address of the first redundant space, the fault handling module is further configured to: restore read and write access to the first region.

[0019] In one possible implementation, when the fault handling module uses the second area in the memory to repair the first area, it is specifically used to: release the mapping relationship between the physical address of the first area and the virtual address of the target business, wherein the target business is a business related to the data stored in the first area; copy the data stored in the first area to the second area; establish a mapping relationship between the virtual address of the target business and the physical address of the second area, and isolate the first area.

[0020] In a possible implementation, the redundant resources include: redundant rows and / or redundant storage cells.

[0021] In a possible implementation, when predicting a region in the memory where a fault risk exists, the fault prediction module is specifically configured to: obtain historical fault information of the memory; and predict the region in the memory where a fault risk exists based on the historical fault information.

[0022] In one possible implementation, when determining the usage type of the first area, the type detection module is specifically used to: determine, based on the physical address of the first area, a first virtual address having a mapping relationship with the physical address of the first area; when the first virtual address is within the virtual address range of the kernel space, determine that the usage type of the first area is kernel-mode memory; when the first virtual address is within the virtual address range of the user space, determine that the usage type of the first area is user-mode memory.

[0023] In a third aspect, the present application provides a memory fault handling device, comprising at least one processor and an interface; the at least one processor obtains program instructions through the interface; and the at least one processor is configured to execute the program instructions to implement the method described in the first aspect or any possible implementation of the first aspect. Exemplarily, the memory fault handling device may be, but is not limited to, a chip.

[0024] In a fourth aspect, the present application provides a computing device comprising: one or more processors; a memory for storing one or more programs; and when the one or more programs are executed by the one or more processors, the one or more processors implement the method described in the first aspect or any possible implementation of the first aspect.

[0025] In a fifth aspect, the present application provides a computer-readable storage medium comprising computer program instructions. When the computer program instructions are executed by a computing device, the computing device executes the method described in the first aspect or any possible implementation of the first aspect.

[0026] In a sixth aspect, the present application provides a computer program product comprising instructions, which, when executed by a computing device, causes the computing device to execute the method described in the first aspect or any possible implementation of the first aspect.

[0027] It can be understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic diagram of the architecture of a computing device provided in an embodiment of the present application;

[0029] FIG2 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0030] FIG3 is a flow chart of a method for handling a memory failure according to an embodiment of the present application;

[0031] FIG4 is a schematic diagram of steps for repairing a risky area in memory using redundant resources according to an embodiment of the present application;

[0032] FIG5 is a schematic structural diagram of a memory fault processing device provided in an embodiment of the present application;

[0033] FIG6 is a schematic structural diagram of another memory fault processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0035] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0036] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0038] In the embodiments of the present application, in order to reduce the waste of redundant memory resources, the main method is to selectively use redundant memory resources for repair based on the usage of risky areas in memory (such as user-mode memory or kernel-mode memory), thereby saving redundant resources to the greatest extent possible. The following is an introduction to the technical solutions provided by the embodiments of the present application.

[0039] For example, FIG1 shows a schematic diagram of the architecture of a computing device provided in an embodiment of the present application. The computing device 100 shown in FIG1 can be any device or device cluster with data processing capabilities, data transmission and reception capabilities, or data storage capabilities. For example, it can be a physical device such as a host, a rack server, a blade server, a bare metal server, etc. The computing device 100 can be configured with hardware components 110 and an operating system (OS) 120. For example, OS 120 can include one or more of a Linux operating system, a Windows operating system, or a Unix operating system.

[0040] The hardware components 110 may include memory 111, memory controller 112, and firmware such as BIOS / BMC 113. Of course, the hardware components 110 may also include components such as a network card and a central processing unit (CPU), which may be determined according to actual conditions and are not limited here.

[0041] Memory 111 can be used for temporary storage and quick access to data and instructions. It can be used, but is not limited to, to store currently running programs, operating systems, and the data they require. Exemplarily, memory 111 can be dual-inline memory modules (DIMMs), small outline dual inline memory modules (SO-DIMMs), fully buffered DIMMs (FB-DIMMs), etc. It should be noted that the embodiments of the present application do not limit the specific form of memory 111; the above description is merely an example. It suffices for memory 111 to have redundant resources (e.g., redundant rows or redundant storage cells, etc.). The following description uses memory 111 as a DIMM as an example. Referring to FIG. 2 , memory 111 has at least one physical storage array (Rank), such as Rank 0 and Rank 1. Each Rank is located on a surface of memory 111, and each Rank includes one or more memory chips, such as Chip 00 and Chip 01. Each chip is divided into multiple storage array groups (BankGroups), each BankGroup including multiple logical storage arrays (Banks), such as Bank 0 and Bank n. One to three rows can be reserved in each BankGroup as redundant resources. Each bank is divided into multiple storage cells (Cells), each cell having a memory row address and a memory column address, and each cell includes one or more bits (not shown). In some embodiments, memory 111 can be divided into Chips, BankGroups, Banks, storage rows / columns, and Cells, from top to bottom. In other embodiments, memory 111 can be divided into multiple memory pages (pages) based on a paging mechanism, with each page corresponding to multiple cells in memory 111. The addresses of memory pages are virtual addresses, which require conversion before becoming real physical addresses. For example, memory failures in memory 111 can be categorized as: Cell failure, row failure, column failure, and Bank failure. A row failure refers to a failure at different locations in a row within a bank; a column failure refers to a failure at different locations in a column within a bank.

[0042] The memory controller 112 is mainly used to detect memory faults in the memory 111 through technologies such as parity check and cyclic redundancy check (CRC). After detecting a memory fault (such as a CE fault or UCE fault), the memory controller 112 can report the fault information to the firmware 113. Exemplarily, the fault information may include: a fault address. Exemplarily, the fault address may refer to the memory array address of the area in the memory where the fault occurred. The memory array address includes one or more of: a Rank address, a BankGroup address, a Bank address, a Row address, and a Column address.

[0043] Firmware 113 may include a fault reporting unit 1131 and a memory repair driver 1132. Fault reporting unit 1131 is primarily used to report fault information reported by memory controller 112 to OS 120. Memory repair driver 1132 is primarily used to utilize redundant resources in memory 111 to perform memory repair and release redundant resources in memory 111.

[0044] The OS 120 may include a fault collection and prediction unit 121 , a risky memory location determination unit 122 , a fault repair unit 123 , and a memory redundancy resource management unit 124 .

[0045] Among them, the fault collection and prediction unit 121 is mainly used to collect the fault information reported by the fault reporting unit 1131, and, based on the fault information, predict the area A in the memory 111 where there is a fault risk, and output the memory array address of area A. Among them, area A refers to an area in the memory 111 where there is a fault risk, such as: one or more rows on a Bank, or a Cell on a Bank, etc. Exemplarily, the fault collection and prediction unit 121 first counts the fault information it collects to identify the fault type of the memory fault, such as: Cell fault, row fault or column fault. For example, when multiple Cell faults are located in the same row, it can be determined that the fault type of the memory fault is a row fault. Then, the fault collection and prediction unit 121 can process the identified fault type through algorithms such as machine learning to predict area A in the memory 111 where there is a fault risk.

[0046] The risky memory location determination unit 122 is primarily used to determine the usage type of region A, such as whether it is user memory, kernel memory, or free memory, based on the memory array address of region A, and to determine whether the data in region A is migratable. Exemplarily, the risky memory location determination unit 122 may first convert the memory array address of region A into a physical address recognizable by the OS 120 using address mapping rules. The risky memory location determination unit 122 then processes the converted physical address using address reverse mapping technology to obtain a virtual address that is mapped to the physical address. Finally, because different memory regions have different virtual address ranges, for example, in the Linux operating system, the virtual address range of user memory is 0x00000000 to 0xBFFFFFFF, and the virtual address range of kernel memory is 0xC0000000 to 0xFFFFFFFF. Therefore, when the virtual address is within the virtual address range of user space, the usage type of region A is determined to be user memory. When the virtual address is within the virtual address range of kernel space, the usage type of region A is determined to be kernel memory. When the virtual address is neither within the virtual address range of user space nor within the virtual address range of kernel space, the usage type of area A is determined to be free memory. Further, when the usage type of area A is determined to be user memory, it can be determined that the data in area A can be migrated; when the usage type of area A is determined to be kernel memory, it can be determined that the data in area A cannot be migrated.

[0047] The fault repair unit 123 can be used to migrate the data in area A to an area in the memory 111 where there is no fault risk when the usage type of area A is user-mode memory, and mark area A with a special mark to mark area A as permanently isolated, so that the OS 120 will not use area A subsequently. Specifically, the fault repair unit 123 can first demap the physical address of area A and the virtual address of the target business to interrupt the read and write access of area A. The target business is the business related to the data stored in area A. Then, the fault repair unit 123 copies the data in area A to area B in the memory 111 where there is no fault risk. Finally, the fault repair unit 123 establishes a mapping relationship between the virtual address of the target business and the physical address of area B, and marks area A as permanently isolated.

[0048] The fault repair unit 123 is also configured to repair region A using redundant resources in memory 111, such as SPPR repair, partial cache line sparing (PCLS) repair, or adaptive double device data correction (ADDDC), when region A is used as kernel-mode memory or when data in region A cannot be migrated. Exemplarily, the fault repair unit 123 may first temporarily interrupt read and write access to region A using a hardware mechanism such as memory back pressure. The fault repair unit 123 then copies the data in region A to an idle redundant space RS within the redundant resources in memory 111. Exemplarily, the redundant space RS may be a redundant row or redundant cell. Next, the fault repair unit 123 removes the mapping between the physical address of region A and the memory array address of region A, and establishes a mapping between the physical address of region A and the memory array address of the redundant space RS, thereby replacing region A with the redundant space RS. Finally, the fault repair unit 123 may restore read and write access to region A. In this way, the OS 120 can subsequently directly access the redundant space RS through the physical address of area A without accessing area A. In addition, the fault repair unit 123 can also mark the redundant space RS as a repaired memory.

[0049] The fault recovery unit 123 is also used to mark the area A with a special mark when the usage type of the area A is free memory, so as to mark the area A as permanently isolated, so that the subsequent OS will not use the area A.

[0050] The memory redundancy resource management unit 124 is mainly used to release the redundant space replacement when the OS 120 releases the memory. If the released memory is the repaired memory, the redundant space is replaced and the redundant space is put back into the free redundant resource pool for use by other memory repairs, thereby completing the release of the redundant resources in the memory 111. The following continues to describe the release of redundant space replacement using area A and redundant space RS as an example. When releasing the redundant space RS replacement, the memory redundancy resource management unit 124 can first release the mapping relationship between the memory array address of the redundant space RS and the physical address of area A; then, it establishes a mapping relationship between the memory array address of area A and the physical address of area A to achieve the purpose of releasing the redundant space RS replacement. Since after the redundant space RS replacement is released, the OS 120 will directly access the memory array address of area A from the physical address of area A, and there is a risk of failure in area A, in order to reduce the probability of memory failure, the area A can be marked as permanently isolated, so that the OS 120 will not use the area A in the future.

[0051] It is understandable that the functions of the various units in the above-mentioned OS120 can be adjusted according to actual needs, and the adjusted scheme is still within the scope of protection of this application. For example, one unit can perform a certain function in another unit, and so on. In addition, the various units in OS120 can be fully integrated together, partially integrated together, or all arranged separately. In addition, the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the computing device 100. In other embodiments of the present application, the computing device 100 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The illustrated components can be implemented in hardware, software, or a combination of software and hardware.

[0052] The above is an introduction to the computing device 100 provided in the embodiment of the present application. Based on the above content, a memory fault processing method provided in the embodiment of the present application is introduced below.

[0053] For example, FIG3 shows a flow chart of a memory fault handling method provided by an embodiment of the present application. It is understood that the method can be executed by any device, equipment, platform, or device cluster with computing and processing capabilities. As shown in FIG3, the memory fault handling method includes the following steps:

[0054] S301: Predicting a region in a memory with a failure risk to obtain a first region.

[0055] In this embodiment, historical memory failure information can be used to predict areas within the memory at risk of failure. This historical failure information can be obtained from data reported by the memory controller. After obtaining this historical failure information, algorithms such as machine learning can be used to process it to predict areas within the memory at risk of failure.

[0056] S302: Determine a usage type of the first area, where the usage type is user-mode memory or kernel-mode memory.

[0057] In this embodiment, after predicting the first area, the address reverse mapping technology can be used to process the physical address of the first area to determine a first virtual address that has a mapping relationship with the physical address of the first area. Then, the usage type of the first area is determined based on the address range of the first virtual address. The usage type can be user-mode memory or kernel-mode memory. In the case where the first virtual address is within the virtual address range of the kernel space, the usage type of the first area can be determined to be kernel-mode memory. In the case where the first virtual address is within the virtual address range of the user space, the usage type of the first area can be determined to be user-mode memory.

[0058] S303: When the usage type of the first area is kernel-mode memory, repair the first area using redundant resources in the memory.

[0059] In this embodiment, when the usage type of the first region is kernel-mode memory, the first region can be repaired using redundant resources in the memory. Exemplarily, the redundant resources in the memory may include redundant rows and / or redundant storage cells.

[0060] As a possible implementation, repairing the first region using redundant resources in memory can be shown in Figure 4. In S401, data stored in the first region is copied to the first redundant space in the redundant resources. To avoid data copy errors, read and write access to the first region can be interrupted by hardware mechanisms before S401. In S402, the mapping relationship between the physical address of the first region and the memory array address of the first region is released. The memory array address includes one or more of a Rank address, a BankGroup address, a Bank address, a Row address, and a Column address. In S403, a mapping relationship is established between the physical address of the first region and the memory array address of the first redundant space. This allows subsequent access to the first redundant space directly using the physical address of the first region, without accessing the first region, thereby repairing the first region. If read and write access to the first region was interrupted before S401, read and write access to the first region must be restored after S430 to allow subsequent read and write access to the first redundant space. Furthermore, after the repair of the first region is complete, the first redundant space can be marked as repaired memory. Furthermore, when the first redundant space is released, the mapping relationship between the physical address of the first region and the memory array address of the first redundant space can be released first. Then, the mapping relationship between the physical address of the first region and the memory array address of the first region can be established. In this way, the replacement relationship between the first redundant space and the first region can be released, so that the first redundant space can be released, that is, the release of redundant resources in the memory is completed, so that the first redundant space can be used for other memory repairs. In addition, after the replacement relationship between the first redundant space and the first region is released, the first region can be accessed. Since the first region is at risk of storage failure, in order to reduce the probability of memory failure, the first region can be isolated so that the first region will not be used again in the future.

[0061] S304: When the first area is used as user memory, repair the first area using a second area in the memory, wherein the second area is an area in the memory that is not at risk of failure and is not a redundant resource. For example, the second area may be an idle memory area that is not at risk of failure.

[0062] In this embodiment, when the usage type of the first area is user-mode memory, the second area in the memory can be used to repair the first area. The second area is an area in the memory where there is no risk of failure, and the second area is not a redundant resource. For example, the mapping relationship between the physical address of the first area and the virtual address of the target business can be released first. The target business is a business related to the data stored in the first area. Then, the data stored in the first area is copied to the second area. Finally, a mapping relationship is established between the virtual address of the target business and the physical address of the second area, and the first area is isolated. In this way, the repair of the first area is completed through the second area, and the first area will not be used subsequently, thereby reducing the probability of memory failure.

[0063] Since data in user-state memory is migratable, while data in kernel-state memory is not, kernel-state memory failures can only be repaired using redundant resources, while user-state memory failures can be repaired with or without redundant resources. User-state memory accounts for the vast majority of memory failures. Using redundant resources to repair user-state memory failures will likely consume all redundant resources, rendering kernel-state memory failures unrepairable. However, the impact of user-state memory failures is often relatively small, while the impact of kernel-state memory failures is relatively large. Therefore, using redundant resources to repair user-state memory failures will likely cause system downtime when kernel-state memory failures occur. Therefore, in this embodiment, selectively using redundant resources for repairs based on the usage of risky areas in memory can maximize the savings in redundant resources and reserve them for kernel-state memory failures with the greater impact, thereby reducing the risk of system downtime.

[0064] It should be understood that the order of execution of the steps in the above embodiments does not necessarily imply a specific order of execution. The order of execution of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of this application. In addition, the various embodiments described above can be combined according to actual circumstances, and the combined solutions are still within the scope of protection of this application.

[0065] Based on the contents in the above embodiments, an embodiment of the present application provides a memory fault processing device.

[0066] Exemplarily, FIG5 shows a schematic structural diagram of a memory fault handling device provided in an embodiment of the present application. As shown in FIG5 , the memory fault handling device includes: a fault prediction module 501, a type detection module 502, and a fault handling module 503. Among them, the fault prediction module 501 is used to predict an area in the memory where there is a risk of failure to obtain a first area. The type detection module 502 is used to determine the usage type of the first area, and the usage type is user-mode memory or kernel-mode memory. The fault handling module 503 is used to repair the first area using redundant resources in the memory when the usage type of the first area is kernel-mode memory; and to repair the first area using a second area in the memory when the usage type of the first area is user-mode memory, wherein the second area is an area in the memory where there is no risk of failure and the second area is not a redundant resource.

[0067] In some embodiments, when the fault handling module 503 uses redundant resources in the memory to repair the first area, it is specifically used to: copy the data stored in the first area to the first redundant space in the redundant resources; release the mapping relationship between the physical address of the first area and the memory array address of the first area, wherein the memory array address includes: one or more of: Rank address, BankGroup address, Bank address, row address and column address; establish a mapping relationship between the physical address of the first area and the memory array address of the first redundant space.

[0068] In some embodiments, after repairing the first area using redundant resources in the memory, the fault handling module 503 is further used to: release the mapping relationship between the physical address of the first area and the memory array address of the first redundant space when the first redundant space is released; establish a mapping relationship between the physical address of the first area and the memory array address of the first area, and isolate the first area.

[0069] In some embodiments, before copying the data stored in the first region to the first redundant space in the redundant resources, the fault handling module 503 is further configured to: interrupt read and write access to the first region through a hardware mechanism. After establishing a mapping relationship between the physical address of the first region and the memory array address of the first redundant space, the fault handling module 503 is further configured to: restore read and write access to the first region.

[0070] In some embodiments, when the fault handling module 503 uses the second area in the memory to repair the first area, it is specifically used to: release the mapping relationship between the physical address of the first area and the virtual address of the target business, where the target business is a business related to the data stored in the first area; copy the data stored in the first area to the second area; establish a mapping relationship between the virtual address of the target business and the physical address of the second area, and isolate the first area.

[0071] In some embodiments, the redundant resources include redundant rows and / or redundant memory cells.

[0072] In some embodiments, when predicting a region in the memory where a fault risk exists, the fault prediction module 501 is specifically configured to: obtain historical fault information of the memory; and predict the region in the memory where a fault risk exists based on the historical fault information.

[0073] In some embodiments, when determining the usage type of the first area, the type detection module 502 is specifically used to: determine a first virtual address having a mapping relationship with the physical address of the first area based on the physical address of the first area; when the first virtual address is within the virtual address range of the kernel space, determine that the usage type of the first area is kernel-mode memory; when the first virtual address is within the virtual address range of the user space, determine that the usage type of the first area is user-mode memory.

[0074] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0075] Based on the methods in the above embodiments, embodiments of the present application also provide a memory fault handling device. Please refer to Figure 6, which is a schematic diagram of the structure of another memory fault handling device provided in embodiments of the present application. As shown in Figure 6, memory fault handling device 600 includes one or more processors 601 and an interface circuit 602. Optionally, memory fault handling device 600 may also include a bus 603. Specifically:

[0076] The processor 601 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 601 or an instruction in the form of software. The above-mentioned processor 601 can be a general-purpose processor, a digital communicator (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The various methods and steps disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0077] The interface circuit 602 can be used to send or receive data, instructions or information. The processor 601 can use the data, instructions or other information received by the interface circuit 602 to process it, and can send the processing completion information through the interface circuit 602.

[0078] Optionally, the memory fault processing device 600 further includes a memory, which may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory (NVRAM).

[0079] Optionally, the memory stores an executable software module or a data structure, and the processor can perform corresponding operations by calling an operation instruction stored in the memory (the operation instruction may be stored in an operating system).

[0080] Optionally, the interface circuit 602 may be configured to output the execution result of the processor 601 .

[0081] It should be noted that the corresponding functions of the processor 601 and the interface circuit 602 can be implemented through hardware design, software design, or a combination of hardware and software, which is not limited here.

[0082] It should be understood that each step of the above method embodiment can be completed by a hardware-based logic circuit or a software-based instruction in a processor.

[0083] Based on the methods in the above embodiments, embodiments of the present application further provide a computing device that may include one or more processors and a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the methods in the above embodiments.

[0084] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, including computer program instructions. When the computer program instructions are executed by a computing device, the computing device executes the method in the above embodiment. Exemplarily, the computer-readable storage medium can be any available medium that can be stored by the computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive), etc.

[0085] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product containing instructions, which, when executed by a computing device, enables the computing device to execute the method in the above embodiment.

[0086] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0087] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0088] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0089] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory fault processing method, characterized in that: include: Predicting an area in the memory having a failure risk to obtain a first area; Determine a usage type of the first area, where the usage type is user-mode memory or kernel-mode memory; In a case where the usage type of the first area is kernel-mode memory, repairing the first area by using redundant resources in the memory; When the usage type of the first area is user-mode memory, the first area is repaired using the second area in the memory, wherein the second area is an area in the memory that has no failure risk and does not belong to the redundant resource.

2. The method according to claim 1, characterized in that The repairing the first area by using the redundant resources in the memory includes: copying the data stored in the first area to the first redundant space in the redundant resource; Release the mapping relationship between the physical address of the first region and the memory array address of the first region, wherein the memory array address includes one or more of: a rank address, a bank group address, a bank address, a row address, and a column address; A mapping relationship between the physical address of the first area and the memory array address of the first redundant space is established.

3. The method according to claim 2, characterized in that After repairing the first area by using the redundant resources in the memory, the method further includes: When the first redundant space is released, releasing the mapping relationship between the physical address of the first region and the memory array address of the first redundant space; A mapping relationship between a physical address of the first region and a memory array address of the first region is established, and the first region is isolated.

4. The method according to claim 2 or 3, characterized in that Before copying the data stored in the first area to the first redundant space in the redundant resource, the method further includes: interrupting read and write access to the first area through a hardware mechanism; After establishing a mapping relationship between the physical address of the first region and the memory array address of the first redundant space, the method further includes: restoring read and write access to the first region.

5. The method according to any one of claims 1 to 4, characterized in that: The repairing the first area by using the second area in the memory includes: Unmapping a physical address of the first region and a virtual address of a target service, wherein the target service is a service related to data stored in the first region; copying the data stored in the first area to the second area; A mapping relationship between the virtual address of the target service and the physical address of the second area is established, and the first area is isolated.

6. The method according to any one of claims 1 to 5, characterized in that: The redundant resources include: redundant rows and / or redundant storage units.

7. The method according to any one of claims 1 to 6, characterized in that: The predicting of the area in the memory having a failure risk includes: Obtaining historical fault information from the memory; Based on the historical fault information, areas in the memory with a fault risk are predicted.

8. The method according to any one of claims 1 to 7, characterized in that: The determining the usage type of the first area includes: Determining, based on the physical address of the first region, a first virtual address having a mapping relationship with the physical address of the first region; When the first virtual address is within the virtual address range of the kernel space, determining that the usage type of the first area is kernel-mode memory; When the first virtual address is within the virtual address range of the user space, it is determined that the usage type of the first area is user-mode memory.

9. A memory fault processing device, characterized in that: include: a fault prediction module, configured to predict an area in the memory having a fault risk to obtain a first area; a type detection module, configured to determine a usage type of the first area, the usage type being user-mode memory or kernel-mode memory; a fault processing module, configured to repair the first area by using redundant resources in the memory when the usage type of the first area is kernel-mode memory; Also, when the usage type of the first area is user-mode memory, the first area is repaired using the second area in the memory, wherein the second area is an area in the memory that has no failure risk and does not belong to the redundant resource.

10. The device according to claim 9, characterized in that When the fault processing module repairs the first area using the redundant resources in the memory, the fault processing module is specifically configured to: copying the data stored in the first area to the first redundant space in the redundant resource; Release the mapping relationship between the physical address of the first region and the memory array address of the first region, wherein the memory array address includes one or more of: a rank address, a bank group address, a bank address, a row address, and a column address; A mapping relationship between the physical address of the first area and the memory array address of the first redundant space is established.

11. The device according to claim 10, characterized in that After repairing the first area using the redundant resources in the memory, the fault processing module is further configured to: When the first redundant space is released, releasing the mapping relationship between the physical address of the first region and the memory array address of the first redundant space; A mapping relationship between a physical address of the first region and a memory array address of the first region is established, and the first region is isolated.

12. The device according to claim 10 or 11, characterized in that Before copying the data stored in the first area to the first redundant space in the redundant resource, the fault processing module is further configured to: interrupt read and write access to the first area through a hardware mechanism; After establishing a mapping relationship between the physical address of the first region and the memory array address of the first redundant space, the fault processing module is further configured to restore read and write access to the first region.

13. The device according to any one of claims 9 to 12, characterized in that: When the fault processing module uses the second area in the memory to repair the first area, the fault processing module is specifically configured to: Unmapping a physical address of the first region and a virtual address of a target service, wherein the target service is a service related to data stored in the first region; copying the data stored in the first area to the second area; A mapping relationship between the virtual address of the target service and the physical address of the second area is established, and the first area is isolated.

14. The device according to any one of claims 9 to 13, characterized in that: The redundant resources include: redundant rows and / or redundant storage units.

15. The device according to any one of claims 9 to 14, characterized in that: When predicting an area in the memory that has a risk of failure, the fault prediction module is specifically configured to: Obtaining historical fault information from the memory; Based on the historical fault information, areas in the memory with a fault risk are predicted.

16. The device according to any one of claims 9 to 15, characterized in that: When determining the usage type of the first area, the type detection module is specifically configured to: Determining, based on the physical address of the first region, a first virtual address having a mapping relationship with the physical address of the first region; When the first virtual address is within the virtual address range of the kernel space, determining that the usage type of the first area is kernel-mode memory; When the first virtual address is within the virtual address range of the user space, it is determined that the usage type of the first area is user-mode memory.

16. A memory fault processing device, comprising at least one processor and an interface; The at least one processor obtains program instructions through the interface; The at least one processor is configured to execute the program line instructions to implement the method according to any one of claims 1-8.

17. A computing device, characterized in that include: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the method according to any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that The method comprises computer program instructions, which, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1 to 8.

19. A computer program product comprising instructions, characterized in that When the instructions are executed by a computing device, the computing device is caused to perform the method according to any one of claims 1 to 8.

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