Memory, controller, chip system, data processing method and electronic device

Abstract

The embodiments are applied in the technical field of data storage. Provided are a memory, a controller, a chip system, a data processing method and an electronic device. The chip system comprises a memory and a controller. The memory comprises at least one storage die, and each storage die is provided with a data cache array and a memory cell array. The memory cell array is used for storing processing data. The data cache array is used for caching part of the processing data. The memory is used for: receiving, on the basis of whether target data is present in the data cache array and from the controller, a data processing instruction of cache type or a data processing instruction of memory type; and on the basis of the data processing instruction, performing data processing on the target data. By means of the embodiments of the present application, the limitation of the processing rate of the memory on the processing performance of a processor is reduced.

Description

Memory, controller, chip system, data processing method and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 29, 2024, with application number 202410386177.3 and application name “Memory, Controller, Chip System, Data Processing Method and Electronic Device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data storage technology, and in particular to a memory, a controller, a chip system, a data processing method and an electronic device. Background Art

[0003] When a processor runs a program, it needs to read or write relevant target data from the memory, which serves as memory. The processor can process data directly in the memory, or it can access the memory through a memory controller. With advancements in chip manufacturing processes, the processor's processing speed has increased significantly, but the memory's processing speed has not increased commensurately. This results in reduced efficiency when the processor accesses the memory (either directly or through a memory controller). As semiconductor manufacturing processes become more advanced, the gap between the processor's processing speed and the memory's processing speed has widened. Furthermore, as the size of memory cells decreases, increasing the memory's processing speed becomes increasingly difficult. This results in the memory's processing speed increasingly limiting the processor's processing performance. Summary of the Invention

[0004] The embodiments of the present application provide a memory, a controller, a chip system, a data processing method, and an electronic device, which reduce the limitation of the processing rate of the memory on the processing performance of the processor.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a memory is provided, comprising at least one memory die, each memory die being provided with a data cache cell array and a memory cell array. The memory cell array is used to store processed data. The data cache cell array is used to cache portions of the processed data. The memory is configured to receive cache-type data processing instructions or memory-type data processing instructions from a controller, depending on whether target data is present in the data cache cell array. The memory is configured to perform data processing on the target data according to the data processing instructions.

[0007] In an embodiment of the present application, based on the same preparation process, a data cache cell array for storing data in a cache cell array and a memory cell array of a memory device are prepared on the same die to obtain a memory. In this memory, the data cache cell array is used as a cache device of the corresponding memory cell array to store a portion of the processed data located in the memory cell array. Under this embodiment, the data cache cell array does not have an independent corresponding control circuit or control device. When data processing is required for a certain target data, the controller corresponding to the memory cell array is reused. According to the different situations of the target data hitting (hit) or missing (miss) in the data cache cell array (i.e., the presence or absence of the target data), the memory can receive the corresponding type of data processing instructions from the controller, such as cache type data processing instructions or memory type data processing instructions. Based on the above processing, the processing rate of the target data in the memory can be improved, thereby reducing its limitation on the operating performance of the processor. At the same time, a controller is reused to control the data processing of the data cache cell array and the memory cell array, and the control of the access, reading and writing processing of the target data is simpler and more efficient. Moreover, based on the same control device for control, it is easier to achieve data consistency management of the data cache cell array and the memory cell array. Providing access to target data based on the data cache cell array avoids the delay of operations such as activation and precharging of the memory cell array, reduces the number of times the memory cell array is used, increases the service life of the memory cell array, and reduces the power consumption of the memory.

[0008] In one possible implementation, the memory may receive different types of read instructions from the controller depending on whether the target read data exists in the data cache unit array:

[0009] In one example, the memory is specifically used to: when the target read data is cached in the data cache cell array, receive a cache read instruction from the controller, the cache read instruction is a cache type data processing instruction, and the cache read instruction is used to instruct the memory to feed back the target read data from the data cache cell array to the controller. In an embodiment of the present application, when the target read data is stored in the data cache cell array, the memory can send the target read data from the data cache cell array to the controller (a processor or a memory controller). In this way, there is no need to access the memory cell array, which reduces the number of accesses to the memory cell array and improves the service life of the memory cell array. In addition, the target read data is read based on the cache read instruction, and there is no pre-charging and activation processing of the memory type read instruction when reading the data. Its read delay is significantly shorter than the read delay required for reading the target read data from the memory cell array. Through this embodiment, the target data in the memory can be quickly obtained to meet the high processing rate requirements of the processing device.

[0010] In one example, the memory is specifically used to: when the target read data is not cached in the data cache cell array, receive a memory read instruction from the controller, and the memory read instruction is used to instruct the memory to feed back the target read data from the memory storage cell array to the controller. In an embodiment of the present application, the data cache cell array and the memory cell array in the memory are controlled by multiplexing a controller. By designing the storage space size of the data cache cell array, it is possible to cover different amounts of data in the memory read instruction. Most of the data in the memory cell array can be hit in the data cache cell array. Only when the target read data is not cached in the data cache cell array, the controller needs to access the target read data from the memory cell array. At this time, the controller corresponding to the memory cell array can directly send a memory-type data read instruction to the memory, and read from the memory cell array based on the memory read instruction. Under this control scheduling method, the memory can achieve a faster data read rate.

[0011] In actual applications, the read latency for reading target data from a memory cell array based on a memory read instruction is longer than the read latency required to read the target data from a data cache cell array. Because the read latency for cache read instructions and memory read instructions is different, in order to better design the processing performance of the processing device, product manufacturers usually design the read latency values ​​corresponding to memory read instructions and cache read instructions. Therefore, in actual products, in addition to being able to distinguish between cache-type and memory-type read instructions by the instruction format of the data read instruction, cache-type and memory-type read instructions can also be clearly distinguished based on the difference in read latency.

[0012] Exemplarily, the memory is also used to: write the target read data into the data cache cell array in response to a memory read instruction. In an embodiment of the present application, only when the target read data is not stored in the data cache cell array will the controller send a memory-type data processing instruction (i.e., a memory read instruction) to the memory to obtain the target read data from the memory cell array. Because the function of the data cache cell array is to store part of the data in the memory cell array, so as to reduce the number of accesses to the memory cell array and increase the processing rate of the target data. In order to achieve this goal as much as possible, the data stored in the data cache cell array is usually data frequently used by the processing device. Because the target read data is the data currently being processed and is data that is not stored in the data cache cell array, the memory can also synchronously store the target write data into the data cache cell array while writing the target read data into the memory cell array based on the memory read instruction, so that the target read data can be read from the data cache cell array the next time it is accessed, and the memory can achieve a faster data read rate.

[0013] In one possible implementation, the memory may receive different types of write instructions from the controller depending on whether the target write data exists in the data cache unit array:

[0014] In one example, the memory is specifically used to: when the target write data is cached in the data cache cell array, receive a first write instruction from the controller, the first write instruction includes a cache type data processing instruction or a memory type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache cell array and the target write data in the memory cell array. In an embodiment of the present application, since the target write data is stored in the data cache cell array, in order to ensure the consistency of data writing, the controller can send a first write instruction to the memory to instruct the memory to update the target write data in the data cache cell array and the memory cell array at the same time. In this way, a single write control operation can achieve consistent write modification of the data in the cache part and the memory part, making the consistency update process of the same data stored in the data cache cell array and the memory cell array more convenient.

[0015] In one example, when the target write data is not cached in the data cache cell array, a second write instruction is received from the controller, the second write instruction is a memory-type data processing instruction, and the second write instruction is used to instruct the memory to write the target write data to the memory cell array. In an embodiment of the present application, when there is no target write data in the data cache cell array, the controller only needs to write the target write data to the memory cell array. Exemplarily, the target write data can be data not stored in the memory cell array, and the memory writes the target write data to the memory cell array based on the second write instruction. Exemplarily, the target write data can be data stored in the memory cell array, and the memory updates the target write data after the value is updated and writes it to the memory cell array based on the second write instruction. Under this embodiment, the controller corresponding to the memory cell array of the memory can write the target write data to the memory cell array through the second write instruction when the target write data does not hit in the data cache cell array. Under this embodiment, the correct write processing of the target write data is realized when the data cache cell array and the memory cell array are in the same storage grain.

[0016] In one possible embodiment, the memory includes a data interface circuit, and the data cache cell array and the memory cell array are respectively connected to the data interface circuit, and the data interface circuit is connected to the controller. The memory is used to: interact with the controller based on the data interface circuit. In an embodiment of the present application, because the data cache cell array and the memory cell array are manufactured on the same storage grain, and both reuse the controller of the memory cell array to control data processing, the data cache cell array and the memory cell array can reuse the data interface circuit (i.e., reuse an IO interface circuit) to realize the interaction of target data with other devices. Reusing the same IO interface circuit for data interaction avoids the occupation of chip area when multiple IO interface circuits are used to interact with data in the memory cell array and the data cache cell array respectively, thereby improving the device integration while increasing the data interaction rate.

[0017] In a second aspect, embodiments of the present application further provide a controller for interfacing with a memory. The memory includes at least one memory die, each of which is provided with a data cache cell array and a memory cell array. The memory cell array is used to store processed data; the data cache cell array is used to cache portions of the processed data in the corresponding memory cell array. The controller is configured to: power on and start operation. After powering on and starting operation, the controller sends cache-type data processing instructions or memory-type data processing instructions to the memory, depending on whether the target data is present in the data cache cell array. In embodiments of the present application, because the data cache cell array and the memory cell array are located on the same memory die, the two arrays store different data. Therefore, correctly controlling and scheduling the writing and reading of data in the memory cell array and the data cache cell array is crucial. By reusing the controller of the memory cell array, the data cache cell array and the memory cell array are managed separately. The controller can send data cache-type or memory-type data processing instructions to the memory, depending on whether the target data is found in the data cache cell, to ensure accurate processing of the target data in different situations.

[0018] In one possible implementation, the controller may send different types of read instructions to the memory based on whether the target read data exists in the data cache unit array:

[0019] In one example, the controller is specifically used to: when the target read data is cached in the data cache cell array, send a cache read instruction to the memory, the cache read instruction is a cache type data processing instruction, and the cache read instruction is used to instruct the memory to feed back the target read data from the data cache cell array to the controller. In the embodiment of the present application, the name of the target read data is different, and the read access operation is also different. When the target read data hits in the data cache cell array, the controller can read the target read data from the data cache cell array through a cache type data processing instruction. When reading the target read data from the data cache cell array, the memory does not need to perform operations such as precharging, and the transmission rate and processing rate of the data cache cell array are also faster than the memory cell array. In this case, the controller can obtain the target read data to be read from the memory more quickly.

[0020] In one example, the controller is specifically used to: when the target read data is not cached in the data cache cell array, send a memory read instruction to the memory, the memory read instruction is a memory-type data processing instruction, and the memory read instruction is used to instruct the memory to feedback the target read data from the memory cell array to the controller. In an embodiment of the present application, a controller is reused to respectively control the data cache cell array and the memory cell array in the memory. By designing the storage space size of the data cache cell array, it is possible to cover different amounts of data in the memory read instruction. Most of the data in the memory cell array can be hit in the data cache cell array. Only when the target read data is not cached in the data cache cell array does the controller need to access the target read data from the memory cell array. At this time, the controller corresponding to the memory cell array can directly send a memory-type data read instruction to the memory, and read from the memory cell array based on the memory read instruction. Under this control scheduling method, the memory can achieve a faster data read rate.

[0021] In one possible implementation, the controller may send different types of write instructions to the memory based on whether the target write data exists in the data cache unit array:

[0022] In one example, the controller is specifically used to: when the target write data is cached in the data cache cell array, send a first write instruction to the memory, the first write instruction includes a cache type data processing instruction or a memory type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache cell array and the target write data in the memory cell array. In an embodiment of the present application, since the target write data is stored in the data cache cell array, in order to ensure the consistency of data writing, the controller can send a first write instruction to the memory to instruct the memory to update the target write data in the data cache cell array and the memory cell array at the same time. In this way, the controller only needs one write control operation to achieve consistent write modification of the data in the cache part and the memory part, making the consistency update process of the same data stored in the data cache cell array and the memory cell array more convenient.

[0023] In one example, the controller is specifically configured to: when the target write data is not cached in the data cache cell array, send a second write instruction to the memory, the second write instruction being a memory-type data processing instruction, and the second write instruction being used to instruct the memory to write the target write data into the memory cell array. In this embodiment, the controller corresponding to the memory cell array of the memory can write the target write data into the memory cell array through the second write instruction when the target write data does not hit in the data cache cell array. This embodiment implements correct write scheduling processing of the target write data under the storage structure of the data cache cell array and the memory cell array in the same storage die.

[0024] In one possible implementation, corresponding label mapping table entries can be designed for the data cache unit array in the memory. The controller queries the existence of the target data in the data cache unit array based on the label mapping table entries, and can more quickly manage the data in the memory. At this time, the controller is also used to: determine whether a certain target data is cached in the data cache unit array based on the label mapping table entries, and the label mapping table entries include cache tags, and the cache tags are used to indicate the address of the data in the data cache unit array. In an embodiment of the present application, when the controller outputs different types of data processing instructions, it can determine what kind of modification processing has been performed on the data in the memory. Therefore, the controller can make corresponding modifications to the stored label mapping table entries when outputting the corresponding data processing instructions. Under this implementation, the controller can quickly query the hit status of the target data, and can also manage the label mapping table entries very conveniently.

[0025] Exemplarily, the storage and management of the tag mapping table entries may be implemented based on an existing cache array in the controller.

[0026] Exemplarily, the controller includes a tag cache cell array, which is used to cache tag mapping table entries. In an embodiment of the present application, a complete cache cell array (cache array) includes a tag cache cell array (tag array) area and a data cache cell array (data array) area. A data cache cell array is designed in the memory, and a corresponding tag cache cell array can be designed in the controller to manage the tag mapping table entries. At the same time, when multiple storage grains are designed in the memory, each storage grain has a corresponding data cache cell array and memory cell array. However, because the tag mapping table entry records the storage address mapping relationship of the target data in the data cache cell array, different data cache cell arrays can correspond to multiple different tag mapping table entries in the controller, or a tag mapping table entry can be designed in the controller to record the mapping relationship of all data cache cell arrays.

[0027] In a third aspect, an embodiment of the present application further provides a chip system comprising a controller and a memory. The memory comprises at least one storage crystal, each storage crystal being provided with a data cache unit array and a memory unit array. The memory unit array is used to store processed data. The data cache unit array is used to cache part of the processed data in the corresponding memory unit array. The controller is used to output cache-type data processing instructions or memory-type data processing instructions to the memory based on the presence or absence of target data in the data cache unit array. The memory is used to perform data processing on the target data according to the data processing instructions.

[0028] Fourthly, embodiments of the present application further provide a data processing method, which is applied to a memory device, the memory device including at least one memory die, each memory die being provided with a data cache cell array and a memory cell array. The memory cell array is used to store processed data; the data cache cell array is used to cache portions of the processed data. The method comprises: receiving a cache-type data processing instruction or a memory-type data processing instruction from a controller, depending on whether target data is present in the data cache cell array; and performing data processing on the target data according to the data processing instruction.

[0029] In a possible embodiment, the above-mentioned receiving a cache-type data processing instruction or a memory-type data processing instruction from the controller according to whether the target data is in the data cache unit array includes: when the target read data is cached in the data cache unit array, receiving a cache read instruction from the controller, the cache read instruction is a cache-type data processing instruction, and the cache read instruction is used to instruct the memory to feedback the target read data from the memory cell array to the controller.

[0030] In a possible embodiment, the above-mentioned receiving a cache-type data processing instruction or a memory-type data processing instruction from the controller according to whether there is target data in the data cache unit array includes: when there is no target read data cached in the data cache unit array, receiving a memory read instruction from the controller, the memory read instruction is a memory-type data processing instruction, and the memory read instruction is used to instruct the memory to feed back the target read data from the data cache unit array to the controller.

[0031] In one possible embodiment, depending on whether there is target data in the data cache unit array, a cache type data processing instruction or a memory type data processing instruction is received from the controller, including: when target write data is cached in the data cache unit array, a first write instruction is received from the controller, the first write instruction includes a cache type data processing instruction or a memory type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache unit array and the target write data in the memory cell array.

[0032] In a possible implementation, the method further includes: writing the target read data into the data cache unit array in response to a memory read instruction.

[0033] In a possible embodiment, the above-mentioned receiving a cache-type data processing instruction or a memory-type data processing instruction from the controller according to whether the target data is in the data cache unit array includes: when the target write data is not cached in the data cache unit array, receiving a second write instruction from the controller, the second write instruction is a memory-type data processing instruction, and the second write instruction is used to instruct the memory to write the target write data to the memory cell array.

[0034] In a fifth aspect, an embodiment of the present application further provides a data processing method, which is applied to a controller. The controller is used to connect to a memory. The memory includes at least one storage die, each of which is provided with a data cache unit array and a memory unit array. The memory unit array is used to store processed data. The data cache unit array is used to cache part of the processed data in the corresponding memory unit array. The method includes: powering on and starting the machine; after powering on and starting the machine, sending a cache-type data processing instruction or a memory-type data processing instruction to the memory based on whether the target data is in the data cache unit array.

[0035] In a possible embodiment, the above-mentioned sending of cache-type data processing instructions or memory-type data processing instructions to the memory based on the presence or absence of target data in the data cache unit array includes: when target read data is cached in the data cache unit array, sending a cache read instruction to the memory, the cache read instruction being a cache-type data processing instruction, and the cache read instruction being used to instruct the memory to feed back the target read data from the data cache unit array to the controller.

[0036] In a possible embodiment, the above-mentioned sending a cache-type data processing instruction or a memory-type data processing instruction to the memory based on the presence or absence of target data in the data cache unit array includes: when the target read data is not cached in the data cache unit array, sending a memory read instruction to the memory, the memory read instruction is a memory-type data processing instruction, and the memory read instruction is used to instruct the memory to feedback the target read data from the memory cell array to the controller.

[0037] In a possible embodiment, the above-mentioned sending a cache-type data processing instruction or a memory-type data processing instruction to the memory based on the presence or absence of target data in the data cache unit array includes: when the target write data is cached in the data cache unit array, sending a first write instruction to the memory, the first write instruction including a cache-type data processing instruction or a memory-type data processing instruction, the first write instruction being used to instruct the memory to update the target write data in the data cache unit array and the target write data in the memory cell array.

[0038] In a possible embodiment, the above-mentioned sending a cache-type data processing instruction or a memory-type data processing instruction to the memory based on the presence or absence of target data in the data cache unit array includes: when the target write data is not cached in the data cache unit array, sending a second write instruction to the memory, the second write instruction being a memory-type data processing instruction, and the second write instruction being used to instruct the memory to write the target write data into the memory cell array.

[0039] In a possible implementation, the method further includes: determining whether a target data is cached in the data cache unit array based on a tag mapping table entry, the tag mapping table entry including a cache tag, and the cache tag is used to indicate the address of the data in the data cache unit array.

[0040] In a sixth aspect, an embodiment of the present application further provides an electronic device comprising a circuit board and a chip system, wherein the chip system is disposed on the circuit board. The chip system comprises the memory as described in the first aspect above and the controller as described in the second aspect above. The controller is connected to the memory.

[0041] In the seventh aspect, an embodiment of the present application also provides a computer-readable storage medium, which includes instructions. When the instructions are executed on a processing device, the processing device executes the data processing method described in the fourth aspect or the data processing method described in the fifth aspect.

[0042] Regarding the technical principles and beneficial effects of the second, third, fourth, fifth, sixth and seventh aspects, please refer to the relevant description of the first aspect above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of the structure of a storage processing architecture provided by an embodiment of the present application in different application scenarios;

[0044] FIG2 is a schematic structural diagram of a second memory provided in an embodiment of the present application;

[0045] FIG3 is a first structural diagram of a chip system provided in an embodiment of the present application;

[0046] FIG4 is a second structural diagram of a chip system provided in an embodiment of the present application;

[0047] FIG5 is a flowchart of a data processing method according to an embodiment of the present application;

[0048] FIG6 is a second flow chart of a data processing method provided in an embodiment of the present application;

[0049] FIG7 is a schematic diagram of a control logic flow when reading target data from a third memory according to an embodiment of the present application;

[0050] FIG8 is a schematic diagram of a control logic flow when writing target data into a third memory provided by an embodiment of the present application. DETAILED DESCRIPTION

[0051] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0052] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0053] The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a physical direct connection, or they may refer to an indirect connection achieved through an electronic device, such as a connection achieved through a bus, resistor, inductor, capacitor or other electronic device. At the same time, depending on the product device and application scenario, the bus may also be a bus based on different protocols or different selections. For example, the bus may be a Peripheral Component Interconnect Express (PCIe) high-speed bus, a Compute Express Link (CXL) bus, a Universal Serial Bus (USB) protocol or other protocol bus, etc. In addition, the embodiments of the present application do not limit the number of buses, etc.

[0054] First, some basic concepts involved in the embodiments of this application are explained:

[0055] Electronic devices include processing devices that process data and instructions. The data may include programs, images, and numerical values. Typically, electronic devices require storage devices to temporarily or permanently store this data. Depending on the application scenario, different application architectures for processing and storage devices can be designed. The following examples illustrate some common application architectures:

[0056] Figure 1 (a) exemplarily provides a schematic structural diagram of a combination of a processing device and a storage device. In the structure shown in Figure 1 (a), a processor 100 and a memory 200 are included. The processor 100 and the memory 200 are connected via a bus BUS1. A register group 110 is provided in the processor 100, and the register group 110 includes a plurality of registers. Different registers can be used to store different contents, such as instructions, addresses, parameters or data. Among them, the memory 200 is a memory, which can also be called main memory. When the processor 100 needs to run a process, the memory 200 obtains the relevant running program data from the flash memory device or flash memory device based on the relevant data query acquisition instruction (such as a load instruction). Then, based on a load instruction, the processor 100 retrieves the data or instructions required for the process from the memory 200 and stores them in the register file 110 within the processor 100. Alternatively, based on a store instruction, the processor 100 updates the data in the register file 110 into the memory 200, or writes data into the memory 200. Typically, the data processing rate of the register file 110 is very fast, reaching over a hundred times the data processing rate of the memory 200. Therefore, this situation can lead to a memory wall phenomenon. The memory wall phenomenon refers to the phenomenon in which the data processing rate of the memory 200, as a memory, is significantly lower than the data processing rate of the processor 100, resulting in the actual processing performance of the processor 100 being limited by the relatively low data processing rate of the memory 200. Improving the read rate of the memory 200 depends on improvements in materials and processes. Significantly increasing the data processing rate of the memory 200 requires very high device costs.

[0057] In order to solve the problem of memory wall caused by the large speed difference between the processor 100 and the memory 200 at a lower device cost, one solution is to add a cache between the register group 110 of the processor 100 and the memory 200. The processing speed of the cache is faster than that of the memory 200, by storing part of the data in the memory 200 in the cache. When the processor 100 needs to access and read a certain target read data in the memory 200, it can first check whether the target read data is stored in the cache. If the target read data is stored in the cache, the target read data can be directly accessed and read from the cache. Compared with the method of reading from the memory 200, the method of reading from the cache can greatly reduce the data reading time of the processor 100.

[0058] In a cache, the size of the cache's storage space is called the cache size, which represents the maximum size of data that the cache can cache. The cache's storage space is typically divided into multiple equal memory blocks, each of which is called a cache line. The cache line size is the smallest unit of granularity for the size of data transferred between the memory 200 and the cache. This means that the cache can only read one or more cache line-sized data from the memory 200 at a time, or can only write one or more cache line-sized data to the memory 200 at a time.

[0059] The cache includes multiple cache units, each of which can store data of a corresponding number of bits. Multiple cache units can form a cache unit array (cache array) of the cache. The cache unit array can be divided into two array areas, namely the tag cache unit array (tag array) and the data cache unit array (data array). The tag cache unit array is used to assist in the search of the storage address area of ​​the data cache unit array of the cache. The specific implementation method is: the storage address area of ​​the data cache unit array of the cache is represented according to the address bit width information, and the address bit width information includes a cache tag (tag), an index (index) and an offset (offset). Wherein:

[0060] A cache tag (tag) is address mapping information in the cache that is used to identify a portion of the storage address of the memory 200. The cache tag is stored in the tag cache unit array of the cache. When the processor 100 needs to access a certain target read data, it will first query the tag cache unit array in the cache to determine whether the required target read data has been cached in the cache. If the relevant cache tag is queried, it indicates a hit, that is, the target read data is stored in the cache, and the processor 100 can read the target read data directly from the cache. If the relevant cache tag is not queried, it indicates a miss, that is, the target read data is not stored in the cache, and the target read data needs to be read from the memory 200.

[0061] The index is used to determine which group (or row) in the cache's data cache cell array stores the desired target data when the processor 100 confirms a hit. The cache's data cache cell array is typically divided into multiple groups, each containing multiple cache lines. The number of bits in the index determines the number of groups in the cache. When the target data is hit, the index can be used to quickly locate the group containing the desired target data.

[0062] The offset is used to determine the location of the desired target data within the corresponding cache line. The number of bits in the offset determines the address range within the cache line. The offset can be used to determine the location of the desired data within the cache line, thereby locating the target data.

[0063] In actual applications, there are many different design architectures based on the combination of the processor 100, the memory 200, and the cache. The following are some common architectures for illustration:

[0064] FIG1(b) exemplarily provides a schematic diagram of the structure of a memory 200 and a cache 300 combined. In the structure shown in FIG1(b), a single-level cache 300 is designed between the register group 110 of the processor 100 and the memory 200. In the architecture shown in FIG1(b), the single-level cache 300 can be set inside the processor 100. Although not shown in FIG1(b), the single-machine cache 300 can also be designed to be external to the processor 100. The processor 100, memory 200, and cache 300 are connected via a bus BUS1.

[0065] FIG1(c) provides an exemplary structural diagram of another embodiment of a combination of memory 200 and cache 300. In the structure shown in FIG1(c), a multi-level cache 300 is designed between the register file 110 of the processor 100 and the memory 200. The multi-level cache 300 is designed within the processor 100 for illustration: the processor 100 may include one or more processing cores, and each processing core is provided with a register file 110 and an L1-level cache 300 and an L2-level cache 300. In addition, a shared L3-level cache 300 is also provided for multiple processing cores. The L1-level cache 300 can be used to store instructions or data required for the operation of the corresponding processing core. The L2-level cache 300 is a cache device shared by all L1-level caches 300 in the corresponding processing core. The L3-level cache 300 is a cache device shared by all processing cores in the processor 100. Different caches 300 in the multi-level cache 300 can store portions of data in the memory 200 for use by the processor 100. Although not shown in FIG1(c), in some other embodiments, the L3 level cache 300 can also be designed external to the processor 100. The multi-level division in FIG1(c) is only an example. In actual applications, new levels of caches 300 can be added, and some levels of caches 300 can also be deleted.

[0066] FIG1 (d) exemplarily provides a schematic diagram of the structure of another combination of memory 200 and cache 300. In the structure shown in FIG1 (d), a memory controller 400 is designed between the cache 300 and the memory 200. At this time, when the processor 100 needs to run some processes, the memory controller 400 sends relevant data processing instructions (such as write instructions or read instructions, etc.) to the memory 200, thereby reading the data in the memory 200 into the cache 300 for the processor 100 to run, or writing (or updating) the data in the register group 110 or the cache 300 of the processor 100 into the memory 200. By processing the data in the memory 200 through the memory controller 400, the performance occupation caused by the processor 100 performing data handling and other processing operations can be reduced, thereby improving the processing performance of the processor 100. In addition, different data scheduling strategies can be configured in the memory controller 400 to improve the hit rate of the cache 300 with respect to the target data. For example, the memory controller 400 can execute relevant algorithm strategies to predict the data required by the processor 100 and pre-fetch the data in the memory 200 into the cache 300 based on the prediction results, thereby improving the hit rate of the processor 100 when querying the target data from the cache 300, thereby improving the processing speed of the processor 100. Figure 1 (d) illustrates the design of the memory controller 400 in the application scenario of a multi-level cache 300. Although not illustrated, the memory controller 400 can also be used in the application scenario architecture shown in Figures (a), (b), and (c) of Figure 1.

[0067] For example, since cache 300 stores part of the data in memory 200, in order to ensure that the data stored in cache 300 is as much as possible the data required by processor 100, that is, in order to maximize the hit rate of the data in cache 300, some strategies can be used to update the data in cache 300.

[0068] As can be seen from the description of FIG1(a) above, there is a significant difference in data processing rates between processor 100 and memory 200. Although various approaches have been employed in FIG1(b), (c), and (d) above to mitigate the impact of this data processing rate difference on the processing rate of processor 100, advancements in semiconductor process technology have led to rapid advancements in processing device technology, and the processing rate of processor 100 has also increased rapidly. However, advancements in memory device technology have been relatively slow, leading to a widening gap in data processing rates between processor 100 and memory 200, and a more severe memory wall phenomenon. Solutions based on cache 300 in FIG1(b), (c), and (d) no longer meet the requirements for optimizing data processing rates. For example, if memory 200 is dynamic random access memory (DRAM), as memory device technology advances, DRAM size continues to shrink. In smaller DRAM designs, increasing data processing rates becomes increasingly difficult. However, the processing rate of processor 100 increases dramatically with the size and number of semiconductor devices. In addition, in a data read solution based on cache 300 assistance, when the relevant target data is not stored in cache 300 (i.e., a miss), the processor 100 needs to re-read or write the data from memory 200, which will result in a large miss penalty. This is especially true in the multi-level cache 300 structure shown in Figures (c) and (d) of Figure 1. In addition, when writing data, the data consistency between cache 300 and memory 200 must also be considered.

[0069] In a related technology, the memory 200 shown in FIG1 may be a first memory having storage rows with different rates. Specifically, a portion of storage rows may be designed in the memory cell array of the first memory, and the read rate of this portion of storage rows is slightly faster than that of the storage rows of other portions. The storage cell rows with a slightly faster read rate are used as cache devices for the storage rows of other portions. However, under this embodiment, the storage cells in all storage rows are essentially the same type of storage cells, that is, the rate difference between the fast rate storage row (fast row) and the slow rate storage row (slow row) is not obvious. At present, this solution is still in the theoretical stage, and its degree of optimization of the processing rate of the processor 100 is very limited. In addition, this solution does not support simultaneous read access of two storage cell rows with different rates.

[0070] In another related technology, the memory 200 described in FIG1 may be a second memory packaged with dies of different memory types. As shown in FIG2 , the second memory 200B includes a first die 1, a second die 2, a first data interface circuit 101, and a second data interface circuit 102. A cache cell array 210B is provided on the first die 1, and a memory cell array 220 is provided on the second die 2. The first data interface circuit 101 and the second data interface circuit 102 are respectively connected to the processor 100, the cache 300, or the memory controller 400 via a bus BUS1. The cache cell array 210B is connected to the first data interface circuit 101 to facilitate data exchange between the cache cell array 210B and the processor 100, the cache 300, or the memory controller 400. The memory cell array 220 is connected to the second data interface circuit 102 to facilitate data exchange between the memory cell array 220 and the processor 100, the cache 300, or the memory controller 400. In this application, the cache and memory die are simply structurally packaged together, but the two arrays remain independent of each other, meaning data exchange continues via independent IO interfaces. The two arrays also independently perform related data processing based on corresponding data processing instructions. Furthermore, although not shown in FIG2 , the designs of the two control devices or control circuits, or other peripheral circuits, also remain independent. Therefore, the embodiment of FIG2 is essentially not much different from a solution that designs cache 300 and memory 200 separately.

[0071] In order to further reduce the performance limitations of the memory device on the performance of the processing device, an embodiment of the present application provides an electronic device, which includes a circuit board and a chip system, wherein the chip system is arranged on the circuit board. As shown in Figure 3, the chip system 1000 includes a controller X and a third memory 200C. The controller X can be the processor 100 in the application scenario shown in Figures (a), (b), and (c) of Figure 1 above, or it can be the memory controller 400 in the application scenario shown in Figure (d) of Figure 1 above. The third memory 200C includes at least one memory die 3. Each memory die 3 is provided with a data cache unit array (data array) 210C and a memory unit array (memory array) 220. The memory unit array 220 is used to store processing data. The data cache unit array 210C is used to cache part of the processing data. The controller X is used to: send a cache-type data processing instruction or a storage-type data processing instruction to the third memory 200C based on the presence or absence of target data in the data cache unit array. Correspondingly, the third memory 200C is configured to receive a cache-type data processing instruction or a storage-type data processing instruction from the controller X according to whether the target data exists in the data cache unit array.

[0072] For example, the cache units in the data cache unit array 210C may be based on a static random access memory (SRAM) storage cell structure.

[0073] Exemplarily, the memory cells in the memory cell array 220 can be a memory cell structure of any of the following technologies: ferroelectric random access memory (FeRAM) technology, dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) technology, double data rate synchronous dynamic random access memory (DDR SDRAM) technology, enhanced synchronous dynamic random access memory (ESDRAM) technology, synchronous link dynamic random access memory (SLDRAM) technology, and direct rambus RAM (DR RAM) technology, etc.

[0074] Exemplarily, as shown in FIG3 , the third memory 200C includes a data interface circuit 230C, the data cache unit array 210C and the memory cell array 220 are respectively connected to the data interface circuit 230C, and the data interface circuit 230C is connected to the controller X. The third memory 200C is used to: exchange target data with the controller X based on the data interface circuit 230C. In the embodiment of the present application, because the data cache unit array 210C and the memory cell array 220 are processed on the same die, the data interface circuit 230C of the memory cell array 220 can be reused to exchange target data. Among them, exchanging target data with the controller X can refer to transmitting target read data to the controller X, or obtaining target write data from the controller X; it can also refer to transmitting target read data to the buffer 300 designated by the controller X, or obtaining target write data from the buffer 300 designated by the controller X.

[0075] With the advancement of semiconductor process technology, current memory fabrication processes have reached the point where a cache array and a memory cell array 220 can be fabricated on the same die. In existing memory devices, the memory cell array 220 is fabricated using the memory cell array 220 as a memory die. Data stored in the memory cell array 220 can be processed based on a controller X, for example, based on the processor 100 shown in Figures (a), (b), and (c) of Figure 1 , or based on the memory controller 400 shown in Figure 1 (d). In the embodiment of the present application, as shown in Figure 3 , the data cache cell array 210C, which is used to store data in the cache array, and the memory cell array 220 are fabricated on the same die using the same fabrication process, resulting in a third memory 200C. In the third memory 200C, the data cache cell array 210C serves as a cache for the corresponding memory cell array 220, storing a portion of the processed data located in the memory cell array 220. In this embodiment, the data cache cell array 210C does not have an independent corresponding control circuit or control device. When controller X needs to process target data, controller X corresponding to the multiplexed memory cell array 220 directly outputs a corresponding type of data processing instruction, such as a cache-type data processing instruction or a memory-type data processing instruction, based on whether the target data hits or misses in the data cache cell array 210C. This embodiment has the following advantages:

[0076] Advantage 1: Data cache cell array 210C and memory cell array 220 reuse the memory cell array's control device for data read control, making data access, read, and write control simpler and more efficient. Furthermore, using the same control device for control makes it easier to manage data consistency between data cache cell array 210C and memory cell array 220.

[0077] Advantage 2: When the memory cell array 220 of the memory device performs read and write processing, it needs to perform auxiliary operations such as activation and pre-charge, which results in a certain data processing delay, etc., while the data cache cell array 210C does not need to perform these auxiliary operations. Combined with the advantages of the data cache cell array 210C in process and materials, its data processing rate is much higher than the data processing rate of the memory cell array 220. The processing performance of the processing device is improved by the data cache cell array 210C with a high data processing rate. In addition, the embodiment shown in Figure 3 is compatible with the solution of the memory 200 in Figure 1, the solution of the first memory, and the solution of the second memory 200B, so as to further improve the processing performance of the processing device.

[0078] Advantage 3: The data cache cell array 210C can further reduce the number and frequency of direct accesses to the memory cell array 220. For example, with a 4MB per row data cache cell array 210C, the number of direct accesses to the memory cell array 220 can be reduced by 50%. This can alleviate crosstalk issues during data processing within the memory cell array 220, thereby increasing the device lifespan of the memory cell array 220.

[0079] Advantage 4: The data cache unit array 210C has lower dynamic reading and writing power consumption, which can reduce the power consumption of memory devices.

[0080] Advantage 5: The data cache cell array 210C and the memory cell array 220 are fabricated on the same die, resulting in higher integration and lower area overhead. Furthermore, compared to designs with separate cache 300 and memory 200, or the separate first die 1 and second die 2 shown in the embodiment of FIG. 2 , data exchange latency is lower.

[0081] In the embodiment of the present application, the processing data stored in the memory cell array 220 in the embodiment shown in Figure 3 should be interpreted in an expanded manner, that is, the processing data not only includes the data required for calculation when running the process, but also includes the instructions required when executing the process (including logical operation instructions, control instructions and data processing instructions, etc.).

[0082] In some possible implementations, controller X is reused to control and manage the data processed in the data cache array 210C and the memory cell array 220 (including writing, reading, and data transfer). To ensure that controller X more efficiently controls and manages data processing, a tag mapping table entry corresponding to the data stored in the data cache array 210C can be set in controller X. Based on the cache tag in the tag mapping table entry, controller X can quickly query whether the target data is stored in the data cache array 210C. Based on the query result (hit or miss), it directly sends a cache-type data processing instruction or a memory-type data processing instruction to the third memory 200C. This implementation improves the efficiency of data scheduling and instruction transmission.

[0083] In some examples, a related cache array in controller X may be reused to store tag mapping table entries.

[0084] In some examples, a tag cache unit array (tag array) can be designed in controller X, and tag mapping table entries can be stored based on the tag cache unit array. For example, as shown in FIG4 , the solution of the embodiment shown in FIG3 is applied to the architecture shown in FIG1 (d) above. In the embodiment shown in FIG3 , controller X can be memory controller 400. A tag cache unit array 410 is designed in memory controller 400 to store tag mapping table entries.

[0085] For example, as shown in FIG4 , when there are multiple storage dies die3, each of the multiple storage dies die3 has a memory cell array 220 and a corresponding data cache cell array 210C. Each data cache cell array 210C stores part of the data in the corresponding memory cell array 220. However, because the cache tag is used to indicate the address of the data in the data cache cell array 210C, that is, different tags are essentially used to map different address areas in the data cache cell array 210C. Therefore, the cache tags that characterize the address area mapping relationship of the data cache cell arrays 210C in different storage dies die3 can be recorded in the same tag mapping table entry or in different tag mapping table entries, and the embodiments of the present application do not limit this.

[0086] Based on the chip system 1000 including the architecture of FIG. 3 and FIG. 4 , a data processing method including operations of steps S100 to S300 as shown in FIG. 5 and FIG. 6 may be executed:

[0087] S100, controller X is powered on and started.

[0088] For example, when the controller X is the processor 100 shown in Figures (a), (b), and (c) of Figure 1 , the controller X can execute certain process programs. Before executing the process program, the controller X needs to retrieve relevant target data from the third memory 200C. Alternatively, during the execution of the process program, the controller X needs to retrieve relevant target data from the third memory 200C. The target data may include computational data or execution instructions required to execute the process.

[0089] For example, when the controller X is the memory controller 400 shown in FIG. 1( d ), the controller X may also execute certain operating programs. The operating programs may be data pre-scheduling or processing, or processing operations executed in response to certain control instructions or data processing instructions of the processor 100. Based on the requirements of the aforementioned operating processes, the controller X, as the memory controller 400, also needs to obtain relevant target data from the third memory 200C. Such target data may also include computational data or operating instructions.

[0090] S200: The controller X sends a cache-type data processing instruction or a memory-type data processing instruction to the third memory 200C.

[0091] In an embodiment of the present application, as shown in FIG5 , in step S200 , the controller X can send a cache-type data processing instruction or a memory-type data processing instruction to the third memory 200C based on whether the target data is in the data cache unit array 210C. Accordingly, as shown in FIG6 , when the controller X sends a data processing instruction to the third memory 200C in step S200 , the third memory 200C will also receive a cache-type data processing instruction or a memory-type data processing instruction from the controller X based on whether the target data is in the data cache unit. The following examples illustrate reading data from and writing data to the third memory 200C:

[0092] In some possible implementations, when the controller X needs to read target read data from the third memory 200C, the controller X may query whether the target read data hits the data cache unit array 210C, and send different types of read instructions to the third memory 200C based on whether the target read data hits.

[0093] In one example, when the target read data is cached in the data cache cell array 210C, the controller X sends a cache read instruction to the third memory 200C. The cache read instruction is used to instruct the third memory 200C to feedback the target read data from the data cache cell array 210C to the controller X. In one example, when the target read data is not cached in the data cache cell array 210C, the controller X sends a memory read instruction to the third memory 200C. The memory read instruction is used to instruct the third memory 200C to feedback the target read data from the memory cell array 220 to the controller X. In an embodiment of the present application, when the target read data is cached in the data cache cell array 210C, the controller X can access and read the target read data from the data cache cell array 210C without accessing and reading the memory cell array 220. When the target read data is not cached in the data cache cell array 210C, the controller X needs to access and read the target read data from the memory cell array 220. This implementation can reduce the number of times the memory cell array 220 is accessed and read, thereby increasing the service life of the memory cell array 220 .

[0094] For example, when the chip system 1000 is applied to an architecture not including the cache 300 as shown in FIG. 1 (a), the controller X may be the processor 100. In this case, the third memory 200 may transmit the target read data from the data cache cell array 210C or the memory cell array 220 back to the processor 100.

[0095] Exemplarily, when the chip system 1000 is applied to the architecture shown in Figures (b), (c) and (d) of Figure 1, the third memory 200 can feedback the target read data from the data cache cell array 210C or the memory cell array 220 to the cache 300, and the processor 100 reads the target read data from the cache 300.

[0096] In some possible implementations, when the controller X needs to write target write data to the memory cell array 220 in the third memory 200C, the controller X may query whether the target write data hits the data cache cell array 210C, and send different types of write instructions to the third memory 200C based on whether the target write data hits the data.

[0097] In one example, when target write data is cached in the data cache cell array 210C, a first write instruction is sent to the third memory 200C. The first write instruction is used to instruct the third memory 200C to update the target write data in the data cache cell array 210C and the target write data in the memory cell array 220. In this embodiment of the present application, since the target write data is stored in the data cache cell array 210C, in order to ensure the consistency of data writes, the controller X can output the first write instruction to instruct the third memory 200C to simultaneously update the target write data in the data cache cell array 210C and the memory cell array 220. In this way, a single write control operation can achieve consistent write modification of data in the cache portion and the memory portion.

[0098] Exemplarily, the first write instruction can be a data processing instruction including a cache-type write processing instruction and a memory-type write processing instruction, and the third memory 200C performs write update processing on the target write data of the two arrays according to the two types of write instructions. Alternatively, the first write instruction can also be a cache-type write processing instruction. Because the data in the data cache cell array 210C is part of the data in the memory cell array 220, the third memory 200C can also simultaneously perform write update processing on the target write data in the two arrays when receiving the cache-type write processing instruction. Alternatively, the first write instruction can also be a memory-type write processing instruction. By setting a flag bit in a traditional memory-type write processing instruction, the third memory 200C is instructed to update the target write data in the data cache cell array 210C when updating the target write data in the memory cell array 220 based on the value of the flag bit.

[0099] In one example, when the target write data is not cached in the data cache cell array 210C, a second write instruction is sent to the third memory 200C. The second write instruction is used to instruct the third memory 200C to write the target write data into the memory cell array 220. In an embodiment of the present application, when there is no target write data in the data cache cell array 210C, the controller X only needs to write the target write data into the memory cell array 220. Exemplarily, the target write data can be data not stored in the memory cell array 220, and the third memory 200C writes the target write data into the memory cell array 220 based on the second write instruction. Exemplarily, the target write data can be data stored in the memory cell array 220, and the third memory 200C updates the target write data with an updated value into the memory cell array 220 based on the second write instruction.

[0100] In some possible implementations, the controller X determines whether target data is cached in the data cache unit array 210C based on the tag mapping table entry, that is, determines whether the target write data or the target write data hits in the data cache unit array 210C. The technical principles and beneficial effects of the tag mapping table entry can be found in the related description of the hardware embodiment above and will not be elaborated here.

[0101] S300 : The third memory 200C processes the target data according to the data processing instruction.

[0102] In the embodiment of the present application, the third memory 200C performs corresponding data processing operations according to the type of the received data processing instruction. For detailed description of the data processing operation performed by the third memory 200C, please refer to the relevant description in the above step S300, which will not be repeated here.

[0103] In some possible implementations, the third memory 200C is further configured to write the target read data into the data cache cell array 210C in response to a memory read instruction. In an embodiment of the present application, only when the target read data is not stored in the data cache cell array 210C will the controller X send a memory-type data processing instruction (i.e., a memory read instruction) to the third memory 200C to obtain the target read data from the memory cell array 220. Because the function of the data cache cell array 210C is to store part of the data in the memory cell array 220, the number of accesses to the memory cell array 220 is reduced and the processing rate of the target data is increased. In order to achieve this goal as much as possible, the data stored in the data cache cell array 210C is generally data frequently used by processing devices such as the processor 100. Because the target read data is the data currently being processed and is not stored in the data cache unit array 210C, the third memory 200C can simultaneously store the target write data in the data cache unit array 210C while writing the target read data to the memory cell array 220 based on the memory read instruction, so that the target read data can be read from the data cache unit array 210C the next time it is accessed.

[0104] Similarly, when executing the second write instruction, the third memory 200C can also write the target write data into the data cache unit array 210C. Regarding the technical principles and beneficial effects of writing the target write data into the data cache unit array 210C based on the second write instruction, reference can be made to the above description of writing the target read data into the data cache unit array 210C in response to the memory read instruction, and will not be repeated here.

[0105] In some possible implementations, the data cache cell array 210C is used as a cache device for the memory cell array 220. Therefore, the selection of data stored in the data cache cell array 210C is related to the hit rate and coverage rate of the target data. In order to maximize the availability of cached data, a relevant cache data update strategy can be designed in the third memory 200C to update the data in the data cache cell array 210C, thereby ensuring that the updated data can meet the current needs of the processor 100 as much as possible. Exemplarily, one update strategy is to store a portion of the data with the highest number of uses in the data cache cell array 210C based on the number of times the processor 100 uses the data. Under this implementation, the third memory 200C can establish a least recently used (LRU) table entry, which is used to record the most recent use time and number of uses of the data in the data cache cell array 210C. According to the LRU table entry, data with a small number of uses and a long recent use time is deleted, and the cache is updated with new data. In this process, the third memory 200C may update the LRU table entry according to the data processing operation on the data cache unit array 210C (eg, the data processing operation performed based on the cache read instruction and the first write instruction).

[0106] For example, as shown in FIG7 , controller X is taken as memory controller 400. When the processor 100 needs to read target read data from the third memory 200C, the memory controller 400, in response to the processor 100's read request for the target read data, queries the tag mapping table entry to determine whether the target read data is found in the data cache cell array 210C. When the target read data is stored in the data cache cell array 210C, the memory controller 400 outputs a cache read instruction. In response to the cache read instruction, the third memory 200C updates the number of uses and the most recent use time of the target read data in the LRU table entry and extracts the target read data from the data cache cell array 210C for feedback. Conversely, if the memory controller 400 determines that the target read data is not found in the data cache cell array 210C after querying the tag mapping table entry, the memory controller 400 outputs a memory read instruction to access and read the target read data from the memory cell array 220. In response to the memory read instruction, the third memory 200C extracts the target read data from the memory cell array 220 and feeds it back, for example, feeding the target read data back to the cache 300 of the last level of the processor 100. Simultaneously, in response to the memory read instruction, the third memory 200C may also record the number of times the target read data has been used and the time of its most recent use in an LRU entry, and cache the target read data in the data cache cell array 210C.

[0107] For example, as shown in FIG8 , controller X is memory controller 400. When processor 100 needs to write target write data to third memory 200C, memory controller 400, in response to processor 100's request for the target write data, queries the tag mapping table entry to determine whether the target write data is found in data cache cell array 210C. If the target write data is stored in data cache cell array 210C, memory controller 400 outputs a first write instruction. In response to the first write instruction, third memory 200C updates the usage count and most recent usage time of the target write data in the LRU table entry and performs a pass-through write operation () to update the target write data in data cache cell array 210C and memory cell array 220, respectively. Conversely, if memory controller 400 determines, after querying the tag mapping entry, that the target write data is not found in data cache cell array 210C, memory controller 400 outputs a second write instruction. In response to the second write instruction, third memory 200C writes the target write data into memory cell array 220.

[0108] An embodiment of the present application also provides a computer-readable storage medium, which includes instructions. When the instructions are executed on a processing device (such as the controller or processor or third memory described in the above embodiments), the processing device executes the data processing method described in the above embodiments (such as the method described in the embodiments of Figures 5, 6, 7 and 8).

[0109] The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0110] The electronic devices involved in the embodiments of the present application may be mobile phones, desktop computers, laptop computers, smart cockpit equipment, communication equipment, image processing equipment, artificial intelligence computing equipment, image acquisition equipment, power supply control equipment, and other devices with memory and control devices.

[0111] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0112] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0113] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0115] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of this embodiment based on actual needs.

[0116] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0117] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0118] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: The invention comprises at least one storage die, each of which is provided with a data cache unit array and a memory unit array; the memory unit array is used to store processing data; the data cache unit array is used to cache part of the processing data; wherein the memory is used to: receiving a cache-type data processing instruction or a memory-type data processing instruction from a controller according to whether the target data exists in the data cache unit array; The target data is processed according to the data processing instruction.

2. The memory according to claim 1, wherein The memory is specifically used for: When target read data is cached in the data cache unit array, a cache read instruction is received from the controller. The cache read instruction is a cache type data processing instruction, and the cache read instruction is used to instruct the memory to feed back the target read data from the data cache unit array to the controller.

3. The memory according to claim 1, wherein: The memory is specifically used for: When the target read data is not cached in the data cache unit array, a memory read instruction is received from the controller, where the memory read instruction is a memory-type data processing instruction, and is used to instruct the memory to feed back the target read data from the memory storage unit array to the controller.

4. The memory according to claim 3, wherein: The memory is further used for: In response to the memory read instruction, the target read data is written into the data cache unit array.

5. The memory according to any one of claims 1 to 4, characterized in that: The memory is specifically used for: When target write data is cached in the data cache unit array, a first write instruction is received from the controller, wherein the first write instruction includes a cache-type data processing instruction or a memory-type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache unit array and the target write data in the memory cell array.

6. The memory according to any one of claims 1 to 4, characterized in that: The memory is specifically used for: When the target write data is not cached in the data cache unit array, a second write instruction is received from the controller, where the second write instruction is a memory-type data processing instruction and is used to instruct the memory to write the target write data into the memory cell array.

7. The memory according to any one of claims 1 to 6, characterized in that: The memory includes a data interface circuit, the data cache unit array and the memory unit array are respectively connected to the data interface circuit, and the data interface circuit is connected to the controller; the memory is used to: The target data is exchanged with the controller based on the data interface circuit.

8. A controller, characterized in that: The controller is used to connect to the memory; the memory includes at least one memory chip, each of which is provided with a data cache unit array and a memory cell array; the memory cell array is used to store processing data; the data cache unit array is used to cache part of the processing data in the corresponding memory cell array; the controller is used to: Power on and start running; After the power-on startup, a cache type data processing instruction or a memory type data processing instruction is sent to the memory according to whether the target data exists in the data cache unit array.

9. The controller according to claim 8, characterized in that The controller is specifically used for: When target read data is cached in the data cache unit array, a cache read instruction is sent to the memory. The cache read instruction is a cache type data processing instruction, and the cache read instruction is used to instruct the memory to feed back the target read data from the data cache unit array to the controller.

10. The controller according to claim 8, characterized in that The controller is specifically used for: When the target read data is not cached in the data cache unit array, a memory read instruction is sent to the memory, where the memory read instruction is a memory-type data processing instruction, and is used to instruct the memory to feed back the target read data from the memory cell array to the controller.

11. The controller according to any one of claims 8 to 10, characterized in that: The controller is specifically used for: When target write data is cached in the data cache unit array, a first write instruction is sent to the memory, wherein the first write instruction includes a cache-type data processing instruction or a memory-type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache unit array and the target write data in the memory cell array.

12. The controller according to any one of claims 8 to 10, characterized in that: The controller is specifically used for: When the target write data is not cached in the data cache unit array, a second write instruction is sent to the memory, where the second write instruction is a memory-type data processing instruction and is used to instruct the memory to write the target write data into the memory cell array.

13. The controller according to any one of claims 8 to 12, characterized in that: The controller is also used for: Whether a certain target data is cached in the data cache unit array is determined based on a tag mapping table entry, wherein the tag mapping table entry includes a cache tag, and the cache tag is used to indicate the address of the data in the data cache unit array.

14. The controller according to claim 13, characterized in that The controller includes a tag cache unit array, and the tag cache unit array is used to cache the tag mapping table entries.

15. A chip system, characterized in that: The system comprises a controller and a memory; the memory comprises at least one memory die, each of which is provided with a data cache unit array and a memory cell array; the memory cell array is used to store processed data; the data cache unit array is used to cache part of the processed data in the corresponding memory cell array; wherein: The controller is configured to: output a cache type data processing instruction or a memory type data processing instruction to the memory according to whether the target data is in the data cache unit array; The memory is used to perform data processing on the target data according to the data processing instruction.

16. A data processing method, characterized in that: Applied to a memory, the memory comprises at least one memory die, each of the memory die being provided with a data cache unit array and a memory unit array; The memory cell array is used to store processing data; The data cache unit array is used to cache part of the processed data; the method includes: receiving a cache-type data processing instruction or a memory-type data processing instruction from a controller according to whether the target data exists in the data cache unit array; The target data is processed according to the data processing instruction.

17. The data processing method according to claim 16, characterized in that: The receiving, from the controller, a cache-type data processing instruction or a memory-type data processing instruction according to whether the target data exists in the data cache unit array, includes: When target read data is cached in the data cache unit array, a cache read instruction is received from the controller. The cache read instruction is a cache type data processing instruction, and the cache read instruction is used to instruct the memory to feed back the target read data from the memory cell array to the controller.

18. The data processing method according to claim 16, characterized in that: The receiving, from the controller, a cache-type data processing instruction or a memory-type data processing instruction according to whether the target data exists in the data cache unit array, includes: When the target read data is not cached in the data cache unit array, a memory read instruction is received from the controller, where the memory read instruction is a memory-type data processing instruction, and is used to instruct the memory to feed back the target read data from the data cache unit array to the controller.

19. The data processing method according to claim 18, characterized in that: The method further comprises: In response to the memory read instruction, the target read data is written into the data cache unit array.

20. The data processing method according to any one of claims 16 to 19, characterized in that: The receiving, from the controller, a cache-type data processing instruction or a memory-type data processing instruction according to whether the target data exists in the data cache unit array, includes: When target write data is cached in the data cache unit array, a first write instruction is received from the controller, wherein the first write instruction includes a cache-type data processing instruction or a memory-type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache unit array and the target write data in the memory cell array.

21. The data processing method according to any one of claims 16 to 19, characterized in that: The receiving, from the controller, a cache-type data processing instruction or a memory-type data processing instruction according to whether the target data exists in the data cache unit array, includes: When the target write data is not cached in the data cache unit array, a second write instruction is received from the controller, where the second write instruction is a memory-type data processing instruction and is used to instruct the memory to write the target write data into the memory cell array.

22. A data processing method, characterized in that: Applicable to a controller; the controller is used to connect to a memory; the memory includes at least one memory crystal, each of which is provided with a data cache unit array and a memory unit array; The memory cell array is used to store processing data; The data cache unit array is used to cache part of the processed data in the corresponding memory cell array; the method includes: Power on and start running; After the power-on startup, a cache type data processing instruction or a memory type data processing instruction is sent to the memory according to whether the target data exists in the data cache unit array.

23. The data processing method according to claim 22, characterized in that: The sending of a cache type data processing instruction or a memory type data processing instruction to the memory according to whether the target data is in the data cache unit array includes: When target read data is cached in the data cache unit array, a cache read instruction is sent to the memory. The cache read instruction is a cache type data processing instruction, and the cache read instruction is used to instruct the memory to feed back the target read data from the data cache unit array to the controller.

24. The data processing method according to claim 22, wherein: The sending of a cache type data processing instruction or a memory type data processing instruction to the memory according to whether the target data is in the data cache unit array includes: When the target read data is not cached in the data cache unit array, a memory read instruction is sent to the memory, where the memory read instruction is a memory-type data processing instruction, and is used to instruct the memory to feed back the target read data from the memory cell array to the controller.

25. The data processing method according to any one of claims 22 to 24, characterized in that: The sending of a cache type data processing instruction or a memory type data processing instruction to the memory according to whether the target data is in the data cache unit array includes: When target write data is cached in the data cache unit array, a first write instruction is sent to the memory, wherein the first write instruction includes a cache-type data processing instruction or a memory-type data processing instruction, and the first write instruction is used to instruct the memory to update the target write data in the data cache unit array and the target write data in the memory cell array.

26. The data processing method according to any one of claims 22 to 24, characterized in that: The sending of a cache type data processing instruction or a memory type data processing instruction to the memory according to whether the target data is in the data cache unit array includes: When the target write data is not cached in the data cache unit array, a second write instruction is sent to the memory, where the second write instruction is a memory-type data processing instruction and is used to instruct the memory to write the target write data into the memory cell array.

27. The data processing method according to any one of claims 22 to 26, characterized in that: The method further comprises: Whether a certain target data is cached in the data cache unit array is determined based on a tag mapping table entry, wherein the tag mapping table entry includes a cache tag, and the cache tag is used to indicate the address of the data in the data cache unit array.

28. An electronic device, characterized in that: It comprises a circuit board and a chip system, wherein the chip system is arranged on the circuit board; the chip system comprises a memory as described in any one of claims 1 to 7 and a controller as described in any one of claims 8 to 14; and the controller is connected to the memory.

29. A computer-readable storage medium, characterized in that The computer-readable storage medium includes instructions, and when the instructions are executed on a processing device, the processing device is caused to execute the data processing method according to any one of claims 16 to 21 or the data processing method according to any one of claims 22 to 27.

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