Transistor module and manufacturing method therefor

Abstract

The present application discloses a transistor module and a manufacturing method therefor. The transistor module comprises: a substrate; a drift layer of a first conductivity type, wherein the transistor module comprises an insulated gate bipolar transistor region, a first transition region and a fast recovery diode region; a secondary main junction region of a second conductive type, the secondary main junction region being arranged in the first transition region; first trenches; an insulating layer, wherein the part of the insulating layer corresponding to the first transition region is provided with first contact holes; semiconductor regions of the second conductive type, wherein semiconductor regions are arranged in the secondary main junction region, and the semiconductor regions correspond to the first contact holes; and an emitter metal layer, wherein connecting protrusions are arranged on the emitter metal layer, and the connecting protrusions penetrate through the first contact holes and are in contact with and electrically connected to the semiconductor regions. Therefore, the avalanche current near the secondary main junction region can be locally relieved and extracted by means of the first contact holes, so that the voltage withstanding capability of the first transition region and even the transistor module can be further improved, without compromising the performance or footprint of the transistor module.

Description

Transistor module and method for manufacturing transistor module

[0001] This application refers to Chinese patent applications with application number 2024103863139 (entitled “Transistor module”) and application number 2024103863355 (entitled “Transistor module and method for manufacturing transistor module”) filed on March 29, 2024, which are incorporated into this application in their entirety by reference. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a transistor module and a method for manufacturing the transistor module. Background Art

[0003] A reverse conducting-insulated gate bipolar transistor (RC-IGBT) is an insulated gate bipolar transistor (IGBT) and a fast recovery diode (FRD) integrated on a single chip. Generally speaking, the industry typically integrates IGBTs and FRDs in the chip's cell area using a lumped or distributed approach, with the two sharing terminals. This creates a highly integrated RC-IGBT, eliminating the need to connect the two discrete devices through packaging.

[0004] Related technologies often prioritize the IGBT's external voltage withstand capability, resulting in complex terminal designs to improve the chip's voltage withstand capability. However, due to less consideration of the IGBT's internal voltage withstand capability, failures and burnouts can occur within the first transition region between the IGBT and the FRD under higher voltage withstand scenarios, significantly compromising the stability of the RC-IGBT system. Technical issues

[0005] In related technologies, although transistor modules are provided with cutoff rings and contact holes for discharging avalanche current, the current path is relatively long and the voltage difference is large, which can easily cause accumulation of avalanche current, leading to local overheating and device failure. Technical Solutions

[0006] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present application is to provide a transistor module having a better voltage resistance.

[0007] An embodiment of the present application provides a transistor module. The transistor module according to the embodiment of the present application includes: a substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being arranged between the first main surface and the second main surface; the transistor module including an insulated gate bipolar transistor region, a first transition region, and a fast recovery diode region, the insulated gate bipolar transistor region being circumferentially arranged outside the fast recovery diode region, the first transition region being arranged around the outside of the fast recovery diode region and located between the insulated gate bipolar transistor region and the fast recovery diode region; a secondary main junction region of a second conductivity type, the secondary main junction region being arranged in the first transition region, the secondary main junction region being arranged around the outside of the fast recovery diode region, the secondary main junction region being located on a side of the drift layer facing the first main surface, and a side of the secondary main junction region facing away from the drift layer constituting at least a portion of the first main surface; and a first trench, the first trench being arranged in the first transition region. And there are multiple first trenches, the lengths of the multiple first trenches extend in the second direction, the multiple first trenches are spaced apart in the third direction, the depths of at least some of the multiple first trenches extend from the first main surface to the secondary main junction region in the first direction and do not extend out of the secondary main junction region, and the first direction, the second direction and the third direction are perpendicular to each other; an insulating layer, the insulating layer is arranged on the first main surface, and a first contact hole is provided on a portion of the insulating layer corresponding to the first transition region, and a projection of the first contact hole in the first direction is staggered from a projection of the first trench in the first direction; a semiconductor region of a second conductivity type is arranged in the secondary main junction region, and a side of the semiconductor region away from the drift layer constitutes at least a part of the first main surface, and the semiconductor region corresponds to the first contact hole; an emitter metal layer, the emitter metal layer is arranged on a side of the insulating layer away from the first main surface, and a connection protrusion is provided on the emitter metal layer, and the connection protrusion passes through the first contact hole and is in contact and electrically connected with the semiconductor region.

[0008] Therefore, by providing a first contact hole in the portion of the insulating layer corresponding to the first transition region, the semiconductor region is provided in the secondary main junction region, the semiconductor region corresponds to the first contact hole, and a connection protrusion is provided on the emitter metal layer, so that the connection protrusion passes through the first contact hole and is electrically connected to the semiconductor region. In this way, the avalanche current near the secondary main junction region can be relieved and led out through the first contact hole nearby, thereby further improving the voltage resistance of the first transition region and even the transistor module without sacrificing the performance and area of ​​the transistor module.

[0009] In some examples of the present application, there are multiple first contact holes and multiple semiconductor regions, and the multiple first contact holes and the multiple semiconductor regions are arranged in a one-to-one correspondence.

[0010] In some examples of the present application, a projection of the secondary main junction region in the first direction covers projections of the plurality of first contact holes in the first direction.

[0011] In some examples of the present application, the projection of the secondary main junction region in the first direction covers a portion of the projections of the multiple first contact holes in the first direction, and another portion of the projections of the multiple first contact holes in the first direction is staggered with the projection of the secondary main junction region in the first direction.

[0012] In some examples of the present application, multiple first contact holes extend in the second direction and are spaced apart in the third direction; and / or multiple first contact holes spaced apart in the second direction constitute a contact hole group, and there are multiple contact hole groups, and multiple contact hole groups are spaced apart in the third direction.

[0013] In some examples of the present application, the first contact hole is in the shape of an elongated strip; and / or the first contact hole is in the shape of a rectangle.

[0014] In some examples of the present application, one first contact hole is provided between at least two adjacent first trenches among the plurality of first trenches; and / or multiple first contact holes are provided between at least two adjacent first trenches among the plurality of first trenches.

[0015] In some examples of the present application, in a top view, the total area of ​​the first contact holes is S1, the total area of ​​the first transition region is S2, and S1 and S2 satisfy the relationship: 0≤S1 / S2≤50%.

[0016] In some examples of the present application, the ion doping concentration of the semiconductor region is greater than the ion doping concentration of the secondary main junction region.

[0017] In some examples of the present application, the transistor module also includes a second trench and a third trench, the second trench being arranged in the fast recovery diode region and being multiple, the multiple second trenches being spaced apart in the third direction, the depth of the second trench extending from the first main surface toward the drift layer, the length of the second trench extending in the second direction, and the second trenches on both sides of the multiple second trenches in the third direction being first boundary trenches; the third trench being arranged in the insulated gate bipolar transistor region and being multiple, the multiple third trenches being spaced apart in the third direction, the depth of the third trench extending from the first main surface toward the drift layer, the length of the third trench extending in the second direction, the multiple third trenches including a main trench and a spacing trench, multiple main trenches spaced apart in the third direction are arranged on both sides of the multiple second trenches in the third direction, and the spacing trenches including a first spacing trench and a second spacing trench. The partition grooves, the first partition grooves and the second partition grooves are respectively arranged on both sides of the second direction of the plurality of second grooves, and one of the plurality of main grooves on one side of the third direction of the plurality of second grooves adjacent to the plurality of second grooves is a second boundary groove; the secondary main junction area includes two first sub-secondary main junction areas and two second sub-secondary main junction areas, the two first sub-secondary main junction areas are respectively located on both sides of the third direction of the plurality of second grooves, the two second sub-secondary main junction areas are respectively located on both sides of the second direction of the plurality of second grooves and are respectively connected to the two first sub-secondary main junction areas, the projection of the first sub-secondary main junction area in the first direction is the first projection, the projections of the adjacent first boundary grooves and the second boundary grooves in the first direction are the second projection and the third projection respectively, the first projection is located between the second projection and the third projection in the third direction, and both sides of the first projection in the third direction do not exceed the second projection and the third projection.

[0018] In some examples of the present application, one side of the first projection in the third direction coincides with the center line extending in the second direction of the second projection, and the other side of the first projection in the third direction coincides with the center line extending in the second direction of the third projection.

[0019] In some examples of the present application, the widths of the first sub-sub main junction region and the second sub-sub main junction region are equal and are both D, and D satisfies the relationship: D≥4μm.

[0020] In some examples of the present application, the transistor module also includes a base region of a second conductivity type, which is arranged on the side of the drift layer facing the first main surface, and the side of the base region away from the drift layer constitutes a part of the first main surface. There are multiple base regions, and the insulated gate bipolar transistor region, the first transition region and the fast recovery diode region are all provided with the base region. The depth of the base region in the first direction is H1, the depth of the secondary main junction region in the first direction is H2, and the thickness of the transistor module in the first direction is H3, H1≤H2≤0.5H3.

[0021] The embodiment of the present application also provides another transistor module. According to the transistor module of the embodiment of the present application, it includes: a substrate, the substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type, the drift layer being arranged between the first main surface and the second main surface, the transistor module including an active area, a transition area and a terminal area, the terminal area being circumferentially arranged outside the active area, the transition area being arranged between the active area and the terminal area; a main junction area of ​​a second conductivity type, the main junction area being arranged in the transition area and located on a side of the drift layer facing the first main surface, and a side of the main junction area facing away from the drift layer constituting a portion of the first main surface. a small portion; an insulating layer, the insulating layer is arranged on the first main surface, and a first contact hole is opened on the insulating layer at one end corresponding to the main junction area adjacent to the active area; a first semiconductor region of a second conductivity type, the first semiconductor region is arranged in the main junction area, and the side of the first semiconductor region away from the drift layer constitutes at least a part of the first main surface, and the first semiconductor region corresponds to the first contact hole; an emitter metal layer, the emitter metal layer is arranged on the side of the insulating layer away from the first main surface, and a first connection protrusion is provided on the emitter metal layer, the first connection protrusion passes through the first contact hole and is in contact with and electrically connected to the first semiconductor region.

[0022] Therefore, a first contact hole is opened at one end of the insulating layer corresponding to the main junction area adjacent to the active area, and a first semiconductor region is set corresponding to the first contact hole, so that the first connection protrusion of the emitter metal layer passes through the first contact hole and is electrically connected to the first semiconductor region. In this way, the avalanche current generated at the main junction area can be relieved and led out through the first contact hole nearby, thereby further improving the voltage resistance of the transistor module without sacrificing the performance and area of ​​the transistor module.

[0023] In some examples of the present application, there are multiple first contact holes and multiple first semiconductor regions, and the multiple first contact holes and the multiple first semiconductor regions are arranged in a one-to-one correspondence.

[0024] In some examples of the present application, the active area is provided with an effective gate trench and a virtual gate trench, the lengths of the effective gate trench and the virtual gate trench extend in the first direction and at least partially extend into the transition region, the depths of the effective gate trench and the virtual gate trench in the transition region extend from the first main surface through the main junction region to reach the drift layer, both ends of the effective gate trench in the first direction protrude from the virtual gate trench, at least two spaced-apart virtual gate trenches are provided between two adjacent effective gate trenches, the first contact hole is provided on at least one side of the transition region in the first direction, and the first contact hole is provided between two adjacent effective gate trenches in the second direction, wherein the first main surface and the second main surface are spaced-apart in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

[0025] In some examples of the present application, there are multiple first contact holes, and the multiple first contact holes are spaced apart from the virtual gate trench in the first direction; the first contact hole is in the shape of a long strip extending continuously in the second direction, and multiple first contact holes spaced apart in the first direction are arranged between two adjacent effective gate trenches; and / or multiple first contact holes spaced apart in the second direction form a second contact hole group, and multiple second contact hole groups spaced apart in the first direction are arranged between two adjacent effective gate trenches; and / or the first contact hole is rectangular, and one first contact hole is arranged between two adjacent effective gate trenches.

[0026] In some examples of this application, the first contact hole is in the shape of a long strip extending continuously in the first direction, a plurality of the first contact holes spaced in the second direction are provided between the adjacent dummy gate trenches and the effective gate trench, and a plurality of the first contact holes spaced in the second direction are also provided between two adjacent dummy gate trenches.

[0027] In some examples of the present application, the first contact hole is disposed on at least one side of the transition region in the second direction.

[0028] In some examples of this application, from a top view, there are a plurality of first contact holes, a plurality of first contact holes spaced apart in a first direction form a first contact hole group, there are a plurality of first contact hole groups, and a plurality of first contact hole groups are spaced apart in a second direction.

[0029] In some examples of this application, the first contact hole is square; and / or the first contact hole is elongated and extends in the first direction; and / or the first contact hole is elongated and extends in the second direction.

[0030] In some examples of this application, when viewed from a top view, the first contact hole is in the shape of a long strip extending continuously in the first direction; there are multiple first contact holes, and the plurality of first contact holes are spaced apart in the second direction; and / or there is one first contact hole, and when viewed from a top view, the first contact hole is rectangular.

[0031] In some examples of the present application, in a top-down perspective, the total area of ​​the first contact holes is S1, the total area of ​​the main junction region is S3, and S1 and S3 satisfy the relationship: 3.2%≤S1 / S3≤50%.

[0032] In some examples of the present application, the ion doping concentration of the first semiconductor region is greater than the ion doping concentration of the main junction region.

[0033] In some examples of the present application, the transistor module also includes a base region of a first conductivity type and a blocking trench, the base region is arranged in the active region and is located on the side of the drift layer facing the first main surface, the side of the base region away from the drift layer constitutes at least a part of the first main surface, the blocking trench passes through the main junction region from the first main surface to reach the drift layer in a depth direction, the blocking trench is located between the transition region and the active region, and the two sides of the blocking trench are the main junction region and the base region respectively.

[0034] In some examples of the present application, the transistor module also includes: a polysilicon field plate, which is arranged on the first main surface and located in the transition region, the polysilicon field plate corresponds to an end of the main junction region adjacent to the terminal region, the insulating layer is located on the side of the polysilicon field plate away from the first main surface, and a second contact hole is provided at a position of the insulating layer adjacent to the polysilicon field plate; a second semiconductor region of a second conductivity type, the second semiconductor region is arranged in the main junction region, and the side of the second semiconductor region away from the drift layer constitutes at least a part of the first main surface, the second semiconductor region corresponds to the second contact hole, and a second connection protrusion is provided on the emitter metal layer, the second connection protrusion passes through the second contact hole and is in contact and electrically connected with the second semiconductor region.

[0035] The embodiment of the present application also provides a method for manufacturing a transistor module. The method for manufacturing a transistor module according to the embodiment of the present application is applicable to the transistor module described above. The method for manufacturing the transistor module includes the following steps: preparing a substrate, and setting a drift layer of a first conductivity type in the substrate; simultaneously injecting dopant ions of a second conductivity type into the terminal region and the first transition region of the insulated gate bipolar transistor region to simultaneously form a main junction region in the terminal region of the insulated gate bipolar transistor region and a secondary main junction region in the first transition region; etching a first trench in the first transition region, wherein the depth of the first trench is from the first conductive layer to the second conductive layer in the first direction; A main surface extends toward the secondary main junction region and does not protrude from the secondary main junction region; second conductive type doping ions are injected into the secondary main junction region to form a base region; an insulating layer is provided on the first main surface; a contact hole is provided in a portion of the insulating layer corresponding to the first transition region, the projection of the contact hole in the first direction is staggered with the projection of the first trench in the first direction, and second conductive type doping ions are injected into the base region to form a semiconductor region; an emitter metal layer is provided on the insulating layer, a connection protrusion is provided on the emitter metal layer, the connection protrusion passes through the contact hole and contacts the semiconductor region.

[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. Beneficial effects

[0037] The transistor module has better voltage resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0039] FIG1 is a partial top view of a transistor module according to a first embodiment of the present application;

[0040] FIG2 is a partial cross-sectional view of a transistor module along the AA direction according to the first embodiment of the present application;

[0041] 3 is a flow chart of a method for manufacturing a transistor module according to the first embodiment of the present application;

[0042] FIG4 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0043] FIG5 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0044] FIG6 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0045] FIG7 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0046] FIG8 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0047] FIG9 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0048] FIG10 is a state diagram of the manufacturing process of the transistor module according to the first embodiment of the present application;

[0049] FIG11 is a state diagram of a manufacturing process of a transistor module according to the first embodiment of the present application;

[0050] FIG12 is a state diagram of the manufacturing process of the transistor module according to the first embodiment of the present application;

[0051] FIG13 is a state diagram of the manufacturing process of the transistor module according to the first embodiment of the present application;

[0052] FIG14 is a top view of a transistor module according to a second embodiment of the present application;

[0053] FIG15 is a partial top view of a transistor module according to a second embodiment of the present application;

[0054] FIG16 is a partial cross-sectional view of a transistor module along the AA direction according to the second embodiment of the present application;

[0055] FIG17 is a partial top view of a transistor module according to another embodiment of the present application;

[0056] FIG18 is a partial top view of a transistor module according to another embodiment of the present application;

[0057] FIG19 is a partial top view of a transistor module according to another embodiment of the present application;

[0058] FIG20 is a partial top view of a transistor module according to another embodiment of the present application;

[0059] FIG21 is a partial top view of a transistor module according to another embodiment of the present application;

[0060] FIG22 is a partial top view of a transistor module according to another embodiment of the present application;

[0061] FIG23 is a partial top view of a transistor module according to another embodiment of the present application;

[0062] FIG24 is a partial top view of a transistor module according to yet another embodiment of the present application;

[0063] FIG25 is a Vce-Ic curve of a transistor module according to an embodiment of the present application and a conventional transistor module;

[0064] FIG26 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0065] FIG27 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0066] FIG28 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0067] FIG29 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0068] FIG30 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0069] FIG31 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0070] FIG32 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0071] FIG33 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0072] FIG34 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0073] FIG35 is a state diagram of a transistor module manufacturing process according to an embodiment of the present application;

[0074] Figure 36 is a state diagram of the transistor module manufacturing process according to an embodiment of the present application.

[0075] : Reference numerals: 100, transistor module; 110, insulated gate bipolar transistor region; 120, first transition region; 130, fast recovery diode region; 140, active region; 150, second transition region; 160, termination region; 10, substrate; 101, first main surface; 102, second main surface; 11, drift layer; 12, secondary main junction region; 121, first sub-secondary main junction region; 122, second sub-secondary main junction region; 112, main junction region; 13, first trench; 14, semiconductor region; 15, second trench; 151, first boundary trench; 16, third trench; 161, main trench; 1611, second boundary trench; 162, spacer trench; 1621, first spacer trench; 141, first semiconductor region; 143, blocking trench; 142, second semiconductor region; 144, dummy gate trench; 145, Effective gate trench; 146, field limiting ring; 147, stop ring; 17, base region; 18, field stop layer; 19, collector layer; 111, cathode layer; 20, insulating layer; 21, first contact hole; 211, first sub-contact hole; 212, second sub-contact hole; 213, third sub-contact hole; 214, fourth sub-contact hole; 215, contact hole group; 22, second contact hole; 2101, first contact hole group; 2102, second contact hole group; 22, second contact hole; 23, third contact hole; 30, emitter metal layer; 31, first connection bump; 32, second connection bump; 40, collector metal layer; 51, polysilicon field plate; 50, field oxide layer; 60, metal field plate; 70, gate pad; 80, collector metal layer.

[0076] Implementation Methods of the Application

[0077] The embodiments of the present application are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present application are described in detail below.

[0078] A first embodiment of the present application provides a transistor module 100. The transistor module 100 according to the embodiment of the present application is described below with reference to FIG1-FIG13 . The transistor module 100 may employ a manufacturing method of the transistor module 100. Specifically, the transistor module 100 may be an RC-IGBT (reverse conducting-insulated gate bipolar transistor). In the following description, N and P represent the conductivity type of a semiconductor. In this application, the first conductivity type is set to N-type and the second conductivity type is set to P-type for description.

[0079] As shown in FIGS. 1 and 2 , the transistor module 100 according to the present application may mainly include: a base 10 , a first conductivity type drift layer 11 , a second conductivity type sub-main junction region 12 , a first trench 13 , an insulating layer 20 , a second conductivity type semiconductor region 14 and an emitter metal layer 30 .

[0080] The transistor module 100 may include an active area and a terminal area arranged outside the active area. The active area may mainly include an insulated gate bipolar transistor region 110, a first transition region 120 and a fast recovery diode region 130. The insulated gate bipolar transistor region 110 is circumferentially arranged outside the fast recovery diode region 130. In this way, the insulated gate bipolar transistor region 110 and the fast recovery diode region 130 can share the terminal area. In this way, the insulated gate bipolar transistor region 110 can realize forward conduction of the transistor module 100, and the fast recovery diode region 130 can realize reverse conduction of the transistor module 100, so that the transistor module 100 has both forward conduction and reverse conduction characteristics.

[0081] Furthermore, by surrounding the first transition region 120 outside the fast recovery diode region 130 and being located between the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, the first transition region 120 can separate the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, ensuring the respective working performances of the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, and improving the reliability of the transistor module 100.

[0082] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 opposite the first main surface 101. The first main surface 101 and the second main surface 102 are spaced apart in a first direction. The drift layer 11 is disposed between the first main surface 101 and the second main surface 102. A plurality of first trenches 13 are disposed in the first transition region 120. The lengths of the plurality of first trenches 13 extend in the second direction and the plurality of first trenches 13 are spaced apart in a third direction. The insulating layer 20 is disposed on the first main surface 101. The first, second, and third directions are mutually perpendicular. This constitutes the basic structure of the first transition region 120.

[0083] Furthermore, the secondary main junction region 12 is arranged in the first transition region 120, and the secondary main junction region 12 is arranged around the outside of the fast recovery diode region 130. The secondary main junction region 12 is located on the side of the drift layer 11 facing the first main surface 101, and the side of the secondary main junction region 12 away from the drift layer 11 constitutes at least a part of the first main surface 101, and the depth of at least part of the multiple first trenches 13 extends from the first main surface 101 to the secondary main junction region 12 in the first direction and does not extend out of the secondary main junction region 12. In this way, on the one hand, the secondary main junction region 12 can widen the depletion region at the edge of the insulated gate bipolar transistor region 110, weaken the electric field peak, avoid local electric field concentration or excessive local electric field strength causing failure and burning of the transistor module 100, and improve the reliability of the transistor module 100. On the other hand, due to the introduction of the secondary main junction region 12 of the second conductivity type, the anode injection efficiency of the fast recovery diode region 130 can be improved, the forward conduction voltage drop of the fast recovery diode region 130 of the transistor module 100 can be reduced, and the system loss can be reduced.

[0084] It should be noted that the injection of the sub-main junction region 12 can be performed together with the voltage-resistant structure of the terminal region, so that it is compatible with the existing process, does not add additional process steps, and can save process steps and time costs.

[0085] Considering the high voltage withstand, the strong electric field causes the carriers to gain sufficient energy during their mean free path to collide with valence electrons in the crystal, freeing them from their valence bonds and exciting electrons in the valence band into the conduction band, generating a pair of secondary electron-hole pairs. This process is called impact ionization. Subsequently, the generated pair of secondary electron-hole pairs continues to undergo collision ionization with particles in the crystal, forming an avalanche multiplication process similar to a chain reaction, resulting in a transient increase in the current in the transistor module 100, generating an avalanche current. If the avalanche current cannot be discharged in time, the accumulated avalanche current can cause local overheating and lead to failure of the transistor module 100.

[0086] A first contact hole 21 is provided in the portion of the insulating layer 20 corresponding to the first transition region 120, so that the projection of the first contact hole 21 in the first direction is offset from the projection of the first trench 13 in the first direction. Furthermore, a semiconductor region 14 is provided in the secondary main junction region 12, with the side of the semiconductor region 14 facing away from the drift layer 11 constituting at least a portion of the first main surface 101, so that the semiconductor region 14 corresponds to the first contact hole 21. Furthermore, an emitter metal layer 30 is provided on the side of the insulating layer 20 facing away from the first main surface 101, and a first connection bump 31 is provided on the emitter metal layer 30, so that the first connection bump 31 penetrates the first contact hole 21 and is in electrical contact with the semiconductor region 14.

[0087] In this way, the avalanche current near the secondary main junction region 12 can be relieved and drawn out in sequence through the semiconductor region 14, the first contact hole 21, and the emitter metal layer 30. This shortens the avalanche current path, prevents local overheating caused by the accumulation of avalanche current, and improves the withstand voltage capability of the transistor module 100. The provision of the semiconductor region 14 can further enhance the current flow capacity and improve the rate and reliability of avalanche current drawing.

[0088] It should be noted that since the first contact hole 21 is located in the first transition region 120, the space of the first transition region 120 can be fully utilized without increasing the overall area of ​​the transistor module 100. Thus, while improving the voltage withstand capability of the transistor module 100, the integration level of the transistor module 100 can be improved, the loss of the transistor module 100 can be reduced, the wafer utilization rate can be improved, and the cost can be reduced.

[0089] In addition, to ensure the normal operation of the transistor module 100, a second contact hole 22 needs to be opened on the insulating layer 20, and second conductive type dopant ions need to be injected under the second contact hole 22. During production, the first contact hole 21 and the second contact hole 22 can be opened and dopant ions can be injected at the same time, so that it can be compatible with the existing process without adding additional process steps, which can save process steps and time costs.

[0090] Therefore, by providing a first contact hole 21 in the portion of the insulating layer 20 corresponding to the first transition region 120, the semiconductor region 14 is provided in the secondary main junction region 12, the semiconductor region 14 corresponds to the first contact hole 21, and a first connection protrusion 31 is provided on the emitter metal layer 30, so that the first connection protrusion 31 passes through the first contact hole 21 and is in contact and electrically connected with the semiconductor region 14. In this way, the avalanche current near the secondary main junction region 12 can be relieved and drawn out through the first contact hole 21 nearby, thereby further improving the voltage resistance of the first transition region 120 and even the transistor module 100 without sacrificing the performance and area of ​​the transistor module 100.

[0091] As shown in FIG2 , there are multiple first contact holes 21 and multiple semiconductor regions 14, and the multiple first contact holes 21 are arranged in a one-to-one correspondence with the multiple semiconductor regions 14. Specifically, the first contact holes 21 can be arranged in a plurality, and the multiple first contact holes 21 are arranged at intervals, and the semiconductor regions 14 can also be arranged in a plurality, and the multiple first contact holes 21 are arranged in a one-to-one correspondence with the multiple semiconductor regions 14. In this way, a leakage channel can be formed in the secondary main junction region 12, which is jointly acted upon by the multiple first contact holes 21 and the corresponding semiconductor regions 14. This can further shorten the path of the avalanche current and promptly lead the avalanche current out from above the secondary main junction region 12, thereby further improving the structural reliability of the transistor module 100.

[0092] Furthermore, the ion doping concentration of the semiconductor region 14 is greater than the ion doping concentration of the secondary main junction region 12. Specifically, the ion doping concentration of the semiconductor region 14 can be set to be greater than the ion doping concentration of the secondary main junction region 12. This can optimize the electric field distribution in the area below the first contact hole 21 and improve the current flow capacity, thereby more promptly and effectively leading the avalanche current near the secondary main junction region 12 through the first contact hole 21, thereby improving the withstand voltage capability of the transistor module 100.

[0093] In some embodiments of the present application, the projection of the sub-main junction region 12 in the first direction covers the projection of the plurality of first contact holes 21 in the first direction. In this way, the plurality of first contact holes 21 can all be located in the area where the sub-main junction region 12 is located, which can ensure the timely extraction of avalanche current.

[0094] In other embodiments of the present application, the projection of the secondary main junction region 12 in the first direction covers a portion of the projections of the multiple first contact holes 21 in the first direction, and the other portion of the projections of the multiple first contact holes 21 in the first direction is staggered with the projection of the secondary main junction region 12 in the first direction. Specifically, when the projection of the secondary main junction region 12 in the first direction does not completely cover the first transition region 120, other locations within the first transition region 120, excluding the location of the secondary main junction region 12, are available for arranging the semiconductor region 14 and the corresponding first contact holes 21. By ensuring that the projection of the secondary main junction region 12 in the first direction covers a portion of the projections of the multiple first contact holes 21 in the first direction, and staggering the other portion of the projections of the multiple first contact holes 21 in the first direction with the projection of the secondary main junction region 12 in the first direction, timely extraction of the avalanche current can also be ensured.

[0095] It should be noted that, in some further embodiments of the present application, in combination with Figure 1, the multiple first contact holes 21 include multiple first sub-contact holes 211 and multiple second sub-contact holes 212, the projection of the secondary main junction region 12 in the first direction covers the projection of the multiple first sub-contact holes 211 in the first direction, and the projection of the secondary main junction region 12 in the first direction covers a part of the projection of the multiple second sub-contact holes 212 in the first direction, and the other part of the projection of the multiple second sub-contact holes 212 in the first direction is staggered with each other and will not be elaborated here.

[0096] In addition, the specific positions of the plurality of first contact holes 21 relative to the sub-main junction area 12 can be designed according to the specific width of the sub-main junction area 12, the length of the first contact holes 21, actual application requirements, etc., and are not specifically limited here.

[0097] In some embodiments of the present application, multiple first contact holes 21 extend in the second direction and are spaced apart in the third direction. Thus, a single first contact hole 21 extending continuously in the second direction can lead out the avalanche current in the second direction, while multiple first contact holes 21 spaced apart in the third direction can lead out the avalanche current at different positions in the third direction. This not only reduces the number of first contact holes 21 and facilitates the creation of the first contact holes 21, but also makes the placement of the multiple first contact holes 21 more reasonable and orderly, allowing the avalanche current near the secondary main junction region 12 to be led out in a timely manner, thereby improving the withstand voltage capability of the transistor module 100.

[0098] In other embodiments of the present application, a plurality of first contact holes 21 spaced apart in the second direction form a contact hole group 215. There are multiple contact hole groups 215, and the plurality of contact hole groups 215 are spaced apart in the third direction. In this way, the plurality of first contact holes 21 in the contact hole group 215 can divert avalanche current in the second direction, while the plurality of contact hole groups 215 spaced apart in the third direction can divert avalanche current at different positions in the third direction. This allows for a more rational and orderly arrangement of the plurality of first contact holes 21, allowing for timely diversion of avalanche current near the secondary main junction region 12, thereby improving the withstand voltage capability of the transistor module 100.

[0099] It should be noted that, in some further embodiments of the present application, in combination with Figure 1, the multiple first contact holes 21 include multiple third sub-contact holes 213 and multiple fourth sub-contact holes 214, so that the multiple third sub-contact holes 213 can extend in the second direction and be spaced apart in the third direction, so that the multiple fourth sub-contact holes 214 form a contact hole group 215, and there are multiple contact hole groups 215, and the multiple contact hole groups 215 are spaced apart in the third direction, which will not be elaborated here.

[0100] As shown in FIG1 , the first contact hole 21 is in the shape of an elongated strip, or the first contact hole 21 is in the shape of a rectangle. Specifically, the shape of the first contact hole 21 includes, but is not limited to, an elongated strip and a rectangle. In actual production, a shape can be selected based on demand to facilitate the production of the first contact hole 21. It should be noted that the multiple first contact holes 21 can also be a combination of a rectangular and an elongated strip, which will not be described in detail here.

[0101] In some embodiments of the present application, as shown in conjunction with Figures 1 and 2 , a first contact hole 21 is provided between at least two adjacent first trenches 13 among the plurality of first trenches 13; and / or multiple first contact holes 21 are provided between at least two adjacent first trenches 13 among the plurality of first trenches 13. In this way, the space between at least two adjacent first trenches 13 among the plurality of first trenches 13 can be fully utilized, facilitating the provision of one or more first contact holes 21 without increasing the area of ​​the transistor module 100 or affecting the normal operation of the first trenches 13, thereby improving the reliability of the transistor module 100. It should be noted that the specific number of first contact holes 21 between at least two adjacent first trenches 13 among the plurality of first trenches 13 can be adjusted according to actual needs and is not specifically limited here.

[0102] Furthermore, in a top view, the total area of ​​the first contact holes 21 is S1, the total area of ​​the first transition region 120 is S2, and S1 and S2 satisfy the relationship: 0≤S1 / S2≤50%.

[0103] Specifically, the ratio of the total area of ​​the first contact hole 21 to the total area of ​​the secondary main junction region 12 , that is, the area proportion of the first contact hole 21 in the secondary main junction region 12 , will affect the size of the avalanche current flux discharged by the first contact hole 21 .

[0104] For a transistor module 100 with a lower voltage specification, the first contact hole 21 may not be provided.

[0105] For the transistor module 100 with a higher voltage specification, on the one hand, the first contact hole 21 can be set to prevent the avalanche current from being unable to be discharged in time above the secondary main junction area 12, causing excessive local current, and then causing local hot spots and burning problems. On the other hand, the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the secondary main junction area 12 can be set to no more than 50% to prevent excessive injection of second conductive type doped ions in the semiconductor region 14 below the first contact hole 21, resulting in increased anode minority carrier injection, resulting in a longer reverse recovery performance time, and avoiding negative impact on the reverse recovery performance of the fast recovery diode area 130.

[0106] As shown in conjunction with FIG1 and FIG2 , the transistor module 100 may further include a second trench 15 . The second trench 15 is disposed in the fast recovery diode region 130 and is in a plurality. The plurality of second trenches 15 are spaced apart in the third direction. The depth of the second trench 15 extends from the first main surface 101 toward the drift layer 11. The length of the second trench 15 extends in the second direction. An oxide insulating layer 20 and polysilicon are disposed on one side of the second trench 15 . The second trench 15 is electrically connected to the emitter metal layer 30 . The second trenches 15 defining both sides of the plurality of second trenches 15 in the third direction are first boundary trenches 151 .

[0107] Furthermore, the transistor module 100 may also include a third trench 16, which is arranged in the insulated gate bipolar transistor region 110 and is multiple, and the multiple third trenches 16 are spaced apart in the third direction, the depth of the third trench 16 extends from the first main surface 101 toward the drift layer 11, the length of the third trench 16 extends in the second direction, and an oxide insulating layer 20 and polysilicon are sequentially arranged in the third trench 16, so that a gate can be formed at the third trench 16, and the multiple third trenches 16 are electrically connected to the gate pad.

[0108] Among them, the multiple third grooves 16 can mainly include main grooves 161 and spacing grooves 162, and the multiple second grooves 15 are provided with multiple main grooves 161 spaced apart in the third direction on both sides of the third direction, and the spacing grooves 162 include first spacing grooves 1621 and second spacing grooves 162, and the first spacing grooves 1621 and the second spacing grooves 162 are respectively spaced apart on both sides of the second direction of the multiple second grooves 15, defining one of the multiple main grooves 161 on one side of the third direction of the multiple second grooves 15 adjacent to the multiple second grooves 15 as a second boundary groove 1611.

[0109] As shown in Figures 1 and 2, the secondary main junction region 12 can mainly include two first sub-sub-main junction regions 121 and two second sub-sub-main junction regions 122. The two first sub-sub-main junction regions 121 are respectively located on both sides of the third direction of the multiple second trenches 15, and the two second sub-sub-main junction regions 122 are respectively located on both sides of the second direction of the multiple second trenches 15 and are respectively connected to the two first sub-sub-main junction regions 121, so that the secondary main junction region 12 can be closed as a whole and surround the outside of the fast recovery diode region 130.

[0110] The projection of the first sub-sub main junction region 121 in the first direction is defined as a first projection, and the projections of the adjacent first boundary trenches 151 and second boundary trenches 1611 in the first direction are defined as a second projection and a third projection, respectively. It can be understood that: the second projection is located between the first transition region 120 and the fast recovery diode region 130, and the third projection is located between the first transition region 120 and the insulated gate bipolar transistor region 110. By making the first projection located between the second projection and the third projection in the third direction, and by not exceeding the second projection and the third projection on both sides of the first projection in the third direction, the width design of the first sub-sub main junction region 121 can be optimized, and the width of the first sub-sub main junction region 121 is avoided from being too wide and affecting the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, thereby ensuring the normal operation of the transistor module 100.

[0111] In a preferred embodiment of the present application, as shown in FIG. 2 , one side of the first projection in the third direction coincides with the center line extending in the second direction of the second projection, and the other side of the first projection in the third direction coincides with the center line extending in the second direction of the third projection.

[0112] Specifically, the center line extending in the second direction of the second projection and the center line extending in the second direction of the third projection are respectively located at the two side boundaries of the width direction of the first transition region 120. By making one side of the third direction of the first projection coincide with the center line extending in the second direction of the second projection, and making the other side of the third direction of the first projection coincide with the center line extending in the second direction of the third projection, the projection of the secondary main junction region 12 in the first direction can coincide with the projection of the first transition region 120 in the first direction, thereby widening the depletion region to the greatest extent without increasing the loss of doping ions, thereby improving the voltage resistance of the transistor module 100.

[0113] Furthermore, as shown in FIG1 , the widths of the first and second sub-sub-main junction regions 121 and 122 are equal and both have a value D, where D satisfies the relationship: D ≥ 4 μm. Specifically, by making the widths of the first and second sub-sub-main junction regions 121 and 122 equal, the overall width distribution of the main junction region can be made more uniform and reasonable, making the electric field modulation effect of the sub-sub-main junction region 12 at its location more uniform, thereby improving the reliability of the transistor module 100.

[0114] Furthermore, the width of the first sub-sub-main junction region 121 and the width of the second sub-sub-main junction region 122 are set to be no less than 4 μm. This can prevent the width of the first sub-sub-main junction region 121 or the second sub-sub-main junction region 122 from being too small, resulting in a smaller widening effect on the depletion region at the edge of the insulated gate bipolar transistor region 110, thereby ensuring the widening effect of the first sub-sub-main junction region 121 and the second sub-sub-main junction region 122 on the depletion region, effectively avoiding local electric field concentration or excessive local electric field strength in the first transition region 120, and more reliably avoiding failure and burning of the transistor module 100, thereby improving the voltage resistance of the transistor module 100 and improving the reliability of the transistor module 100.

[0115] It should be noted that the sub-main junction area 12 is arranged around the horizontal direction, and the width of the first sub-sub-main junction area 121 or the width of the second sub-sub-main junction area 122 or the width of the sub-main junction area 12 is a horizontal direction and is a direction perpendicular to the direction in which the sub-main junction area 12 is arranged around.

[0116] As shown in Figure 2, the transistor module 100 may further include a base region 17 of a second conductivity type. The base region 17 is arranged on the side of the drift layer 11 facing the first main surface 101, and the side of the base region 17 facing away from the drift layer 11 constitutes a part of the first main surface 101. There are multiple base regions 17, and the insulated gate bipolar transistor region 110, the first transition region 120 and the fast recovery diode region 130 are all provided with the base region 17. The depth of the base region 17 in the first direction is H1, the depth of the secondary main junction region 12 in the first direction is H2, and the thickness of the transistor module 100 in the first direction is H3, H1≤H2≤0.5H3.

[0117] Specifically, by setting the depth of the sub-main junction region 12 in the first direction to no less than the depth of the base region 17 in the first direction, the sub-main junction region 12 can play a role in broadening the depletion region, ensuring that the sub-main junction region 12 can further expand the depletion region, reduce the peak electric field intensity, thereby improving the voltage withstand capability of the first transition region 120 and even the transistor module 100.

[0118] Furthermore, by setting the depth of the secondary main junction region 12 in the first direction to be no greater than half the thickness of the transistor module 100 in the first direction, not only can the main junction region be separated from the super junction region of the transistor module 100 to ensure the normal operation of the transistor module 100, but also it can avoid the secondary main junction region 12 being too deep in the first direction, causing the depletion region to expand too wide and affect the insulated gate bipolar transistor region 110 and the fast recovery diode region 130, or causing the electric field in the first transition region 120 to change too quickly, resulting in excessively high local field strength, leading to failure of the transistor module 100.

[0119] In this way, the depth design of the primary and secondary junction regions in the first direction can be optimized, and the depth of the primary and secondary junction regions in the first direction can be set within a reasonable range, thereby improving the voltage withstand capability of the first transition region 120 and even the entire transistor module 100 while ensuring the normal operation of the transistor module 100.

[0120] The embodiment of the present application also provides a manufacturing method of the transistor module 100. As shown in FIGS. 3-10, the manufacturing method of the transistor module 100 according to the present application can be applied to the transistor module 100 of the above embodiments, and can also be applied to the transistor module 100 of the following embodiments.

[0121] The manufacturing method of the transistor module 100 may mainly include the following steps: preparing a substrate 10, setting a drift layer 11 of a first conductivity type in the substrate 10; simultaneously implanting dopant ions of a second conductivity type into the terminal region of the insulated gate bipolar transistor region 110 and the first transition region 120, so as to simultaneously form a main junction region in the terminal region of the insulated gate bipolar transistor region 110 and a secondary main junction region 12 in the first transition region 120; etching a first trench 13 in the first transition region 120, wherein the depth of the first trench 13 extends from the first main surface 101 to the secondary main junction region 12 in a first direction and does not extend beyond the secondary main junction region 12; Dopant ions of the second conductivity type are injected into the secondary main junction region 12 to form a base region 17; an insulating layer 20 is provided on the first main surface 101; a first contact hole 21 is provided in a portion of the insulating layer 20 corresponding to the first transition region 120, and a projection of the first contact hole 21 in the first direction is staggered with a projection of the first trench 13 in the first direction, and dopant ions of the second conductivity type are injected into the base region 17 to form a semiconductor region 14; an emitter metal layer 30 is provided on the insulating layer 20, and a first connection protrusion 31 is provided on the emitter metal layer 30, and the first connection protrusion 31 passes through the first contact hole 21 and contacts the semiconductor region 14.

[0122] Specifically, when manufacturing the transistor module 100, a substrate 10 can be provided first, and a drift layer 11 of the first conductivity type can be set in the substrate 10. Then, after taking certain protective measures, second conductivity type dopant ions are simultaneously implanted into the terminal area of ​​the insulated gate bipolar transistor region 110 and the first transition region 120 to simultaneously form a main junction region in the terminal area of ​​the insulated gate bipolar transistor region 110 and a secondary main junction region 12 in the first transition region 120. Then, a first trench 13, a second trench 15 and a third trench 16 are etched in the first transition region 120 so that the depth of the first trench 13 extends from the first main surface 101 to the secondary main junction region 12 in the first direction and does not protrude out of the secondary main junction region 12, and processes such as rounding and oxide layer growth are completed.

[0123] Among them, the transverse expansion effect generated when the sub-main junction region 12 is implanted can be utilized to make the sub-main junction region 12 located in the first transition region 120 . In this way, the process of the sub-main junction region 12 can be made compatible with the main junction region of the terminal region of the insulated gate bipolar transistor region 110 without adding additional process steps, thereby saving process steps and time costs.

[0124] Furthermore, dopant ions of the second conductive type are injected into the secondary main junction region 12 to form a base region 17, and then an insulating layer 20 is arranged on the first main surface 101, and then a first contact hole 21 and a second contact hole 22 are arranged on the insulating layer 20, the projection of the first contact hole 21 in the first direction is staggered with the projection of the first trench 13 in the first direction, and dopant ions of the second conductive type are injected into the base region 17 to form a semiconductor region 14, and then an emitter metal layer 30 is deposited on the insulating layer 20, and the emitter metal layer 30 is formed with a first connection protrusion 31 at the first contact hole 21, and the first connection protrusion 31 penetrates the first contact hole 21 and contacts the semiconductor region 14.

[0125] Among them, the formation process corresponding to the first contact hole 21 can be made compatible with the formation process of the second contact hole 22, and the formation process corresponding to the semiconductor region 14 can be made compatible with the formation process of the voltage-resistant structure of the terminal region, so that no additional process steps are required, and process steps and time costs can be saved.

[0126] 3 and 11-13 , after the emitter metal layer 30 is provided on the insulating layer 20, the first connection protrusion 31 is provided on the emitter metal layer 30, and the first connection protrusion 31 passes through the first contact hole 21 and contacts the semiconductor region 14, the manufacturing method of the transistor module 100 may further include: sequentially injecting a first conductive type field stop layer 18 and a second conductive type collector layer 19 on the side of the drift layer 11 facing the second main surface 102; injecting a first conductive type cathode layer 111 into the collector; and depositing a collector metal layer 40 on the second main surface 102.

[0127] In this way, the manufacturing of the transistor module 100 can be completed, and the transistor module 100 has better voltage withstand capability. Moreover, the manufacturing of the transistor module 100 can also be compatible with existing processes without adding additional process steps, thereby saving process steps and time costs.

[0128] Embodiment 2 of the present application provides a transistor module 100. The transistor module 100 according to the embodiment of the present application is described below with reference to Figures 14 to 36. The transistor module 100 may be an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor), but is not limited thereto. In the following description, N and P represent the conductivity type of the semiconductor. In this application, the first conductivity type is set to N-type and the second conductivity type is set to P-type for description.

[0129] As shown in Figures 14 to 25 , the transistor module 100 according to the present application may mainly include: a base 10, a drift layer 11 of a first conductive type, a main junction region 112 of a second conductive type, an insulating layer 20, a first semiconductor region 141 of a second conductive type, and an emitter metal layer 30.

[0130] The transistor module 100 may include an active region 140, a second transition region 150, and a terminal region 160. The terminal region 160 is circumferentially disposed outside the active region 140, and the second transition region 150 is disposed between the active region 140 and the terminal region 160. The active region 140 may serve as a key region in the transistor module 100 responsible for generating, amplifying, or regulating electrical signals. A depletion region may be formed within the second transition region 150, and the terminal region 160 may improve the electric field distribution at the edge to prevent premature breakdown caused by severe electric field concentration.

[0131] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 opposite the first main surface 101. The drift layer 11 is disposed between the first and second main surfaces 101, 102. A main junction region 112 is disposed in the second transition region 150, located on the side of the drift layer 11 facing the first main surface 101. The side of the main junction region 112 facing away from the drift layer 11 constitutes at least a portion of the first main surface 101. An insulating layer 20 is disposed on the first main surface 101 to protect the first main surface 101 and reduce the risk of damage to the transistor module 100. This forms the basic structure of the second transition region 150 of the transistor module 100.

[0132] During withstand voltage, the strong electric field causes carriers to gain sufficient energy during their mean free path, colliding with valence electrons in the crystal and freeing them from valence bonds. This excites electrons in the valence band into the conduction band, generating a pair of secondary electron-hole pairs. This process is called impact ionization. Subsequently, the generated pair of secondary electron-hole pairs continues to undergo collision ionization with particles in the crystal, forming an avalanche multiplication process similar to a chain reaction, resulting in a transient increase in the current in the transistor module 100 within a short period of time, generating an avalanche current. When the transistor module 100 withstands voltage, the main junction region 112 is equivalent to applying a reverse bias voltage, forming a depletion region. At this time, an electric field peak is generated, which is prone to premature breakdown.

[0133] It is considered that although the avalanche current can be discharged by setting the cutoff ring 147 in the terminal area 160 and the metal field plate 60 electrically connected to it, the avalanche current travels far and the voltage difference is large, which can easily cause the accumulation of avalanche current, leading to local overheating and device failure.

[0134] A first contact hole 21 is opened at one end of the insulating layer 20 corresponding to the main junction region 112 adjacent to the active region 140, and a first semiconductor region 141 is arranged in the main junction region 112. The side of the first semiconductor region 141 facing away from the drift layer 11 constitutes at least a portion of the first main surface 101. The first semiconductor region 141 corresponds to the first contact hole 21, and the emitter metal layer 30 is arranged on the side of the insulating layer 20 away from the first main surface 101. A first connection protrusion 31 is provided on the emitter metal layer 30, so that the first connection protrusion 31 passes through the first contact hole 21 and contacts and electrically connects with the first semiconductor region 141.

[0135] In this way, the avalanche current generated at the main junction region 112 can be relieved and drawn out through the first semiconductor region 141, the first contact hole 21, and the emitter metal layer 30. This shortens the avalanche current path, prevents local overheating caused by the accumulation of avalanche current, and improves the withstand voltage capability of the transistor module 100. The provision of the first semiconductor region 141 can further improve the current flow capacity and increase the speed and reliability of drawing out the avalanche current.

[0136] It should be noted that since the first contact hole 21 is located in the second transition region 150, it has no impact on the active area 140. This improves the voltage withstand capability of the transistor module 100 without affecting the dynamic and static performance of the transistor module 100. There is no need to compromise between electrical performance and stability.

[0137] In addition, to ensure the normal operation of the transistor module 100, it is necessary to open a third contact hole 23 on the insulating layer 20. During production, the newly added first contact hole 21 can be processed and formed at the same time as the original third contact hole 23, so that it can be compatible with the existing process without adding additional process steps, which can save process steps and time costs.

[0138] FIG25 shows Vce (collector-emitter voltage)-Ic (collector current) curves for a transistor module 100 according to a specific embodiment of the present application and a transistor module according to the prior art. The transistor module according to the prior art is an IGBT without a first contact hole 21, while the transistor module 100 according to the specific embodiment of the present application is an IGBT with a first contact hole 21. The ratio of the total area of ​​the first contact hole 21 to the area of ​​the main junction region 112 is 9.93%.

[0139] It can be seen that by providing the first contact hole 21, the inflection point of the Vce-Ic curve is pushed back, the avalanche current is prolonged, and there is no snapback phenomenon when the test clamp current is reached, that is, no device failure or burnout occurs. Therefore, it can be concluded that the provision of the first contact hole 21 can effectively improve the withstand voltage capability of the transistor module 100, promoting the miniaturization and robustness optimization of the transistor module 100.

[0140] Therefore, by opening a first contact hole 21 at one end of the insulating layer 20 corresponding to the main junction area 112 adjacent to the active area 140, and setting a first semiconductor region 141 corresponding to the first contact hole 21, the first connection protrusion 31 of the emitter metal layer 30 passes through the first contact hole 21 and is in contact and electrically connected with the first semiconductor region 141. In this way, the avalanche current generated at the main junction area 112 can be relieved and led out through the first contact hole 21 nearby, thereby further improving the voltage resistance of the transistor module 100 without sacrificing the performance and area of ​​the transistor module 100.

[0141] As shown in Figures 15-18 and 21-24, there are multiple first contact holes 21 and multiple first semiconductor regions 141, and the multiple first contact holes 21 are arranged in a one-to-one correspondence with the multiple first semiconductor regions 141. Specifically, the first contact holes 21 can be arranged in a plurality, and the multiple first contact holes 21 can be arranged at intervals, and the first semiconductor regions 141 can also be arranged in a plurality, and the multiple first contact holes 21 and the multiple first semiconductor regions 141 can be arranged in a one-to-one correspondence. In this way, a leakage channel can be formed in the main junction region 112, which is jointly acted upon by the multiple first contact holes 21 and the corresponding first semiconductor regions 141, thereby further shortening the path of the avalanche current, timely diverting the avalanche current, and further improving the structural reliability of the transistor module 100.

[0142] Furthermore, the ion doping concentration of the first semiconductor region 141 is greater than the ion doping concentration of the main junction region 112. Specifically, the ion doping concentration of the first semiconductor region 141 can be set to be greater than the ion doping concentration of the main junction region 112. This can optimize the electric field distribution in the area below the first contact hole 21, improve the current flow capacity, and thus more promptly and effectively lead the avalanche current through the first contact hole 21, thereby improving the withstand voltage capability of the transistor module 100.

[0143] In addition, during the manufacturing process of the transistor module 100, since second conductive type dopant ions with a higher doping concentration than the base region 17 are injected under the third contact hole 23 to form a plug region, by setting the first semiconductor region 141, the first contact hole 21 and the third contact hole 23 can be opened and dopant ions can be injected at the same time, thereby reducing process time and process costs.

[0144] As shown in Figures 15-24 , the active area 140 is provided with an effective gate trench 145 and a dummy gate trench 144. The effective gate trench 145 and the dummy gate trench 144 extend in the second direction and at least partially into the second transition region 150. The depth of the effective gate trench 145 and the dummy gate trench 144 in the second transition region 150 extends from the first main surface 101 through the main junction region 112 to the drift layer 11. Both ends of the effective gate trench 145 in the second direction protrude beyond the dummy gate trench 144. At least two dummy gate trenches 144 are spaced apart between two adjacent effective gate trenches 145 in the third direction. In this manner, an effective gate can be formed in the effective gate trench 145, and a dummy gate can be formed in the dummy gate trench 144. This allows the transistor module 100 to form a dual-gate structure, thereby improving the operating performance of the transistor module 100. The first main surface 101 and the second main surface 102 are spaced apart in the first direction, and the second direction, the third direction, and the first direction are mutually perpendicular.

[0145] In some embodiments of the present application, as shown in FIG. 21 to FIG. 24 , the first contact hole 21 is disposed on at least one side of the second transition region 150 in the second direction, and a first contact hole 21 is disposed between two adjacent effective gate trenches 145 .

[0146] Specifically, considering that the second transition region 150 is arranged around the active area 140, the virtual gate trench 144 and the effective gate trench 145 extend in the second direction to the portion of the second transition region 150 located on both sides of the active area 140 in the second direction, and the end of the virtual gate trench 144 is shorter than the end of the effective gate trench 145, the end of the effective gate trench 145 is connected to the gate pad 70, the end of the virtual gate trench 144 is spaced apart from the gate pad 70, and the virtual gate trenches 144 and the virtual gate trenches 144, the effective gate trenches 145 and the effective gate trenches 145, and the virtual gate and the effective gate trench 145 are all spaced apart, therefore: the portion of the second transition region 150 located between two adjacent effective gate trenches 145 also has sufficient setting space.

[0147] By setting the first contact hole 21 between two adjacent effective gate trenches 145, the space of the second transition region 150 located on both sides of the active area 140 in the second direction can be fully utilized, the integration of the transistor module 100 can be improved, and the utilization rate of the second transition region 150 can be improved.

[0148] Among them, the portion of the second transition region 150 located between two adjacent effective gate trenches 145 includes but is not limited to: the portion of the second transition region 150 located between two adjacent effective gate trenches 145 and between the end of the virtual gate trench 144 and the gate pad 70, the portion of the second transition region 150 located between the adjacent virtual gate trench 144 and the effective gate trench 145, and the portion between two adjacent virtual gate trenches 144 in the second transition region 150.

[0149] Optionally, as shown in Figure 21, there are multiple first contact holes 21, and the multiple first contact holes 21 are arranged in the second transition region 150 between two adjacent effective gate trenches 145 and between the end of the virtual gate trench 144 and the gate pad 70, so that the multiple first contact holes 21 and the virtual gate trench 144 are spaced apart in the second direction, and the first contact holes 21 are in the shape of long strips continuously extending in the third direction, and multiple first contact holes 21 spaced apart in the second direction are arranged between two adjacent effective gate trenches 145. In this way, in the area between two adjacent effective gate trenches 145, a first contact hole 21 continuously extending in the third direction can lead out the avalanche current in the third direction, and multiple first contact holes 21 spaced apart in the second direction can lead out the avalanche current at different positions in the second direction, thereby not only shortening the number of first contact holes 21 and facilitating the opening of the first contact holes 21, but also making the setting positions of the multiple first contact holes 21 more reasonable and orderly, timely leading out the avalanche current at various locations in the main junction area 112, and improving the voltage resistance of the transistor module 100.

[0150] Optionally, as shown in FIG. 22 , multiple first contact holes 21 are provided. These multiple first contact holes 21 are disposed in a portion of the second transition region 150 between two adjacent effective gate trenches 145 and between the end of the dummy gate trench 144 and the gate pad 70. The multiple first contact holes 21 are spaced apart from the dummy gate trench 144 in the second direction. A plurality of first contact holes 21 spaced apart in the third direction form a second contact hole group 2102. A plurality of second contact hole groups 2102 spaced apart in the second direction are disposed between two adjacent effective gate trenches 145. In this manner, in the region between two adjacent effective gate trenches 145, the multiple first contact holes 21 in the second contact hole group 2102 can divert avalanche current in the third direction, while the multiple second contact hole groups 2102 spaced apart in the second direction can divert avalanche current at different locations in the second direction. This allows for more rational and orderly placement of the multiple first contact holes 21, timely diversion of avalanche current from various locations in the main junction region 112, and improved withstand voltage capability of the transistor module 100.

[0151] Optionally, as shown in Figure 23, there are multiple first contact holes 21, and the multiple first contact holes 21 are spaced apart from the virtual gate trench 144 in the second direction. The first contact hole 21 is rectangular, and a first contact hole 21 is arranged between two adjacent effective gate trenches 145, that is, the portion of the second transition region 150 located between the two adjacent effective gate trenches 145 and between the end of the virtual gate trench 144 and the gate pad 70 is provided with a continuous, large-area first contact hole 21, thereby further reducing the number of first contact holes 21 and facilitating the opening of the first contact hole 21 while ensuring the improvement of the voltage resistance of the transistor module 100.

[0152] Optionally, as shown in Figure 24, the first contact hole 21 is in the shape of a long strip extending continuously in the second direction, and a plurality of first contact holes 21 spaced apart in the third direction are arranged between adjacent virtual gate trenches 144 and effective gate trenches 145, and a plurality of first contact holes 21 spaced apart in the third direction are also arranged between two adjacent virtual gate trenches 144. In this way, the plurality of first contact holes 21 make full use of the space between adjacent virtual gate trenches 144 and effective gate trenches 145, as well as the space between two adjacent virtual gate trenches 144, further improving the space utilization rate of the second transition region 150, facilitating the arrangement of a plurality of first contact holes 21 with a larger total area, and further improving the voltage resistance of the transistor module 100.

[0153] In some other embodiments of the present application, as shown in FIG. 15 to FIG. 20 , the first contact hole 21 is disposed on at least one side of the second transition region 150 in the third direction.

[0154] Specifically, considering that the second transition region 150 is arranged around the active area 140, the virtual gate trench 144 and the effective gate trench 145 extend in the second direction to the portion of the second transition region 150 located on both sides of the active area 140 in the second direction. Therefore, the portion of the second transition region 150 located on both sides of the active area 140 in the third direction has sufficient arrangement space.

[0155] By arranging the first contact hole 21 on at least one side of the third direction of the second transition region 150, the space of the portion of the second transition region 150 located on both sides of the third direction of the active area 140 can be fully utilized, which facilitates the arrangement of the first contact hole 21, can improve the integration of the transistor module 100, and can improve the utilization rate of the second transition region 150.

[0156] Optionally, in combination with Figures 17 to 19, from a top-down perspective, there are multiple first contact holes 21, and multiple first contact holes 21 spaced apart in the second direction form a first contact hole group 2101. There are multiple first contact hole groups 2101, and multiple first contact hole groups 2101 are spaced apart in the third direction. In this way, the multiple first contact holes 21 in the first contact hole group 2101 can lead out the avalanche current in the second direction, and the multiple first contact hole groups 2101 spaced apart in the third direction can lead out the avalanche current at different positions in the third direction, so that the setting positions of the multiple first contact holes 21 can be made more reasonable and orderly, and the avalanche current at various locations in the main junction area 112 can be led out in time, thereby improving the voltage resistance of the transistor module 100.

[0157] The first contact holes 21 may be square, strip-shaped, and extend in the second direction, or strip-shaped and extend in the third direction. In actual manufacturing, these options may be selected based on actual needs to facilitate the production of the first contact holes 21 and are not specifically limited here. It should be noted that the plurality of first contact holes 21 may also be a combination of at least two of the following: square, strip-shaped, and extend in the second direction, and strip-shaped, extend in the third direction. This is not further detailed here.

[0158] Optionally, in combination with Figure 15, from a top-down perspective, the first contact hole 21 is in the shape of a long strip extending continuously in the second direction, and there are multiple first contact holes 21, and the multiple first contact holes 21 are arranged at intervals in the third direction. In this way, a first contact hole 21 extending continuously in the second direction can lead out the avalanche current in the second direction, while multiple first contact holes 21 arranged at intervals in the third direction can lead out the avalanche current at different positions in the third direction, thereby not only reducing the number of first contact holes 21 and facilitating the opening of the first contact holes 21, but also making the setting positions of the multiple first contact holes 21 more reasonable and orderly, thereby timely leading out the avalanche current at various locations in the main junction area 112, and improving the voltage resistance of the transistor module 100.

[0159] Optionally, as shown in FIG20 , there is one first contact hole 21, which is rectangular in a top-down view. Specifically, the first contact hole 21 can be provided as a single hole, so that the entire first contact hole 21 is a continuous rectangle in a top-down view, and the first contact hole 21 extends in the second direction. That is, a single, continuous, large-area first contact hole 21 is provided in the main junction region 112. This ensures that the withstand voltage capability of the transistor module 100 is improved while reducing the number of first contact holes 21 to only one, facilitating the creation of the first contact hole 21.

[0160] 15 to 24 , in a top view, the total area of ​​the first contact holes 21 is S1 , the total area of ​​the main junction region 112 is S3 , and S1 and S3 satisfy the relationship: 3.2% ≤ S1 / S3 ≤ 50%.

[0161] Specifically, the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the main junction region 112, that is, the area proportion of the first contact hole 21 in the main junction region 112, will affect the size of the avalanche current flux generated by the first contact hole 21 when discharging the reverse withstand voltage.

[0162] When the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the main junction region 112 is less than 3.2%, the area of ​​the first contact hole 21 in the main junction region 112 accounts for a small proportion, which will result in insufficient avalanche current flux generated when discharging the reverse withstand voltage, making it impossible for the avalanche current to be discharged in time above the main junction region 112, resulting in excessive local current, and then causing local hot spots and leading to burning.

[0163] When the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the main junction region 112 is greater than 50%, excessive injection of second conductive type dopant ions in the first semiconductor region 141 below the first contact hole 21 will cause increased anode minority carrier injection, resulting in a longer reverse recovery performance time, which will have a negative impact on the reverse recovery performance of the transistor module 100.

[0164] In this way, by setting the ratio between the total area of ​​the first contact hole 21 and the total area of ​​the main junction region 112 in a top-down perspective within a reasonable range, it is possible to ensure that the avalanche current is discharged from above the main junction region 112 in a timely manner without affecting other performances of the transistor module 100, thereby improving the voltage resistance of the transistor module 100.

[0165] As shown in Figures 15 to 24, the transistor module 100 may further include a base region 17 of the first conductive type and a blocking trench 143. The base region 17 is arranged in the active area 140 and is located on the side of the drift layer 11 facing the first main surface 101. The side of the base region 17 away from the drift layer 11 constitutes at least a part of the first main surface 101. The blocking trench 143 penetrates the main junction region 112 from the first main surface 101 in the depth direction and reaches the drift layer 11. The blocking trench 143 is located between the second transition region 150 and the active area 140. The two sides of the blocking trench 143 are the main junction region 112 and the base region 17 respectively.

[0166] Specifically, considering that the base region 17 and the main junction region 112 are spaced apart, electric field strength superposition is likely to occur at the intersection of the base region 17 and the main junction region 112, resulting in an electric field strength spike, which in turn causes failure and burning of the transistor module 100. By setting a blocking trench 143, the blocking trench 143 is located between the second transition region 150 and the active region 140, and the two side walls of the blocking trench 143 are in contact with the main junction region 112 and the base region 17 respectively. In this way, the blocking trench 143 can be blocked between the main junction region 112 and the base region 17, thereby avoiding electric field concentration at the intersection of the base region 17 and the main junction region 112, thereby improving the reliability of the transistor module 100 and increasing the safe operating area of ​​the transistor module 100.

[0167] As shown in Figures 15, 16, and 21-24, the transistor module 100 may further include a polysilicon field plate 51 and a second semiconductor region 142 of the second conductivity type. The polysilicon field plate 51 is disposed on the first main surface 101 and in the second transition region 150. The polysilicon field plate 51 corresponds to an end of the main junction region 112 adjacent to the termination region 160. The insulating layer 20 is located on a side of the polysilicon field plate 51 facing away from the first main surface 101. A second contact hole 22 is defined in the insulating layer 20 adjacent to the polysilicon field plate 51. The second semiconductor region 142 is disposed in the main junction region 112. The side of the second semiconductor region 142 facing away from the drift layer 11 constitutes at least a portion of the first main surface 101. The second semiconductor region 142 corresponds to the second contact hole 22. A second connection bump 32 is disposed on the emitter metal layer 30. The second connection bump 32 passes through the second contact hole 22 and is in electrical contact with the second semiconductor region 142.

[0168] Specifically, by arranging the polysilicon field plate 51 on the first main surface 101 and in the second transition region 150, the polysilicon field plate 51 corresponds to one end of the main junction region 112 adjacent to the terminal region 160. In this way, the polysilicon field plate 51 can optimize the electric field distribution at one end of the main junction region 112 adjacent to the terminal region 160, avoid breakdown at the position of the second transition region 150 adjacent to the terminal region 160, and improve the voltage resistance of the second transition region 150 and even the transistor module 100.

[0169] By opening a second contact hole 22 at a position adjacent to the polysilicon field plate 51 in the insulating layer 20 and arranging the second semiconductor region 142 in the main junction area 112, so that the second semiconductor region 142 corresponds to the second contact hole 22, and the second connection protrusion 32 passes through the second contact hole 22 and is in contact and electrically connected with the second semiconductor region 142, the avalanche current on the side of the main junction area 112 close to the terminal area 160 can be relieved and led out through the second semiconductor region 142, the second contact hole 22 and the emitter metal layer 30, thereby further shortening the avalanche current path, avoiding local overheating caused by the accumulation of avalanche current, and improving the voltage resistance of the transistor module 100.

[0170] The following describes a method for manufacturing a transistor module 100 by way of example with reference to FIG. 26 to FIG. 36. The method for manufacturing a transistor module 100 includes the following steps: providing a substrate 10 with a structured N-drift layer 11; after taking certain protective measures, implanting P+ into the first main surface 101 of the substrate 10 to form a field limiting ring 146 and a main junction region 112; growing a field oxide layer 50; etching an effective gate trench 145, a dummy gate trench 144, and a blocking trench 143, and completing processes such as rounding and gate oxide growth; growing polysilicon, and performing back Engraving; implanting a cutoff ring 147, a carrier storage layer (not shown) and other structures into the first main surface 101 of the substrate 10; growing an insulating layer 20; etching the insulating layer 20 to form a third contact hole 23, a first contact hole 21 and a second contact hole 22, and implanting; depositing metal and etching to form a metal field plate 60 and an emitter metal layer 30; implanting N-type ions and P-type ions into the second main surface 102 of the substrate 10 in sequence to form a field stop layer 18 and a collector layer 19 in sequence; depositing a collector metal 80 on the second main surface 102.

[0171] In this way, the transistor module 100 can be manufactured, and the voltage resistance of the transistor module 100 is improved. In addition, the first contact hole 21 and the second contact hole 22 can be formed simultaneously with the third contact hole 23. The manufacturing of the transistor module 100 is also compatible with existing processes, without adding additional process steps, which can save process steps and time costs.

[0172] It should be noted that other structures and operations of the transistor module 100 according to the embodiment of the present application are well known to those skilled in the art and will not be described in detail here.

[0173] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0174] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0175] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A transistor module, characterized in that: include: A substrate (10), the substrate (10) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101), the first main surface (101) and the second main surface (102) being spaced apart in a first direction; a first conductive type drift layer (11), the drift layer (11) being arranged between the first main surface (101) and the second main surface (102); the transistor module (100) comprising an insulated gate bipolar transistor region (110), a first transition region (120) and a fast recovery diode region (130); the insulated gate bipolar transistor region (110) being arranged circumferentially outside the fast recovery diode region (130); and the first transition region (120) being arranged circumferentially outside the fast recovery diode region (130) and being located between the insulated gate bipolar transistor region (110) and the fast recovery diode region (130); a secondary main junction region (12) of a second conductivity type, the secondary main junction region (12) being arranged in the first transition region (120), the secondary main junction region (12) being arranged around the outside of the fast recovery diode region (130), the secondary main junction region (12) being located on a side of the drift layer (11) facing the first main surface (101), and a side of the secondary main junction region (12) facing away from the drift layer (11) constituting at least a portion of the first main surface (101); a first trench (13), wherein the first trench (13) is arranged in the first transition region (120) and is in plurality, the lengths of the plurality of first trenches (13) extending in the second direction, the plurality of first trenches (13) being spaced apart in the third direction, the depths of at least some of the plurality of first trenches (13) extending from the first main surface (101) toward the secondary main junction region (12) in the first direction and not extending beyond the secondary main junction region (12), and the first direction, the second direction and the third direction being perpendicular to each other; an insulating layer (20), the insulating layer (20) being provided on the first main surface (101), a first contact hole (21) being provided in a portion of the insulating layer (20) corresponding to the first transition region (120), a projection of the first contact hole (21) in the first direction being offset from a projection of the first trench (13) in the first direction; a semiconductor region (14) of a second conductivity type, the semiconductor region (14) being arranged in the secondary main junction region (12), the side of the semiconductor region (14) facing away from the drift layer (11) constituting at least a portion of the first main surface (101), and the semiconductor region (14) corresponding to the first contact hole (21); An emitter metal layer (30), the emitter metal layer (30) being arranged on a side of the insulating layer (20) away from the first main surface (101), the emitter metal layer (30) being provided with a first connection protrusion (31), the first connection protrusion (31) penetrating the first contact hole (21) and being in electrical contact with the semiconductor region (14).

2. The transistor module according to claim 1, wherein: There are a plurality of first contact holes (21), a plurality of semiconductor regions (14), and the plurality of first contact holes (21) and the plurality of semiconductor regions (14) are arranged in a one-to-one correspondence.

3. The transistor module according to claim 2, wherein: The projection of the secondary main junction region (12) in the first direction covers the projections of the plurality of first contact holes (21) in the first direction.

4. The transistor module according to claim 2, wherein: The projection of the secondary main junction region (12) in the first direction covers a portion of the projections of the plurality of first contact holes (21) in the first direction, and another portion of the projections of the plurality of first contact holes (21) in the first direction is staggered with the projection of the secondary main junction region (12) in the first direction.

5. The transistor module according to claim 2, wherein: A plurality of the first contact holes (21) extend in the second direction and are spaced apart in the third direction; and / or A plurality of the first contact holes (21) spaced apart in the second direction form a contact hole group (215), and the plurality of contact hole groups (215) are spaced apart in the third direction.

6. The transistor module according to claim 2, wherein: The first contact hole (21) is in the shape of an elongated strip; and / or the first contact hole (21) is in the shape of a rectangle.

7. The transistor module according to claim 2, wherein: A first contact hole (21) is provided between at least two adjacent first trenches (13) among the plurality of first trenches (13); and / or A plurality of first contact holes (21) are provided between at least two adjacent first trenches (13) among the plurality of first trenches (13).

8. The transistor module according to any one of claims 2, wherein: In a top view, the total area of ​​the first contact hole (21) is S1, the total area of ​​the first transition region (120) is S2, and S1 and S2 satisfy the relationship: 0≤S1 / S2≤50%.

9. The transistor module according to claim 1, wherein: The ion doping concentration of the semiconductor region (14) is greater than the ion doping concentration of the secondary main junction region (12).

10. The transistor module according to claim 1, wherein: The invention also includes a second trench (15) and a third trench (16), wherein the second trench (15) is arranged in the fast recovery diode region (130) and is in plurality, the plurality of second trenches (15) are arranged at intervals in the third direction, the depth of the second trench (15) extends from the first main surface (101) toward the drift layer (11), the length of the second trench (15) extends in the second direction, and the second trenches (15) on both sides of the plurality of second trenches (15) in the third direction are first boundary trenches (151); The third trenches (16) are arranged in the insulated gate bipolar transistor region (110) and are multiple. The multiple third trenches (16) are arranged at intervals in the third direction. The depth of the third trenches (16) extends from the first main surface (101) toward the drift layer (11). The length of the third trenches (16) extends in the second direction. The multiple third trenches (16) include main trenches (161) and spacing trenches (162). The multiple second trenches (15) are arranged on both sides of the third direction. There are a plurality of main grooves (161) spaced apart in a third direction, the spacer grooves (162) include a first spacer groove (1621) and a second spacer groove (162), the first spacer groove (1621) and the second spacer groove (162) are spaced apart on both sides of the plurality of second grooves (15) in the second direction, respectively, and one of the plurality of main grooves (161) on one side of the plurality of second grooves (15) in the third direction adjacent to the plurality of second grooves (15) is a second boundary groove (1611); The secondary main junction region (12) includes two first sub-secondary main junction regions (121) and two second sub-secondary main junction regions (122), the two first sub-secondary main junction regions (121) are respectively located on both sides of the plurality of second grooves (15) in the third direction, the two second sub-secondary main junction regions (122) are respectively located on both sides of the plurality of second grooves (15) in the second direction and are respectively connected to the two first sub-secondary main junction regions (121), the projection of the first sub-secondary main junction region (121) in the first direction is the first projection, the projections of the adjacent first boundary groove (151) and the second boundary groove (1611) in the first direction are the second projection and the third projection respectively, the first projection is located between the second projection and the third projection in the third direction, and both sides of the first projection in the third direction do not exceed the second projection and the third projection.

11. The transistor module according to claim 10, wherein: One side of the first projection in the third direction coincides with a center line of the second projection extending in the second direction, and the other side of the first projection in the third direction coincides with a center line of the third projection extending in the second direction.

12. The transistor module according to claim 10, wherein: The widths of the first sub-sub main junction region (121) and the second sub-sub main junction region (122) are equal and both are D, and D satisfies the relationship: D≥4μm.

13. The transistor module according to claim 1, wherein: The invention also includes a base region (17) of a second conductive type, wherein the base region (17) is arranged on a side of the drift layer (11) facing the first main surface (101), and a side of the base region (17) facing away from the drift layer (11) constitutes a part of the first main surface (101). There are multiple base regions (17), and the insulated gate bipolar transistor region (110), the first transition region (120) and the fast recovery diode region (130) are all provided with the base region (17). The depth of the base region (17) in the first direction is H1, the depth of the secondary main junction region (12) in the first direction is H2, and the thickness of the transistor module (100) in the first direction is H3, where H1≤H2≤0.5H3.

14. A transistor module, characterized in that: include: A substrate (10), the substrate (10) having a first main surface (101) and a second main surface (102) opposite to the first main surface (101); a first conductive type drift layer (11), the drift layer (11) being arranged between the first main surface (101) and the second main surface (102); the transistor module (100) comprising an active area (140), a second transition area (150) and a terminal area (160); the terminal area (160) being arranged circumferentially outside the active area (140); and the second transition area (150) being arranged between the active area (140) and the terminal area (160); a main junction region (112) of a second conductivity type, the main junction region (112) being arranged in the second transition region (150) and located on a side of the drift layer (11) facing the first main surface (101), and a side of the main junction region (112) facing away from the drift layer (11) constituting at least a portion of the first main surface (101); an insulating layer (20), the insulating layer (20) being disposed on the first main surface (101), and a first contact hole (21) being formed at one end of the insulating layer (20) corresponding to the main junction region (112) and adjacent to the active region (140); a first semiconductor region (141) of a second conductivity type, the first semiconductor region (141) being arranged in the main junction region (112), the side of the first semiconductor region (141) facing away from the drift layer (11) constituting at least a portion of the first main surface (101), and the first semiconductor region (141) corresponding to the first contact hole (21); An emitter metal layer (30), the emitter metal layer (30) being arranged on a side of the insulating layer (20) away from the first main surface (101), the emitter metal layer (30) being provided with a first connection protrusion (31), the first connection protrusion (31) penetrating the first contact hole (21) and being in contact and electrically connected with the first semiconductor region (141).

15. The transistor module according to claim 14, characterized in that There are a plurality of first contact holes (21), a plurality of first semiconductor regions (141), and the plurality of first contact holes (21) and the plurality of first semiconductor regions (141) are arranged in a one-to-one correspondence.

16. The transistor module according to claim 14, wherein: The active area (140) is provided with an effective gate trench (145) and a virtual gate trench (144), the lengths of the effective gate trench (145) and the virtual gate trench (144) extend in the second direction and at least partially extend into the second transition region (150), the depths of the effective gate trench (145) and the virtual gate trench (144) in the second transition region (150) extend from the first main surface (101) through the main junction region (112) to reach the drift layer (11), and both ends of the effective gate trench (145) in the second direction protrude In the virtual gate trench (144), at least two spaced virtual gate trenches (144) are provided between two adjacent effective gate trenches (145), the first contact hole (21) is provided on at least one side of the second transition region (150) in the second direction, and the first contact hole (21) is provided between two adjacent effective gate trenches (145) in the third direction, wherein the first main surface (101) and the second main surface (102) are spaced apart in the first direction, and the second direction, the third direction and the first direction are perpendicular to each other.

17. The transistor module according to claim 16, wherein: There are a plurality of first contact holes (21), and the plurality of first contact holes (21) and the virtual gate trench (144) are spaced apart in the second direction; The first contact hole (21) is in the shape of a long strip extending continuously in the third direction, and a plurality of the first contact holes (21) spaced apart in the second direction are provided between two adjacent effective gate trenches (145); and / or A plurality of the first contact holes (21) spaced apart in the third direction form a second contact hole group (2102), and a plurality of the second contact hole groups (2102) spaced apart in the second direction are provided between two adjacent effective gate trenches (145); and / or The first contact hole (21) is rectangular, and one first contact hole (21) is provided between two adjacent effective gate trenches (145).

18. The transistor module according to claim 16, wherein: The first contact hole (21) is in the shape of a long strip extending continuously in the second direction; a plurality of the first contact holes (21) spaced apart in a third direction are provided between adjacent virtual gate trenches (144) and the effective gate trenches (145); and a plurality of the first contact holes (21) spaced apart in the third direction are also provided between two adjacent virtual gate trenches (144).

19. The transistor module according to claim 14, wherein: The first contact hole (21) is arranged on at least one side of the second transition region (150) in the third direction.

20. The transistor module according to claim 19, wherein: In a top view, there are a plurality of first contact holes (21), and a plurality of first contact holes (21) spaced apart in the second direction form a first contact hole group (2101). There are a plurality of first contact hole groups (2101), and a plurality of first contact hole groups (2101) are spaced apart in the third direction.

21. The transistor module according to claim 20, characterized in that The first contact hole (21) is square; and / or The first contact hole (21) is in a long strip shape, and the first contact hole (21) is extended in the second direction; and / or The first contact hole (21) is in the shape of an elongated strip, and the first contact hole (21) is extended in the third direction.

22. The transistor module according to claim 19, wherein: In a top view, the first contact hole (21) is in the shape of a long strip extending continuously in the second direction, there are a plurality of first contact holes (21), and the plurality of first contact holes (21) are arranged at intervals in the third direction; and / or There is one first contact hole (21), and in a top view, the first contact hole (21) is rectangular.

23. The transistor module according to any one of claims 14 to 22, characterized in that In a top view, the total area of ​​the first contact hole (21) is S1, the total area of ​​the main junction region (112) is S3, and S1 and S3 satisfy the relationship: 3.2%≤S1 / S3≤50%.

24. The transistor module according to claim 14, wherein: The ion doping concentration of the first semiconductor region (141) is greater than the ion doping concentration of the main junction region (112).

25. The transistor module according to claim 14, wherein: The present invention also includes a base region (17) of the first conductive type and a blocking trench (143), wherein the base region (17) is arranged in the active region (140) and is located on the side of the drift layer (11) facing the first main surface (101), and the side of the base region (17) facing away from the drift layer (11) constitutes at least a part of the first main surface (101), and the blocking trench (143) passes through the main junction region (112) from the first main surface (101) in a depth direction and reaches the drift layer (11), and the blocking trench (143) is located between the second transition region (150) and the active region (140), and the two sides of the blocking trench (143) are the main junction region (112) and the base region (17) respectively.

26. The transistor module according to claim 14, wherein: Also includes: A polysilicon field plate (51), the polysilicon field plate (51) being arranged on the first main surface (101) and located in the second transition region (150), the polysilicon field plate (51) corresponding to an end of the main junction region (112) adjacent to the terminal region (160), the insulating layer (20) being located on a side of the polysilicon field plate (51) facing away from the first main surface (101), and a second contact hole (22) being formed in the insulating layer (20) adjacent to the polysilicon field plate (51); A second semiconductor region (142) of a second conductivity type is provided in the main junction region (112); a side of the second semiconductor region (142) facing away from the drift layer (11) constitutes at least a portion of the first main surface (101); the second semiconductor region (142) corresponds to the second contact hole (22); a second connection protrusion (32) is provided on the emitter metal layer (30); the second connection protrusion (32) penetrates the second contact hole (22) and is in contact and electrically connected with the second semiconductor region (142).

27. A method for manufacturing a transistor module, applicable to the transistor module according to any one of claims 1 to 26, characterized in that , including the following steps: preparing a substrate (10), and disposing a drift layer (11) of a first conductivity type in the substrate (10); Simultaneously implanting doping ions of a second conductivity type into the terminal region of the insulated gate bipolar transistor region (110) and the first transition region (120) to simultaneously form a main junction region in the terminal region of the insulated gate bipolar transistor region (110) and a secondary main junction region (12) in the first transition region (120); Etching a first trench (13) in the first transition region (120), wherein the depth of the first trench (13) extends from the first main surface (101) toward the secondary main junction region (12) in a first direction and does not extend beyond the secondary main junction region (12); Implanting dopant ions of a second conductivity type into the secondary main junction region (12) to form a base region (17); providing an insulating layer (20) on the first main surface (101); A first contact hole (21) is provided in a portion of the insulating layer (20) corresponding to the first transition region (120), wherein a projection of the first contact hole (21) in a first direction is staggered from a projection of the first trench (13) in the first direction, and dopant ions of a second conductivity type are implanted into the base region (17) to form a semiconductor region (14); An emitter metal layer (30) is provided on the insulating layer (20), a first connection protrusion (31) is provided on the emitter metal layer (30), and the first connection protrusion (31) penetrates the first contact hole (21) and contacts the semiconductor region (14).

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