Compound semiconductor device, AMD method for manufacturing compound semiconductor device

Abstract

Provided are: a compound semiconductor device having high performance by improving alignment accuracy; and a method for manufacturing the same.　This compound semiconductor device (1) comprises: a first substrate (10); a second substrate (20) which includes a compound semiconductor layer (21) segmented into individual pieces and is bonded to the surface of the first substrate (10), the compound semiconductor layer (21) including a plurality of elements (23) and separation regions (22) that separate the plurality of elements (23) from each other; and a first mark (4) disposed on the second substrate (20), and used for alignment of the compound semiconductor layer (21).

Description

Compound semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a compound semiconductor device and a method for manufacturing the compound semiconductor device.

[0002] Patent Document 1 discloses a light-emitting device and a method for manufacturing the light-emitting device. The light-emitting device includes a substrate and a light-emitting body. The light-emitting body is bonded to the substrate. The light-emitting body is formed of a compound semiconductor layer in which a plurality of light-emitting elements are arranged in a row and column direction. The compound semiconductor layer is cut out from a semiconductor wafer and separated into individual pieces having rectangular shapes in a plan view. In addition, optical lenses are arranged in the light-emitting device corresponding to the plurality of light-emitting elements. A drive circuit for driving the light-emitting elements is arranged on the substrate.

[0003] International Publication No. 2022 / 185976 A1

[0004] During the manufacturing process of a light-emitting device, particularly during the manufacturing process of a light-emitting body, a singulated compound semiconductor layer is attached to a support substrate, and in this state, multiple light-emitting elements, isolation regions between the light-emitting elements, electrodes, etc. are formed in the compound semiconductor layer. At this time, the outer shape of the compound semiconductor layer is used as a reference for alignment (positioning), and the compound semiconductor layer is attached to the support substrate. Because isolation regions between the light-emitting elements, electrodes, etc. are formed in the compound semiconductor layer attached to the support substrate, a deviation of, for example, 100 μm or more is tolerated for the alignment accuracy between the compound semiconductor layer and the support substrate. On the other hand, to improve the characteristics of the compound semiconductor layer, it is desirable to form isolation regions in the compound semiconductor layer before singulation, and then perform sidewall epitaxial growth at high temperatures, or sidewall doping or the formation of a sidewall protective film. However, with the alignment accuracy of the outer shape, the singulated compound semiconductor layer attached to the support substrate is misaligned, making it difficult to form electrodes, etc. relative to the alignment marks on the support substrate. Furthermore, in the manufacturing process of a light-emitting device, the separation regions between light-emitting elements in the compound semiconductor layer and electrodes formed relative to alignment marks on the support substrate are used as alignment references, and an optical lens is formed in the light-emitting body. However, because the individual compound semiconductor layers are misaligned, exposure misalignment occurs when multiple dies are exposed together in a single shot. The present disclosure provides a high-performance compound semiconductor device and a method for manufacturing a compound semiconductor device by improving the alignment accuracy of one or more selected from the light-emitting elements, separation regions, and optical lenses in the light-emitting body.

[0005] A compound semiconductor device according to a first embodiment of the present disclosure includes a first substrate, a singulated compound semiconductor layer, the compound semiconductor layer having a plurality of elements and isolation regions that isolate the plurality of elements, a second substrate bonded to a surface of the first substrate, and a first mark disposed on the second substrate and used for aligning the compound semiconductor layer.

[0006] In a compound semiconductor device according to a second embodiment of the present disclosure, the first mark in the compound semiconductor device according to the first embodiment is formed with the same configuration as at least a part of the isolation region.

[0007] A compound semiconductor device according to a third embodiment of the present disclosure is the compound semiconductor device according to the second embodiment, wherein the first mark is formed to contain a metal or a metal compound.

[0008] In a compound semiconductor device according to a fourth embodiment of the present disclosure, in the compound semiconductor device according to the second embodiment, the isolation region is formed by including a trench dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and a filling member filled in the trench, and the first mark is formed of the same material as the filling member.

[0009] In a compound semiconductor device according to a fifth embodiment of the present disclosure, in the compound semiconductor device according to the second embodiment, the isolation region is formed to include a trench dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and the first mark is formed by a trench having the same cross-sectional shape as the trench, or a mesa whose side surfaces are surrounded by a trench having the same cross-sectional shape as the trench.

[0010] A method for manufacturing a compound semiconductor device according to a sixth embodiment of the present disclosure includes forming a plurality of elements and an isolation region isolating the plurality of elements in a compound semiconductor layer, forming a first mark having the same configuration as at least a portion of the isolation region, forming a second substrate by singulating the compound semiconductor layer, forming a third mark on the third substrate to be used for alignment with the first mark, aligning the first mark with the third mark, and bonding the second substrate to the third substrate.

[0011] A method for manufacturing a compound semiconductor device according to a seventh embodiment of the present disclosure includes forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer, forming first marks having the same configuration as at least a portion of the isolation regions, forming a second substrate by singulating the compound semiconductor layer, and forming optical lenses in the second substrate that are aligned with the first marks and correspond to the plurality of elements. Here, in the method for manufacturing a compound semiconductor device according to the seventh embodiment, the optical lenses include second marks that are aligned with the first marks, and the optical lenses are formed in the second substrate by aligning the second marks with the first marks.

[0012] A method for manufacturing a compound semiconductor device according to an eighth embodiment of the present disclosure includes forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer, forming first marks having the same configuration as at least a portion of the isolation regions, forming second substrates by singulating the compound semiconductor layer, forming third marks on the third substrate to be used for alignment with the first marks, aligning the first marks with the third marks, bonding the second substrate to the third substrate, bonding the first substrate to a surface of the second substrate opposite to the surface to which the third substrate is attached, and then removing the third substrate, and forming optical lenses, aligned with the first marks as a reference, on the surface of the second substrate from which the third substrate has been removed, corresponding to the plurality of elements.

[0013] FIG. 1 is a schematic longitudinal sectional view of a main portion of a compound semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a schematic plan view of a main portion of the compound semiconductor device shown in FIG. 1. FIG. 3 is a schematic plan view of a semiconductor wafer forming a compound semiconductor layer of the compound semiconductor device shown in FIG. 2. FIG. 4 is an enlarged plan view including a main portion of the compound semiconductor layer of the compound semiconductor device shown in FIGS. 1 and 2. FIG. 5 is a cross-sectional view of a first step for explaining a manufacturing method of a compound semiconductor device according to a first embodiment (hereinafter simply referred to as a "first manufacturing method" in this section). FIG. 6 is a cross-sectional view of a second step of the first manufacturing method. FIG. 7 is a cross-sectional view of a third step of the first manufacturing method. FIG. 8 is a cross-sectional view of a fourth step of the first manufacturing method. FIG. 9 is a cross-sectional view of a fifth step of the first manufacturing method. FIG. 10 is a cross-sectional view of a sixth step of the first manufacturing method. FIG. 11 is a cross-sectional view of a seventh step of the first manufacturing method. FIG. 12 is a cross-sectional view of an eighth step of the first manufacturing method. FIG. 13 is a cross-sectional view of a ninth step of the first manufacturing method. FIG. 14 is a cross-sectional view of a tenth step of the first manufacturing method. FIG. 15 is a cross-sectional view at an eleventh step of the first manufacturing method. FIG. 16 is an enlarged cross-sectional view at a step of a main portion of the compound semiconductor device shown in FIG. 15. FIG. 17 is a cross-sectional view at a twelfth step of the first manufacturing method. FIG. 18 is a cross-sectional view at a thirteenth step of the first manufacturing method. FIG. 19 is a cross-sectional view at a fourteenth step of the first manufacturing method. FIG. 20 is a cross-sectional view at a fifteenth step of the first manufacturing method. FIG. 21 is a cross-sectional view at a sixteenth step of the first manufacturing method. FIG. 22 is a cross-sectional view at a seventeenth step of the first manufacturing method. FIG. 23 is a cross-sectional view at an eighteenth step of the first manufacturing method. FIG. 24 is a cross-sectional view at a nineteenth step of the first manufacturing method. FIG. 25 is a cross-sectional view at a twentieth step of the first manufacturing method. FIG. 26 is a cross-sectional view at a twenty-first step of the first manufacturing method. FIG. 27 is a cross-sectional view at a twenty-second step of the first manufacturing method. FIG. 28 is a cross-sectional view at a twenty-third step of the first manufacturing method. FIG. 29 is a cross-sectional view at a twenty-fourth step of the first manufacturing method. Fig. 30 is a plan view of the compound semiconductor device in the cross-sectional view at the 24th step shown in Fig. 29. Fig. 31 is a cross-sectional view at the 25th step of the first manufacturing method. Fig. 32 is a cross-sectional view at the 26th step of the first manufacturing method. Fig. 33 is a cross-sectional view at the 27th step of the first manufacturing method. Fig. 34 is a cross-sectional view at the 28th step of the first manufacturing method. Fig. 35 is a plan view of the compound semiconductor device in the cross-sectional view at the 28th step shown in Fig. 29.FIG. 36 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a second embodiment of the present disclosure. FIG. 37 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 36 . FIG. 38 is an enlarged cross-sectional view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a first modified example of the second embodiment. FIG. 39 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 38 . FIG. 40 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a second modified example of the second embodiment. FIG. 41 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 40 . FIG. 42 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a third modified example of the second embodiment. FIG. 43 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 42 . FIG. 44 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a fourth modified example of the second embodiment. FIG. 45 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 44 . FIG. 46 is a schematic longitudinal cross-sectional configuration view corresponding to FIG. 1 of a main portion of a compound semiconductor device according to a third embodiment of the present disclosure. FIG. 47 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to the third embodiment. FIG. 48 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 47 at a predetermined step. FIG. 49 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a first modified example of the third embodiment. FIG. 50 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 49 at a predetermined step. FIG. 51 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a second modified example of the third embodiment. FIG. 52 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 51 at a predetermined step.FIG. 53 is an enlarged plan view corresponding to FIG. 4 including a main portion of a compound semiconductor layer at a predetermined step in a manufacturing method of a compound semiconductor device according to a third modified example of the third embodiment. FIG. 54 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 53 at a predetermined step in a manufacturing method of a compound semiconductor device according to a fourth modified example of the third embodiment. FIG. 55 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 55 at a predetermined step in a manufacturing method of a compound semiconductor device according to a fourth modified example of the third embodiment. FIG. 56 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 55 at a predetermined step in a manufacturing method of a compound semiconductor device according to a fifth modified example of the third embodiment. FIG. 58 is an enlarged cross-sectional view corresponding to FIG. 15 of a main portion of the compound semiconductor device shown in FIG. 57 at a predetermined step in a manufacturing method of a compound semiconductor device according to a fifth modified example of the third embodiment. FIG. 59 is a schematic vertical cross-sectional view corresponding to FIG. 1 of a main portion of a compound semiconductor device according to a fourth embodiment of the present disclosure. FIG. 60 is a schematic vertical cross-sectional view corresponding to FIG. 1 of a main portion of a compound semiconductor device according to a fifth embodiment of the present disclosure. FIG. 61 is a cross-sectional view at a first step for explaining a manufacturing method of a compound semiconductor device according to a fifth embodiment (hereinafter, in this section, simply referred to as the "fifth manufacturing method"). FIG. 62 is a cross-sectional view at a second step of the fifth manufacturing method. FIG. 63 is a plan view of the compound semiconductor device in the cross-sectional view at the second step shown in FIG. 62. FIG. 64 is a cross-sectional view at a third step of the fifth manufacturing method. FIG. 65 is a cross-sectional view at a fourth step of the fifth manufacturing method. FIG. 66 is a plan view of the compound semiconductor device in the cross-sectional view at the fourth step shown in FIG. 65. FIG. 67 is a cross-sectional view at a fifth step of the fifth manufacturing method. FIG. 68 is a cross-sectional view at a sixth step of the fifth manufacturing method. FIG. 69 is a cross-sectional view at a sixth step of the fifth manufacturing method. FIG. 70 is a cross-sectional view at a seventh step of the fifth manufacturing method. FIG. 71 is a cross-sectional view at an eighth step of the fifth manufacturing method. FIG. 72 is a cross-sectional view at a ninth step of the fifth manufacturing method. FIG. 73 is a cross-sectional view at a tenth step of the fifth manufacturing method. FIG. 74 is a cross-sectional view at an eleventh step of the fifth manufacturing method. Fig. 75 is a cross-sectional view of a twelfth step of the fifth manufacturing method. Fig. 76 is a cross-sectional view of a thirteenth step of the fifth manufacturing method. Fig. 77 is a cross-sectional view of a fourteenth step of the fifth manufacturing method. Fig. 78 is a cross-sectional view of a fifteenth step of the fifth manufacturing method. Fig. 79 is a cross-sectional view of a sixteenth step of the fifth manufacturing method.80 is a cross-sectional view of a 17th step of the fifth manufacturing method. FIG. 81 is a cross-sectional view of an 18th step of the fifth manufacturing method. FIG. 82 is a cross-sectional view of a 19th step of the fifth manufacturing method. FIG. 83 is a cross-sectional view of a 20th step of the fifth manufacturing method. FIG. 84 is a cross-sectional view of a 21st step of the fifth manufacturing method. FIG. 85 is a schematic longitudinal cross-sectional configuration diagram corresponding to FIG. 1 of a main part of a compound semiconductor device according to a sixth embodiment of the present disclosure. FIG. 86 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 87 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit. FIG. 88 is a block diagram showing an example of a schematic configuration of an in-vivo information acquisition system. FIG. 89 is a front view showing an example of the appearance of a digital still camera which is a first application example of the light emitting device of the present disclosure. FIG. 90 is a rear view showing an example of the appearance of the digital still camera shown in FIG. 89. FIG. 91 is a perspective view showing an example of the appearance of a head-mounted display which is a second application example of the light emitting device of the present disclosure. FIG. 92 is a perspective view showing an example of the appearance of a television device which is a third application example of the light emitting device of the present disclosure.

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment describes a first example in which the present technology is applied to a compound semiconductor device and a method for manufacturing the compound semiconductor device. The first embodiment describes in detail the longitudinal cross-sectional structure, planar structure, and manufacturing method of the compound semiconductor device. 2. Second Embodiment The second embodiment describes a second example in which the structure of the mark used for alignment is changed in the compound semiconductor device and the method for manufacturing the compound semiconductor device according to the first embodiment. The second embodiment also describes several modified examples. 3. Third Embodiment The third embodiment describes a third example in which the structure of the mark used for alignment is changed in the compound semiconductor device and the method for manufacturing the compound semiconductor device according to the first embodiment. The second embodiment also describes several modified examples. 4. Fourth Embodiment The fourth embodiment describes a fourth example in which the structure of the mark used for alignment is changed in the compound semiconductor device and the method for manufacturing the compound semiconductor device according to the first embodiment. 5. Fifth Embodiment The fifth embodiment describes a fifth example in which the structure of the mark used for alignment is changed in the compound semiconductor device and the method for manufacturing the compound semiconductor device according to the first embodiment. In the fifth embodiment, the longitudinal cross-sectional structure, planar structure, and manufacturing method of the compound semiconductor device will be described in detail. 6. Sixth embodiment The sixth embodiment will describe a sixth example in which the structure of the mark used for alignment is changed in the compound semiconductor device and manufacturing method of the compound semiconductor device according to the fifth embodiment. 7. Application example to a moving body This application example is an example in which the present technology is applied to a moving body. 8. Application example to an in-vivo information acquisition system This application example is an example in which the present technology is applied to an in-vivo information acquisition system. 9. First to third application examples The first application example is an example in which the present technology is applied to a digital still camera. The second application example is an example in which the present technology is applied to a head-mounted display. The third application example is an example in which the present technology is applied to a television device. 10. Other embodiments

[0015] 1 to 35 , a compound semiconductor device 1 and a manufacturing method for the compound semiconductor device 1 according to a first embodiment of the present disclosure will be described. Here, the arrow X direction shown as appropriate in the figures indicates one planar direction of the compound semiconductor device 1 placed on a flat surface for convenience. The arrow Y direction indicates another planar direction perpendicular to the arrow X direction. The arrow Z direction indicates an upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are shown to facilitate understanding of the description and do not limit the directions of the present technology.

[0016] [Configuration of Compound Semiconductor Device 1] (1) Overall Schematic Configuration of Compound Semiconductor Device 1 FIG. 1 shows an example of a longitudinal cross-sectional configuration of a main part of the compound semiconductor device 1. FIG. 2 shows an example of a planar configuration of a main part of the compound semiconductor device 1. The compound semiconductor device 1 according to the first embodiment constitutes a light-emitting device having a plurality of light-emitting elements 23 (see FIGS. 1 and 2 ), each of which emits light. For example, the compound semiconductor device 1 constitutes a micro-light-emitting device. Furthermore, although illustration and detailed description here are omitted, the basic structure is substantially the same, and therefore the compound semiconductor device 1 can also be constructed as a light-receiving device having a plurality of light-receiving elements, each of which receives light.

[0017] 1 and 2 , a compound semiconductor device 1 according to a first embodiment of the present technology includes a first base 10, a second base 20, and an optical lens 5, which are sequentially stacked in the direction of the arrow Z when viewed in the direction of the arrow Y (hereinafter simply referred to as "side view"). The compound semiconductor device 1 is configured to emit light L in the direction of the arrow Z.

[0018] (2) Configuration of First Base 10 The first base 10 includes a substrate 11. That is, the first base 10 includes the substrate 11 and a wiring layer 12. The substrate 11 is, for example, a single-crystal silicon (Si) substrate. Although the actual device structure is not shown, a drive circuit 110 that drives the light-emitting element 23 is disposed on the substrate 11. The drive circuit 110 is constructed with elements such as transistors, capacitors, and resistors. The transistors are, for example, insulated gate field-effect transistors. When the compound semiconductor device 1 is constructed as a light-receiving device, a readout circuit that reads out information from the light-receiving element is provided on the first base 10.

[0019] A wiring layer 12 is disposed on the surface of the substrate 11 on the arrow Z direction side. The wiring layer 12 includes, within an insulating layer 123, wiring 121 disposed on the substrate 11 side and wiring 122 disposed on the second base 20 side. Here, each of the wiring 121 and the wiring 122 is a single layer, but at least one of them may be multi-layered. The wiring 121 electrically connects elements of the drive circuit 110, for example. The wiring 121 is formed, for example, with aluminum (Al) as its main composition. The wiring 122 is formed, for example, with copper (Cu) as its main composition. The insulating layer 123 is actually formed of multiple layers. The insulating layer 123 may be formed, for example, with a silicon nitride (SiN) film or a silicon oxide (SiO ２ ) membranes can be practically used.

[0020] Furthermore, terminals 121P1 and 121P2 are disposed on the surface of the substrate 11 in the peripheral region of the first base 10, specifically, in the region corresponding to the outer periphery of the compound semiconductor layer 21 of the second base 20. A plurality of terminals 121P1 are disposed along the periphery of the side surface of the compound semiconductor layer 21 (see FIG. 30 ). The terminals 121P1 are electrically connected to the light-emitting elements 23 disposed in the compound semiconductor layer 21. A plurality of terminals 121P2 are disposed along the periphery of the side surface of the compound semiconductor layer 21, further outward than the terminals 121P1 (see FIG. 35 ). The terminals 121P2 are configured to be electrically connected to an external device (or terminal) (not shown) of the compound semiconductor device 1. For example, a wire W is used for the connection.

[0021] Each of the terminals 121P1 and 121P2 is disposed in the same conductive layer as the wiring 121 and is made of the same conductive material as the wiring 121. In other words, each of the terminals 121P1 and 121P2 is formed in the same manufacturing process as the wiring 121 in the manufacturing method of the compound semiconductor device 1.

[0022] Although illustrations and detailed explanations are omitted, the wiring layer 12 is provided with one or more selected from a shielding film that blocks light leaking from the light-emitting element 23 to the drive circuit 110 side and a light-absorbing film that absorbs the leaking light.

[0023] 1 and 2 , the second base 20 is attached to the surface of the first base 10 on the arrow Z direction side, and is bonded to the surface of the first base 10. The second base 20 is configured to include a compound semiconductor layer 21. When viewed from the arrow Z direction (hereinafter simply referred to as "in a plan view"), a plurality of light-emitting elements 23 are regularly arranged in the arrow X direction and the arrow Y direction in the compound semiconductor layer 21.

[0024] (3-1) Configuration of Compound Semiconductor Layer 21 FIG. 3 shows an example of a schematic planar configuration of the semiconductor wafer 200. As shown in FIGS. 2 and 3, the compound semiconductor layer 21 is formed from the semiconductor wafer 200. A detailed description will be given. In the method for manufacturing the compound semiconductor device 1, a plurality of compound semiconductor layer 21 regions are formed in the semiconductor wafer 200. Then, a plurality of compound semiconductor layers 21 are cut out from the semiconductor wafer 200 by dicing, thereby forming individual compound semiconductor layers 21. In a planar view, the compound semiconductor layer 21 has a rectangular planar shape. Here, the planar shape of the compound semiconductor layer 21 is formed, for example, in a square shape.

[0025] In the first embodiment, the compound semiconductor layer 21 is formed mainly from a III-V group compound semiconductor, such as gallium nitride (GaN).

[0026] 1 and 2, the compound semiconductor layer 21 includes a plurality of light-emitting elements 23 and isolation regions 22 that isolate the plurality of light-emitting elements 23. In other words, the lateral periphery of each of the plurality of light-emitting elements 23 is surrounded by the isolation region 22.

[0027] The isolation region 22 is formed to include a groove 22A, a buried member 22B, and a buried member 22C. In a side view, the groove 22A is dug from a first surface 21A on the arrow Z direction side of the compound semiconductor layer 21 toward a second surface 21B opposite the first surface 21A. Here, the groove 22A penetrates the compound semiconductor layer 21 in the thickness direction. In a plan view, the grooves 22A extend in the arrow X direction and are arranged at regular intervals in the arrow Y direction, and further extend in the arrow Y direction and are arranged at regular intervals in the arrow X direction. In other words, the grooves 22A are formed in a lattice shape in a plan view.

[0028] The embedding member 22B is disposed along the inner wall of the groove 22A and is made of an insulating material, for example, SiO ２ and SiN.

[0029] The embedding member 22C is embedded in the groove 22A with the embedding member 22B interposed therebetween. Because the embedding member 22B is made of an insulating material, the embedding member 22C is formed to contain a metal or a metal compound. More specifically, the embedding member 22C is formed to contain one or more selected from titanium (Ti), tungsten (W), Al, Cu, cobalt (Co), silver (Ag), gold (Au), nickel (Ni), palladium (Pd), titanium nitride (TiN), and tantalum nitride (TaN). In the first embodiment, the isolation region 22 is formed to have light-blocking properties and optically separate adjacent light-emitting elements 23, and is therefore formed, for example, from light-blocking Ti. Furthermore, when the isolation region 22 is to have reflectivity, it is formed, for example, from Al.

[0030] 1, the light-emitting element 23 is configured by sequentially stacking a first compound semiconductor 23A, an active layer 23B, and a second compound semiconductor 23C from the second surface 21B side toward the first surface 21A of the compound semiconductor layer 21. That is, the light-emitting element 23 is configured by a light-emitting diode (LED). The first compound semiconductor 23A is formed of, for example, n-type GaN. The second compound semiconductor 23C is formed of, for example, p-type GaN.

[0031] (3-4) Configuration of the Wiring Layer 25, Electrode 26, and Wiring 27 The second base 20 includes a compound semiconductor layer 21, a wiring layer 25, an electrode 26, and wiring 27. The wiring layer 25 is disposed on the second surface 21B of the compound semiconductor layer 21. The wiring layer 25 includes, within an insulating layer 253, an electrode 251 disposed on the compound semiconductor layer 21 side, and wiring 252 disposed on the first base 10 side. Here, the electrode 251 and the wiring 252 are each a single layer, but at least one of them may be a multi-layer. The electrode 251 electrically connects the first compound semiconductor 23A and the wiring 252. The electrode 251 is preferably an electrode that can make ohmic contact with a semiconductor layer containing one or more selected from titanium (Ti), tungsten (W), Al, gold (Au), nickel (Ni), palladium (Pd), titanium nitride (TiN), and tantalum nitride (TaN), but may be formed from the same conductive material as the wiring 121. The wiring 252 is electrically connected to the wiring 122 of the first base 10. The wiring 252 is formed from, for example, the same conductive material as the wiring 122. The insulating layer 253 is actually formed from a plurality of layers. The insulating layer 253 is formed from, for example, a SiN film or SiO ２ can be used practically.

[0032] In the first embodiment, the wiring 122 of the first base 10 and the wiring 252 of the second base 20 are electrically connected and mechanically joined by a Cu--Cu bonding structure.

[0033] An electrode 26 is disposed on the first surface 21A side of the compound semiconductor layer 21. The electrode 26 is electrically connected to the second compound semiconductor 23C of the light-emitting element 23. The electrode 26 is formed of a transparent electrode material such as indium tin oxide (ITO).

[0034] The electrode 26 is electrically connected to the terminal 121P1 of the first base 10 via a wiring 27 and an opening 253H1 formed in the insulating layer 253. An opening 253H2 is also formed in the insulating layer 253, and the wire W is electrically connected to the terminal 121P2 of the first base 10 through the opening 253H2.

[0035] (4) Configuration of the Optical Lens 5 In the second base 20, the optical lens 5 is disposed on the first surface 21A side of the compound semiconductor layer 21 with a protective film 28 interposed therebetween. In the first embodiment, the optical lens 5 is formed in a cross-sectional shape that curves in the direction of the arrow Z for each light-emitting element 23 in a side view. In other words, the optical lens 5 collects the light L emitted from the light-emitting element 23. The optical lens 5 is formed of, for example, a resin material or an inorganic material. The optical lens 5 is formed as a so-called on-chip lens.

[0036] (5) Configuration of Mark 4 As shown in Figures 1 and 2, in the first embodiment, the mark 4 is provided on the second base 20. A detailed description will be given below. The mark 4 is used for alignment (positioning) in the manufacturing process of the compound semiconductor layer 21. The mark 4 will be described in the manufacturing method of the compound semiconductor device 1, and here, the mark 4 is used for one or more selected from alignment between the compound semiconductor layer 21 and the third base (support substrate) 30 and alignment between the compound semiconductor layer 21 and the optical lens 5.

[0037] The marks 4 are disposed on the first surface 21A of the compound semiconductor layer 21 of the second substrate 20, outside the region in which a plurality of light-emitting elements 23 are arranged. The light-emitting elements 23 are, in other words, "pixels" that emit light. The marks 4 are disposed outside the pixel region PE in which a plurality of these pixels are arranged. While the number of marks 4 is not limited, in the first embodiment, the pixel region PE is formed in a rectangular shape in a plan view, and a mark 4 is disposed at each of the four corners of the pixel region PE. In other words, four marks 4 are disposed. Although it depends on the planar shape of the marks 4, as long as two or more marks 4 are disposed, alignment of the compound semiconductor layer 21 can be achieved.

[0038] 4 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21. As shown in Fig. 2 and Fig. 4, the mark 4 extends from a corner portion of the pixel region PE slightly along a side portion of the pixel region PE, and is formed in an L-shape in plan view.

[0039] 1, the mark 4 is formed with the same configuration as at least a part of the isolation region 22. To explain in more detail, in the first embodiment, the mark 4 is formed of the same material as the embedding member 22C embedded in the groove 22A of the isolation region 22. In other words, the mark 4 is formed to contain a metal or a metal compound.

[0040] Here, the mark 4 corresponds to a "first mark" according to the present technology. The mark 4 may be disposed within the pixel region PE. When the pixel region PE is formed to include an effective pixel region and a non-effective pixel region, the mark 4 can be disposed in at least one of the effective pixel region and the non-effective pixel region. A light-emitting element 23 that actually emits light is disposed in the effective pixel region. Furthermore, a dummy light-emitting element that does not emit light is disposed in the non-effective pixel region.

[0041] [Method for Manufacturing Compound Semiconductor Device 1] The method for manufacturing the compound semiconductor device 1 according to the first embodiment includes the manufacturing steps shown in Figure 5 to Figure 35. The method for manufacturing the compound semiconductor device 1 is as follows.

[0042] (1) Manufacturing Method of Second Base 20 First, a semiconductor wafer 200 is prepared as shown in Fig. 5. Here, the semiconductor wafer 200 is, for example, in a state where a compound semiconductor layer 210 is formed on a single crystal Si substrate 201. The compound semiconductor layer 210 is formed by sequentially stacking a first compound semiconductor (n-GaN) 230A, an active layer 230B, and a second compound semiconductor (p-GaN) 230C on the surface of the single crystal Si substrate 201.

[0043] 6, in a semiconductor wafer 200, a mask 61 is formed on the surface of a compound semiconductor layer 210. In the mask 61, an opening 61H1 is formed in a region where the isolation region 22 is to be formed, and an opening 61H2 is formed in a region where the mark 4 is to be formed. The mask 61 is made of, for example, SiN as a hard mask.

[0044] 7, a mask 62 that covers the opening 61H2 is formed on the mask 61. The mask 62 is made of, for example, a photoresist.

[0045] 8, the compound semiconductor layer 210 exposed from the opening 61H1 is removed using the mask 61 and the mask 62, thereby forming the groove 22A of the isolation region 22. Here, for example, dry etching is used.

[0046] As shown in FIG. 9, mask 62 is removed, and then mask 61 is removed.

[0047] 10, a burying member 22B is formed along the surface of the compound semiconductor layer 210 and the inner wall of the groove 22A. The burying member 22B is made of, for example, SiO ２ It is formed by SiO ２ The insulating film is formed by a method with good step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0048] 11 , a buried member 22C is formed on the surface of the compound semiconductor layer 210 and in the groove 22A with a buried member 22B interposed therebetween. The buried member 22C is made of, for example, Ti. The Ti is formed by, for example, a CVD method or a sputtering method. In the manufacturing method of the compound semiconductor device 1 according to the first embodiment, in the same step as the step of forming the buried member 22C, a mark 4 made of the same material as the buried member 22C and arranged in the same layer as the buried member 22C is formed.

[0049] Subsequently, the excess embedded members 22C and 22B on the surface of the compound semiconductor layer 210 are sequentially removed, and the surface of the compound semiconductor layer 210 is planarized (see FIG. 12). For example, chemical mechanical polishing (CMP) is used for planarization. Then, as shown in FIG. 12, an insulating film 63 is formed on the surface of the compound semiconductor layer 210. The insulating film 63 is made of, for example, SiO ２ It is formed by

[0050] 12, a separation region 22 is formed in the compound semiconductor layer 210. Furthermore, the separation region 22 subdivides the first compound semiconductor 230A, the active layer 230B, and the second compound semiconductor 230C into first compound semiconductor 23A, active layer 23B, and second compound semiconductor 23C, thereby forming a plurality of light-emitting elements 23. That is, as shown in the above-mentioned FIG. 3, a semiconductor wafer 200 is formed having a plurality of regions of the compound semiconductor layer 21.

[0051] 13, the surface of the insulating film 63 is planarized by CMP.

[0052] As shown in FIG. 14, the semiconductor wafer 200 is diced to form a plurality of individual compound semiconductor layers 21 .

[0053] (2) Method for Manufacturing the Electrodes 251 and Wiring 252 of the Second Base 20 As shown in Fig. 15 , a third base 30 is prepared, and the singulated compound semiconductor layer 21 is attached and bonded to the surface of this third base 30. The third base 30 is a support substrate used when forming the electrodes 251 and wiring 252 shown in Fig. 1. The third base 30 is formed using, for example, a single crystal Si substrate as a main component.

[0054] 16 shows an example of an enlarged cross-sectional configuration of a main part during a manufacturing process of the compound semiconductor device 1. FIG. 16 corresponds to a cross-sectional view taken along the line A-A shown in FIG. 4 described above. As shown in FIGS. 4, 15, and 16, a mark 31 is formed in advance on the surface of the third base 30. The mark 31 is used for alignment with the mark 4. In the first embodiment, the planar shape of the mark 31 is formed in point symmetry with respect to the planar shape of the mark 4 of the compound semiconductor layer 21.

[0055] The mark 4 of the compound semiconductor layer 21 is aligned with the mark 31 of the third base 30, and the first surface 21A side of the compound semiconductor layer 21 is bonded to the surface of the third base 30. Here, the mark 31 corresponds to the “third mark” according to the present technology.

[0056] 17 , the single-crystal Si substrate 201 of the semiconductor wafer 200 that was bonded to the second surface 21B side of the compound semiconductor layer 21 is removed. This step exposes the second surface 21B side of the compound semiconductor layer 21. Grinding or wet etching is used to remove the single-crystal Si substrate 201.

[0057] 18, an insulating film 64 is formed on the second surface 21B of the compound semiconductor layer 21. The insulating film 64 is made of, for example, tetraethoxysilane (TEOS) and is formed by a CVD method.

[0058] 19 , an opening 64H is formed in the insulating film 64 at a position corresponding to the first compound semiconductor 23A of the light-emitting element 23. The opening 64H is formed by etching using a mask formed by photolithography, for example. As shown in FIG. 20 , an electrode 251 is formed on the insulating film 64 and electrically connected to the first compound semiconductor 23A through the opening 64H.

[0059] 21, an insulating layer 253 covering the compound semiconductor layer 21 is formed on the surface of the third substrate 30. Subsequently, as shown in Fig. 22, the surface of the insulating layer 253 is planarized. For example, a CMP method is used for planarization.

[0060] Subsequently, an opening (reference numeral omitted) that leads to the electrode 251 is formed in the insulating layer 253 (see FIG. 23 ). As shown in FIG. 23 , a wiring 252 that is electrically connected to the electrode 251 through the opening formed in the insulating layer 253 is formed in the opening.

[0061] (3) Manufacturing Method of Electrodes 26 and Wiring 27 of Second Base 20 As shown in Fig. 24, a first base 10 is prepared, and a compound semiconductor layer 21 is attached and bonded to the surface of this first base 10. As shown in Fig. 1, the first base 10 includes a substrate 11 and a wiring layer 12. Wiring 121, wiring 122, terminals 121P1, and terminals 121P2 are already formed on the wiring layer 12. In addition, a driving circuit 110 is already formed on the first base 10. To explain in more detail, the wiring 122 of the first base 10 is bonded to the wiring 252 of the compound semiconductor layer 21, thereby bonding the compound semiconductor layer 21 to the first base 10.

[0062] 25 , the third base 30 bonded to the first surface 21A side of the compound semiconductor layer 21 is removed. This step exposes the first surface 21A side of the compound semiconductor layer 21. Grinding or wet etching is used to remove the third base 30.

[0063] 26 , an opening 63H is formed in the insulating film 63 at a position corresponding to the second compound semiconductor 23C of the light-emitting element 23. The opening 63H is formed by etching using a mask formed by photolithography, for example. As shown in FIG. 27 , a wiring 27 is formed on the insulating film 63, electrically connected to the second compound semiconductor 23C through the opening 63H.

[0064] 28 , a first protective film 28A of the protective film 28 is formed to cover the electrode 26. As shown in FIGS. 29 and 30 , an opening 253H1 is formed around the outer periphery of the compound semiconductor layer 21 at a position corresponding to the terminal 121P1 of the first base 10, penetrating the first protective film 28A, the insulating film 63, and the insulating layer 253. The opening 253H1 is formed by dry etching using a mask formed by photolithography, for example. When the opening 253H1 is formed, the surface of the terminal 121P1 is exposed.

[0065] 31, a wiring 27 is formed through the opening 253H1 to electrically connect the electrode 26 and the terminal 121P1. By this step, the second compound semiconductor 23C of the light emitting element 23 and the terminal 121P1 are electrically connected.

[0066] 32, a second protective film 28B of the protective film 28 is formed to cover the wiring 27. When this step is completed, the individualized second base body 20 is substantially completed.

[0067] (4) Manufacturing Method of Optical Lens 5 Next, as shown in FIG. 33, the optical lens 5 is formed on the second substrate 20 on the first surface 21A side of the compound semiconductor layer 21.

[0068] Although a detailed description of the process will be omitted, the optical lens 5 is formed by first forming, for example, a transparent resin film, and then forming a mask on the transparent resin film. The mask is a photoresist mask formed by photolithography. The mask is exposed using a reticle 50 of an exposure tool, which is shown imaginarily by a dashed line in FIG. 33 . The reticle 50 has a light-shielding film 53 that forms the pattern of the optical lens 5 on a transparent glass substrate 51, and further has a mark 52. The mark 52 of the reticle 50 is aligned with the mark 4 of the compound semiconductor layer 21. When the transparent resin film is reflowed using the mask, the optical lens 5 having a curved shape in side view is formed. Here, the mark 52 corresponds to the "second mark" according to the present technology.

[0069] 34 and 35 , an opening 253H2 is formed around the compound semiconductor layer 21 and the terminal 121P1 at a position corresponding to the terminal 121P2 of the first base 10, penetrating the optical lens 5, the first protective film 28A, the insulating film 63, and the insulating layer 253. The opening 253H2 is formed by dry etching using a mask formed by photolithography, for example. When the opening 253H2 is formed, the surface of the terminal 121P2 is exposed.

[0070] As shown in FIG. 1, a wire W is bonded to the terminal 121P2 through the opening 253H2.

[0071] When this series of steps is completed, the compound semiconductor device 1 according to the first embodiment is completed, and the manufacturing method is completed.

[0072] [Effects] As shown in FIGS. 1 and 2 , the compound semiconductor device 1 according to the first embodiment includes a first base 10 and a second base 20. The second base 20 has an individualized compound semiconductor layer 21, which includes a plurality of light-emitting elements 23 and isolation regions 22 separating the light-emitting elements 23. The second base 20 is bonded to the surface of the first base 10. A mark (first mark) 4 is disposed on the second base 20. The mark 4 is used for aligning the compound semiconductor layer 21. With the compound semiconductor device 1 configured in this manner, the plurality of light-emitting elements 23, the isolation regions 22, the electrodes 251 and 26 connected to the plurality of light-emitting elements 23, the wiring 27, and the like can be formed using the mark 4 as a reference for alignment. The alignment accuracy here is higher than when the outer shape of the compound semiconductor layer 21 is used as a reference. The alignment accuracy is, for example, 2 μm or less.

[0073] For example, in the compound semiconductor device 1, the alignment precision between the plurality of light emitting elements 23 and the electrodes 251, 26, wiring 27, etc. is improved, so that minute light emitting elements 23 can be formed.

[0074] Furthermore, since the alignment accuracy is improved, the separation region 22 can be formed in the compound semiconductor layer 21 in a process prior to the process of bonding the individual compound semiconductor layer 21 to the third base 30 (see FIG. 15 ). For example, the separation region 22 can be formed using a high-temperature process, and the generation of dark current in the separation region 22 can be effectively suppressed or prevented.

[0075] 33, the mark 4 is used as a reference for alignment to form the optical lens 5. This allows the light-emitting center position of the light-emitting element 23 to coincide with the optical axis of the optical lens 5, thereby improving the light-emitting efficiency.

[0076] As described above, the alignment accuracy can be improved, and therefore a high-performance compound semiconductor device 1 can be provided.

[0077] 1 and 2, in the compound semiconductor device 1, the mark 4 is disposed outside the region (pixel region PE) in which the plurality of light-emitting elements 23 are disposed. According to the compound semiconductor device 1 configured in this manner, the mark 4 can be disposed without changing the shapes of the light-emitting elements 23 or the isolation region 22. In other words, in the manufacturing method of the compound semiconductor device 1 according to the first embodiment, the mark 4 can be formed simply by adding a pattern for the opening 61H2 to the mask 61 in the step shown in FIG. 6. Therefore, the mark 4 can be disposed easily, and as described above, a high-performance compound semiconductor device 1 can be provided.

[0078] 1 and 2, in the compound semiconductor device 1, the mark 4 is formed with the same configuration as at least a portion of the isolation region 22. Here, the mark 4 is formed to contain a metal or a metal compound. More specifically, the mark 4 is formed of the same material as the embedded member 22C of the isolation region. According to the compound semiconductor device 1 configured in this manner, the mark 4 is formed using the configuration of at least a portion of the isolation region 22, so that the mark 4 can be easily disposed, and as described above, a high-performance compound semiconductor device 1 can be provided.

[0079] 5 to 13 , the manufacturing method of the compound semiconductor device 1 according to the first embodiment first forms a plurality of light-emitting elements 23 and isolation regions 22 separating the plurality of light-emitting elements 23 in the compound semiconductor layer 21, and then forms marks 4 having the same configuration as at least a portion of the isolation regions 22. Next, as shown in FIG. 14 , a second base 20 is formed by singulating the compound semiconductor layer 21. Next, a mark 31 used for alignment with the mark 4 is formed on the third base 30 (see FIGS. 4 , 15 , and 16 ). Next, as shown in FIGS. 4 , 15 , and 16 , the mark 4 is aligned with the mark 31, and the second base 20 is bonded to the third base 30. According to the manufacturing method of the compound semiconductor device 1 configured in this manner, the alignment accuracy between the plurality of light-emitting elements 23 and the electrodes 251, 26, wiring 27, etc. can be improved in the compound semiconductor device 1, thereby enabling the manufacture of a high-performance compound semiconductor device 1.

[0080] 5 to 13, the method for manufacturing the compound semiconductor device 1 according to the first embodiment first forms a plurality of light-emitting elements 23 and isolation regions 22 separating the plurality of light-emitting elements 23 in the compound semiconductor layer 21, and then forms marks 4 having the same configuration as at least a portion of the isolation regions 22. Next, as shown in FIG. 14, a second base 20 is formed by singulating the compound semiconductor layer 21. Next, as shown in FIG. 33, optical lenses 5 are formed on the second base 20 in correspondence with the plurality of light-emitting elements 23, aligned with reference to the marks 4. According to the method for manufacturing the compound semiconductor device 1 configured in this manner, the alignment accuracy between the plurality of light-emitting elements 23 and the optical lenses 5 in the compound semiconductor device 1 can be improved, thereby enabling the manufacture of a high-performance compound semiconductor device 1.

[0081] 36 to 45, a compound semiconductor device 1 and a manufacturing method for the compound semiconductor device 1 according to a second embodiment of the present disclosure will be described. The second embodiment describes an example in which the structures of the marks 4 and 31 used for alignment are changed in the compound semiconductor device 1 and the manufacturing method for the compound semiconductor device 1 according to the first embodiment.

[0082] In the second embodiment, the embodiments subsequent to the second embodiment, and the modified examples thereof, the same or substantially the same components as those of the compound semiconductor device 1 and its manufacturing method according to the first embodiment are designated by the same reference numerals, and duplicated explanations will be omitted.

[0083] [Configuration of Compound Semiconductor Device 1] Fig. 36 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21. Fig. 37 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1. Fig. 37 corresponds to a cross-sectional view taken along the line B-B shown in Fig. 36 described above. Note that the cross-sectional location is the same in first to fourth modified examples described below.

[0084] 36 and 37 , the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 according to the second embodiment is formed in a rectangular shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 31 disposed on the third base 30 is formed in a rectangular shape that is slightly larger than the mark 4. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 31, and the singulated compound semiconductor layer 21 is bonded to the third base 30 (see FIG. 15 ).

[0085] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0086] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the second embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the first embodiment can be obtained.

[0087] 38 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a first modification of the second embodiment. Fig. 39 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0088] 38 and 39 , in the first modification of the second embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in a cross shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 31 disposed on the third base 30 is formed in a parenthetical shape located on both sides of the mark 4. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 31, and the singulated compound semiconductor layer 21 is bonded to the third base 30 (see FIG. 15 ).

[0089] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0090] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the first modified example of the second embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the first embodiment can be obtained.

[0091] 40 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a second modification of the second embodiment. Fig. 41 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0092] 40 and 41 , in the second modification of the second embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in an L-shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 31 disposed on the third base 30 is formed in an L-shape that is point-symmetric with respect to the mark 4. The planar shapes of the marks 4 and 31 are in the opposite positional relationship to the planar shapes of the marks 4 and 31 according to the first embodiment described above. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 31, and the singulated compound semiconductor layer 21 is bonded to the third base 30 (see FIG. 15 ).

[0093] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0094] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the second variant of the second embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the first embodiment can be obtained.

[0095] 42 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a third modification of the second embodiment. Fig. 43 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0096] 42 and 43 , in the third modification of the second embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in a rectangular shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 31 disposed on the third base 30 is formed in a rectangular shape that is slightly smaller than the mark 4. The planar shapes of the marks 4 and 31 are opposite in position to the planar shapes of the marks 4 and 31 according to the second embodiment described above. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 31, and the singulated compound semiconductor layer 21 is bonded to the third base 30 (see FIG. 15 ).

[0097] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0098] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third modified example of the second embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the first embodiment can be obtained.

[0099] 44 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a fourth modification of the second embodiment. Fig. 45 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0100] 44 and 45 , in the fourth modification of the second embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in the shape of a pair of parentheses spaced apart from each other in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 31 disposed on the third base 30 is formed in the shape of a cross located within the pair of parentheses of the mark 4. The planar shapes of the marks 4 and 31 are opposite in positional relationship to the planar shapes of the marks 4 and 31 according to the first modification of the second embodiment described above. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 31, and the singulated compound semiconductor layer 21 is bonded to the third base 30 (see FIG. 15 ).

[0101] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0102] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the fourth modified example of the second embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the first embodiment can be obtained.

[0103] 46 to 58, a compound semiconductor device 1 and a manufacturing method for the compound semiconductor device 1 according to a third embodiment of the present disclosure will be described. The third embodiment describes an example in which the structures of the marks 4 and 52 used for alignment are changed in the compound semiconductor device 1 and the manufacturing method for the compound semiconductor device 1 according to the first embodiment.

[0104] [Configuration of Compound Semiconductor Device 1] Fig. 46 shows an example of a vertical cross-sectional configuration of a main part of the compound semiconductor device 1 according to the third embodiment. As shown in Fig. 46, the compound semiconductor device 1 includes a mark 52 on the optical lens 5 that is aligned with the mark 4 as a reference. That is, the mark 52 is aligned with the mark 4, and the optical lens 5 is formed on the second base 20.

[0105] Fig. 47 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21. Fig. 48 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1. Fig. 48 corresponds to a cross-sectional view taken along the line CC shown in Fig. 47 described above. Note that the cross-sectional location is the same in the first to fifth modified examples described below.

[0106] 47 and 48 , in the third embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in an L-shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 52 disposed on the optical lens 5 is formed in an L-shape that is point-symmetric with respect to the mark 4. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 52, and the optical lens 5 is formed on the singulated compound semiconductor layer 21 (see FIG. 46 ).

[0107] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0108] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the third embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the first embodiment can be obtained.

[0109] 5 to 13, the manufacturing method of the compound semiconductor device 1 according to the third embodiment first forms a plurality of light-emitting elements 23 and isolation regions 22 separating the plurality of light-emitting elements 23 in the compound semiconductor layer 21, and then forms marks 4 having the same configuration as at least a portion of the isolation regions 22. Next, as shown in FIG. 14, the compound semiconductor layer 21 is singulated to form second substrates 20. Next, as shown in FIGS. 46 to 48, optical lenses 5 are formed corresponding to the plurality of light-emitting elements 23, aligned with reference to the marks 4. The optical lenses 5 include marks 52 that are aligned with reference to the marks 4. According to the manufacturing method of the compound semiconductor device 1 configured in this manner, the alignment accuracy between the plurality of light-emitting elements 23 and the optical lenses 5 in the compound semiconductor device 1 can be improved, thereby enabling the manufacture of a high-performance compound semiconductor device 1.

[0110] 49 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a first modification of the third embodiment. Fig. 50 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0111] 49 and 50 , the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 according to the first modification of the third embodiment is formed in a rectangular shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 52 disposed on the optical lens 5 is formed in a rectangular shape that is slightly larger than the mark 4. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 52, and the optical lens 5 is formed on the singulated compound semiconductor layer 21 (see FIG. 46 ).

[0112] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0113] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the first modified example of the third embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third embodiment can be obtained.

[0114] 51 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a second modification of the third embodiment. Fig. 52 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0115] 51 and 52 , in the second modification of the third embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in a cross shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the marks 52 disposed on the optical lens 5 are formed in a bracket shape located on both sides of the mark 4. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 52, and the optical lens 5 is formed on the singulated compound semiconductor layer 21 (see FIG. 46 ).

[0116] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0117] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the second modified example of the third embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third embodiment can be obtained.

[0118] 53 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a third modification of the third embodiment. Fig. 54 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0119] 53 and 54 , in the third modification of the third embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in an L-shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 52 disposed on the optical lens 5 is formed in an L-shape that is point-symmetric with respect to the mark 4. The planar shapes of the marks 4 and 52 are in the opposite positional relationship to the planar shapes of the marks 4 and 52 according to the third embodiment described above. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 52, and the optical lens 5 is formed on the singulated compound semiconductor layer 21 (see FIG. 46 ).

[0120] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the third embodiment.

[0121] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third modified example of the third embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third embodiment can be obtained.

[0122] 55 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a fourth modification of the third embodiment. Fig. 56 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0123] 55 and 56 , in the fourth modification of the third embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in a rectangular shape in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 52 disposed on the optical lens 5 is formed in a rectangular shape that is slightly smaller than the mark 4. The planar shapes of the marks 4 and 52 are in the opposite positional relationship to the planar shapes of the marks 4 and 52 according to the first modification of the third embodiment described above. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 52, and the optical lens 5 is formed on the singulated compound semiconductor layer 21 (see FIG. 46 ).

[0124] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the third embodiment.

[0125] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the fourth modified example of the third embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third embodiment can be obtained.

[0126] 57 shows an example of an enlarged planar configuration including a main part during the manufacturing process of the compound semiconductor layer 21 in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to a fifth modification of the third embodiment. Fig. 58 shows an example of an enlarged cross-sectional configuration of a main part during the manufacturing process of the compound semiconductor device 1.

[0127] 57 and 58 , in the fifth modification of the third embodiment, the mark 4 disposed on the compound semiconductor layer 21 of the compound semiconductor device 1 is formed in the shape of a pair of parentheses spaced apart from each other in a plan view. On the other hand, in the manufacturing method of the compound semiconductor device 1, the mark 52 disposed on the optical lens 5 is formed in the shape of a cross located within the pair of parentheses of the mark 4. The planar shapes of the marks 4 and 52 are opposite in position to the planar shapes of the marks 4 and 52 according to the second modification of the third embodiment described above. In the manufacturing method of the compound semiconductor device 1, the mark 4 is aligned with the mark 52, and the optical lens 5 is formed on the singulated compound semiconductor layer 21 (see FIG. 46 ).

[0128] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0129] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the fifth modified example of the third embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 relating to the third embodiment can be obtained.

[0130] 59 , a compound semiconductor device 1 and a manufacturing method for the compound semiconductor device 1 according to a fourth embodiment of the present disclosure will be described. The fourth embodiment describes an example in which the structure of the mark 4 used for alignment is changed in the compound semiconductor device 1 and the manufacturing method for the compound semiconductor device 1 according to the first embodiment.

[0131] [Configuration of Compound Semiconductor Device 1] Fig. 59 shows an example of a vertical cross-sectional configuration of a main part of a compound semiconductor device 1 according to the fourth embodiment. As shown in Fig. 59, the compound semiconductor device 1 includes a second base 20 having an individualized compound semiconductor layer 21. The compound semiconductor layer 21 has marks 4 disposed thereon.

[0132] The mark 4 is formed with the same configuration as the separation region 22. That is, the mark 4 is configured to include the groove 22A of the separation region 22, the embedded member 22B, and the embedded member 22C.

[0133] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0134] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the fourth embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the first embodiment can be obtained.

[0135] 60 to 84, a compound semiconductor device 1 and a manufacturing method for the compound semiconductor device 1 according to a fifth embodiment of the present disclosure will be described. The fifth embodiment describes an example in which the structure of the mark 4 used for alignment is changed in the compound semiconductor device 1 and the manufacturing method for the compound semiconductor device 1 according to the first embodiment.

[0136] [Configuration of Compound Semiconductor Device 1] Fig. 60 shows an example of a vertical cross-sectional configuration of a main part of a compound semiconductor device 1 according to the fifth embodiment. As shown in Fig. 60, the compound semiconductor device 1 includes a second base 20 having an individualized compound semiconductor layer 21. The compound semiconductor layer 21 has a mark 4 disposed thereon.

[0137] The compound semiconductor layer 21 is upside down. That is, the first surface 21A of the compound semiconductor layer 21 is disposed on the first base 10 side, and the second surface 21B is disposed on the arrow Z direction side. The light-emitting element 23 is formed by sequentially stacking a second compound semiconductor 23C, an active layer 23B, and a first compound semiconductor 23A in the arrow Z direction. An electrode 26 is electrically connected to the first compound semiconductor 23A. An electrode 251 is electrically connected to the second compound semiconductor 23C via an electrode 254.

[0138] The mark 4 is formed by a groove 22A having the same cross-sectional shape as the groove 22A of the isolation region 22, or a mesa whose side periphery is surrounded by grooves 22A having the same cross-sectional shape as the groove 22A of the isolation region 22. A part of the insulating layer 253 is buried in the groove 22A of the mark 4.

[0139] Also, in the compound semiconductor layer 21, marks 41 and 42 used for alignment, similar to the mark 4, are arranged. The mark 41 is made of the same material and is formed in the same layer as the embedded member 22C of the isolation region 22. The mark 42 is made of the same material and is formed in the same layer as the electrode 251.

[0140] In the fifth embodiment, the marks 4, 41 and 42 are all provided, but it is sufficient if at least one of them is provided.

[0141] [Method for Manufacturing Compound Semiconductor Device 1] The method for manufacturing the compound semiconductor device 1 according to the fifth embodiment includes the manufacturing steps shown in Figures 61 to 84. The method for manufacturing the compound semiconductor device 1 is as follows.

[0142] (1) Manufacturing Method of Second Substrate 20 First, as shown in Fig. 61 , a semiconductor wafer 200 is prepared. Here, the semiconductor wafer 200 is, for example, a GaAs substrate or an InP substrate 202 on which a compound semiconductor layer 210 is formed. The compound semiconductor layer 210 is formed by sequentially stacking, from the surface of the GaAs substrate or the InP substrate 202, a first compound semiconductor (an n-type compound layer containing at least two elements selected from Al, Ga, In, As, and P) 230A, an active layer 230B, and a second compound semiconductor (a p-type compound layer containing at least two elements selected from Al, Ga, In, As, and P) 230C.

[0143] 62 and 63 , grooves 22A of the separation regions 22 are formed in the compound semiconductor layer 210. The grooves 22A are formed by digging down through the second compound semiconductor 230C and the active layer 230B of the compound semiconductor layer 210 and then digging down partway through the first compound semiconductor 230A. A mask (not shown) and, for example, dry etching are used to form the grooves 22A. When the grooves 22A are formed, the first compound semiconductor 23A, the active layer 230B, and the second compound semiconductor 230C are subdivided into first compound semiconductors 23A, active layers 23B, and second compound semiconductors 23C, respectively, and a plurality of light-emitting elements 23 are essentially formed.

[0144] Here, the mark 4 is formed by a groove 22A having the same cross-sectional shape as the groove 22A of the isolation region 22, or a mesa whose side periphery is surrounded by grooves 22A having the same cross-sectional shape as the groove 22A of the isolation region 22. In other words, the mark 4 is formed by the same process as the process for forming the groove 22A of the isolation region 22.

[0145] Furthermore, the compound semiconductor layer 210 is further dug down in a region corresponding to the outer periphery of the pixel region PE, thereby forming an individual compound semiconductor layer 21 having a rectangular shape in a plan view.

[0146] Subsequently, a burying member 22B is formed along the inner wall of the groove 22A (see FIG. 64). The burying member 22B is also formed on the surface of the second compound semiconductor 23C of the light-emitting element 23. As shown in FIG. 64, a part of the burying member 22B is removed in the region corresponding to the second compound semiconductor 23C, and an opening 22H is formed.

[0147] Subsequently, an electrode 254 is formed, electrically connected to the second compound semiconductor 23C through the opening 22H (see FIG. 65 ). As shown in FIGS. 65 and 66 , a buried member 22C is formed in the groove 22A of the isolation region 22 with a buried member 22B interposed therebetween. The buried member 22C is formed to cover a portion of the plurality of light-emitting elements 23 and is electrically connected to the second compound semiconductor 23C through the electrode 254. The buried member 22C is also used as a light shield or reflector. Furthermore, by using a conductive metal and applying an electric field, it is possible to provide a binning effect that prevents electrons or holes from escaping from defect levels on the mesa sidewall.

[0148] Here, in the same step as the step of forming the embedding member 22C, a mark 41 made of the same material as the embedding member 22C and arranged in the same layer as the embedding member 22C is formed on the surface of the embedding member 22B.

[0149] 67, an insulating layer 253 is formed in which the compound semiconductor layer 21 is embedded and whose surface is planarized. As shown in Figures 68 and 69, an electrode 251 electrically connected to the second compound semiconductor 23C via the embedded member 22C and the electrode 254 is formed on the surface of the insulating layer 253. Here, in the same step as the step of forming the electrode 251, a mark 42 made of the same material as the electrode 251 and arranged in the same layer as the electrode 251 is formed on the surface of the insulating layer 253.

[0150] As shown in FIG. 70, an insulating layer 253 is formed to cover the embedded member 22C, and an adhesive layer 65 is formed on the surface of the insulating layer 253.

[0151] (2) Manufacturing Method of Electrode 26 of Second Base 20 As shown in Fig. 71 , a third base 30 is prepared, and an individualized compound semiconductor layer 21 is attached and bonded to the surface of this third base 30. The third base 30 is a support substrate used when forming the electrode 26 shown in Fig. 60. The third base 30 is formed using, for example, a single crystal Si substrate as a main component.

[0152] 72 , the GaAs substrate or InP substrate 202 of the semiconductor wafer 200 that was bonded to the second surface 21B side of the compound semiconductor layer 21 is removed. This step exposes the second surface 21B side of the compound semiconductor layer 21. Grinding or wet etching is used to remove the GaAs substrate or InP substrate 202.

[0153] Subsequently, an insulating film 66 is formed on the second surface 21B of the compound semiconductor layer 21 (see FIG. 73 ). As shown in FIG. 73 , an opening 66H is formed in the insulating film 66 in a region corresponding to the electrode 251 penetrating the first compound semiconductor 23A of the compound semiconductor layer 21 and the insulating layer 253. To form the opening 66H, for example, one or more marks selected from the mark 4, the mark 41, and the mark 42 are used for alignment.

[0154] As shown in Fig. 74, an electrode 26 is formed that is electrically connected to the first compound semiconductor 23A and the electrode 251 through the opening 66H. As shown in Fig. 75, an insulating film 67 that covers the electrode 26 and has a planarized surface is formed. Subsequently, as shown in Fig. 76, an adhesive layer 68 is formed on the insulating film 67.

[0155] As shown in FIG. 77, the semiconductor wafer 200 is diced to form a plurality of individual compound semiconductor layers 21 .

[0156] (3) Manufacturing Method of Wiring 252 of Second Base 20 As shown in Fig. 78, a third base 300 is prepared, and the individualized compound semiconductor layer 21 is attached and bonded to the surface of this third base 300. The third base 300 is a support substrate used when forming the wiring 252 shown in Fig. 60. The third base 300 is formed using, for example, a single crystal Si substrate as a main component.

[0157] A mark 301 is formed in advance on the surface of the third base 300. The mark 301 is used for alignment with one or more selected from the mark 4, the mark 41, and the mark 42. Any one of the mark 4, the mark 41, and the mark 42 of the compound semiconductor layer 21 is aligned with the mark 301 of the third base 300, and the first surface 21A side of the compound semiconductor layer 21 is bonded to the surface of the third base 300. Here, the mark 301 corresponds to a "third mark" according to the present technology.

[0158] 79 , the third base 30 bonded to the first surface 21A side of the compound semiconductor layer 21 is removed. This step exposes the first surface 21A side of the compound semiconductor layer 21. Grinding or wet etching is used to remove the third base 30.

[0159] 80, an insulating layer 253 is formed with the compound semiconductor layer 21 buried therein. Subsequently, as shown in Fig. 81, wiring 252 electrically connected to the electrode 251 is formed in the insulating layer 253. Through this step, the second base 20 having the singulated compound semiconductor layer 21 is substantially completed.

[0160] 82, a first base 10 is prepared, and a second base 20 having a compound semiconductor layer 21 is attached and bonded to the surface of the first base 10. That is, the wiring 122 of the first base 10 and the wiring 252 of the second base 20 are bonded to each other.

[0161] 83 , the third base 300 bonded to the first surface 21A side of the compound semiconductor layer 21 is removed. This step exposes the first surface 21A side of the compound semiconductor layer 21. Grinding or wet etching is used to remove the third base 300.

[0162] (5) Manufacturing Method of Optical Lens 5 Next, as shown in Fig. 84, an optical lens 5 is formed on the second substrate 20 on the first surface 21A side of the compound semiconductor layer 21. In the fifth embodiment, a mark 52 is formed on the optical lens 5, and the mark 52 is aligned with the mark 4 of the compound semiconductor layer 21. Note that the alignment of the optical lens 5 and the compound semiconductor layer 21 may be performed using the mark 52 of the reticle 50 of an exposure tool, similar to the step shown in Fig. 33 in the manufacturing method of the compound semiconductor device 1 according to the first embodiment.

[0163] When this series of steps is completed, the compound semiconductor device 1 according to the fifth embodiment is completed, and the manufacturing method is completed.

[0164] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the first embodiment.

[0165] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the fifth embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the first embodiment can be obtained.

[0166] 85 , a compound semiconductor device 1 and a manufacturing method of the compound semiconductor device 1 according to a sixth embodiment of the present disclosure will be described. The fifth embodiment describes an example in which the structure of the mark 4 used for alignment is changed in the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 according to the sixth embodiment.

[0167] [Configuration of Compound Semiconductor Device 1] Fig. 85 shows an example of a vertical cross-sectional configuration of a main part of a compound semiconductor device 1 according to the sixth embodiment. As shown in Fig. 85, the compound semiconductor device 1 includes a second base 20 having an individualized compound semiconductor layer 21. The compound semiconductor layer 21 has a mark 4 disposed thereon.

[0168] The mark 4 is formed by further deepening the groove 22A of the isolation region 22 to form an opening 22H penetrating the compound semiconductor layer 21 in the thickness direction, or by a mesa whose side surfaces are surrounded by the opening 22H.

[0169] The other components are the same as those of the compound semiconductor device 1 and the method for manufacturing the compound semiconductor device 1 according to the fifth embodiment.

[0170] [Effects] According to the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the sixth embodiment, effects similar to those obtained by the compound semiconductor device 1 and the manufacturing method of the compound semiconductor device 1 of the fifth embodiment can be obtained.

[0171] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0172] FIG. 86 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0173] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 86, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown in the figure are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053 as functional components of the integrated control unit 12050.

[0174] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0175] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0176] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0177] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0178] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0179] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0180] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0181] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0182] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 86, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0183] FIG. 87 is a diagram showing an example of the installation position of the imaging unit 12031.

[0184] In FIG. 87, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0185] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0186] 87 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0187] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0188] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0189] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0190] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0191] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031, etc., among the components described above. By applying the technology according to the present disclosure to the imaging unit 12031, etc., it is possible to provide the imaging unit 12031, etc., equipped with a high-performance compound semiconductor device.

[0192] 8. Application Example to Intra-Vivo Information Acquisition System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0193] FIG. 88 is a block diagram showing an example of a schematic configuration of a system for acquiring information from within a patient's body using a capsule endoscope, to which the technology according to the present disclosure (the present technology) can be applied.

[0194] The in-vivo information acquisition system 10001 includes a capsule endoscope 10100 and an external control device 10200 .

[0195] The capsule endoscope 10100 is swallowed by a patient during an examination. The capsule endoscope 10100 has an imaging function and a wireless communication function, and moves through the inside of organs such as the stomach and intestines by peristaltic movement or the like until it is naturally expelled from the patient, sequentially capturing images of the inside of the organs (hereinafter also referred to as in-vivo images) at predetermined intervals, and sequentially wirelessly transmitting information about the in-vivo images to an external control device 10200 outside the body.

[0196] The external control device 10200 comprehensively controls the operation of the in-vivo information acquisition system 10001. The external control device 10200 also receives information about the in-vivo images transmitted from the capsule endoscope 10100, and generates image data for displaying the in-vivo images on a display device (not shown) based on the received information about the in-vivo images.

[0197] In this way, the in-vivo information acquisition system 10001 can obtain in-vivo images of the state inside the patient's body at any time from the time the capsule endoscope 10100 is swallowed until it is expelled.

[0198] The configurations and functions of the capsule endoscope 10100 and the external control device 10200 will be described in more detail.

[0199] The capsule endoscope 10100 has a capsule-shaped housing 10101, which houses a light source unit 10111, an imaging unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power supply unit 10116, and a control unit 10117.

[0200] The light source unit 10111 is composed of a light source such as an LED (light emitting diode), and irradiates the imaging field of the imaging unit 10112 with light.

[0201] The imaging unit 10112 is composed of an imaging element and an optical system consisting of multiple lenses provided in front of the imaging element. Reflected light (hereinafter referred to as observation light) of light irradiated onto the body tissue to be observed is collected by the optical system and incident on the imaging element. In the imaging unit 10112, the imaging element photoelectrically converts the incident observation light, generating an image signal corresponding to the observation light. The image signal generated by the imaging unit 10112 is provided to the image processing unit 10113.

[0202] The image processing unit 10113 is configured with processors such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and performs various signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 provides the image signal that has been subjected to the signal processing to the wireless communication unit 10114 as RAW data.

[0203] The wireless communication unit 10114 performs predetermined processing such as modulation on the image signal that has been subjected to signal processing by the image processing unit 10113, and transmits the image signal to the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 also receives a control signal related to drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides the control signal received from the external control device 10200 to the control unit 10117.

[0204] The power supply unit 10115 is composed of an antenna coil for receiving power, a power regeneration circuit that regenerates power from the current generated in the antenna coil, a boost circuit, etc. The power supply unit 10115 generates power using the principle of so-called contactless charging.

[0205] The power supply unit 10116 is configured by a secondary battery and stores the power generated by the power supply unit 10115. In Fig. 88, to avoid cluttering the drawing, arrows and the like indicating the destinations of the power supply unit 10116 are omitted, but the power stored in the power supply unit 10116 is supplied to the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the control unit 10117 and can be used to drive these units.

[0206] The control unit 10117 is composed of a processor such as a CPU, and appropriately controls the operation of the light source unit 10111, the imaging unit 10112, the image processing unit 10113, the wireless communication unit 10114, and the power supply unit 10115 in accordance with control signals transmitted from the external control device 10200.

[0207] The external control device 10200 is configured with a processor such as a CPU or a GPU, or a microcomputer or control board equipped with a processor and a storage element such as a memory. The external control device 10200 controls the operation of the capsule endoscope 10100 by transmitting a control signal to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A. In the capsule endoscope 10100, for example, the light irradiation conditions of the light source unit 10111 for the observation object can be changed by the control signal from the external control device 10200. Furthermore, the imaging conditions (e.g., the frame rate and exposure value of the imaging unit 10112) can be changed by the control signal from the external control device 10200. Furthermore, the control signal from the external control device 10200 can change the content of processing in the image processing unit 10113 and the conditions for transmitting image signals from the wireless communication unit 10114 (e.g., the transmission interval, the number of transmitted images, etc.).

[0208] The external control device 10200 also performs various image processing on the image signal transmitted from the capsule endoscope 10100 to generate image data for displaying the captured in-vivo image on a display device. The image processing can include various signal processing such as development processing (demosaic processing), image quality improvement processing (band enhancement processing, super-resolution processing, NR (Noise Reduction) processing, and / or image stabilization processing), and / or enlargement processing (electronic zoom processing). The external control device 10200 controls the driving of the display device to display the captured in-vivo image based on the generated image data. Alternatively, the external control device 10200 may record the generated image data in a recording device (not shown) or print it out on a printing device (not shown).

[0209] An example of an in-vivo information acquisition system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 10112 among the above-described configurations. By applying the technology according to the present disclosure to the imaging unit 10112, it is possible to provide the imaging unit 10112 equipped with a high-performance compound semiconductor device.

[0210] 9. Application Examples Next, application examples of the present technology will be described. [First Application Example] Fig. 89 is a front view showing an example of the appearance of a digital still camera (electronic device) 1310. Fig. 90 is a rear view showing an example of the appearance of the digital still camera 1310. This digital still camera 1310 is a single-lens reflex camera with interchangeable lenses. The digital still camera 1310 has an interchangeable taking lens unit (interchangeable lens) 1312 located approximately in the center of the front of a camera main body (camera body) 1311, and a grip part 1313 for the photographer to hold on the left side of the front.

[0211] A monitor 1314 is provided at a position shifted to the left from the center of the back of the camera body 1311. An electronic viewfinder (eyepiece window) 1315 is provided above the monitor 1314. By looking through the electronic viewfinder 1315, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 1312 and determine the composition of the image. The electronic viewfinder 1315 is equipped with the compound semiconductor device 1.

[0212] 91 is a perspective view showing an example of the appearance of a head-mounted display (electronic device) 1320. The head-mounted display 1320 has, for example, ear hooks 1322 on both sides of a glasses-shaped display unit 1321 for wearing on the user's head. The display unit 1321 includes the compound semiconductor device 1.

[0213] 92 is a perspective view showing an example of the appearance of a television set (electronic device) 1330. This television set 1330 has, for example, an image display screen unit 1331 including a front panel 1332 and a filter glass 1333. The image display screen unit 1331 is equipped with the compound semiconductor device 1.

[0214] 10. Other Embodiments The present technology is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present technology. For example, two or more of the above-described embodiments can be combined.

[0215] A compound semiconductor device according to a first embodiment of the present disclosure includes a first substrate, a second substrate having an individualized compound semiconductor layer, the compound semiconductor layer having a plurality of elements and isolation regions separating the plurality of elements, bonded to a surface of the first substrate, and a first mark disposed on the second substrate and used for aligning the compound semiconductor layer. The compound semiconductor device configured in this manner can improve alignment accuracy, thereby achieving high performance.

[0216] In a compound semiconductor device according to a second embodiment of the present disclosure, the first mark is formed with the same configuration as at least a portion of the isolation region in the compound semiconductor device according to the first embodiment. In the compound semiconductor device configured in this manner, the first mark is formed using the configuration of at least a portion of the isolation region, which makes it possible to easily provide the first mask.

[0217] A compound semiconductor device according to a third embodiment of the present disclosure is the compound semiconductor device according to the second embodiment, wherein the first mark is formed to contain a metal or a metal compound.

[0218] In a compound semiconductor device according to a fourth embodiment of the present disclosure, in the compound semiconductor device according to the second embodiment, the isolation region is formed by including a trench dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and a filling member filled in the trench. The first mark is formed of the same material as the filling member. In this compound semiconductor device configured in this manner, the first mark is formed using the filling member of the isolation region, which makes it possible to easily provide a first mask.

[0219] In a compound semiconductor device according to a fifth embodiment of the present disclosure, in the compound semiconductor device according to the second embodiment, the isolation region is formed to include a trench dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface. The first mark is formed by a trench having the same cross-sectional shape as the trench, or a mesa whose side surfaces are surrounded by a trench having the same cross-sectional shape as the trench. A compound semiconductor device configured in this manner can improve alignment accuracy, thereby achieving high performance.

[0220] A method for manufacturing a compound semiconductor device according to a sixth embodiment of the present disclosure includes forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer, forming first marks having the same configuration as at least a portion of the isolation regions, forming second substrates by singulating the compound semiconductor layer, forming third marks on the third substrate to be used for alignment with the first marks, aligning the first marks with the third marks, and bonding the second substrate to the third substrate. According to the method for manufacturing a compound semiconductor device configured in this manner, alignment is performed using the first marks and the third marks, so that alignment accuracy can be improved when bonding the second substrate and the third substrate.

[0221] A method for manufacturing a compound semiconductor device according to a seventh embodiment of the present disclosure includes forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer, forming first marks having the same configuration as at least a portion of the isolation regions, forming a second substrate by singulating the compound semiconductor layer, and forming optical lenses on the second substrate that are aligned with the first marks and correspond to the plurality of elements. Here, in the method for manufacturing a compound semiconductor device according to the seventh embodiment, the optical lenses include second marks that are aligned with the first marks, and the second marks are aligned with the first marks to form the optical lenses on the second substrate. According to the method for manufacturing a compound semiconductor device configured in this manner, alignment is performed using the first marks and the second marks, thereby improving alignment accuracy when forming the optical lenses on the second substrate.

[0222] A method for manufacturing a compound semiconductor device according to an eighth embodiment of the present disclosure includes forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer, forming first marks having a configuration identical to at least a portion of the isolation regions, forming second substrates by singulating the compound semiconductor layer, forming third marks on the third substrate to be used for alignment with the first marks, aligning the first marks with the third marks, bonding the second substrate to the third substrate, bonding the first substrate to a surface of the second substrate opposite to the surface to which the third substrate is attached, and then removing the third substrate, and forming optical lenses on the surface of the second substrate from the side from which the third substrate has been removed, aligned with the first marks. This method for manufacturing a compound semiconductor device configured in this manner can achieve a combination of the effects achieved by the method for manufacturing a compound semiconductor device according to the sixth embodiment and the method for manufacturing a compound semiconductor device according to the seventh embodiment.

[0223] <Configuration of the Present Technology> The present technology has the following configuration: By providing the following configuration, it is possible to improve alignment accuracy and provide a high-performance compound semiconductor device and a method for manufacturing a compound semiconductor device.

[0224] (1) A compound semiconductor device comprising: a first base; a second base having an individualized compound semiconductor layer, the compound semiconductor layer having a plurality of elements and separation regions separating the plurality of elements, the second base being bonded to a surface of the first base; and a first mark disposed on the second base and used for aligning the compound semiconductor layer. (2) The plurality of elements are a plurality of light-emitting elements that respectively emit light or a plurality of light-receiving elements that respectively receive light. (3) The compound semiconductor device according to (1) or (2), wherein the first mark is disposed within a region in which the plurality of elements are disposed. (4) The compound semiconductor device according to (1) or (2), wherein the first mark is disposed outside the region in which the plurality of elements are disposed. (5) The compound semiconductor device according to any one of (1) to (4), wherein the first mark is formed with the same configuration as at least a portion of the separation region. (6) The compound semiconductor device according to any one of (1) to (5), wherein the first mark is formed containing a metal or a metal compound. (7) The compound semiconductor device according to any one of (1) to (6), wherein the first mark is formed containing one or more selected from Ti, W, Al, Cu, Co, Ag, Au, Ni, Pd, TiN, and TaN. (8) The compound semiconductor device according to any one of (5) to (7), wherein the separation region is formed including a groove dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and a filling member filled in the groove, and the first mark is formed of the same material as the filling member. (9) The compound semiconductor device according to any one of (1) to (9), wherein the isolation region is formed including a trench dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and the first mark is formed by a trench having the same cross-sectional shape as the trench or a mesa whose side surfaces are surrounded by trenches having the same cross-sectional shape as the trench. (10) The compound semiconductor device according to any one of (1) to (9), wherein two or more first marks are arranged on the second base.(11) The compound semiconductor device according to any one of (1) to (10), wherein optical lenses are disposed on the second base corresponding to the plurality of elements, and the optical lenses are aligned with reference to the first marks. (12) The compound semiconductor device according to any one of (1) to (11), wherein the optical lenses include second marks that are aligned with reference to the first marks. (13) The compound semiconductor device according to any one of (1) to (12), wherein the first base includes a drive circuit that causes the plurality of light-emitting elements to emit light, or a readout circuit that reads out signals from the plurality of light-receiving elements. (14) A method for manufacturing a compound semiconductor device, comprising: forming a plurality of elements and separation regions separating the plurality of elements in a compound semiconductor layer, and forming first marks having the same configuration as at least a portion of the separation regions, forming a second base by singulating the compound semiconductor layer, forming third marks on the third base to be used for alignment with the first marks, and bonding the second base to the third base while the first marks are aligned with the third marks. (15) A method for manufacturing a compound semiconductor device, comprising: forming a plurality of elements and separation regions separating the plurality of elements in a compound semiconductor layer, and forming first marks having the same configuration as at least a portion of the separation regions, forming a second base by singulating the compound semiconductor layer, and forming optical lenses on the second base that are aligned with the first marks and correspond to the plurality of elements. (16) The method for manufacturing a compound semiconductor device according to (15), wherein the optical lens includes a second mark that is aligned with respect to the first mark, and the second mark is aligned with respect to the first mark, and the optical lens is formed on the second substrate.(17) A method for manufacturing a compound semiconductor device, comprising: forming a plurality of elements and separation regions isolating the plurality of elements in a compound semiconductor layer, and forming first marks having the same configuration as at least a portion of the separation regions; forming second substrates by singulating the compound semiconductor layer; forming third marks on the third substrate to be used for alignment with the first marks; bonding the second substrate to the third substrate while aligning the first marks with the third marks; bonding the first substrate to a surface of the second substrate opposite to the surface to which the third substrate is attached; thereafter removing the third substrate; and forming optical lenses, aligned with the first marks as reference, on the surface of the second substrate from which the third substrate has been removed, corresponding to the plurality of elements.

[0225] This application claims priority based on Japanese Patent Application No. 2024-048462, filed on March 25, 2024, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0226] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A compound semiconductor device comprising: a first substrate; a second substrate bonded to the surface of the first substrate, the second substrate having an individualized compound semiconductor layer, the compound semiconductor layer having a plurality of elements and isolation regions that isolate the plurality of elements; and a first mark disposed on the second substrate and used for aligning the compound semiconductor layer.

2. The compound semiconductor device according to claim 1, wherein said plurality of elements are a plurality of light-emitting elements that each emit light, or a plurality of light-receiving elements that each receive light.

3. The compound semiconductor device according to claim 1, wherein the first mark is disposed within the region in which the plurality of elements are disposed.

4. The compound semiconductor device according to claim 1, wherein the first mark is disposed outside the region in which the plurality of elements are disposed.

5. The compound semiconductor device according to claim 1, wherein the first mark is formed with the same configuration as at least a part of the isolation region.

6. The compound semiconductor device according to claim 5, wherein the first mark is formed to contain a metal or a metal compound.

7. The compound semiconductor device according to claim 5, wherein the first mark is formed containing one or more selected from the group consisting of Ti, W, Al, Cu, Co, Ag, Au, Ni, Pd, TiN, and TaN.

8. The compound semiconductor device according to claim 5, wherein the isolation region is formed by including a groove dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and a buried member buried in the groove, and the first mark is formed from the same material as the buried member.

9. The compound semiconductor device according to claim 5, wherein the isolation region is formed to include a trench dug from a first surface of the compound semiconductor layer toward a second surface opposite the first surface, and the first mark is formed by a trench having the same cross-sectional shape as the trench, or a mesa whose side surfaces are surrounded by trenches having the same cross-sectional shape as the trench.

10. The compound semiconductor device according to claim 1, wherein two or more of the first marks are disposed on the second substrate.

11. The compound semiconductor device according to claim 1, wherein optical lenses are disposed on said second substrate in correspondence with said plurality of elements, and said optical lenses are aligned with reference to said first marks.

12. The compound semiconductor device according to claim 11, wherein the optical lens is provided with a second mark that is aligned with the first mark as a reference.

13. The compound semiconductor device according to claim 1, wherein the first substrate is provided with a drive circuit for causing the plurality of light-emitting elements to emit light, or a readout circuit for reading out signals from the plurality of light-receiving elements.

14. A method for manufacturing a compound semiconductor device, comprising: forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer; forming a first mark having the same configuration as at least a portion of the isolation region; forming a second substrate by singulating the compound semiconductor layer; forming a third mark on the third substrate to be used for alignment with the first mark; and bonding the second substrate to the third substrate while the first mark is aligned with the third mark.

15. A method for manufacturing a compound semiconductor device, comprising: forming a plurality of elements and isolation regions separating the plurality of elements in a compound semiconductor layer; forming a first mark having the same configuration as at least a portion of the isolation region; forming a second base by singulating the compound semiconductor layer; and forming optical lenses on the second base that are aligned with the first marks and correspond to the plurality of elements.

16. The method for manufacturing a compound semiconductor device according to claim 15, wherein the optical lens comprises a second mark that is aligned with respect to the first mark, and the second mark is aligned with respect to the first mark, and the optical lens is formed on the second substrate.

17. A method for manufacturing a compound semiconductor device, comprising: forming a plurality of elements and isolation regions isolating the plurality of elements in a compound semiconductor layer, and forming first marks having the same configuration as at least a portion of the isolation regions; forming second substrates by singulating the compound semiconductor layer; forming third marks on the third substrate to be used for alignment with the first marks; bonding the second substrate to the third substrate while aligning the first mark with the third marks; bonding the first substrate to the surface of the second substrate opposite to the surface to which the third substrate is attached; thereafter removing the third substrate; and forming optical lenses, aligned with the first marks as a reference, on the surface of the second substrate from which the third substrate has been removed, corresponding to the plurality of elements.

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