Plasma processing device, power supply system, and control method

Abstract

The disclosed plasma processing device identifies, from a plurality of digital values obtained by A / D conversion of an envelope signal of a sensor signal in a waveform cycle of electrical bias, the degree of reflection of source high-frequency power in the waveform cycle or the degree of reflection of the source high-frequency power in each of a plurality of phase periods within the waveform cycle. A power supply control unit adjusts a source frequency for each of the plurality of phase periods so as to reduce the degree of reflection in a subsequent waveform cycle in accordance with the identified degree of reflection. A sampling frequency of the A / D conversion is at least twice the product of a bias frequency of the electrical bias and the quantity of the plurality of phase periods in the waveform cycle, and is equal to or less than the minimum frequency at which the source high-frequency power can be adjusted.

Description

Plasma processing apparatus, power supply system, and control method

[0001] SUMMARY Exemplary embodiments of the present disclosure relate to a plasma processing apparatus, a power supply system, and a control method.

[0002] A plasma processing apparatus is used in plasma processing of a substrate. In the plasma processing apparatus, bias high frequency power is used to attract ions from a plasma generated in a chamber to the substrate. Patent Document 1 listed below discloses a plasma processing apparatus in which the power level and frequency of the bias high frequency power are modulated.

[0003] Japanese Patent Application Laid-Open No. 2009-246091

[0004] The present disclosure provides a technique for adjusting the source frequency of source high frequency power by identifying the degree of reflection of the source high frequency power in the waveform cycle of the electrical bias at low cost.

[0005] In one exemplary embodiment, a plasma processing apparatus is disclosed. The plasma processing apparatus includes a chamber, a substrate support within the chamber, a radio frequency power source, a bias power source, a sensor, a detector, an A / D converter, and a power supply controller. The radio frequency power source is configured to supply source radio frequency power to generate plasma from gas within the chamber. The bias power source is configured to supply an electrical bias to the substrate support to attract ions from the plasma to a substrate on the substrate support. The sensor is configured to acquire a sensor signal reflecting a degree of reflection of the source radio frequency power. The detector is configured to detect an envelope signal of the sensor signal. The A / D converter is configured to perform A / D conversion on the envelope signal output from the detector. The power supply controller is configured to adjust a source frequency of the source radio frequency power for each of a plurality of phase periods dividing the waveform period in response to a degree of reflection within the waveform period or a degree of reflection in each of a plurality of phase periods dividing the waveform period, the degree of reflection being determined from a plurality of digital values ​​generated by the A / D converter from the envelope signal in the waveform period of the electrical bias. This degree of reflection is determined in the waveform period. The sampling frequency of the A / D converter is at least twice the product of the bias frequency, which is the reciprocal of the time length of the waveform period, and the number of phase periods in the waveform period, and is at most the source frequency of the source high frequency power.

[0006] According to one exemplary embodiment, a technique is provided for inexpensively determining the degree of reflection of source RF power in a waveform cycle of an electrical bias and adjusting the source frequency of the source RF power.

[0007] 5A and 5B are timing charts showing an example of a source high frequency power and an electric bias in a plasma processing apparatus according to an exemplary embodiment. 5B are flowcharts showing a control method according to an exemplary embodiment. 5C are flowcharts showing an example of a feedback process. 5D are flowcharts showing an example of a process in step ST9 shown in FIG. 7. 5E are flowcharts showing another example of a feedback process. 5F are flowcharts showing an example of a process in step ST9a shown in FIG. 9. 5G are timing charts showing an example of a source high frequency power and an electric bias in a plasma processing apparatus according to an exemplary embodiment. 5G are timing charts related to a power supply system according to an exemplary embodiment. 5H are timing charts related to a power supply system according to an exemplary embodiment. 5I are flowcharts showing a control method of a first example. 5I are flowcharts showing a control method of a first example shown in FIG. 14. 5I are flowcharts showing a control method of a second example. 5I are flowcharts showing a control method of a second example shown in FIG. 16. 5I are flowcharts showing a control method of a second example shown in FIG. 16. 5I are flowcharts showing a control method of a second example shown in FIG. 16. 5I are flowcharts showing a control method of a second example shown in FIG. 16. Fig. 21 is a block diagram of a processing circuit for implementing the operations described herein on a computer.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0009] FIG. 1 is a diagram illustrating an exemplary configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), or surface wave plasma (SWP). Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0012] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0018] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0022] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0024] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026] Reference will now be made to Fig. 3, which is a diagram illustrating a plasma processing apparatus according to an exemplary embodiment. As shown in Fig. 3, the plasma processing apparatus 1 includes a power supply system 30S. The power supply system 30S includes a high-frequency power supply 41, a bias power supply 42, a sensor 45, a detector 51, and an A / D converter 52.

[0027] The high frequency power source 41 is the first RF generating unit 31a. The high frequency power source 41 is configured to generate a source RF signal, i.e., a source high frequency power HF. The source high frequency power HF has a source frequency f. That is, the source high frequency power HF has a sinusoidal waveform whose frequency is the source frequency f. The source frequency f can be a frequency within a range of 10 MHz to 150 MHz. The high frequency power source 41 generates the source frequency f at a minimum frequency f ＭＩＮ and its maximum frequency f ＭＡＸ In one example, the minimum frequency f ＭＩＮ is 36 MHz, and the maximum frequency f ＭＡＸ is 44 MHz. The source frequency f is adjusted to reduce the degree of reflection of the source high frequency power HF from the load of the high frequency power supply 41, as will be described later.

[0028] The high frequency power supply 41 is electrically connected to the high frequency electrode via a matching box 43 and is configured to supply source high frequency power HF to the high frequency electrode. The high frequency electrode may be provided within the substrate support 11. The high frequency electrode may be at least one electrode provided within the conductive member or ceramic member 1111a of the base 1110. Alternatively, the high frequency electrode may be an upper electrode. When the source high frequency power HF is supplied to the high frequency electrode, plasma is generated from the gas within the chamber 10.

[0029] The matching circuit 43 has a variable impedance. The variable impedance of the matching circuit 43 is set to reduce reflection of the source high frequency power HF from the load. The matching circuit 43 can be controlled by, for example, the control unit 2.

[0030] In one embodiment, the high frequency power supply 41 may include a signal generator 41g, a D / A converter 41c, and an amplifier 41a. The signal generator 41g generates a high frequency signal having a source frequency f. The signal generator 41g may be composed of a programmable processor, a programmable logic device such as an FPGA (Field-Programmable Gate Array), or a dedicated circuit such as an ASIC (Application Specific Integrated Circuit).

[0031] The output of the signal generator 41g is connected to the input of the D / A converter 41c. The D / A converter 41c converts the high frequency signal from the signal generator 41g into an analog signal. The output of the D / A converter 41c is connected to the input of the amplifier 41a. The amplifier 41a amplifies the analog signal from the D / A converter 41c to generate the source high frequency power HF. The gain of the amplifier 41a is specified to the high frequency power supply 41 by the control unit 2. Note that the high frequency power supply 41 does not need to include the D / A converter 41c. In this case, the output of the signal generator 41g is connected to the input of the amplifier 41a, and the amplifier 41a amplifies the high frequency signal from the signal generator 41g to generate the source high frequency power HF.

[0032] The bias power supply 42 includes the second RF generator 31b or the first DC generator 32a. The bias power supply 42 is electrically coupled to the substrate support 11. The bias power supply 42 is electrically connected to a bias electrode in the substrate support 11 and is configured to supply an electric bias EB to the bias electrode. The bias electrode may be at least one electrode provided in the conductive member or ceramic member 1111a of the base 1110. The bias electrode may be common to the radio frequency electrode. When the electric bias EB is supplied to the bias electrode, ions from the plasma are attracted to the substrate W.

[0033] Reference will now be made to FIG. 4 in conjunction with FIG. 3. FIG. 4 is a diagram illustrating an example of the waveform of the electric bias. The bias power supply 42 is configured to periodically apply an electric bias EB having a waveform period CY to the bias electrode. That is, the electric bias EB is applied to the bias electrode in each of a plurality of waveform periods CY, which are repetitions of the waveform period CY. The waveform period CY is defined by a bias frequency. The bias frequency is, for example, not less than 50 kHz and not more than 27 MHz. The time length of the waveform period CY is the reciprocal of the bias frequency. The bias frequency may be not more than 13.56 MHz or not more than 400 kHz.

[0034] The electrical bias EB may be a bias RF signal, i.e., a bias high frequency power LF having a bias frequency. That is, the electrical bias EB may have a sinusoidal waveform whose frequency is the bias frequency. In this case, the bias power supply 42 is electrically connected to the bias electrode via a matching box 44. The variable impedance of the matching box 44 is set to reduce reflection of the bias high frequency power LF from the load.

[0035] Alternatively, the electric bias EB may include a pulsed first DC signal, i.e., a voltage pulse VP. The voltage pulse VP is applied to the bias electrode in a waveform period CY. The voltage pulse VP is periodically applied to the bias electrode at time intervals equal to the time length of the waveform period CY. The waveform of the voltage pulse VP may be a square wave, a triangular wave, or any other waveform. The polarity of the voltage pulse VP is set so as to generate a potential difference between the substrate W and the plasma, thereby attracting ions from the plasma to the substrate W. The voltage pulse VP is applied to the bias electrode so that the waveform period CY includes a period during which the potential of the substrate W is negative. The voltage pulse VP applied to the bias electrode may have a negative potential, a positive potential, or a potential that changes between a positive potential and a negative potential. The voltage pulse VP may be a negative voltage pulse or a negative DC voltage pulse. Note that when the electric bias EB is a voltage pulse VP, the plasma processing apparatus 1 does not need to include the matching unit 44.

[0036] 3 and 4, and also FIGS. 5(a) and 5(b) will be referred to below. Each of FIGS. 5(a) and 5(b) is a timing chart of an example of the source RF power and the electric bias in a plasma processing apparatus according to one exemplary embodiment. In these figures, "ON" for the source RF power HF indicates that the source RF power HF is being supplied, and "OFF" for the source RF power HF indicates that the supply of the source RF power HF is stopped. Also, in FIG. 5(b), "HIGH" for the source RF power HF indicates that a source RF power HF having a power level higher than the power level indicated by "LOW" is being supplied. Also, in these figures, "ON" for the electric bias EB indicates that the electric bias EB is being supplied, and "OFF" for the electric bias EB indicates that the supply of the electric bias EB is stopped. In (b) of Figure 5, "HIGH" of the electric bias EB indicates that an electric bias EB having a level higher than the level indicated by "LOW" is being supplied. When the electric bias EB is the bias high frequency power LF, the level of the electric bias EB is the power level of the bias high frequency power LF. When the electric bias EB includes a voltage pulse VP, the electric bias EB has a higher level as the energy of the ions attracted to the substrate W increases. When the electric bias EB includes a voltage pulse VP, the level of the electric bias EB may be the absolute value of the voltage level of the voltage pulse VP in the negative direction relative to a reference voltage (e.g., 0 V).

[0037] The high frequency power supply 41 is configured to supply source high frequency power HF in parallel with the periodic supply of electric bias EB from the bias power supply 42. As shown in Fig. 5A, the electric bias EB and the source high frequency power HF may be supplied simultaneously and continuously from the start to the end of the process. That is, a continuous wave of the electric bias EB and a continuous wave of the source high frequency power HF may be supplied in parallel.

[0038] Alternatively, as shown in FIG. 5B, the pulse of the electric bias EB and the pulse of the source high frequency power HF may be supplied synchronously with each other. That is, during the pulse period PP １ , PP ２ , PP ３ , ... (i.e., multiple pulse periods PP), a pulse of the electric bias EB and a pulse of the source high frequency power HF may be supplied simultaneously. Each of the multiple pulse periods PP includes multiple waveform periods CY. That is, in each of the multiple pulse periods PP, the electric bias EB is supplied periodically. The pulse of the electric bias EB may be an ON / OFF pulse that alternates between a supply state (ON state in FIG. 5B) and a stop state (OFF state in FIG. 5B). Alternatively, the pulse of the electric bias EB may be a HIGH / LOW pulse that alternates between a high level state (HIGH state in FIG. 5B) and a low level state (LOW state in FIG. 5B). Furthermore, the pulse of the source high frequency power HF may be an ON / OFF pulse that alternates between a supply state (ON state in FIG. 5B) and a stop state (OFF state in FIG. 5B). Alternatively, the pulse of the source high frequency power HF may be a HIGH / LOW pulse that alternates between a high level state (HIGH state in FIG. 5(b)) and a low level state (LOW state in FIG. 5(b)). The power level of the source high frequency power HF may be modulated during a period when the source high frequency power HF is ON. The power level of the source high frequency power HF may be modulated during a period when the power level of the source high frequency power HF is HIGH. The power level of the source high frequency power HF may be modulated during a period when the power level of the source high frequency power HF is LOW.

[0039] As shown in FIG. 3, the sensor 45 measures the degree of reflection R of the source high frequency power HF from the load. Ｄ The sensor 45 is configured to acquire a sensor signal SS reflecting the reflected wave of the source high frequency power HF. In one embodiment, the sensor 45 may include a directional coupler. In this case, the sensor signal SS is a voltage signal VS of the reflected wave of the source high frequency power HF. The output of the sensor 45 is connected to the input of the detector 51.

[0040] The detector 51 is configured to detect an envelope signal ES of the sensor signal SS output from the sensor 45. The output of the detector 51 is connected to the input of the A / D converter 52. The A / D converter 52 is configured to perform A / D conversion on the envelope signal ES output from the detector 51.

[0041] The plasma processing apparatus 1 further includes a power supply control unit. In the example shown in Fig. 3, the power supply control unit may be a signal generator 41g. The power supply control unit may be the control unit 2 or another control unit in the plasma processing apparatus 1 or the power supply system 30S.

[0042] The power supply control unit calculates the degree of reflection R in the waveform cycle CY. Ｄ or the degree of reflection R in each of a plurality of phase periods PH (see FIG. 4) that divide the waveform period CY. Ｄ In response to this, the degree of reflection R Ｄ The source frequency f for each of the phase periods PH is adjusted to reduce the degree of reflection R Ｄ is a plurality of digital values ​​V generated by the A / D converter 52 from the envelope signal ES in the waveform period CY. Ｄ The degree of reflection R Ｄ can be obtained in the power supply control unit.

[0043] Reflectivity R Ｄ is a representative value of a plurality of evaluation values ​​obtained from a plurality of digital values ​​in the waveform period CY or each phase period PH. The representative value may be an average value. For example, Ｄ When the above equation is used, each of the multiple evaluation values ​​is a power level of a reflected wave, and the average value of the power levels of the reflected wave is calculated as the degree of reflection R Ｄ is obtained as In addition, in formula (1), V Ｄｊ is a plurality of digital values ​​V used in the calculation of equation (1). Ｄ It is the j-th digital value of Z ０is the characteristic impedance, for example, 50Ω. C is the coupling coefficient of the directional coupler, which is determined in advance. g is the gain that reflects the characteristics of the detector 51, which is determined in advance. N Ｖ When the average value of a plurality of evaluation values ​​in a waveform period CY is calculated, the average value of a plurality of digital values ​​V in the waveform period CY is calculated. Ｄ Also, N Ｖ When the average value of a plurality of evaluation values ​​in each phase period PH within the waveform cycle CY is calculated, the average value of a plurality of digital values ​​V in each phase period PH is calculated. Ｄ is the number of.

[0044] In the plasma processing apparatus 1, the sampling frequency of the A / D converter 52 is set to at least twice the product of the bias frequency of the electric bias EB and the number of phase periods PH in the waveform cycle CY, and is set to a minimum frequency f ＭＩＮ The A / D converter 52 converts two or more digital values ​​V from the envelope signal ES in each of the multiple phase periods PH. Ｄ Furthermore, the plasma processing apparatus 1 can use an A / D converter 52 having a relatively small sampling frequency. Therefore, the plasma processing apparatus 1 can obtain the degree of reflection R in the waveform cycle CY. Ｄ or the degree of reflection R in each phase period PH Ｄ can be specified inexpensively to adjust the source frequency f for each phase period PH.

[0045] In one embodiment, the detector 51 may include an attenuator 511, a first filter 512, a detection circuit 513, a second filter 514, and an amplifier 515. An input of the attenuator 511 is connected to the sensor 45. The attenuator 511 is configured to generate a signal AS by attenuating the signal level of the sensor signal SS. An output of the attenuator 511 is connected to an input of the first filter 512.

[0046] The first filter 512 is a band-pass filter configured to generate a signal BPS (first signal) by filtering the signal AS. The upper cutoff frequency of the first filter 512 is a maximum frequency f ＭＡＸ and the minimum frequency f ＭＩＮ The lower limit cutoff frequency of the first filter 512 may be equal to or less than twice the minimum frequency f ＭＩＮ or less. The first filter 512 substantially removes harmonics having frequencies equal to or greater than twice the source frequency from the sensor signal SS. The output of the first filter 512 is connected to the input of the detection circuit 513. Alternatively, the output of the sensor 45 may be connected to the input of the first filter 512, the output of the first filter 512 may be connected to the input of the attenuator 511, and the output of the attenuator 511 may be connected to the input of the detection circuit 513.

[0047] The detector circuit 513 is configured to detect the envelope signal EAS (first envelope signal) of the signal BPS. The output of the detector circuit 513 is connected to the input of the second filter 514.

[0048] The second filter 514 is a low-pass filter configured to generate a signal LPS by filtering the envelope signal EAS. The upper cutoff frequency of the second filter 514 has a value between the upper cutoff frequency of the first filter 512 and the product of the bias frequency of the electrical bias EB and the number of phase periods PH in the waveform period CY. The upper cutoff frequency of the second filter 514 is a value between the minimum frequency f ＭＩＮ The second filter 514 removes high frequency components without removing necessary signal components in each of the phase periods PH. The output of the second filter 514 is connected to the amplifier 515.

[0049] The amplifier 515 is configured to amplify the signal LPS to generate the above-mentioned envelope signal ES (i.e., the second envelope signal). The output of the amplifier 515 is connected to the input of the A / D converter 52. The A / D converter 52 performs A / D conversion on the envelope signal ES output from the amplifier 515. As a result, the above-mentioned plurality of digital values ​​V Ｄ is obtained.

[0050] A control method according to one exemplary embodiment will be described below with reference to Fig. 6. Fig. 6 is a flow chart showing the control method according to one exemplary embodiment. The control method shown in Fig. 6 (hereinafter referred to as "method MT") is performed in a plasma processing apparatus 1. In each step of method MT, each part of the plasma processing apparatus 1 can be controlled by a control unit 2 and a power supply control unit.

[0051] The method MT may include a step STp. In the step STp, a substrate W is prepared in the chamber 10. The substrate W is placed on the substrate support 11 and held by the electrostatic chuck 1111.

[0052] In step STa, a source high frequency power HF is supplied from the high frequency power supply 41 to the high frequency electrode to generate plasma from the gas in the chamber 10. In step STb, an electric bias EB is supplied from the bias power supply 42 to the substrate support 11 (or the bias electrode) to attract ions from the plasma to the substrate W on the substrate support 11.

[0053] In a process STc, the sensor signal SS is acquired by the sensor 45. In a process STd, the envelope signal ES is detected by the detector 51. In a process STe, the envelope signal ES is A / D converted by the A / D converter 52. In a process STf, a plurality of digital values ​​V are generated by the A / D converter 52 from the envelope signal ES in the waveform period CY. Ｄ From this, the degree of reflection R in the waveform period CY Ｄ or the degree of reflection R in each phase period PH Ｄ is identified.

[0054] In the process STJ, it is determined whether or not the stop condition is satisfied. The determination in the process STJ can be made by the power supply control unit. In the process STJ, the stop condition is satisfied when, for example, an instruction to terminate is issued from the control unit 2. If it is determined that the stop condition is not satisfied in the process STJ, the process STg is performed. In the process STg, the degree of reflection R specified in the process STf is used to determine whether or not the stop condition is satisfied. Ｄ In response to the determined value, the power supply control unit adjusts the source frequency f for each of the plurality of phase periods PH so as to reduce the degree of reflection in the subsequent waveform period CY. After step STg, the process is repeated from step STa. In step STa, the source high frequency power HF having the source frequency f for each of the plurality of phase periods PH determined in step STg is supplied. On the other hand, if it is determined in step STJ that the stop condition is satisfied, the method MT ends.

[0055] Hereinafter, several embodiments relating to the adjustment of the source frequency f in the method MT will be described, along with the adjustment of the source frequency f by the power supply control unit.

[0056] In one embodiment, the power supply controller adjusts the source frequency f using a feedback process that is applied over multiple designated phase periods DP within a waveform period CY.

[0057] In the feedback process according to the first embodiment, the multiple designated phase periods DP in the waveform period CY may be all of the phase periods PH in the waveform period CY. That is, in the feedback process according to the first embodiment, the number of the multiple designated phase periods DP in the waveform period CY is M, where M is N, which is the number of the multiple phase periods PH in the waveform period CY.

[0058] In the feedback process according to the second embodiment, the multiple designated phase periods DP within the waveform period CY may be a selected number of phase periods PH that are a portion of all phase periods PH within the waveform period CY. That is, in the feedback process according to the second embodiment, the number of the multiple designated phase periods DP within the waveform period CY is M, where M is less than N, the number of phase periods PH within the waveform period CY. In the feedback process according to the second embodiment, the power supply control unit determines the source frequency f for each of the multiple phase periods PH within the waveform period CY other than the multiple designated phase periods DP by interpolation using the source frequencies f for the multiple designated phase periods DP. The interpolation may be linear interpolation using the source frequencies f for each of two adjacent designated phase periods DP. The interpolation may also be performed by other methods.

[0059] In the feedback process, the power supply control unit calculates the i-th waveform period CY in the series CYS of waveform periods CY. ｉ mth designated phase period DP ｍ The source frequency f[i,m] for the mth designated phase period DP in the preceding several waveform periods CY in the sequence CYS is ｍ The degree of reflection is determined so as to suppress the change in the source frequency and the degree of reflection of the source high frequency power. ｉ The preceding waveform period CY is the waveform period CY ｉ－Ｉｆｂ and C.Y. ｉ－２×Ｉｆｂ Here, "Ifb" is an integer of 1 or greater.

[0060] The feedback process includes a first feedback process and / or a second feedback process. The first feedback process is applied when the source high frequency power HF and the electrical bias EB are supplied simultaneously and continuously, as shown in FIG. 5A. In the first feedback process, the series CYS is composed of a plurality of waveform periods CY that are continuously repeated.

[0061] The second feedback process is applied when a pulse of the source high frequency power HF and a pulse of the electrical bias EB are supplied in synchronization with each other, as shown in FIG. 5B. In the second feedback process, the sequence CYS is a sequence of waveform periods CY in the same order in each of the plurality of pulse periods PP, i.e., the kth waveform period CY in each of the plurality of pulse periods PP. ｋ It consists of:

[0062] In the example shown in FIG. 5B, the second feedback process may be applied to all waveform periods CY in each of the plurality of pulse periods PP. Alternatively, the second feedback process may be applied to the first to Kth waveform periods CY in each of the plurality of pulse periods PP. １ A second feedback process may be applied to each of the first through second waveform periods CY, and (K １ +1) to the last waveform period CY, where K １ is an integer equal to or greater than 1. Alternatively, the first to Kth pulse periods PP are １ A second feedback process may be applied to each of the first through second waveform periods CY, and (K １ +1) to the last waveform period CY, １ The source frequency for each assigned phase period of the th waveform period CY may be used for the same assigned phase period.

[0063] An example of the feedback process applied to each series CYS will be described below with reference to Figures 7 and 8. Figure 7 is a flowchart showing an example of the feedback process. Figure 8 is a flowchart showing an example of the process in step ST9 shown in Figure 7. The example of the feedback process described below is an example in which the above-mentioned "Ifb" is 1. However, as described above, "Ifb" may be an integer greater than 1.

[0064] 7, the feedback process may include steps ST1 to ST9, which are performed for a plurality of designated phase periods DP in each waveform period CY in the series CYS.

[0065] In step ST1, the power supply control unit sets i to 1. "i" represents the order of the waveform period CY in the series CYS.

[0066] In the subsequent step ST2, a source frequency f and a shift value Δf are set for each of the multiple designated phase periods DP of the i-th waveform period CY in the series CYS. Specifically, in step ST2, the power supply control unit sets the source frequency f[i,m] and the shift value Δf[i,m]. In step ST2, the source frequency f[i,m] and the shift value Δf[i,m], i.e., the source frequency f[1,m] and the shift value Δf[1,m], are set to respective predetermined values. In the feedback processing according to the second embodiment, the source frequency f for phase periods other than the multiple designated phase periods DP is set by interpolation in step ST2, as described above.

[0067] The subsequent step ST3 corresponds to step STa of the method MT. In step ST3, the power supply control unit supplies, from the high frequency power supply 41, source high frequency power HF having a source frequency f for each of the plurality of phase periods PH in the waveform period CY set in step ST2. That is, in step ST3, the power supply control unit ｉ The designated phase period DP ｍ In the above-described steps STb, an electric bias is supplied, and in the above-described steps STc to STf, the degree of reflection R Ｄ is obtained.

[0068] Steps ST4, ST5, and ST6 correspond to step STg of the method MT. The process consisting of steps ST4, ST5, and ST6 is performed for each of a plurality of designated phase periods DP in the i-th waveform period CY in the series CYS.

[0069] In step ST4, the power supply control unit ｉ The designated phase period DP ｍ The degree of reflection R of the source high frequency power HF at Ｄ, i.e., the degree of reflection R Ｄ In step ST4, it is determined whether [i, m] is large enough to satisfy the frequency change condition. ｉ The designated phase period DP ｍ The degree of reflection R of the source high frequency power HF at Ｄ In step ST4, the frequency change condition is satisfied when [i, m] is greater than the threshold. Ｄ [i, m] is the first threshold R ｔｈ１ [m]. Note that the first threshold value R for each of the multiple designated phase periods DP may be satisfied when the first threshold value R ｔｈ１ may be the same as or different from each other.

[0070] If it is determined in step ST4 that the frequency change condition is satisfied, the power supply control unit 100 changes the frequency of the subsequent waveform period CY in the series CYS in step ST5. ｉ＋１ The designated phase period DP ｍ The source frequency f[i+1,m] for is set by the following formula: f[i+1,m]=f[i,m]+Δf[i,m]

[0071] On the other hand, if it is determined in step ST4 that the frequency change condition is not satisfied, the power supply control unit sets the source frequency f[i+1, m] according to the following equation in step ST6: f[i+1, m]=f[i, m]

[0072] In the case of the feedback processing according to the second embodiment, before the processing moves to the next step ST7, the source frequency f for the phase periods other than the multiple designated phase periods DP is set by interpolation as described above.

[0073] Next, steps ST7 to ST9 are performed. Steps ST7 to ST9 are repeated until it is determined that the stop condition is satisfied in step STJ of method MT. In step ST7, the power supply control unit increments i by 1.

[0074] Steps ST8 and ST9 are performed for each of the multiple designated phase periods DP of the i-th waveform period CY in the series CYS. Step ST8 corresponds to step STa of the method MT. In step ST8, the power supply control unit supplies, from the high-frequency power supply 41, the source high-frequency power HF having the source frequency f for each of the multiple phase periods PH in the waveform period CY that was set immediately before. That is, in step ST8, the power supply control unit ｉ The designated phase period DP ｍ In the above-described steps STb, an electric bias is supplied, and in the above-described steps STc to STf, the degree of reflection R Ｄ is obtained.

[0075] In the subsequent step ST9, the power supply control unit calculates the degree of reflection R Ｄ [i, m], the next waveform period CY in the sequence CYS ｉ＋１ The designated phase period DP ｍ Determine the source frequency f[i+1,m] for

[0076] 8, the process ST9 starts with a process ST901. In the process ST901, the power supply control unit calculates the degree of reflection R Ｄ In step ST901, it is determined whether [i, m] is increasing. Ｄ [i, m] is R Ｄ [i, m]>R Ｄ Alternatively, if the i-th waveform period CY in the series CYS is satisfied, it may be determined that the trend is increasing. ｉ The mth designated phase period DP over two or more waveform periods CY up to ｍ If the degree of reflection at Ｄ It may be determined that [i, m] is on the rise.

[0077] In step ST901, the degree of reflection R ＤIf it is determined that [i, m] is not increasing, the power supply control unit maintains the sign of the shift value Δf[i, m] in step ST902. That is, in step ST902, the power supply control unit sets the shift value Δf[i, m] using the following formula: Δf[i, m]=Δf[i-1, m]

[0078] On the other hand, in step ST901, the degree of reflection R Ｄ If it is determined that [i, m] is on the increase, the power supply control unit changes the sign of the shift value Δf[i, m] in step ST903. That is, in step ST903, the power supply control unit sets the shift value Δf[i, m] using the following formula: Δf[i, m]=-Δf[i-1, m]

[0079] In the next step ST904, the power supply control unit ｉ The designated phase period DP ｍ The degree of reflection R of the source high frequency power HF at Ｄ In step ST904, it is determined whether [i, m] is large enough to satisfy the frequency change condition. ｉ The designated phase period DP ｍ The degree of reflection R of the source high frequency power HF at Ｄ Satisfied if [i, m] is greater than a threshold.

[0080] In one embodiment, the designated phase period DP in any waveform period in the series CYS ｍ The degree of reflection at and the first threshold R ｔｈ１ If it is determined that the degree of reflection is small as a result of the comparison with [m], the designated phase period DP ｍ The degree of reflection at and the second threshold R ｔｈ２ The frequency change condition may not be satisfied in step ST904 until it is determined that the degree of reflection is large as a result of the comparison with the second threshold value R ｔｈ２ [m] is the first threshold R ｔｈ１ [m] or more. The second threshold R ｔｈ２ [m] is the first threshold R ｔｈ１[m]. The second threshold value R for each of the multiple designated phase periods DP may be greater than [m]. ｔｈ２ [m] may be the same or different.

[0081] Specifically, the designated phase period DP in any waveform period in the series CYS ｍ The degree of reflection at ｔｈ１ If it is determined that the specified phase period DP is less than [m], the specified phase period DP is ｍ A second threshold R is used as a threshold to be compared with the degree of reflection at ｔｈ２ [m] may be used. Then, the designated phase period DP in any waveform period in the series CYS ｍ The degree of reflection at ｔｈ２ If it is determined that the specified phase period DP is greater than [m], the specified phase period DP is then set in step ST904. ｍ A first threshold R is used as a threshold to be compared with the degree of reflection at ｔｈ１ [m] may also be used.

[0082] If it is determined in step ST904 that the frequency change condition is satisfied, the power supply control unit 100 changes the waveform period CY in the series CYS in step ST905. ｉ＋１ The designated phase period DP ｍ The source frequency f[i+1,m] for is set by the following formula: f[i+1,m]=f[i,m]+Δf[i,m]

[0083] On the other hand, if the frequency change condition is not satisfied in step ST904, the power supply control unit sets the source frequency f[i+1, m] according to the following equation in step ST906: f[i+1, m]=f[i, m]

[0084] In the case of the feedback processing according to the second embodiment, before the processing moves to the next step, the source frequency f for the phase periods other than the multiple designated phase periods DP is set by interpolation as described above.

[0085] According to the feedback process, the degree of reflection R ＤBy adjusting the source frequency f[i+1, m] according to [i, m], reflection of the source high frequency power HF is suppressed. ｔｈ１ and the second threshold R ｔｈ２ By using the method MT, excessive changes in the source frequency are suppressed. Furthermore, when the method MT is repeated, high reproducibility of the time change in the source frequency can be achieved. Furthermore, according to the feedback process of the second embodiment, the source frequency of each of the phase periods PH other than the plurality of designated phase periods DP is determined by interpolation based on the source frequencies for the plurality of designated phase periods DP. Therefore, according to the feedback process of the second embodiment, large fluctuations in the source frequency within the waveform period CY are suppressed.

[0086] Another example of the feedback process will be described below with reference to Figures 9 and 10. Figure 9 is a flow chart showing another example of the feedback process. Figure 10 is a flow chart showing an example of the process in step ST9a shown in Figure 9. The feedback process shown in Figures 9 and 10 will be described below from the perspective of differences from the feedback process shown in Figures 7 and 8. In the process shown in Figures 9 and 10, the power supply control unit calculates the shift value Δf[i,m] as the degree of reflection R Ｄ It is set to a value according to the magnitude of [i, m].

[0087] 9, the power supply control unit sets the source frequency f[i, m] and the coefficient α[i, m] in a step ST2a between the step ST1 and the step ST3. In the step ST2a, the source frequency f[i, m] and the coefficient α[i, m], i.e., the source frequency f[1, m] and the coefficient α[1, m], are set to respective values ​​that are set in advance.

[0088] If it is determined in step ST4 that the frequency change condition is satisfied, the power supply control unit sets the shift value Δf[i,m] by the following formula in step ST5a between step ST4 and step ST5: Δf[i,m]=α[i,m]*(R Ｄ [i,m]-R ｔｈ１ [m])

[0089] Then, in step ST9a following step ST8, the power supply control unit calculates the degree of reflection R Ｄ [i, m], the next waveform period CY in the sequence CYS ｉ＋１ The designated phase period DP ｍ Determine the source frequency f[i+1,m] for

[0090] As shown in Fig. 10, the process ST9a starts with a step ST901. Ｄ If it is determined that [i, m] is not increasing, the power supply control unit maintains the sign of the coefficient α[i, m] in step ST902a. That is, in step ST902a, the power supply control unit sets the coefficient α[i, m] using the following formula: α[i, m] = α[i-1, m]

[0091] On the other hand, in step ST901, the degree of reflection R Ｄ If it is determined that [i, m] is on the increase, the power supply control unit changes the sign of the coefficient α[i, m] in step ST903a. That is, in step ST903a, the power supply control unit sets the coefficient α[i, m] using the following formula: α[i, m] = -α[i-1, m]

[0092] As shown in FIG. 10 , if it is determined in step ST904 that the frequency change condition is satisfied, in step ST905a between step ST904 and step ST905, the power supply control unit sets the shift value Δf[i,m] by the following formula: Δf[i,m]=α[i,m]*(R Ｄ [i,m]-R ｔｈ１ [m])

[0093] 11 is a timing chart showing an example of the source high frequency power and the electric bias in a plasma processing apparatus according to an exemplary embodiment. Similar to FIG. 5B, FIG. 11 shows an example in which a pulse of the electric bias EB and a pulse of the source high frequency power HF are supplied in synchronization with each other. In FIG. 11, the pulse period PP ｋ As shown in FIG. 11, each pulse period PP is a first feedback period P Ｆ [1] and the second feedback period PＦ [2]. The first feedback period P Ｆ [1] is the period from the start of the pulse period PP to the end of the pulse period PP. Ｆ [2] is the first feedback period P Ｆ This is the period following [1] and continuing until the end of the pulse period PP. Ｆ [1] and the second feedback period P Ｆ Each of [2] may include multiple waveform periods CY.

[0094] The power supply control unit Ｆ The second feedback process described above may be performed to determine the source frequency f for each of the plurality of designated phase periods DP within each of the plurality of waveform periods CY in [1].

[0095] In the case of the feedback process according to the second embodiment, the power supply control unit Ｆ The last designated phase period in the j-th waveform period CY in [1] and the first feedback period P Ｆ The first designated phase period DP in the (j+1)th waveform period CY in [1] １ The source frequency f of each phase period between the last designated phase period and the first designated phase period DP １ Alternatively, the source frequency f may be set to a value obtained by interpolation (for example, linear interpolation) using the source frequency f. In the case of the feedback process according to the second embodiment, Ｆ The number of designated phase periods included in each of the plurality of waveform periods CY in [1] may be different. In addition, in the case of the feedback process according to the second embodiment, the first feedback period P Ｆ In each of the plurality of waveform periods CY in [1], the time positions of the plurality of designated phase periods may be different.

[0096] As described above, in the period between the supply of a pulse of source high frequency power HF and the supply of the next pulse of source high frequency power HF, source high frequency power HF having a power level lower than that of the pulse may be supplied. Hereinafter, this period in which source high frequency power HF having a power level lower than that of the pulse of source high frequency power HF is supplied will be referred to as a LOW period. The source frequency f used in the LOW period may be constant or may be predetermined.

[0097] In the case of the feedback process according to the second embodiment, the first feedback period P Ｆ The first phase period PH in the first waveform period CY in [1] １ is the first designated phase period DP among the multiple designated phase periods DP. １ Alternatively, in the case of the feedback process according to the second embodiment, the first feedback period P Ｆ The first phase period PH in the first waveform period CY in [1] １ is the first designated phase period DP among the multiple designated phase periods DP. １ In the latter case, the power supply control unit may determine whether the final point in the LOW period is equal to the first feedback period P Ｆ The first designated phase period DP in [1] １ The source frequency f in each phase period between the LOW period and the first feedback period P Ｆ The first designated phase period DP in [1] １ Alternatively, the source frequency f may be set to a value obtained by interpolation (for example, linear interpolation) using the source frequency f.

[0098] The power supply control unit also Ｆ The first feedback process described above may be performed to determine the source frequency f for each of the plurality of designated phase periods DP in each of the plurality of waveform periods CY in [2]. In addition, in the case of the feedback process according to the second embodiment, the power supply control unit may perform the second feedback process ＦAlternatively, the source frequency f for each phase period other than the plurality of designated phase periods DP in each of the plurality of waveform periods CY in [2] may be determined by interpolation using the source frequency f for the plurality of designated phase periods DP. Ｆ [2] as the source frequency for the plurality of phase periods PH in each of the plurality of waveform periods CY in the immediately preceding first feedback period P Ｆ The source frequency for multiple phase periods PH in the final waveform period CY in [1] may be used.

[0099] Hereinafter, the multiple designated phase periods DP within a waveform period CY in the feedback process according to the second embodiment will be described with reference to FIGS. 12 and 13. Each of FIGS. 12 and 13 is a timing chart related to a power supply system according to an exemplary embodiment. As shown in FIG. 12, the number M of the multiple designated phase periods DP within a waveform period CY is less than the number N of the multiple phase periods PH within the waveform period CY. Note that although the number M of the multiple designated phase periods DP within the waveform period CY is 11 in the example of FIG. 12, the number M is not limited to 11.

[0100] The intervals between multiple designated phase periods DP within the waveform period CY may be set to be smaller in sections within the waveform period CY where the change in the potential of the substrate W is large than in sections within the waveform period CY where the change in the potential of the substrate W is small.

[0101] The phases of the plurality of designated phase periods DP in the waveform period CY may be predetermined. As shown in FIG. 13, when the electric bias EB includes a voltage pulse VP, the waveform period CY has a first period P １ , the second period P ２ , and the third period P ３ The voltage pulse VP may include a first period P １ The power supply is in an OFF state during the second period P ２ is the first period P １ The voltage pulse VP continues for a second period P ２ The third period P ３ is the second period P ２The voltage pulse VP continues for a third period P ３ It is in the OFF state.

[0102] In one embodiment, the plurality of designated phase periods DP are ２ The interval between the first period P of the plurality of designated phase periods DP １ and the third period P ３ In this case, the interval between the first and second periods P ２ In this case, the source frequency f can be adjusted to more effectively suppress reflections of the source high frequency power HF.

[0103] In one embodiment, the third period P of the plurality of designated phase periods DP ３ The interval in the first period P of the plurality of designated phase periods DP １ , and the first period P of the plurality of designated phase periods DP １ The interval between the third period P of the plurality of designated phase periods DP may be smaller than the interval between the third period P ３ The interval in the first period P of the designated phase periods DP １ If the interval between the voltage pulses VP and VP is smaller than the interval between the voltage pulses VP and VP, the source frequency f can be adjusted to more effectively suppress the reflection of the source high frequency power HF immediately after the voltage pulses VP are switched from the ON state to the OFF state.

[0104] In one embodiment, the second period P ２ is the first sub-period SP １ , second sub-period SP ２ , and the third sub-period SP ３ The first sub-period SP １ is the first period P １ The first sub-period SP is the period immediately following the first sub-period SP. １ During the second sub-period SP, the voltage level of the voltage pulse VP changes in the negative direction from its reference voltage level (e.g., 0 V) ​​to a set voltage level. ２ is the first sub-period SP １ The second sub-period SP ２In the third sub-period SP, the voltage level of the voltage pulse VP is at its set voltage level. ３ is the second sub-period SP ２ The third sub-period SP ３ During the first sub-period SP, the voltage level of the voltage pulse VP changes from its set voltage level to the reference voltage level. １ , second sub-period SP ２ , and the third sub-period SP ３ The intervals between the multiple designated phase periods DP in each may be the same or may be different from each other.

[0105] In one embodiment, a plurality of designated phase periods DP may be predetermined from a source frequency f for each of a plurality of phase periods PH in a waveform period CY obtained by performing the above-described feedback process for each phase period PH in the series CYS of waveform periods CY. Specifically, ｎ The source frequency f[n] and the (n-u)th phase period PH within the waveform period CY ｎ－ｕ The absolute value of the difference between the source frequency f[n-u] and the source frequency f[n] and the (n+u)th phase period PH within the waveform period CY ｎ＋ｕ When the absolute values ​​of the differences between the source frequency f[n+u] and the source frequency f[n-u] are greater than a predetermined value, and both the source frequency f[n-u] and the source frequency f[n+u] are greater than or smaller than the source frequency f[n], the phase period PH ｎ A plurality of designated phase periods DP may be pre-selected from the plurality of phase periods PH so as to exclude

[0106] Alternatively, the multiple designated phase periods DP may be determined by calculation by the power supply control unit. In one embodiment, the power supply control unit acquires, during the preparation period, a series of source frequencies f for the multiple phase periods PH within the waveform period CY, obtained by performing the above-described feedback processing for each phase period PH in the series CYS of the waveform period CY. The power supply control unit determines the multiple designated phase periods DP such that the intervals between the multiple designated phase periods DP become smaller in sections where the source frequency f changes more significantly in the series of source frequencies f obtained by smoothing the series of source frequencies f.

[0107] In one embodiment, the power supply control unit may acquire a voltage waveform of the electric bias EB. In this embodiment, the power supply control unit may acquire the voltage waveform of the electric bias EB during the first period P １ , the second period P ２ , and the third period P ３ and the first period P １ , the second period P ２ , and the third period P ３ The intervals between the multiple designated phase periods DP in each of the designated phase periods DP may be set as described above.

[0108] Hereinafter, several embodiments will be described in which the adjustment of the source frequency f by the power supply control unit in the method MT is performed by a shift and / or scaling process (hereinafter referred to as "SS process").

[0109] In the SS process, when the source high frequency power HF and the electric bias EB are supplied simultaneously and continuously as shown in (a) of Fig. 5, the series CYS is made up of a plurality of waveform periods CY that are repeated continuously. Also in the SS process, when the source high frequency power HF pulse and the electric bias EB pulse that are synchronized with each other are supplied as shown in (b) of Fig. 5, the series CYS is made up of waveform periods CY in the same order in each of the plurality of pulse periods PP. Alternatively, in the SS process, the first to Kth pulses in each of the plurality of pulse periods PP are supplied. １ For each of the waveform periods CY up to the th, the waveform periods CY in the same order in each of the plurality of pulse periods PP form a series CYS, and the (K１ +1)th to last waveform periods CY may form a series CYS. Alternatively, in the SS process, the first to Kth waveform periods CY of each of the plurality of pulse periods PP may form a series CYS. １ For each of the waveform periods CY up to the th, the waveform periods CY in the same order in each of the plurality of pulse periods PP form a series CYS, and the (K １ +1) to the last waveform period CY, １ The source frequency of each phase period of the th waveform cycle CY may be used in the same phase period. The SS process applied to each series CYS will now be described.

[0110] In the method MT including the SS process, initially, in step STa, the power supply control unit generates a basic time series TS, which is a time series of a predetermined frequency. Ｂ is used as a time series of source frequencies f within a waveform period CY, and a source high frequency power HF is supplied from the high frequency power supply 41. The time series of source frequencies f includes a plurality of frequencies, and the plurality of frequencies are used as frequencies of the source high frequency power HF in each of a plurality of phase periods PH within the waveform period CY. Ｂ is prepared in advance. Ｂ may be determined by performing the first feedback process or the second feedback process described above in advance.

[0111] Furthermore, through steps STb to STf, the degree of reflection R in the waveform cycle CY Ｄ In the SS process, the degree of reflection R Ｄ is a plurality of digital values ​​V in a waveform period CY. Ｄ It is a representative value, for example an average value, of a plurality of evaluation values ​​obtained from

[0112] Next, in step STg, the power supply control unit adjusts the time series of the source frequency f to generate a changed time series TS of the source frequency f. Ｍ Then, in step STa, the power supply control unit generates a time series TS as the source frequency f for each of the plurality of phase periods PH in the subsequent waveform period CY in the series CYS. ＭThe source high frequency power HF having a plurality of frequencies is supplied from the high frequency power supply 41. Then, the steps STb to STg are performed again. In the method MT including the SS process, the degree of reflection R in the waveform period CY in the series CYS is Ｄ Steps STa to STg are repeated to reduce the

[0113] In the process STg, the time series TS Ｍ The time series TS1 is a time series TS2, a time series TS3, or a time series TS4. ... Ｂ The time series TS2 is a frequency time series obtained by applying the basic time series TS Ｂ The time series TS3 is a time series of frequencies obtained by scaling (i.e., expanding or contracting) the basic time series TS in the frequency direction. Ｂ The time series TS3 is a time series of frequencies that contains the same number of frequencies as the basic time series TS. Ｂ It is a time series of frequencies obtained by scaling (expanding or contracting) two or more of the multiple time zones in the time direction.

[0114] Below, some examples of the method MT including SS processing will be described.

[0115] [First Example]

[0116] A first example of the method MT including SS processing, i.e., a first example control method (hereinafter referred to as "method MTA"), will be described with reference to Figures 14 and 15. Figure 14 is a flow chart showing the first example control method. Figure 15 is a diagram for explaining the first example control method shown in Figure 14. In Figure 15, the horizontal axis represents time, and the vertical axis represents the electric bias EB and the source frequency f. Figure 15 shows an example of the waveform of the electric bias EB in a waveform period CY. Figure 15 also shows a basic time series TS used as the source frequency f for each of a plurality of phase periods PH within the waveform period CY. Ｂ and the modified time series TS Ｍ In the method MTA, the modified time series TS Ｍ The above-described time series TS1 is used as the time series TS1.

[0117] The method MTA is applied to each sequence CYS. As shown in FIG. 14, the method MTA begins with step STAa1, which corresponds to step STa. In step STAa1, the power supply controller selects a basic time sequence TS as the source frequency f for each of a plurality of phase periods PH within a waveform period CY. Ｂ A source high frequency power HF having a plurality of frequencies is supplied from the high frequency power supply 41. As described above for the method MT, the method MTA may also perform the step STb.

[0118] Next, the process STAf1 is performed. The process STAf1 corresponds to the processes STc to STf. In the process STAf1, the degree of reflection R Ｄ is obtained.

[0119] Next, a process STAg1 is performed. The process STAg1 corresponds to the process STg. In the process STAg1, the power supply control unit generates a basic time series TS for the waveform period CY. Ｂ The time series TS obtained by applying a phase shift to Ｍ Prepare the following.

[0120] Next, a process STAa2 is performed. The process STAa2 corresponds to the process STa. In the process STAa2, the power supply control unit 100 sets the time series TS as the source frequency f for each of the plurality of phase periods PH in the waveform cycle CY. Ｍ A source high frequency power HF having a plurality of frequencies is supplied from a high frequency power supply 41.

[0121] Next, the process STAf2 is performed. In the process STAf2, the degree of reflection R in the waveform cycle CY is calculated in the same manner as in the process STAf1. Ｄ is obtained.

[0122] Next, a process STAJ1 is performed. The process STAJ1 corresponds to the process STJ. The determination in the process STAJ1 may be made by the power supply control unit. If it is determined in the process STAJ1 that the stop condition is not satisfied, a process STAJ2 is performed.

[0123] In step STAJ2, the degree of reflection R obtained in step STAf2 ＤIt is determined whether the reflection degree R is equal to or less than a specified value. The determination in the step STAJ2 can be performed by the power supply control unit. Ｄ The fact that the reflection degree R is equal to or less than the specified value indicates that the alignment is good. Ｄ If it is determined that the degree of reflection R is equal to or less than the specified value, the process is repeated from step STAa2. Ｄ If it is determined that the value is greater than the specified value, step STAJ3 is performed.

[0124] In the process STAJ3, the degree of reflection R in the waveform period CY acquired in the process STAf2 is Ｄ and the reflection degree R obtained immediately before in the processing for the series CYS. Ｄ are compared with each other to determine the degree of reflection R Ｄ Is the reflection rate R improved? Ｄ It is determined whether the degree of reflection R has been reduced. The determination of the step STAJ3 is made by the power supply control unit. Ｄ If it is determined that the degree of reflection R has improved, the step STAg2 is performed. Ｄ If it is determined that the condition has not improved, step STAg3 is performed.

[0125] The process STAg2 corresponds to the process STg. The process STAg2 can be performed by the power supply control unit. In the process STAg2, the phase shift amount is changed in the same direction as the phase shift amount used immediately before in the process for the series CYS. If the phase shift amount used immediately before in the process for the series CYS is increased compared to the phase shift amount used previously, the phase shift amount is increased in the process STAg2 as shown by the right-pointing arrow in FIG. 15. If the phase shift amount used immediately before in the process for the series CYS is decreased compared to the phase shift amount used previously, the phase shift amount is decreased in the process STAg2. Then, the changed phase shift amount is added to the basic time series TS. Ｂ The time series TS obtained by ＭThen, the time series TS prepared in step STAg2 is Ｍ Step STAa2 is performed again using the above.

[0126] The process STAg3 corresponds to the process STg. The process STAg3 can be performed by the power supply control unit. In the process STAg3, the phase shift amount is changed in the opposite direction to the phase shift amount used immediately before in the processing for the series CYS. If the phase shift amount used immediately before is increased compared to the phase shift amount used previously, the phase shift amount is decreased in the process STAg3 as shown by the left-pointing arrow in FIG. 15. If the phase shift amount used immediately before in the processing for the series CYS is decreased compared to the phase shift amount used previously, the phase shift amount is increased in the process STAg3. Then, the changed phase shift amount is added to the basic time series TS. Ｂ The time series TS obtained by Ｍ Then, the process STAa2 is performed again. That is, the time series TS prepared in the process STAg3 is Ｍ Step STAa2 is performed again using the above.

[0127] The method MTA ends when it is determined in step STJ1 that the stop condition is satisfied.

[0128] [Second Example]

[0129] A second example of the method MT including SS processing, i.e., a second example control method (hereinafter referred to as "method MTB"), will be described below with reference to FIGS. 16 to 20. FIG. 16 is a flow chart showing the second example control method. Each of FIGS. 17 to 20 is a diagram for explaining the second example control method shown in FIG. 16. In each of FIGS. 17 to 20, the horizontal axis represents time, and the vertical axis represents the electric bias EB and the source frequency f. Each of FIGS. 17 to 20 shows an example of the waveform of the electric bias EB in the waveform period CY. Each of FIGS. 17 to 20 also shows a basic time series TS used as the source frequency f for each of the multiple phase periods PH within the waveform period CY. Ｂ and the modified time series TS Ｍ In the method MTB, the modified time series TSＭ The above-described time series TS2 is used as the time series TS2.

[0130] Method MTB is applied to each series CYS. As shown in Fig. 16, method MTB starts with step STBa1. Step STBa1 is the same as step STAa1. Next, step STBf1 is performed. Step STBf1 is the same as step STAf1.

[0131] Next, a step STBg1 is performed. The step STBg1 corresponds to the step STg. In the step STBg1, the power supply control unit Ｂ The time series TS obtained by scaling, i.e., expanding or contracting, Ｍ Prepare the following.

[0132] Time series TS prepared in process STBg1 Ｍ is a basic time series TS as shown in FIG. Ｂ The lowest frequency f ｍｉｎ While maintaining the basic time series TS Ｂ In the following description, the time series TS21 prepared in step STBg1 may be obtained by scaling the time series TS21 in the frequency direction. Ｍ As shown in FIG. 18, Ｂ The highest frequency f ｍａｘ While maintaining the basic time series TS Ｂ In the following description, the time series TS22 prepared in step STBg1 may be obtained by scaling the time series TS22 in the frequency direction. Ｍ As shown in FIG. 19, Ｂ At the specified frequency f ｓｐ While maintaining the following frequency, the basic time series TS Ｂ In the following description, the time series TS prepared in step STBg1 may be obtained by scaling the time series TS23 in the frequency direction. Ｍ As shown in FIG. 20, ＢAt the specified frequency f ｓｐ While maintaining the above frequency, the basic time series TS Ｂ In the following description, the time series changed as shown in FIG. 20 is referred to as time series TS24. In step STBg1, any one of the time series TS21 to TS24 is converted to time series TS Ｍ It is prepared as.

[0133] Next, a process STBa2 is performed. The process STBa2 corresponds to the process STa. In the process STBa2, the power supply control unit calculates a time series TS as a source frequency f for each of a plurality of phase periods PH in the waveform cycle CY. Ｍ A source high frequency power HF having a plurality of frequencies is supplied from a high frequency power supply 41.

[0134] Next, step STBf2 is performed. In step STBf2, the degree of reflection R in the waveform cycle CY is calculated in the same manner as in step STBf1. Ｄ is obtained.

[0135] Next, the process STBJ is performed. The determination in the process STBJ can be performed by the power supply control unit. In the process STBJ, the stop condition is satisfied when, for example, a cycle including the process STBa2 has been performed a predetermined number of times.

[0136] If it is determined in the step STBJ that the stop condition is not satisfied, a step STBg2 is performed. The step STBg2 corresponds to the step STg. The step STBg2 can be performed by the power supply control unit. In the step STBg2, the basic time series TS Ｂ The scaling factor in the frequency direction for the time series TS is changed as shown by the arrows in FIGS. 17 to 20. Ｍ is prepared. Ｍ is prepared by the power supply control unit. Then, the time series TS prepared in the step STBg2 ＭStep STBa2 is performed again using the time series TS21 to TS24. That is, in the method MTB, a cycle including step STBa2 is repeated. In the repetition of the cycle including step STBa2, any one of the time series TS21 to TS24 may be used, and the scaling factor may be changed. In the repetition of the cycle including step STBa2, the time series TS21 to TS24 may be used in order while the scaling factor is changed. When it is determined that the stop condition is satisfied in step STBJ, step STBh is performed.

[0137] In the step STBh, the degree of reflection R Ｄ That is, the degree of reflection R Ｄ The time series TS that most reduces Ｍ (first time series) is the degree of reflection R Ｄ The power supply control unit selects the time series TS Ｍ The source high frequency power HF having a plurality of frequencies included in the source frequency f of each of a plurality of phase periods PH in the waveform period CY is supplied from the high frequency power supply 41. After this step STBh, the method MTB may be terminated. Alternatively, after step STBh, step STBi may be performed. In step STBi, the time series TS selected in step STBh is Ｍ The method MTA is carried out using as the base time series.

[0138] [Third Example]

[0139] A third example of the method MT including SS processing, i.e., a third example control method (hereinafter referred to as "method MTC"), will be described below with reference to Figures 21 and 22. Figure 21 is a flow chart showing the third example control method. Figure 22 is a diagram for explaining the third example control method shown in Figure 21. In Figure 22, the horizontal axis represents time, and the vertical axis represents the electric bias EB and the source frequency f. Figure 22 shows an example of the waveform of the electric bias EB in a waveform period CY. Figure 22 also shows a basic time series used as the source frequency f for each of a plurality of phase periods PH within the waveform period CY. In method MTC, a modified time series TS Ｍ The above-mentioned time series TS3 is used as the time series TS3.

[0140] The method MTC is applied to each sequence CYS. As shown in FIG. 21, the method MTC may start at step STCp1. In step STCp1, the basic time sequence TS Ｂ The method MTA is performed using the time series of the reflections R Ｄ That is, the degree of reflection R Ｄ The time series TS that most reduces Ｍ (First time series) is the degree of reflection R obtained in the step STCp1. Ｄ is identified based on and selected as the base time series.

[0141] Next, a step STCp3 may be performed. In the step STCp3, the method MTB is performed using the basic time series selected in the step STCp2. Next, a step STCp4 may be performed. In the step STCp4, the degree of reflection R Ｄ That is, the degree of reflection R Ｄ The time series TS that most reduces Ｍ (Second time series) is the degree of reflection R obtained in step STCp3. Ｄ is identified based on and selected as the base time series.

[0142] Next, a process STCg1 is executed. The process STCg1 corresponds to the process STg. In the process STCg1, the power supply control unit scales (expands or contracts) two or more of the time zones of the basic time series selected in the process STCp4 in the time direction to generate the basic time series TS. Ｂ The modified time series TS contains the same number of frequencies as Ｍ In addition, steps STAa1 and STAf1 of the method MTA are performed without performing steps STCp1 to STCp4, and the basic time series TS is prepared in step STCg1. Ｂ Time series TS Ｍ may be prepared.

[0143] The plurality of time zones may include zones Z1 to Z6 as shown in Fig. 22. To determine the zones Z1 to Z6, the lowest frequency f of the basic time series used in the process STCg1 is used. ｍｉｎ , highest frequency f ｍａｘ , and the average frequency f ａｖｅ Then, the lowest frequency f included in the fundamental time series is identified. ｍｉｎ and maximum frequency f ｍａｘ The difference between the minimum frequency f ｍｉｎ to the minimum frequency f ｍｉｎ The time zone corresponding to the range up to the sum of the maximum frequency f and 10% of the frequency width is determined as zone Z2. ｍａｘ The maximum frequency f is calculated by subtracting 10% of the frequency width from ｍａｘ The time zone corresponding to the range from the start of the waveform period CY to the start of zone Z2 is determined as zone Z1. The time zone corresponding to the range from the end of zone Z2 to the average frequency f ａｖｅ The time zone up to the point corresponding to the average frequency f is determined as the zone Z3. ａｖｅ The time zone from the time corresponding to the waveform period CY to the start of zone Z5 is determined as zone Z4. The time zone from the end of zone Z5 to the end of waveform period CY is determined as zone Z6.

[0144] In the process STCg1, the zone Z2 of the basic time series may be expanded in the time direction. Ｂ The modified time series TS contains the same number of frequencies as Ｍ Zones Z1 and Z3 of the base time series may be compressed in time to generate

[0145] Next, a process STCa is performed. The process STCa corresponds to the process STa. In the process STCa, the power supply control unit sets the time series TS as the source frequency f for each of the plurality of phase periods PH in the waveform cycle CY. Ｍ A source high frequency power HF having a plurality of frequencies is supplied from a high frequency power supply 41.

[0146] Next, the process STCf is performed. In the process STCf, the degree of reflection R in the waveform cycle CY is calculated in the same manner as in the process STAf1. Ｄ is obtained.

[0147] Next, the process STCJ is performed. The process STCJ corresponds to the process STJ. The determination at the process STCJ can be performed by the power supply control unit. At the process STCJ, the stop condition is satisfied when, for example, a cycle including the process STCa has been performed a predetermined number of times.

[0148] If it is determined in the process STCJ1 that the stop condition is not satisfied, the process STCg2 is performed. The process STCg2 corresponds to the process STg. The process STCg2 can be performed by the power supply control unit. In the process STCg2, the scaling factor in the time direction of two or more of the multiple time zones of the basic time series is changed. In the process STCg2, the time series TS Ｍ Then, the time series TS prepared in the process STCg2 is Ｍ In other words, the cycle including the step STCa is repeated. On the other hand, if it is determined that the stop condition is satisfied in the step STCJ, the step STCh described below is performed.

[0149] In the repetition of the cycle including the step STCa, similarly to the step STCg1, the zone Z2 of the basic time series may be expanded in the time direction, and the zones Z1 and Z3 of the basic time series may be contracted in the time direction while changing the scaling factor of the zone Z2 in the time direction. Ｄ Based on the reflectivity R Ｄ This will be continued until it is determined that the condition is no longer improving.

[0150] Next, in the repetition of the cycle including the step STCa, the zone Z5 of the basic time series may be expanded in the time direction, and the zones Z4 and Z6 of the basic time series may be contracted in the time direction while changing the scaling factor of the zone Z5 in the time direction. Ｄ Based on the reflectivity RＤ This will be continued until it is determined that the condition is no longer improving.

[0151] In the step STCh, the degree of reflection R obtained by repeating the cycle including the step STCa is calculated. Ｄ The degree of reflection R Ｄ That is, the degree of reflection R Ｄ The time series TS that most reduces Ｍ is identified and selected as a third time series. The selection of the third time series in the process STCh is performed by the power supply control unit. The power supply control unit then uses the multiple frequencies included in the selected time series (third time series) as the source frequencies f for each of the multiple phase periods PH in the waveform cycle CY. Note that the processing from process STCp1 may be repeated using the third time series as a basic time series.

[0152] As described above, in the plasma processing apparatus 1, the time series of the source frequency f in the waveform period CY corresponds to the degree of reflection R. Ｄ The degree of reflection R Ｄ These time series are changed to the time series TS1, TS2, or TS3 so as to improve the basic time series TS. Ｂ Therefore, it is possible to easily suppress the reflection of the source high frequency power HF used for generating the plasma.

[0153] Below, several other examples of the sensor 45 will be described. In another example, the sensor signal SS acquired by the sensor 45 may include a voltage signal of a forward wave of the source high frequency power HF in addition to a voltage signal VS of a reflected wave of the source high frequency power HF. In this case, an envelope signal is also obtained from the forward wave voltage signal in the detector 51, and multiple digital values ​​are obtained in the A / D converter 52. In this case, the power supply control unit calculates the degree of reflection R using the multiple digital values ​​obtained from the reflected wave voltage signal VS and the multiple digital values ​​obtained from the forward wave voltage signal. Ｄ The reflectance, that is, (power level of reflected wave) / (power level of traveling wave), may be calculated as follows.

[0154] In yet another example, the sensor 45 may include a voltage sensor and a current sensor. In this example, the sensor 45 detects a voltage V in a power supply line connecting the high frequency power supply 41 and the high frequency electrode. ＨＦ and current I ＨＦ In this case, the sensor signal SS is configured to measure the voltage V ＨＦ and current I ＨＦ The impedance Z of the load of the high frequency power supply 41 is determined from Ｌ A signal representing the voltage V ＨＦ and current I ＨＦ A signal or voltage V representing the phase difference θ between ＨＦ and current I ＨＦ In this example, the power supply control unit 50 also calculates the degree of reflection R by using a plurality of digital values ​​obtained from the sensor signal SS via the detector 51 and the A / D converter 52. Ｄ The degree of reflection R Ｄ is the impedance Z in each of the waveform periods CY or multiple phase periods PH Ｌ and the characteristic impedance (for example, 50Ω). Alternatively, the reflection degree R Ｄ may be a representative value (for example, an average value) of the phase difference θ in each of the waveform period CY or the multiple phase periods PH. Alternatively, the degree of reflection R Ｄ may be a representative value (e.g., an average value) of the reflection coefficient Γ in the waveform period CY or in each of the multiple phase periods PH.

[0155] The following describes examples of processing circuits that can be used as one or more processing circuits in the plasma processing apparatus 1, such as the control unit 2 and / or the power supply control unit. FIG. 23 is a block diagram of a processing circuit that implements the operations described herein on a computer. FIG. 23 illustrates a processing circuit 130 that can be used to control a control process on any computer. The descriptions or blocks in the flowcharts represent modules, segments, or portions of code that include one or more executable instructions for implementing specific logical functions or steps of the process. As will be understood by those skilled in the art, other examples having functions that can be performed in a different order than that shown or described, such as substantially simultaneously or in reverse order, depending on the functionality involved, are within the scope of the exemplary embodiments of the present disclosure. The various elements, features, and processes described herein may be used independently of each other or combined in various ways. All conceivable combinations and subcombinations are within the scope of the present disclosure.

[0156] In Figure 23, processing circuitry 130 includes a CPU 1200 that performs one or more of the control processes described above and / or below. Process data and instructions may be stored in memory 1202. These process data and instructions may be stored on a storage medium disk 1204, such as a hard disk drive (HDD) or a portable storage medium, or may be stored remotely. Furthermore, the present disclosure as claimed is not limited by the form of computer-readable medium on which instructions for processes according to the present invention are stored. For example, these instructions may be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device, such as a server and / or computer, with which processing circuitry 130 communicates.

[0157] Furthermore, the claimed disclosure may be provided as a utility application, a background daemon, a component of an operating system, or a combination thereof, and may execute in conjunction with CPU 1200 and an operating system known to those skilled in the art, such as Microsoft Windows®, UNIX®, Solaris®, LINUX®, Apple MAC-OS, etc.

[0158] The hardware elements making up the processing circuit 130 can be realized by various circuit elements. Furthermore, each function of the above-described embodiments can be implemented by a circuit including one or more processing circuits. As shown in FIG. 23, the processing circuit includes a specifically programmed processing unit, such as a processing unit (CPU) 1200. The processing circuit also includes devices such as application specific integrated circuits (ASICs) or conventional circuit components configured to perform the described functions.

[0159] 23, processing circuitry 130 includes CPU 1200 that performs the above-described processing. Processing circuitry 130 may be a general-purpose computer or a specific dedicated machine. In one embodiment, processing circuitry 130 functions as a specific dedicated machine when processing device 1200 is programmed to control plasma generation unit 12 and gas supply unit 20, and / or to control each unit of plasma processing device 1 in adjusting source frequency f as described above.

[0160] Alternatively or additionally, CPU 1200 may be implemented on an FPGA, ASIC, PLD, or using discrete logic circuitry, as will be appreciated by those skilled in the art. Furthermore, CPU 1200 may be implemented as multiple processing units cooperating to perform in parallel the instructions of the processes of the present invention described above.

[0161] The processing circuitry 130 of Figure 23 also includes a network controller 1206, such as an Intel Ethernet PRO network interface card from Intel Corporation of America, for interfacing with a network 1228. As can be appreciated, the network 1228 may be a public network such as the Internet, a private network such as a LAN or WAN, or any combination thereof, and may also include sub-networks such as PSTN or ISDN. The network 1228 may also be wired, such as an Ethernet network, or wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network may also be Wi-Fi, Bluetooth, or any other known form of wireless communication.

[0162] The processing circuitry 130 further includes a display device controller 1208, such as a graphics card or graphics adapter, for interfacing with a display device 1210, such as a monitor. A general-purpose I / O interface 1212 interfaces with a keyboard and / or mouse 1214 and a touch panel 1216, which may be integral with or separate from the display device 1210. The general-purpose I / O interface also connects to various peripheral devices 1218, such as printers and scanners.

[0163] The storage controller 1224 is connected to the storage media disk 1204 via a communication bus 1226, such as ISA, EISA, VESA, PCI, etc., and all components of the processing circuit 130 are connected to each other. The display device 1210, keyboard and / or mouse 1214, and the general features and functions of the display device controller 1208, storage controller 1224, network controller 1206, audio controller 1220, and general purpose I / O interface 1212 are not described herein for the sake of brevity, as they are well known.

[0164] The exemplary circuit elements described in this disclosure may be substituted with other elements and may have different structures than the examples described herein. Furthermore, circuits configured to implement the features described herein may be implemented in multiple circuit units (e.g., chips), or these features may be combined into the circuitry of a single chipset.

[0165] The functions and features described herein may also be performed by various distributed components on a system. For example, one or more processing devices may perform the functions of these systems, where the processing devices are distributed across multiple components communicating within a network. Distributed components may include various human interface and communication devices (e.g., display monitors, smartphones, tablets, personal digital assistants (PDAs)), as well as one or more client and server machines that can share processing. The network may be a private network, such as a LAN or WAN, or a public network, such as the Internet. Input to the system may be received directly by a user or remotely in real time or as a batch process. Furthermore, portions of the embodiments may be implemented on modules or hardware other than those described above. Accordingly, other embodiments are within the scope of the claims.

[0166] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. Furthermore, elements in different embodiments may be combined to form other embodiments.

[0167] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

[0168] 1... plasma processing apparatus, 10... chamber, 30S... power supply system, 41... high frequency power supply, 42... bias power supply, 45... sensor, 51... detector, 52... A / D converter

Claims

a bias power supply configured to supply an electric bias to the substrate support to attract ions from the plasma to a substrate on the substrate support; a sensor configured to acquire a sensor signal reflecting a degree of reflection of the source high frequency power; a detector configured to detect an envelope signal of the sensor signal; an A / D converter configured to perform A / D conversion on the envelope signal output from the detector; and a power supply controller configured to control the high frequency power supply, wherein the power supply controller is configured to adjust a source frequency of the source high frequency power for each of a plurality of phase periods dividing the waveform period of the electric bias in accordance with the degree of reflection in the waveform period or the degree of reflection in each of a plurality of phase periods dividing the waveform period, the degree of reflection being identified from a plurality of digital values ​​generated by the A / D converter from the envelope signal in the waveform period, so as to reduce the degree of reflection in a subsequent waveform period of the electric bias, a sampling frequency of the A / D converter is equal to or greater than twice the product of a bias frequency, which is the reciprocal of the time length of the waveform period, and the number of the plurality of phase periods within the waveform period, and is equal to or less than a minimum frequency of the source frequency that can be adjusted by the high frequency power supply.

2. The plasma processing apparatus of claim 1, wherein the detector includes: a detection circuit; an attenuator and a first filter connected between the sensor and the detection circuit; and a second filter and an amplifier connected between the detection circuit and the A / D converter; the detection circuit is configured to detect a first envelope signal from a first signal generated by attenuating the sensor signal with the attenuator and filtering with the first filter; and the detector is configured to output a second envelope signal generated by filtering the first envelope signal with the second filter and amplifying it with the amplifier to the A / D converter.

3. The plasma processing apparatus according to claim 2, wherein the upper cutoff frequency of the first filter is equal to or greater than the maximum frequency of the source frequency to which the high frequency power supply can be adjusted and is equal to or less than twice the minimum frequency, and the lower cutoff frequency of the first filter is equal to or less than the minimum frequency.

4. The plasma processing apparatus according to claim 3, wherein the second filter is a low-pass filter, and the upper cutoff frequency of the second filter has a value between the upper cutoff frequency of the first filter and the product of the bias frequency and the number of the plurality of phase periods in the waveform cycle.

5. The plasma processing apparatus according to claim 4, wherein the upper cutoff frequency of the second filter is equal to or lower than the minimum frequency.

6. The plasma processing apparatus according to any one of claims 1 to 5, wherein the sensor is a directional coupler, and the sensor signal is a voltage signal of a reflected wave of the source high frequency power.

7. A plasma processing apparatus comprising: a radio frequency power supply configured to supply source radio frequency power to generate plasma from gas in a chamber of the plasma processing apparatus; a bias power supply configured to supply an electric bias to a substrate support in the chamber to attract ions from the plasma to a substrate on the substrate support in the chamber; a sensor configured to acquire a sensor signal reflecting a degree of reflection of the source radio frequency power; a detector configured to detect an envelope signal of the sensor signal; an A / D converter configured to perform A / D conversion on the envelope signal output from the detector; and a power supply controller configured to control the radio frequency power supply, wherein the power supply controller is configured to adjust a source frequency of the source radio frequency power for each of a plurality of phase periods dividing the waveform period of the electric bias in accordance with the degree of reflection in the waveform period or the degree of reflection in each of a plurality of phase periods dividing the waveform period, the degree of reflection being identified from a plurality of digital values ​​generated by the A / D converter from the envelope signal in the waveform period of the electric bias, so as to reduce the degree of reflection in a subsequent waveform period of the electric bias, A power supply system, wherein the sampling frequency of the A / D converter is equal to or greater than twice the product of a bias frequency, which is the inverse of the time length of the waveform period, and the number of the plurality of phase periods within the waveform period, and is equal to or less than the minimum frequency of the source frequency to which the high frequency power supply can be adjusted.

8. The power supply system according to claim 7, wherein the sensor is a directional coupler, and the sensor signal is a voltage signal of a reflected wave of the source high frequency power.

9. (a) supplying a source high frequency power from a high frequency power supply to generate plasma from a gas in a chamber of a plasma processing apparatus; (b) supplying an electric bias from a bias power supply to a substrate support in the chamber to attract ions from the plasma to a substrate on the substrate support; (c) acquiring a sensor signal reflecting the degree of reflection of the source high frequency power in a sensor; (d) detecting an envelope signal of the sensor signal in a detector; (e) performing A / D conversion on the envelope signal output from the detector in an A / D converter; and (f) determining the degree of reflection in a waveform period of the electric bias or in each of a plurality of phase periods dividing the waveform period from a plurality of digital values ​​generated by the A / D converter from the envelope signal in the waveform period. (g) adjusting, by a power supply control unit, the source frequency of the source high frequency power for each of the plurality of phase periods in accordance with the degree of reflection identified in (f) so as to reduce the degree of reflection in a subsequent waveform period of the electrical bias, wherein the sampling frequency of the A / D converter is at least twice the product of a bias frequency, which is the reciprocal of the time length of the waveform period, and the number of the plurality of phase periods within the waveform period, and is at most the minimum frequency of the source frequency to which the high frequency power supply can be adjusted.

10. The control method according to claim 9, wherein the sensor is a directional coupler, and the sensor signal is a voltage signal of a reflected wave of the source high frequency power.

Images