Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a build-up insulating layer which includes a top surface and a bottom surface, and which includes a plurality of insulating layers stacked between the top surface and the bottom surface and an upper circuit layer arranged on the top surface; and a protective layer arranged on the upper circuit layer of the build-up insulating layer, wherein the protective layer includes a through hole having a first depth in the vertical direction, and a recess having a second depth that differs from the first depth in the vertical direction, the through hole and the recess being spaced apart from each other in the horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] Meanwhile, a package substrate and / or interposer applied to a semiconductor package may be provided with a plurality of bump portions connected to semiconductor elements and / or semiconductor chiplets. In addition, as the number of pads of the connecting member and the number of terminals of the semiconductor element increase, a fine pitch between the plurality of bumps is required. However, according to the prior art, there is a limit to reducing the size of the through holes overlapping along the vertical direction with the bump portion due to limitations in the exposure and / or development resolution of the solder resist. Accordingly, the prior art has a limit to reducing the pitch between the plurality of adjacent bumps.

[0006] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0007] In addition, the embodiment provides a circuit board capable of implementing a fine pitch of a bump portion connected to a semiconductor element and a semiconductor package including the same.

[0008] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0009] A circuit board according to an embodiment includes an upper surface and a lower surface, a build-up insulating layer including a plurality of insulating layers laminated between the upper surface and the lower surface, and an upper circuit layer disposed on the upper surface; and a protective layer disposed on the upper circuit layer of the build-up insulating layer; wherein the protective layer includes a through hole having a first depth in a vertical direction and a recess having a second depth different from the first depth in the vertical direction, and the through hole and the recess are spaced apart from each other in a horizontal direction.

[0010] Additionally, the first depth of the through hole is greater than the second depth of the recess.

[0011] Additionally, the upper circuit layer includes a bump portion disposed in the recess and protruding from the bottom surface of the recess, and a pad portion disposed in the through hole and having at least a portion of the upper surface overlapped with the through hole along the vertical direction.

[0012] Additionally, the upper circuit layer further includes a wiring portion connected to at least one of the pad portion and the bump portion, and the wiring portion is covered with the protective layer.

[0013] Additionally, the bottom surface of the recess includes a concave surface that is concave toward the build-up layer.

[0014] Additionally, the bump portion includes a plurality of bumps spaced apart along a horizontal direction, and the concave surface is provided between the plurality of bumps.

[0015] Additionally, the side wall of the recess includes a concave trench facing outward of the recess.

[0016] Additionally, the trench is located at the boundary between the bottom surface of the recess and the side wall of the recess.

[0017] Additionally, the trench is provided along the circumferential direction of the bottom surface of the recess.

[0018] Additionally, the vertical thickness of the bump portion is greater than the vertical thickness of the pad portion.

[0019] Additionally, the vertical thickness of the bump portion is the same as the vertical thickness of the wiring portion.

[0020] In addition, the bump portion includes a first portion disposed on the build-up layer and having a first width along the horizontal direction, and a second portion disposed on the first portion and having a second width different from the first width along the horizontal direction.

[0021] Additionally, the vertical thickness of the first portion of the bump portion is the same as the vertical thickness of the pad portion.

[0022] In addition, the first width is larger than the second width, and the side surface of the first portion and the side surface of the second portion of the bump portion have a step.

[0023] In addition, the horizontal central axis of the first portion of the bump portion and the horizontal central axis of the second portion of the bump portion are misaligned with each other.

[0024] Additionally, the bottom surface of the recess is positioned higher than the first portion of the bump portion.

[0025] Additionally, the circuit board further includes a connecting member embedded within the build-up layer and overlapping at least a portion of the recess along a vertical direction.

[0026] Additionally, the slope of the side wall of the through hole is different from the slope of the side wall of the recess.

[0027] Meanwhile, a semiconductor package according to an embodiment includes a build-up insulating layer including an upper surface and a lower surface, a plurality of insulating layers stacked between the upper surface and the lower surface, and an upper circuit layer disposed on the upper surface; a protective layer disposed on the upper circuit layer of the build-up insulating layer; and a semiconductor element disposed on the protective layer, wherein the protective layer includes a through hole having a first depth along a vertical direction and a recess having a second depth different from the first depth along the vertical direction, and the through hole and the recess are spaced apart from each other along a horizontal direction.

[0028] Additionally, the semiconductor package further includes a buried insulating layer for burying the semiconductor element, wherein the buried insulating layer fills at least a portion of the recess.

[0029] The circuit board of the embodiment may include a build-up layer, and a pad portion and a bump portion arranged on the build-up layer. The bump portion may include a first portion having a first width in a horizontal direction on the build-up layer, and a second portion having a second width smaller than the first width in a horizontal direction on the first portion.

[0030] Through this, the embodiment can ensure that the bump portion has a height greater than a certain level, and further, can refine the pitch between a plurality of bump portions spaced apart in the horizontal direction. Specifically, the bump portion must be arranged on the build-up layer with a certain height. At this time, the bump portion can be arranged by forming an opening by exposing and developing a dry film and then filling the above-described opening with a metal material. As the height of the bump portion increases, the thickness of the dry film also increases, and thus the exposure resolution of the dry film may deteriorate. For example, when performing the exposure process by irradiating light on the upper surface of the dry film, sufficient light may not be transmitted to the area adjacent to the lower surface of the dry film, and thus a portion of the dry film may not be exposed and developed. Furthermore, as the thickness of the dry film increases, the problem of resolution deterioration due to light refraction may become greater. Therefore, in the prior art, there is a limit to reducing the width of the bump portion in the horizontal direction, and further, there is a limit to reducing the pitch between the plurality of bump portions.

[0031] In contrast, the embodiment forms a bump portion using a plurality of dry films stacked along a vertical direction. For example, when the bump portion has a height of 200 μm, in the prior art, the bump portion is arranged using a 200 μm dry film, but in the embodiment, the bump portion is arranged after stacking two layers of 100 μm dry films. Through this, the embodiment can solve the problem of reduced exposure resolution due to light refraction that occurs depending on the thickness of the dry film, and thereby reduce the width of the bump portion in the horizontal direction. Furthermore, in the present invention, by making the horizontal width of the second portion of the bump portion narrower than the horizontal width of the first portion of the bump portion, the gap between neighboring bump portions can be increased while maintaining the pitch between neighboring bump portions, and thus, the problem of a circuit short that occurs when neighboring bump portions are electrically connected to each other can be solved.

[0032] The embodiment includes a protective layer disposed on a build-up layer. At this time, the protective layer includes a through hole that overlaps a pad portion disposed on the build-up layer in a vertical direction, and a recess that overlaps a bump portion in a vertical direction. At this time, the recess is provided in an area where the bump portion is disposed, and may have a vertical depth that is smaller than a vertical depth of the through hole. At this time, the embodiment provides a bump portion that has a vertical thickness that is larger than a vertical thickness of the pad portion, and may overlap the bump portion with a recess provided in the protective layer in a vertical direction and / or a horizontal direction, so that the bump portion can be stably supported and / or protected by the protective layer. Accordingly, the embodiment can increase the height of the bump portion (preferably, the thickness of a second portion of the bump portion) compared to the comparative example, thereby ensuring a stand-off so that a semiconductor device can be stably disposed on an upper build-up layer.

[0033] In addition, the bottom surface of the recess of the protective layer may be positioned higher than the first portion of the bump portion. Accordingly, the interface between the first portion and the second portion of the bump portion may be positioned lower than the recess of the protective layer. In other words, the interface between the first portion and the second portion of the bump portion may be covered with the first protective layer. Accordingly, the embodiment can prevent cracks from occurring at the interface between the first portion and the second portion of the bump portion or intermetallic compounds from penetrating, thereby further improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0034] In addition, the recesses of the protective layer may be spaced apart from the through holes of the protective layer in the horizontal direction. For example, the protective layer may have a plurality of through holes spaced apart from each other in the horizontal direction, and each of the plurality of through holes may be spaced apart without being connected to the recesses. Through this, the mechanical reliability and / or electrical reliability that may occur when the through holes of the protective layer and the recesses of the first protective layer are connected to each other can be improved. For example, the electrical reliability problem, such as a circuit short due to the flow of a bonding material such as solder that may occur when the through holes of the protective layer (104) and the recesses of the protective layer are connected can be solved. In particular, the embodiment can prevent warping of the circuit board that may occur due to the difference in volume of the upper insulating layer and the lower insulating layer, and thus, the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package can be further improved.

[0035] Additionally, the pad portion may be arranged around the bump portion. For example, the pad portion may be arranged closer to the outer surface of the upper build-up layer than the bump portion. At this time, the horizontal width of the pad portion may be larger than the horizontal width of the bump portion. That is, the pad portion having a relatively large horizontal width may be arranged close to the outer surface of the upper build-up layer, thereby ensuring rigidity around the upper surface of the upper build-up layer, thereby preventing the circuit board from being significantly bent in a specific direction.

[0036] The bump portion may have a relatively fine width or a fine pitch compared to the pad portion. The bump portion may be connected to a terminal of a semiconductor element having a relatively small line width and / or pitch, and the pad portion may be connected to a terminal of a semiconductor element having a relatively large line width and / or pitch and / or a pad of an external substrate. For example, the pad portion may be used as a power supply wire that supplies power to the semiconductor element and / or the connecting member, and the bump portion may be used as a signal wire that exchanges a communication signal other than a power signal with the semiconductor element and / or the connecting member. At this time, the pad portion may be arranged in multiple numbers along the periphery of the bump portion at a position spaced apart from the bump portion, thereby enabling a stable power supply without interfering with the communication signal transmitted through the pad portion by the power signal transmitted through the pad portion.

[0037] In addition, the pad portion can function as a shield to prevent interference signals such as external noise from being transmitted to the bump portion, thereby minimizing the loss of communication signals transmitted through the bump portion and improving communication characteristics, thereby further improving the operational reliability of the circuit board and semiconductor package.

[0038] In addition, the embodiment may allow the side walls of the through hole to have different slopes than the side walls of the recess. The side walls of the through hole may have a certain slope with respect to the upper or lower surface of the protective layer. For example, the side walls of the through hole may have a slope such that the horizontal width of the through hole becomes narrower from the upper side to the lower side of the through hole. This allows the volume of the joining member within the through hole having a relatively large volume to be controlled, thereby reducing the manufacturing cost. In addition, the side walls of the through hole may have a slope such that the horizontal width of the through hole becomes narrower from the upper side to the lower side of the through hole, thereby allowing the joining member to be easily seated within the through hole having a relatively large vertical depth.

[0039] Alternatively, the sidewalls of the recess may have a different slope than the sidewalls of the through hole. For example, the sidewalls of the recess may be closer to vertical than the sidewalls of the through hole. This allows for securing the area of ​​the bottom surface of the recess, allowing for precise control of the space in which the semiconductor devices are placed, and thus, for more stable placement of the semiconductor devices.

[0040] Additionally, a trench may be formed on the sidewall of the recess of the protective layer. The trench may be formed concavely outwardly along the circumferential direction of the bottom surface of the recess. The trench may be filled with a bonding member, such as solder, disposed on the bump portion, thereby acting as an anchor to strengthen the bonding force between the bonding member and the circuit board. Alternatively, the trench may be filled with a molding member for molding the semiconductor element, thereby further strengthening the bonding force between the molding member and the circuit board.

[0041] In addition, a concave surface may be provided on the bottom surface of the recess of the protective layer. The concave surface functions to increase the surface area of ​​the bottom surface of the recess of the protective layer, thereby reducing the degree of thermal deformation (e.g., degree of expansion and / or degree of contraction) of the protective layer caused by thermal stress. Accordingly, the concave surface provided on the upper surface of the protective layer can prevent stress caused by thermal deformation of the protective layer from acting on the bump portion. For example, the concave surface can alleviate stress caused by thermal stress and prevent it from being transmitted in the direction toward the bump portion. Accordingly, the embodiment can stably attach a semiconductor element to a circuit board, thereby improving mechanical reliability and electrical reliability between the circuit board and the semiconductor element. Furthermore, the embodiment can stably operate a semiconductor element, thereby improving the operational reliability of electronic products such as servers to which the semiconductor package is applied.

[0042] In addition, the concave surface is provided with a concave curved surface from the upper surface to the lower surface of the protective layer. Through this, the embodiment can further enhance the effect of preventing stress action due to the concave surface. For example, if the concave surface has an angular square shape, stress may be concentrated at the angular portion, which may cause problems such as reduced mechanical reliability or reduced electrical reliability. In contrast, the embodiment can provide the concave surface with a concave curved surface, thereby preventing stress from being concentrated at a specific portion of the concave surface. Therefore, the embodiment can further enhance the physical reliability and / or electrical reliability of the semiconductor package.

[0043] In addition, the protective layer, the bump portion, and the semiconductor element may be formed of different materials. For example, the protective layer may be formed of a solder resist, the bump portion may be formed of a metal material such as copper, and the semiconductor element may be formed of a silicon material. In this case, the thermal expansion coefficients of the protective layer, the bump portion, and the semiconductor element are each different. For example, the thermal expansion coefficient of the protective layer is greater than the thermal expansion coefficients of the bump portion and the semiconductor element. Therefore, when the same thermal stress is applied to the protective layer, the bump portion, and the semiconductor element, the degree of thermal deformation of the protective layer may be the greatest compared to the bump portion and the semiconductor element. Therefore, the embodiment can provide a concave surface on the upper surface of the protective layer, and can prevent stress due to thermal deformation such as expansion and / or contraction from acting on the electrical joint between the circuit board and the semiconductor element, thereby improving the mechanical reliability and / or electrical reliability of the semiconductor package.

[0044] In addition, the first and second portions of the bump portion of the embodiment may have their central axes misaligned in the horizontal direction. For example, the central axis of the first portion of the bump portion in the horizontal direction may be misaligned with the central axis of the second portion in the horizontal direction. Accordingly, the side surface of the bump portion may have a step due to the difference in the horizontal width of the first portion and the horizontal width of the second portion, and the horizontal distance of the step may not be uniform along the circumferential direction of the upper or lower surface of the bump portion due to the misalignment of the horizontal central axes of the first portion and the second portion. For example, the first side surface of the first portion and the first side surface of the second portion on one side of the bump portion may have a first horizontal distance along the horizontal direction, and the second side surface of the first portion and the second side surface of the second portion on the other side of the bump portion may have a second horizontal distance different from the first horizontal distance along the horizontal direction. Through this, the embodiment can prevent the circuit board from being significantly warped in a specific direction due to a misalignment of the horizontal central axis of the first part of the bump portion and the horizontal central axis of the second part, and further, can selectively increase or / and decrease the separation distance between the plurality of bump portions while maintaining the pitch between the plurality of bump portions according to the characteristics that the plurality of bump portions should have, thereby minimizing signal transmission loss while minimizing signal interference, and thereby improving communication characteristics.

[0045] By way of example, the embodiment can cause the central axis of the second portion of the bump portion to be misaligned with the central axis of the first portion of the bump portion in a specific direction and a specific distance based on the direction in which the circuit board is bent, thereby preventing the circuit board from being bent in a specific direction and avoiding excessive stress applied to the circuit board. Accordingly, the mechanical reliability and / or electrical reliability of the circuit board can be improved. In addition, the embodiment can alleviate the warpage of the circuit board, thereby allowing the semiconductor element to be stably attached on the circuit board. In this case, when the circuit board is bent in a specific direction, a height difference may occur between the plurality of bump portions provided on the circuit board, and the terminals of the semiconductor element may not be stably coupled on the plurality of bump portions. In contrast, the embodiment can alleviate the overall warpage of the circuit board by causing the horizontal central axes of the first portion and the second portion of the bump portion to be misaligned with each other, thereby allowing the semiconductor element to be stably attached on the circuit board. Therefore, the embodiment can enable the semiconductor element to operate stably, thereby improving product reliability. Furthermore, the embodiment can enable a product such as a server to which a semiconductor package is applied to operate stably.

[0046] FIG. 1a is a cross-sectional view illustrating a circuit board according to an embodiment.

[0047] Figure 1b is a cross-sectional view illustrating a circuit board according to a comparative example.

[0048] Fig. 2 is a plan view showing the layout structure of the first circuit layer illustrated in Fig. 1a.

[0049] Figure 3 is a plan view showing the recess and through hole of the first protective layer illustrated in Figure 1a.

[0050] FIG. 4 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the first embodiment.

[0051] FIG. 5 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the second embodiment.

[0052] FIG. 6 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the third embodiment.

[0053] FIG. 7 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the fourth embodiment.

[0054] FIGS. 8a and 8b are cross-sectional views showing detailed structures of a bump portion according to another embodiment.

[0055] Fig. 9 is a cross-sectional view showing a detailed structure of a bump portion according to another embodiment.

[0056] Fig. 10 is a cross-sectional view showing a circuit board according to the second embodiment.

[0057] Fig. 11 is a cross-sectional view showing a circuit board according to the third embodiment.

[0058] Fig. 12 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0059] Fig. 13 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0060] Figures 14a to 14f are cross-sectional views showing a method for manufacturing a circuit board according to one embodiment in process order.

[0061] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0062] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0063] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0064] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0065] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0066] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0067] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0068] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0069]

[0070] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0071]

[0072] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0073] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bump portion for electrically connecting the semiconductor element to the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0074] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0075] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0076]

[0077] FIG. 1A is a cross-sectional view showing a circuit board according to an embodiment, FIG. 1B is a cross-sectional view showing a circuit board according to a comparative example, FIG. 2 is a plan view showing the arrangement structure of the first circuit layer shown in FIG. 1A, FIG. 3 is a plan view showing a recess and a through hole of the first protective layer shown in FIG. 1A, FIG. 4 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the first embodiment, FIG. 5 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the second embodiment, FIG. 6 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the third embodiment, FIG. 7 is a cross-sectional view showing a recess and a through hole of the first protective layer of FIG. 3 according to the fourth embodiment, FIGS. 8A and 8B are cross-sectional views showing a detailed structure of a bump portion according to another embodiment, and FIG. 9 is a cross-sectional view showing a detailed structure of a bump portion according to yet another embodiment. Fig. 10 is a cross-sectional view showing a circuit board according to a second embodiment, Fig. 11 is a cross-sectional view showing a circuit board according to a third embodiment, Fig. 12 is a cross-sectional view showing a semiconductor package according to the first embodiment, and Fig. 13 is a cross-sectional view showing a semiconductor package according to the second embodiment. Hereinafter, a schematic structure of a circuit board according to an embodiment will be described with reference to the drawings.

[0078]

[0079] Referring to FIG. 1A, the circuit board (100) includes a build-up layer (101, 102, 103), a first protective layer (104) disposed on one surface of the build-up layer (101, 102, 103), and a second protective layer (105) disposed on the other surface of the build-up layer (101, 102, 103). The build-up layers (101, 102, 103) may have a structure laminated along a vertical direction. Preferably, the build-up layers (101, 102, 103) may include a plurality of insulating layers and a plurality of circuit layers laminated along a vertical direction on one surface and therebetween. Here, the one surface may mean the upper surface of the build-up layer (101, 102, 103), and the other surface may mean the lower surface of the build-up layer (101, 102, 103). In this case, the upper surface of the build-up layer (101, 102, 103) may refer to the upper surface of the insulating layer positioned at the uppermost position among the plurality of insulating layers. In addition, the lower surface of the build-up layer (101, 102, 103) may refer to the lower surface of the insulating layer positioned at the lowest position among the plurality of insulating layers.

[0080] The build-up layers (101, 102, 103) include a core layer (101), an upper build-up layer (102), and a lower build-up layer (103). The upper build-up layer (102) may be disposed on one side of the core layer (101), and the lower build-up layer (103) may be disposed on the other side of the core layer (101), but is not limited thereto. Here, the meaning of being disposed on one side and the other side is not to be understood as being limited to a configuration in direct contact with the one side and the other side, but should also be understood as having other configurations between the one side and the upper build-up layer (102), and between the other side and the lower build-up layer (103).

[0081] The core layer (101) may include a core insulating layer (141). The core insulating layer (141) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0082] As the number of terminals of semiconductor devices arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the thickness of the upper and lower build-up layers (102, 103) is increasing. Accordingly, the core insulating layer (141) of the core layer (101) of the present embodiment may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board (100) and prevent excessive signal loss. A via hole penetrating one surface and the other surface may be formed in the core insulating layer (141).

[0083] The via hole of the core insulating layer (141) can be formed using a mechanical drilling process or a CO2 laser, etc. When the via hole of the core insulating layer (141) is formed using a mechanical drill, the slope of the inner wall of the via hole can be perpendicular to one surface and / or the other surface of the core insulating layer (141), and when the via hole of the core insulating layer (141) is formed using a CO2 laser, the inner wall of the via hole can have a plurality of concave portions and / or convex portions that are alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the core insulating layer (141), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the core insulating layer (141).

[0084] And, the concave and convex portions may be alternately provided along the vertical direction of the inner wall forming the via hole of the core insulating layer (141). Here, being alternately provided may mean that the convex portion is provided between a plurality of concave portions, and that the concave portion is provided between a plurality of convex portions. In the case of a via hole formed using a mechanical drilling process, the path for transmitting an electrical signal may be shortened, which may be advantageous for electrical characteristics, but the process cost may increase. In addition, in the case of forming the concave and convex portions on the inner wall of the via hole using a CO2 laser, the thickness of the core via electrode (142) provided on the inner wall of the via hole can be thickened in a subsequent process, which may have the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the core layer (101) may be freely and selectively used depending on the application field of the semiconductor package.

[0085] A core via electrode (142) may be placed within the via hole of the core insulating layer (141). The core via electrode (142) functions to electrically connect the upper build-up layer (102) and the lower build-up layer (103). Therefore, it is desirable for the core via electrode (142) to densely fill the via hole for resistance or heat dissipation. However, when the thickness of the core insulating layer (141) becomes thick as described above, it may become difficult for the core via electrode (142) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core insulating layer (141) as described above according to the plating process, a void may occur within the core via electrode (142). The void expands due to heat generated during the operation of the semiconductor package, which may deteriorate the mechanical reliability of the circuit board.

[0086] Accordingly, a core via electrode (142) having a predetermined thickness is arranged on the inner wall of the via hole of the core insulating layer (141). The thickness of the core via electrode (142) refers to the thickness in the horizontal direction perpendicular thereto, not the thickness in the vertical direction in which the upper build-up layer (102), the core insulating layer (141), and the lower build-up layer (103) are laminated. The thickness of the core via electrode (142) may be arranged to have a thickness of 5 μm to 20 μm in order to prevent a voltage drop that occurs as the thickness of the core insulating layer (141) increases and to prevent the occurrence of voids. The inner side of the core via electrode (142) is difficult to densely fill with metal through a process such as plating, resulting in the formation of empty spaces. The empty spaces may cause problems in that it is difficult to evenly arrange the upper build-up layer (102) when laminating the upper build-up layer (102).

[0087] The insulating member (143) may be arranged on the inner side of the core via electrode (142), thereby ensuring the flatness of the core layer (101). For example, the insulating member (143) may be arranged in the via hole of the core insulating layer (141), and the core via electrode (142) may surround the side of the insulating member (143) and be arranged between the inner wall of the via hole and the outer surface of the insulating member (143). The upper surface of the insulating member (143) may be on the same plane as the upper surface of the core insulating layer (141), or may be arranged closer to the upper build-up layer (102) in the vertical direction than the upper surface of the core insulating layer (141). The lower surface of the insulating member (143) may be on the same plane as the lower surface of the core insulating layer (141), or may be arranged closer to the lower build-up layer (103) in the vertical direction than the lower surface of the core insulating layer (141). This can be freely designed to solve the flatness during lamination of the upper build-up layer (102) and the lower build-up layer (103), or to secure the flatness of the sixth circuit layer (116) and / or the seventh circuit layer (122) to be described later.

[0088] An upper build-up layer (102) is arranged on one side of the core layer (101). The upper build-up layer (102) includes a plurality of insulating layers (106, 107, 108, 109, 110) and a plurality of circuit layers (116, 117, 118, 119, 120, 121).

[0089] The plurality of circuit layers (116, 117, 118, 119, 120, 121) of the upper build-up layer (102) may include a first circuit layer (116) that is farthest from the core layer (101) in the vertical direction, a second circuit layer (117) that is closer to the core layer (101) in the vertical direction than the first circuit layer (116), a third circuit layer (118) that is closer to the core layer (101) in the vertical direction than the second circuit layer (117), a fourth circuit layer (119) that is closer to the core layer (101) in the vertical direction than the third circuit layer (118), a fifth circuit layer (120) that is closer to the core layer (101) in the vertical direction than the fourth circuit layer (119), and a sixth circuit layer (121) that is closer to the core layer (101) in the vertical direction than the fifth circuit layer (120). Here, the first circuit layer (116) refers to the circuit layer positioned at the uppermost side, farthest from the core layer (101), among the circuit layers provided in the upper build-up layer (102), and accordingly, the first circuit layer (116) may also be referred to as the upper circuit layer.

[0090] The first to sixth circuit layers (116, 117, 118, 119, 120, 121) may function to electrically connect with semiconductor elements arranged on a circuit board (100). Each of the first to sixth circuit layers (116, 117, 118, 119, 120, 121) may be freely designed in consideration of impedance. In addition, via electrodes (131, 132, 133, 134, 135) may be arranged to connect each of the first to sixth circuit layers (116, 117, 118, 119, 120, 121). For example, a first via electrode (131) is disposed between a first circuit layer (116) and a second circuit layer (117), a second via electrode (132) is disposed between a second circuit layer (117) and a third circuit layer (118), a third via electrode (133) is disposed between a third circuit layer (118) and a fourth circuit layer (119), a fourth via electrode (134) is disposed between a fourth circuit layer (119) and a fifth circuit layer (120), and a fifth via electrode (135) is disposed between a fifth circuit layer (120) and a sixth circuit layer (121), thereby electrically connecting the first to sixth circuit layers (116, 117, 118, 119, 120, 121).

[0091] The first to fifth via electrodes (131, 132, 133, 134, 135) can be formed simultaneously in the process of arranging the first to fifth circuit layers (116, 117, 118, 119, 120). For example, in the process of arranging the fifth circuit layer (120) on the sixth circuit layer (121), a through hole can be formed in the fifth insulating layer (110) to expose a portion of the sixth circuit layer (121), and through this, the fifth circuit layer (120) can be arranged together with the fifth via electrode (135) filling the through hole of the fifth insulating layer (110). Therefore, the fifth via electrode (135) can be distinguished as a protrusion of the fifth circuit layer (120). Likewise, each of the first to fourth via electrodes (131, 132, 133, 134) is separated by a protrusion of the first to fourth circuit layers (116, 117, 118, 119) and can be connected to another circuit layer disposed below each circuit layer.

[0092] The first circuit layer (116) may be arranged adjacent to the first protective layer (104). The first circuit layer (116) may include a plurality of circuit patterns. The plurality of circuit patterns of the first circuit layer (116) may include a pad portion (116a), a bump portion (116b), and a wiring portion (116c) depending on the arrangement position, function, size, and / or shape.

[0093] The pad portion (116a) may have a horizontal width that is relatively larger than the horizontal widths of the bump portion (116b) and the wiring portion (116c). Alternatively, the pad portion (116a) may be positioned closer to the outer surface of the upper build-up layer (102) than the bump portion (116b). Alternatively, the pad portion (116a) may be a bonding portion connected to a terminal of a semiconductor element and / or an external substrate. However, the pad portion (116a) may be a bonding portion connected to a terminal of a semiconductor element and / or an external substrate with a size that is relatively larger than the size of the terminal of the semiconductor element and / or the external substrate connected to the bump portion (116b). Furthermore, the pad portion (116a) may mean a circuit layer that vertically overlaps with a through hole (104a) provided in the first protective layer (104) among the first circuit layers (116).

[0094] The bump portion (116b) may have a horizontal width that is relatively smaller than the horizontal width of the pad portion (116a). Alternatively, the pad portion (116a) may be positioned further apart from the outer surface of the upper build-up layer (102) than the bump portion (116b). Alternatively, the bump portion (116b) may be a bonding portion connected to a terminal of a semiconductor element and / or an external substrate. However, the bump portion (116b) may be a bonding portion connected to a terminal of a semiconductor element and / or an external substrate that is relatively smaller in size than the size of the terminal of the semiconductor element and / or the external substrate connected to the pad portion (116a). Furthermore, the bump portion (116b) may refer to a circuit layer that overlaps vertically and / or horizontally with a recess (104b) provided in the first protective layer (104).

[0095] The vertical thickness of the bump portion (116b) may be different from the vertical thickness of the pad portion (116a). For example, the vertical thickness of the bump portion (116b) may be greater than the vertical thickness of the pad portion (116a). The bump portion (116b) may refer to an electrode on which a bonding member, such as solder, is disposed for bonding with a semiconductor element. The bump portion (116b) may refer to an electrode protruding onto the bottom surface of a recess (104b) provided in the first protective layer (104) for bonding with a semiconductor element. To this end, the bump portion (116b) may include a first portion (116b1) corresponding to the pad portion (116a), and a second portion (116b2) disposed on the first portion (116b1). The second portion (116b2) of the bump portion (116b) can protrude above the first portion (116b1), thereby enabling the semiconductor element to be stably placed on the bump portion (116b), and further enabling the semiconductor element to operate stably.

[0096] That is, as the functions provided by semiconductor devices increase and the performance of semiconductor devices improves, the number of I / O terminals provided in semiconductor devices also increases. Accordingly, as the width and / or pitch of the I / O terminals provided in the semiconductor devices become finer, an electrical short circuit may occur when a plurality of bonding members come into contact with each other in the process of connecting the I / O terminals of the semiconductor devices using bonding members such as solder. Therefore, in order to reduce the amount of bonding members such as solder used as the terminal density of the semiconductor device increases, the first circuit layer (116) may be provided with a bump portion (116b) protruding from the bottom surface of the recess (104b) of the first protective layer (104). For example, in the embodiment, a bonding member such as solder is applied to the upper surface of the bump portion (116b) and then a fine bonding process such as thermal compression bonding (hereinafter referred to as 'TC bonding') may be performed. And when a micro bonding process is performed, in order to improve the alignment between the terminal of the semiconductor element and the bump portion (116b), the bump portion (116b) may be provided to protrude above the bottom surface of the recess (104b) of the first protective layer (104).

[0097] To this end, the bump portion (116b) may include a first portion (116b1) disposed on the upper build-up layer (102), and a second portion (116b2) disposed on the first portion (116b1). The first portion (116b1) of the bump portion (116b) may be a portion corresponding to the pad portion (116a) and / or the wiring portion (116c), and the second portion (116b2) of the bump portion (116b) may be a protrusion additionally disposed on the first portion (116b1). At this time, the first portion (116b1) and the second portion (116b2) may have different widths in the horizontal direction, and preferably, the horizontal width of the second portion (116b2) disposed relatively higher may be smaller than the horizontal width of the first portion (116b1). Accordingly, the embodiment provides a bump portion (116b) including a second portion (116b2) having a relatively small horizontal width, so that the pitch between a plurality of adjacent bumps can be refined, or the spacing between a plurality of bumps can be increased, thereby improving the circuit integration density or solving the circuit short problem where adjacent solders come into contact with each other.

[0098] The wiring portion (116c) can electrically connect between a plurality of pad portions (116a) and / or a plurality of bump portions (116b). The wiring portion (116c) may be a circuit line connecting between a plurality of pad portions (116a) and / or bump portions (116b). For example, the wiring portion (116c) may be a signal transmission line and may be referred to as a trace.

[0099] The sixth circuit layer (121) may be in contact with one surface of the core layer (101). In this case, a part of the sixth circuit layer (121) may be arranged to cover the above-described insulating member (142). That is, the lower surface of the sixth circuit layer (121) may include a first portion in contact with the upper surface of the core via electrode (141), a second portion in contact with the upper surface of the insulating member (142), and a third portion in contact with the upper surface of the core layer (101).

[0100] The plurality of insulating layers (106, 107, 108, 109, 110) of the upper build-up layer (102) may include a first insulating layer (106) that is furthest from the core layer (101) in a vertical direction, a second insulating layer (107) that is closer to the core layer (101) in a vertical direction than the first insulating layer (106), a third insulating layer (108) that is closer to the core layer (101) in a vertical direction than the second insulating layer (107), a fourth insulating layer (109) that is closer to the core layer (101) in a vertical direction than the third insulating layer (108), and a fifth insulating layer (110) that is closer to the core layer (101) in a vertical direction than the fourth insulating layer (109).

[0101] The first to fifth insulating layers (106, 107, 108, 109, 110) are arranged to vertically insulate the first to sixth circuit layers (116, 117, 118, 119, 120, 121) described above. For example, the first to sixth insulating layers (106, 107, 108, 109, 110) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Image-able Dielectric, PID) for forming a fine pattern may be used.

[0102] The first protective layer (104) may be disposed on the upper build-up layer (102). The first protective layer (104) may protect the first circuit layer (116) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (100) using a material such as solder, the first protective layer (104) functions to prevent short circuits between solders due to its low wettability with the solder. The first protective layer (104) may be formed using a photocurable insulating material, and for example, a solder resist may be used.

[0103] The first protective layer (104) may expose a bonding portion where a bonding member, such as solder, is disposed for bonding with a semiconductor element and / or an external substrate among the first circuit layers (116). For example, the first protective layer (104) may have a through hole (104a). The through hole (104a) may penetrate the first protective layer (104) from the upper surface of the first protective layer (104) toward the lower surface of the first protective layer (104). At this time, the through hole (104a) may overlap with the pad portion (116a) in a vertical direction. For example, the through hole (104a) may be provided in a region that vertically overlaps with the pad portion (116a) among the entire region of the first protective layer (104). Accordingly, the lower surface of the first protective layer (104) in the vertically overlapping area may be a portion that contacts the upper surface of the pad portion (116a), and at least a portion of the upper surface of the pad portion (116a) may be exposed to the outside of the circuit board through the through hole (104a) provided in the first protective layer (104).

[0104] The first protective layer (104) may further include a recess (104b) having a depth in the vertical direction different from the depth in the vertical direction of the through hole (104a). The recess (104b) may be provided in an area of ​​the first circuit layer (116) where the bump portion (116b) is arranged. The recess (104b) may be provided so as to cover at least a portion of the side surface of the bump portion (116b) while exposing the remaining portion of the side surface and the upper surface of the bump portion (116b). Through this, the first protective layer (104) stably supports the bump portion (116b) using the recess (104b) so that the height of the bump portion (116b) can be secured, thereby allowing the semiconductor element to be more stably arranged on the bump portion (116b).

[0105] The vertical depth of the recess (104b) of the first protective layer (104) may be greater than the vertical depth of the through hole (104a) of the first protective layer (104). Accordingly, the vertical length of the side wall of the recess (104b) of the first protective layer (104) may be less than the vertical length of the side wall of the through hole (104a). Alternatively, the bottom surface of the recess (104b) of the first protective layer (104) may be positioned higher than the upper surface of the pad portion (116a). Accordingly, the first protective layer (104) may entirely cover the upper surface and the side surface of the first portion (116b1) of the bump portion (116b), and may cover a portion of the side surface of the second portion (116b2) of the bump portion (116b).

[0106] At this time, the comparative example had a limit in the size of the through hole (104a) that could be formed in the first protective layer (104). Referring to FIG. 1b, the circuit board of the comparative example includes a build-up layer (10), an upper circuit layer (20), a protective layer (30), and a bump portion (50), and the protective layer (30) has a through hole (40). At this time, the protective layer (30) has a limit in reducing the size of the through hole (40) due to the limit in the resolution of the exposure and development process. Accordingly, in the comparative example, it was difficult to implement a fine pitch between a plurality of bonding portions and / or pad portions due to the limit in reducing the size of the through hole (40) formed in the protective layer (30). Furthermore, the comparative example implements a fine pitch by arranging a protruding electrode (50) such as a metal pillar on the pad portion, but the above-described metal pillar has a structure in which it is arranged within the through hole (40) of the protective layer (30) without being in contact with the protective layer (30). As a result, the protruding electrode (50) is not stably supported, which limits the height that the protruding electrode (50) can have, and furthermore, a reliability problem in which a crack occurs in the protruding electrode (50) during the process of forming the through hole (40) in the protective layer (30) may occur. In addition, since the interface between the upper circuit layer (20) and the protruding electrode (50) has a structure in which it is not covered by the protective layer (30), there may be a problem in which physical and / or electrical reliability is lowered. For example, a bonding member such as solder may be arranged on the protruding electrode (50), and an intermetallic compound (IMC) may be formed upon contact between the bonding member and the protruding electrode (50). At this time, the intermetallic compound may penetrate between the upper circuit layer (20) and the protruding electrode (50), thereby reducing the adhesion between the upper circuit layer (20) and the protruding electrode or acting as a factor that reduces the electrical characteristics.

[0107] The embodiment provides a bump portion (116b) having a vertical thickness greater than the vertical thickness of the pad portion (116a), and overlaps the bump portion (116b) with a recess (104b) provided in the first protective layer (104) in the vertical direction and / or the horizontal direction so that the bump portion (116b) can be stably supported and / or protected by the first protective layer (104). Accordingly, the embodiment can increase the height of the bump portion (116b) (preferably, the thickness of the second portion of the bump portion) compared to the comparative example, thereby securing a stand-off so that a semiconductor element can be stably placed on the upper build-up layer (102).

[0108] The bottom surface of the recess (104b) of the first protective layer (104) may be positioned higher than the first portion (116b1) of the bump portion (116b). Accordingly, the interface between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) may be positioned lower than the recess (104b) of the first protective layer (104). That is, the interface between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) may be covered by the first protective layer (104). Through this, the embodiment can prevent cracks from occurring at the interface between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) or intermetallic compounds from penetrating, thereby further improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0109] The recess (104b) of the first protective layer (104) may be spaced apart from the through hole (104a) of the first protective layer (104) in the horizontal direction. For example, the first protective layer (104) may have a plurality of through holes (104a) spaced apart from each other in the horizontal direction, and each of the plurality of through holes (104a) may be spaced apart from the recess (104b) without being connected to each other. Through this, the mechanical reliability and / or electrical reliability that may occur when the through hole (104a) of the first protective layer (104) and the recess (104b) of the first protective layer (104) are connected to each other can be improved. For example, the electrical reliability problem, such as a circuit short due to the flow of a joining material such as solder that may occur when the through hole (104a) of the protective layer (104) and the recess (104b) of the protective layer (104) are connected can be solved. In addition, for example, when the through hole (104a) of the first protective layer (104) and the recess (104b) of the protective layer (104) are connected, the volume of the first protective layer (104) may be significantly lower than the volume of the second protective layer (105), and the circuit board may be significantly warped in a specific direction due to the volume difference between the first protective layer (104) and the second protective layer (105) described above. Therefore, the embodiment can prevent the circuit board from being significantly warped in a specific direction by preventing the through hole (104a) and the recess (104b) from being connected to each other, and thereby further improve the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package.

[0110] The recess (104b) of the first protective layer (104) may be provided to surround a plurality of bump portions (116b), and a plurality of through holes (104a) of the first protective layer (104) may be arranged along the periphery of the recess (104b).

[0111] A lower build-up layer (103) is arranged on the other side of the core layer (101). The lower build-up layer (103) includes a plurality of insulating layers (111, 112, 113, 114, 115), a plurality of circuit layers (122, 123, 124, 125, 126, 127), and a second protective layer (127).

[0112] The plurality of circuit layers (122, 123, 124, 125, 126, 127) of the lower build-up layer (103) may include a seventh circuit layer (122) that is most adjacent to the core layer (101) in the vertical direction, an eighth circuit layer (123) arranged under the seventh circuit layer (116), a ninth circuit layer (124) arranged under the eighth circuit layer (123), a tenth circuit layer (125) arranged under the ninth circuit layer, an eleventh circuit layer (126) arranged under the tenth circuit layer (125), and a twelfth circuit layer (127) arranged under the eleventh circuit layer (126). The seventh to twelfth circuit layers (122, 123, 124, 125, 126, 127) may electrically connect a main board (not shown) of an electronic device and semiconductor elements arranged on a circuit board (100). Each of the seventh to twelfth circuit layers (122, 123, 124, 125, 126, 127) may be freely designed in consideration of impedance.

[0113] Additionally, via electrodes (136, 137, 138, 139, 140) may be arranged to connect each of the seventh to twelfth circuit layers (122, 123, 124, 125, 126, 127). The sixth via electrode (136) is disposed between the seventh circuit layer (122) and the eighth circuit layer (123), the seventh via electrode (137) is disposed between the eighth circuit layer (123) and the ninth circuit layer (124), the eighth via electrode (138) is disposed between the ninth circuit layer (124) and the tenth circuit layer (125), the ninth via electrode (139) is disposed between the tenth circuit layer (125) and the eleventh circuit layer (126), and the tenth via electrode (140) is disposed between the eleventh circuit layer (126) and the twelfth circuit layer (127), thereby electrically connecting the seventh to twelfth circuit layers (122, 123, 124, 125, 126, 127).

[0114] As described above with respect to the first to fifth via electrodes (131, 132, 133, 134, 135) of the upper build-up layer (102), the arrangement of the sixth to tenth via electrodes (136, 137, 138, 139, 140) can also be performed simultaneously with the process of arranging the eighth to twelfth circuit layers (123, 124, 125, 126, 127). Therefore, as described above, the seventh via electrode (137) can be distinguished as a protrusion of the ninth circuit layer (124). However, since the 8th to 12th circuit layers (123, 124, 125, 126, 127) are laminated in a different direction from the upper build-up layer (102), the inclination direction of each via electrode (131, 132, 133, 134, 135) of the upper build-up layer (102) may have a direction opposite to the inclination direction of each via electrode (136, 137, 138, 139, 140) of the lower build-up layer (103). For example, each via electrode (131, 132, 133, 134, 135) of the upper build-up layer (102) may have a slope that becomes narrower toward the core layer (101), and each via electrode (136, 137, 138, 139, 140) of the lower build-up layer (103) may also have a slope that becomes narrower toward the core layer (101). For example, the slope of each via electrode (131, 132, 133, 134, 135) of the upper build-up layer (102) may be symmetrical with respect to the slope of each via electrode (136, 137, 138, 139, 140) of the lower build-up layer (103) with respect to the core layer (101).

[0115] The seventh circuit layer (122) may be in contact with the other surface of the core layer (101). In this case, a part of the seventh circuit layer (122) may be arranged to cover the above-described insulating member (142). That is, the lower surface of the seventh circuit layer (122) may include a first portion in contact with the lower surface of the core via electrode (141), a second portion in contact with the lower surface of the insulating member (142), and a third portion in contact with the lower surface of the core layer (101).

[0116] The plurality of insulating layers (111, 112, 113, 114, 115) of the lower build-up layer (103) may include a sixth insulating layer (111) that is most adjacent to the core layer (101) in the vertical direction, a seventh insulating layer (112) arranged under the sixth insulating layer (111), an eighth insulating layer (113) arranged under the seventh insulating layer (112), a ninth insulating layer (114) arranged under the eighth insulating layer (113), and a tenth insulating layer (115) arranged under the ninth insulating layer (114). The 6th to 10th insulating layers (111, 112, 113, 114, 115) are arranged to vertically insulate the 7th to 12th circuit layers (122, 123, 124, 125, 126, 127) described above. In addition, as an example, the 6th to 10th insulating layers (111, 112, 113, 114, 115) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0117] The second protective layer (105) can protect the 12th circuit layer (127) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the second protective layer (105) functions to prevent short circuits between solders due to its low wettability with the solder. The second protective layer (105) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0118] In addition, each via electrode (131, 132, 133, 134, 135, 136, 137, 138, 139, 140) of the upper build-up layer (102) and the lower build-up layer (103) may have a structure in which at least a portion thereof overlaps with each other along the vertical direction. Through this, problems of voltage drop and / or signal loss can be solved, and the degree of freedom for wiring design can be increased. However, when a load is applied to each vertically overlapping via electrode (131, 132, 133, 134, 135, 136, 137, 138, 139, 140) by the load applied to the circuit board (100) when a semiconductor element is mounted on the circuit board (100), there may be a problem that a crack occurs at the interface between each via electrode (131, 132, 133, 134, 135, 136, 137, 138, 139, 140) and each circuit layer (116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127), and for this, in one example, as described above, The bump portion (116b) may have a structure that does not vertically overlap with each via electrode (131, 132, 133, 134, 135, 136, 137, 138, 139, 140).

[0119] Below, the detailed arrangement structure of the first circuit layer (116) of the embodiment and the arrangement relationship between the through hole (104a) and the recess (104b) of the first circuit layer (116) and the first protective layer (104) are specifically described.

[0120] Referring to FIG. 2, a first circuit layer (116) may be arranged on the upper build-up layer (102). The first circuit layer (116) may include a pad portion (116a), a bump portion (116b), and a wiring portion (116c). The pad portion (116a) may be arranged around the bump portion (116b). For example, the pad portion (116a) may be arranged closer to the outer surface of the upper build-up layer (102) than the bump portion (116b). At this time, the horizontal width of the pad portion (116a) may be greater than the horizontal width of the bump portion (116b). That is, a pad portion (116a) having a relatively large horizontal width can be placed adjacent to the outer surface of the upper build-up layer (102), thereby ensuring rigidity around the upper surface of the upper build-up layer (102), thereby preventing the circuit board from being significantly bent in a specific direction.

[0121] The bump portion (116b) may have a relatively fine width or a fine pitch compared to the pad portion (116a). The bump portion (116b) may be connected to a terminal of a semiconductor element having a relatively small line width and / or pitch, and the pad portion (116a) may be connected to a terminal of a semiconductor element having a relatively large line width and / or pitch and / or a pad of an external substrate. For example, the pad portion (116a) may be used as a power supply wire that supplies power to the semiconductor element and / or the connecting member, and the bump portion (116b) may be used as a signal wire that exchanges communication signals other than power signals with the semiconductor element and / or the connecting member. At this time, a plurality of pad portions (116a) can be arranged along the periphery of the bump portion (116b) at a position spaced apart from the bump portion (116b), thereby enabling stable power supply without interfering with the communication signal transmitted through the pad portion (116a) by the power signal transmitted through the pad portion (116a).

[0122] In addition, the pad portion (116a) can have a shield function that prevents interference signals such as external noise from being transmitted to the bump portion (116b), thereby minimizing loss of communication signals transmitted through the bump portion (116b) and improving communication characteristics, thereby further improving the operational reliability of the circuit board and semiconductor package.

[0123] At this time, the pad portion (116a) is depicted in the drawing as being arranged on one side of the bump portion (116b) and the other side opposite to the one side, but is not limited thereto. For example, from a planar viewpoint of the upper build-up layer (102), the pad portion (116a) may be provided on each of the left, right, upper, and lower sides of the bump portion (116b).

[0124] The first circuit layer (116) further includes a wiring portion (116c). The wiring portion (116c) may overlap the bump portion (116b) and the pad portion (116a) in a horizontal direction. The wiring portion (116c) may electrically connect between the bump portion (116b) and / or the pad portion (116a). For example, as shown in FIG. 2, the wiring portion (116c) may electrically connect between a plurality of bump portions (116b). However, the embodiment is not limited thereto, and the wiring portion (116c) may electrically connect between a plurality of pad portions (116a), or may electrically connect between the pad portions (116a) and the bump portion (116b).

[0125] Below, various embodiments of the through hole (104a) and recess (104b) of the first protective layer (104) are described.

[0126] According to the embodiments of FIGS. 3 and 4, the first protective layer (104) can be placed on the upper build-up layer (102).

[0127] The first protective layer (104) may have a through hole (104a). The through hole (104a) may overlap with the pad portion (116a) of the first circuit layer (116) of the upper build-up layer (102) in the vertical direction. At this time, the through hole (104a) may overlap with a portion of the upper surface of the pad portion (116a) in the vertical direction. However, the embodiment is not limited thereto, and the through hole (104a) may overlap with the entire upper surface of the pad portion (116a) in the vertical direction. Hereinafter, it will be described that the through hole (104a) overlaps with a portion of the upper surface of the pad portion (116a) in the vertical direction. For example, the horizontal width of the through hole (104a) may be smaller than the horizontal width of the pad portion (116a). Through this, at least a portion of the upper surface of the pad portion (116a) can be covered with the first protective layer (104), and the remaining portion can be exposed to the outside of the circuit board by overlapping with the through hole (104a) in a direction perpendicular to the through hole (104a). For example, the upper surface of the pad portion (116a) can include a first upper surface portion (116a1) that overlaps with the through hole (104a) of the first protective layer (104) in a direction perpendicular to the through hole (104a), and a second upper surface portion (116a2) that is positioned closer to the outer surface of the pad portion (116a) than the first upper surface portion (116a1) and is covered with the first protective layer (104).

[0128] The through holes (104a) may be provided in multiple numbers. For example, the upper build-up layer (102) may be provided with multiple pad portions (116a) spaced apart in the horizontal direction, and the through holes (104a) of the first protective layer (104) may be provided in multiple numbers so as to overlap each of the multiple pad portions (116a) in the vertical direction.

[0129] A recess (104b) may be provided on the inside of a plurality of through holes (104a). For example, a plurality of through holes (104a) may be arranged along a peripheral area of ​​the recess (104b). The recess (104b) may cover at least a portion of the bump portion (116b) while exposing at least a remaining portion of the bump portion (116b). For example, the recess (104b) may be a concave portion that is positioned lower than the upper surface of the first protective layer (104) and higher than the lower surface of the first protective layer (104). The recess (104b) may be provided in an area where a plurality of bump portions (116b) are arranged. For example, the recess (104b) may be provided to surround the plurality of bump portions (116b). That is, the recess (104b) may be provided around the plurality of bump portions (116b). Additionally, the recesses (104b) provided around the plurality of bump portions (116b) can be connected to each other.

[0130] At this time, the bottom surface (104b1) of the recess (104b) may have a certain height. For example, the bottom surface (104b1) of the recess (104b) may be positioned lower than the upper surface of the first protective layer (104) and higher than the lower surface of the first protective layer (104).

[0131] In addition, the bottom surface (104b1) of the recess (104b) may be positioned lower than the upper surface of the bump portion (116b). Accordingly, at least a portion of the bump portion (116b) may overlap with the recess (104b) in the horizontal direction. Accordingly, the upper surface of the bump portion (116b) may not be covered with the first protective layer (104) and may be exposed to the outside. In addition, at least a portion of the side surface of the bump portion (116b) may overlap with the recess (104b) in the horizontal direction, and thus may not be covered with the first protective layer (104) and may be exposed to the outside. At this time, at least a portion of the side surface of the bump portion (116b) that overlaps with the recess (104b) in the horizontal direction may not be covered with the first protective layer (104) and may be exposed to the outside. And, among the entire area of ​​the bump portion (116b), the area that overlaps the recess (104b) in the horizontal direction can be used as a bonding portion where a bonding member such as solder is placed.

[0132] In addition, the bottom surface (104b1) of the recess (104b) may be positioned on a different plane from the bottom surface of the through hole (104a). At this time, the through hole (104a) overlaps the top surface of the pad portion (116a) in the vertical direction, and accordingly, the bottom surface of the through hole (104a) may mean the top surface of the pad portion (116a). The depth of the through hole (104a) in the vertical direction may be different from the depth of the recess (104b) in the vertical direction. The depth of the through hole (104a) in the vertical direction may be greater than the depth of the recess (104b) in the vertical direction. The bottom surface (104b1) of the recess (104b) may be positioned higher than the bottom surface of the through hole (104a). That is, the bottom surface (104b1) of the recess (104b) may be positioned higher than the top surface of the pad portion (116a).

[0133] At this time, the vertical thickness (H1) of the pad portion (116a) may be smaller than the vertical thickness (H2) of the bump portion (116b). For example, the bump portion (116b) may include a first portion (116b1) and a second portion (116b2). The first portion (116b1) of the bump portion (116b) may correspond to the pad portion (116a). Here, correspondence may mean that the first portion (116b1) of the bump portion (116b) is formed together with the pad portion (116a) when manufacturing the pad portion (116a). Therefore, the vertical thickness (H1) of the pad portion (116a) may be equal to the vertical thickness (H2) of the first portion (116b1) of the bump portion (116b). In addition, the vertical thickness (H2) of the bump portion (116b) may be greater than the vertical thickness (H1) of the pad portion (116a) by the thickness (H3) of the second portion (116b2). Accordingly, the bottom surface (104b1) of the recess (104b) may be positioned higher than the first portion (116b1) of the bump portion (116b), and thus, the upper surface and side surfaces of the first portion (116b1) may be entirely covered by the first protective layer (104). In addition, since the bottom surface (104b1) of the recess (104b) is positioned higher than the upper surface of the first portion (116b1), at least a portion of the side surfaces of the second portion (116b2) may be covered by the first protective layer (104). For example, the bottom surface (104b1) of the recess (104b) may be located between the upper surface of the second part (116b2) of the bump part (116b) and the lower surface of the second part (116b2).

[0134] Through this, the bump portion (116b) having a vertical thickness (H2) greater than the vertical thickness (H1) of the pad portion (116a) is provided, and the bump portion (116b) overlaps with the recess (104b) provided in the first protective layer (104) in the vertical direction and / or the horizontal direction so that the bump portion (116b) can be stably supported and / or protected by the first protective layer (104). Therefore, the embodiment can increase the height of the bump portion (116b) (preferably, the thickness of the second portion of the bump portion) compared to the comparative example, and thereby secure a stand-off so that the semiconductor element can be stably placed on the upper build-up layer (102). Therefore, the mounting of the semiconductor element can be enabled by using the second portion (116b2) of the bump portion (116b) having a relatively small width in the horizontal direction. In addition, the gap between adjacent second portions (116b2) may be greater than the gap between adjacent first portions (116b1), thereby solving the problem of a circuit short circuit in which bonding members such as solder are electrically connected to each other. Furthermore, the bottom surface of the recess (104b) of the first protective layer (104) may be positioned higher than the top surface of the wiring portion (116c) arranged in the area where the recess (104b) is provided, thereby covering the wiring portion (116c) entirely. Through this, the wiring portion (116c) may be stably protected while supporting the bump portion (116b).

[0135] In addition, the bottom surface of the recess (104b) of the first protective layer (104) may be positioned higher than the first portion (116b1) of the bump portion (116b). Accordingly, the interface between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) may be positioned lower than the recess (104b) of the first protective layer (104). That is, the interface between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) may be covered by the first protective layer (104). Through this, the embodiment can prevent cracks from occurring at the interface between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) or intermetallic compounds from penetrating, thereby further improving the mechanical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0136] In addition, the side surface of the second portion (116b2) of the bump portion (116b) may include a buried portion covered with the first protective layer (104), and an exposed portion disposed on the buried portion and exposed to the outside. That is, the exposed portion of the second portion (116b2) may overlap with the recess (104b) in the horizontal direction. In this case, the thickness of the buried portion and the thickness of the exposed portion of the second portion (116b2) of the bump portion (116b) may be different from each other. For example, the thickness of the exposed portion of the second portion (116b2) of the bump portion (116b) may be greater than the thickness of the buried portion. That is, the thickness (H31) of the exposed portion may range from 120% to 600% of the thickness (H32) of the buried portion. If the thickness (H31) of the exposed portion is less than 120% of the thickness (H32) of the buried portion, it may be difficult to secure a sufficient contact area with the bonding member, and as a result, the bonding force with the bonding member may be reduced, making it difficult to stably mount the semiconductor element. If the thickness (H31) of the exposed portion is more than 600% of the thickness (H32) of the buried portion, the thickness of the exposed portion may be excessively larger than the thickness of the buried portion supported by the first protective layer (104), and as a result, it may be difficult to stably support the second portion (116b2) of the bump portion (116b) by the first protective layer (104). Accordingly, mechanical reliability problems, such as cracks occurring in the bump portion (116b), may occur.

[0137]

[0138] Meanwhile, the slope of the side wall of the through hole (104a) of the first protective layer (104) and the slope of the side wall of the recess (104b) may be the same. Alternatively, the slope of the side wall of the through hole (104a) of the first protective layer (104) and the slope of the side wall of the recess (104b) may be different from each other.

[0139] Preferably, the through hole (104a) may overlap vertically with the pad portion (116a) having a relatively large horizontal width and may have a relatively large vertical depth. Alternatively, the recess (104b) may be provided in an area where the bump portion (116b) having a relatively small horizontal width is arranged and may have a relatively small vertical depth. Accordingly, the embodiment may allow the side walls of the through hole (104a) and the recess (104b) to have different inclination angles.

[0140] According to the embodiment of FIG. 5, the side wall of the through hole (104a) may have a certain slope with respect to the upper or lower surface of the first protective layer (104). For example, the side wall of the through hole (104a) may have a slope such that the horizontal width of the through hole (104a) becomes narrower from the upper part of the through hole (104a) to the lower part of the through hole (104a). Through this, the volume of the joining member within the through hole (104a) having a relatively large volume can be controlled, thereby reducing the manufacturing cost. In addition, the side wall of the through hole (104a) may have a slope such that the horizontal width of the through hole (104a) becomes narrower from the upper part of the through hole (104a) to the lower part of the through hole (104a), thereby allowing the joining member to be easily seated inside the through hole (104a) having a relatively large vertical depth.

[0141] Alternatively, the side wall of the recess (104b) may have a different slope from the side wall of the through hole (104a). For example, the slope of the side wall of the recess (104b) may be closer to vertical than the slope of the side wall of the through hole (104a). This allows the area of ​​the bottom surface (104b1) of the recess (104b) to be secured, thereby enabling precise control of the space in which the semiconductor element is placed, and thus enabling the semiconductor element to be more stably installed.

[0142] According to the embodiment of FIG. 6, a trench (104b2) may be provided on the side wall of the recess (104b). The trench (104b2) may be provided concavely toward the outward direction away from the recess (104b) on the side wall of the recess (104b). The trench (104b2) may be provided on the inner wall of the recess (104b) by controlling the exposure intensity in the area where the recess (104b) is to be formed during the process of forming the recess (104b). For example, by controlling the exposure intensity in the area where the recess (104b) is to be formed, it is possible to prevent curing of a portion adjacent to the periphery of the bottom surface (104b1) of the recess (104b). Therefore, the trench (104b2) that is concave toward the outward direction may be provided on the side wall of the recess (104b). That is, the trench (104b2) may be provided at the boundary between the side wall and the bottom surface of the recess (104b). In addition, the trench (104b2) may be provided along the circumferential direction of the bottom surface (104b1) of the recess (104b). The trench (104b2) may be filled with a bonding member, such as solder, which is disposed on the bump portion (116b), thereby acting as an anchor to strengthen the bonding force between the bonding member and the circuit board. Alternatively, the trench (104b2) may be filled with a molding member for molding a semiconductor element, thereby further strengthening the bonding force between the molding member and the circuit board.

[0143] According to the embodiment of FIG. 7, the bottom surface (104b1) of the first protective layer (104) may not be flat but may have a curve. For example, the bottom surface (104b1) of the first protective layer (104) may have a concave surface facing the upper build-up layer (102).

[0144] That is, the first protective layer (104) is arranged with a recess (104b) between a plurality of bumps of the bump portion (116b), and accordingly, the concave surface provided on the bottom surface (104b1) of the first protective layer (104) can be concave in a downward direction between the plurality of bumps or in a direction toward the upper surface of the insulating layer (110). The concave surface of the first protective layer (104) can have the function of increasing the surface area of ​​the upper surface of the first protective layer (104), and thus can prevent stress applied by a heat cycle such as expansion and / or contraction from being transmitted to the bump portion (116b).

[0145] For example, the concave surface provided on the upper surface of the first protective layer (104) increases the surface area of ​​the upper surface of the first protective layer (104), and thus can have the function of increasing the surface area of ​​the upper surface of the first protective layer (104) between the bump portions (116b) compared to when the upper surface of the first protective layer (104) is a flat plane.

[0146] Through this, the embodiment can solve the problem of cracks in the bump portion (116b) that may occur due to thermal stress acting on the circuit board, and through this, can solve the reliability problem of the terminal of the semiconductor element and / or the conductive adhesive such as solder placed on the bump portion (116b) being electrically separated from the bump portion (116b).

[0147] For example, when thermal deformation such as expansion and / or contraction of the circuit board occurs, stress may be applied accordingly and the stress may be transmitted to the bump portion (116b). Here, thermal deformation may mean a change in the volume of the first protective layer (104) due to expansion and / or contraction of the first protective layer (104).

[0148] When thermal deformation of the first protective layer (104) is repeated, stress may be applied to the bump portion (116b) positioned within the first protective layer (104), and cracks may occur at the connection portion between the first portion (116b1) and the second portion (116b2) of the bump portion (116b) due to the stress. As a result, the bump portion (116b) may be peeled off from the circuit board, resulting in mechanical reliability and / or electrical reliability problems.

[0149] In addition, if thermal deformation of the first protective layer (104) is repeated, stress may be applied to the bonding member, such as solder, placed on the bump portion (116b), which may cause cracks in the bonding member. This may result in an electrical open problem between the semiconductor element and the bump portion.

[0150] The concave surface provided on the bottom surface (104b1) of the recess (104b) of the first protective layer (104) functions to increase the surface area of ​​the bottom surface (104b1) of the recess (104b) of the first protective layer (104), thereby reducing the degree of thermal deformation (e.g., degree of expansion and / or degree of contraction) of the first protective layer (104) caused by thermal stress. Through this, the concave surface provided on the upper surface of the first protective layer (104) can prevent the stress caused by thermal deformation of the first protective layer (104) from acting on the bump portion (116b). For example, the concave surface can alleviate the stress caused by thermal stress and prevent it from being transmitted in the direction toward the bump portion (116b). Therefore, the embodiment can enable a semiconductor element to be stably attached on a circuit board, and thereby improve the mechanical reliability and electrical reliability between the circuit board and the semiconductor element. Furthermore, the embodiment can enable a semiconductor device to operate stably, thereby improving the operational reliability of electronic products such as servers to which the semiconductor package is applied.

[0151] In addition, the concave surface is provided with a concave curved surface from the upper surface toward the lower surface of the first protective layer (104). Through this, the embodiment can further enhance the effect of preventing stress action due to the concave surface. For example, if the concave surface has an angular square shape, stress may be concentrated at the angular portion, which may cause problems such as reduced mechanical reliability or reduced electrical reliability. In contrast, the embodiment can provide the concave surface with a concave curved surface, thereby preventing stress from being concentrated at a specific portion of the concave surface. Therefore, the embodiment can further enhance the physical reliability and / or electrical reliability of the semiconductor package.

[0152] In addition, the first protective layer (104), the bump portion (116b), and the semiconductor element may be formed of different materials. For example, the first protective layer (104) may be formed of a solder resist, the bump portion (116b) may be formed of a metal material such as copper, and the semiconductor element may be formed of a silicon material. In this case, the thermal expansion coefficients of the first protective layer (104), the bump portion (116b), and the semiconductor element are different from each other. For example, the thermal expansion coefficient of the first protective layer (104) is greater than the thermal expansion coefficients of the bump portion (116b) and the semiconductor element. Therefore, when the same thermal stress is applied to the first protective layer (104), the bump portion (116b), and the semiconductor element, the degree of thermal deformation of the first protective layer (104) may be the greatest compared to the bump portion (116b) and the semiconductor element. Accordingly, the embodiment can be provided with a concave surface on the upper surface of the first protective layer (104), and can prevent stress due to thermal deformation such as expansion and / or contraction from acting on the electrical joint portion between the circuit board and the semiconductor element, thereby improving the mechanical reliability and / or electrical reliability of the semiconductor package.

[0153] According to the embodiments of (a) and (b) of FIGS. 8A and 8B, respectively, the circuit board may include a build-up layer (201), bump portions (202, 206), and a protective layer (205). The protective layer (205) may have a recess (206) as described in the previous embodiment.

[0154] The bump portion (202, 206) may include a first portion (203, 207) having a first width spaced apart from each other in the horizontal direction, and a second portion (204, 208) disposed on the first portion (203, 207) and having a second width smaller than the first width in the horizontal direction.

[0155] In the embodiment, the horizontal central axes of the first portions (203, 207) of the bump portions (202, 206) and the horizontal central axes of the second portions (204, 208) may be misaligned with each other. At this time, the circuit board may have a plurality of bump portions, and the horizontal central axes of the first portions of each bump portion and the horizontal central axes of the second portion may be misaligned with each other, and the misaligned directions of the respective bump portions may be the same. Alternatively, the horizontal central axes of the first portions of each bump portion and the horizontal central axes of the second portion may be misaligned with each other, and the misaligned directions of the respective bump portions may be different from each other. Hereinafter, an embodiment in which the misaligned directions of each bump portion are different from each other will be described, but the embodiment is not limited thereto.

[0156] According to the embodiment of FIG. 8A, the first bump portion (202) may include a first portion (203) disposed on the first pad portion (220) and having a first width in the horizontal direction, and a second portion (204) disposed on the first portion (203) and having a second width in the horizontal direction smaller than the first width. In addition, the central axis (X1) of the first portion (203) of the first bump portion (202) in the horizontal direction and the central axis (X2) of the second portion (204) of the first bump portion (202) in the horizontal direction may be misaligned with each other. That is, the outer surface of the first portion (203) of the first bump portion (202) and the outer surface of the second portion (204) may have a step.

[0157] At this time, the horizontal central axis (X1) of the first part (203) of the first bump part (202) may not be aligned with the horizontal central axis (X2) of the second part (204) of the first bump part (202) and may be spaced apart from each other in the horizontal direction. That is, the horizontal central axis (X1) of the first part (203) of the first bump part (202) and the horizontal central axis (X2) of the second part (204) of the first bump part (202) may be misaligned with each other. Here, when the upper surface of the first part (203) of the first bump part (202) has a circular or elliptical shape, the horizontal central axis (X1) of the first part (203) of the first bump part (202) may mean the intersection point where the major axis and the minor axis of the upper surface of the first part (203) meet. Alternatively, when the upper surface of the first part (203) of the first bump part (202) has a square shape, the horizontal central axis (X1) of the first part (203) may mean a point where a line segment connecting two vertices facing each other on the upper surface of the first part (203) of the first bump part (202) meets. Correspondingly, the horizontal central axis (X2) of the second part (204) of the first bump part (202) may mean an intersection where a major axis and a minor axis meet, or a point where two line segments connecting two vertices facing each other meet.

[0158] The horizontal central axis (X1) of the first part (203) of the first bump portion (202) and the horizontal central axis (X2) of the second part (204) of the first bump portion (202) are misaligned with each other, and may have a horizontal separation distance (W3) as an example. For example, the horizontal central axis (X2) of the second part (204) of the first bump portion (202) may be shifted horizontally by a horizontal separation distance (W3) based on the horizontal central axes (X1) of the first part (144) and the second part (145) of the first bump portion (202). Here, shifting may mean that the central axis (X2) of the second part (204) of the first bump part (202) and the central axis (X1) of the first part (203) of the first bump part (202) are not aligned along the vertical direction but are misaligned. For example, the shift described above may mean that the horizontal distance from the horizontal central axis (X0) of the build-up layer (201) to the central axis (X2) of the second part (204) of the first bump portion (202) and the horizontal distance from the horizontal central axis (X0) of the build-up layer (201) to the central axis (X1) of the first part (203) of the first bump portion (202) are applied differently from each other, and for example, the horizontal distance from the horizontal central axis (X0) of the build-up layer (201) to the central axis (X2) of the second part (204) of the first bump portion (202) may mean that it is smaller or larger than the horizontal distance from the horizontal central axis (X0) of the build-up layer (201) to the central axis (X1) of the first part (203) of the first bump portion (202). In addition, the shift described above means that the horizontal central axis (X1) of the first part (203) of the first bump part (202) and the central axis (X2) of the second part (204) of the first bump part (202) are not aligned with each other and are misaligned. In the following, for the convenience of explanation, the terms “shift” and / or “misalignment” will be used in the above-described meanings.

[0159] The circuit board (100) can be prevented from being bent in a specific direction depending on the direction and distance in which the central axis (X2) of the second portion (204) of the first bump portion (202) is shifted based on the central axis (X1) of the first portion (203) of the first bump portion (202). At this time, depending on the direction and distance in which the central axis (X2) of the second portion (204) of the first bump portion (202) is shifted based on the central axis (X1) of the first portion (203) of the first bump portion (202), warping of the circuit board (100) in a specific direction may occur, and the meaning of the above-described alleviation may mean that the central axes of the first portion (203) and the second portion (204) of the first bump portion (202) are misaligned with each other so that warping of the circuit board occurs in the opposite direction based on the direction in which the circuit board (100) is bent before the above-described misalignment is applied.

[0160] By making the central axis (X2) of the second portion (204) of the first bump portion (202) misaligned with the central axis (X1) of the first portion (203) of the first bump portion (202) based on the direction in which the circuit board (100) is bent, the circuit board (100) can be prevented from being bent in a specific direction, excessive stress applied to the circuit board can be avoided, and mechanical reliability and / or electrical reliability of the circuit board can be improved accordingly. In addition, the embodiment can alleviate the warpage of the circuit board so that a semiconductor element can be stably attached on the circuit board. At this time, when the circuit board is bent in a specific direction, a height deviation may occur between a plurality of bonding portions provided on the circuit board, and terminals of the semiconductor element may not be stably bonded on the plurality of bonding portions. In contrast, the embodiment can alleviate the overall warpage of the circuit board through the misalignment between the center axes (X1, X2) of the first portion (203) and the second portion (204) of the first bump portion (202), and can enable the semiconductor element to be stably attached on the circuit board. Therefore, the embodiment can enable the semiconductor element to operate stably, thereby improving product reliability. Furthermore, the embodiment can enable the stable operation of products such as servers to which the semiconductor package is applied.

[0161] In addition, since the horizontal central axis (X2) of the second portion (204) of the first bump portion (202) is misaligned with respect to the horizontal central axis (X1) of the first portion (203) of the first bump portion (202), the horizontal distances of the steps on the outer surfaces of the first portion (203) and the second portion (204) of the first bump portion (202) may have different horizontal distances along the circumferential direction of the upper surface and / or lower surface of the first bump portion (202).

[0162] That is, based on the vertical cross-section of the first bump portion (202), the step between the outer surface of the first portion (203) and the outer surface of the second portion (204) on one side of the first bump portion (202) may have a first horizontal distance (W1), and the step between the outer surface of the first portion (203) and the outer surface of the second portion (204) on the other side opposite to the one side may have a second horizontal distance (W2) different from the first horizontal distance (W1). Furthermore, the steps provided on the outer surfaces of the first portion (203) and the second portion (204) of the first bump portion (202) may not be uniform along the circumferential direction of the upper surface and / or lower surface of the first bump portion (202).

[0163] At this time, the first horizontal distance (W1) and the second horizontal distance (W2) can be determined according to the misalignment direction and misalignment degree between the respective central axes (X1, X2) of the first part (203) and the second part (204) of the first bump part (202). Here, the misalignment direction can mean the direction in which the horizontal central axis (X2) of the second part (204) of the first bump part (202) is located with respect to the horizontal central axis (X1) of the first part (203) of the bonding part (260), and the misalignment degree can mean the horizontal distance between the horizontal central axis (X1) of the first part (203) of the bonding part (260) and the horizontal central axis (X2) of the second part (204) of the first bump part (202). In addition, the embodiment can alleviate the overall warpage of the circuit board (100) by aligning the horizontal central axis (X2) of the second portion (204) of the first bump portion (202) with respect to the horizontal central axis (X1) of the first portion (203) of the bonding portion (260).

[0164] At this time, Fig. 8a illustrates that the horizontal central axis (X2) of the second part (204) of the first bump part (202) is misaligned in the first horizontal direction based on the horizontal central axis (X1) of the first part (203) of the first bump part (202), and Fig. 8b illustrates the second bump part misaligned in the second horizontal direction opposite to the first horizontal direction.

[0165] Referring to (a) and (b) of FIG. 8B, the second bump portion (206) may include a first portion (207) and a second portion (208) disposed on the first portion (207). In addition, the first portion (207) and the second portion (208) of the second bump portion (206) may have different widths in the horizontal direction, and further, the horizontal central axis (X3) of the first portion (207) and the horizontal central axis (X4) of the second portion (208) may not be aligned but may be spaced apart in the horizontal direction. The horizontal central axis (X3) of the first portion (207) of the second bump portion (206) and the horizontal central axis (X4) of the second portion (208) of the second bump portion (206) may be misaligned with each other.

[0166] The horizontal central axis (X3) of the first part (207) of the second bump portion (206) and the horizontal central axis (X4) of the second part (208) of the second bump portion (206) are misaligned with each other, and may have a horizontal separation distance (W6) as an example. For example, the horizontal separation distance (X4) of the second part (208) of the second bump portion (206) may be misaligned with respect to the horizontal separation distance (W6) with respect to the central axis (X3) of the first part (207) of the second bump portion (206).

[0167] And, depending on the direction and distance in which the central axis (X4) of the second part (208) of the second bump part (206) moves or deviates from the central axis (X3) of the first part (207) of the second bump part (206), the circuit board (100) can be alleviated from being bent in a specific direction.

[0168] At this time, depending on the direction and distance in which the central axis (X4) of the second part (208) of the second bump part (206) is misaligned with respect to the central axis (X3) of the first part (207) of the second bump part (206), warping of the circuit board (100) in a specific direction may occur, and the meaning of the above-described alleviation may mean that the central axes of the first part (207) and the second part (208) of the second bump part (206) are misaligned with respect to the direction in which the circuit board (100) is bent before the above-described misalignment is applied so that warping of the circuit board occurs in the opposite direction.

[0169] The central axis (X4) of the second portion (208) of the second bump portion (206) is misaligned with the central axis (X3) of the first portion (207) of the second bump portion (206) based on the direction in which the circuit board (100) is bent, thereby preventing the circuit board (100) from being bent in a specific direction, avoiding excessive stress applied to the circuit board, and thereby improving the mechanical reliability and / or electrical reliability of the circuit board. In addition, the embodiment can alleviate the warpage of the circuit board so that the semiconductor element can be stably attached on the circuit board. At this time, when the circuit board is bent in a specific direction, a height deviation may occur between the plurality of bonding portions provided on the circuit board, and the terminals of the semiconductor element may not be stably bonded on the plurality of bonding portions. In contrast, the embodiment can alleviate the overall warpage of the circuit board through the misalignment between the center axes (X3, X4) of the first portion (207) and the second portion (208) of the second bump portion (206), and can stably attach the semiconductor element on the circuit board. Therefore, the embodiment can enable the semiconductor element to operate stably, thereby improving product reliability. Furthermore, the embodiment can enable the stable operation of products such as servers to which the semiconductor package is applied.

[0170] In addition, since the horizontal central axis (X4) of the second part (208) of the second bump part (206) is misaligned with respect to the horizontal central axis (X3) of the first part (207) of the second bump part (206), the horizontal distance of the step on the outer surface of the first part (207) and the second part (208) of the second bump part (206) may have different horizontal distances along the circumferential direction of the upper surface and / or lower surface of the second bump part (206).

[0171] That is, based on the vertical cross-section of the second bump portion (206), the step between the outer surface of the first portion (207) and the outer surface of the second portion (208) on one side of the second bump portion (206) may have a third horizontal distance (W4), and the step between the outer surface of the first portion (207) and the outer surface of the second portion (208) on the other side opposite to the one side may have a fourth horizontal distance (W5) different from the third horizontal distance (W4). Furthermore, the steps provided on the outer surfaces of the first portion (207) and the second portion (208) of the second bump portion (206) may not be uniform along the circumferential direction of the upper surface and / or lower surface of the second bump portion (206).

[0172] At this time, the third horizontal distance (W4) and the fourth horizontal distance (W5) can be determined according to the misalignment direction and misalignment degree between the respective central axes (X3, X4) of the first part (207) and the second part (208) of the second bump part (206). Here, the misalignment direction can mean the direction in which the horizontal central axis (X4) of the second part (208) of the second bump part (206) is located with respect to the horizontal central axis (X3) of the first part (207) of the second bump part (206), and the misalignment degree can mean the horizontal distance between the horizontal central axis (X3) of the first part (207) of the second bump part (206) and the horizontal central axis (X2) of the second part (208) of the second bump part (206). And, the embodiment can alleviate the overall warpage of the circuit board (100) by aligning the horizontal central axis (X2) of the second part (208) of the second bump part (206) with respect to the horizontal central axis (X3) of the first part (207) of the second bump part (206).

[0173] Meanwhile, the circuit board of the embodiment may be provided with only the first bump portion (202) described above, may be provided with only the second bump portion (206), or may be provided with both the first bump portion (202) and the second bump portion (206). Furthermore, the embodiment may be provided with both the first bump portion (202) and the second bump portion (206) based on the position at which each bonding portion is arranged.

[0174] According to the embodiment of FIG. 9, the circuit board may include a build-up layer (301), a plurality of bump portions (302, 306) arranged on the build-up layer (301), and a protective layer (305) having a through hole (304a) and a recess (305b). The plurality of bump portions (302, 306) may be positioned in different directions with respect to a central axis (X0) in a horizontal direction of the build-up layer (301). The central axis (X0) of the build-up layer (301) may mean a point where two line segments connecting two vertices facing each other with respect to a plane of the build-up layer (301) meet.

[0175] The plurality of bump portions (302, 306) may include a first bump portion (302) located on one side with respect to the central axis (X0) of the build-up layer (301), and a second bump portion (306) located on the other side opposite to the one side with respect to the central axis (X0) of the build-up layer (301).

[0176] The first bump portion (302) may include a first portion (303) disposed on the first pad portion of the first circuit layer (320) and a second portion (304) disposed on the first portion (303). In addition, the horizontal width of the first portion (303) of the first bump portion (302) is larger than the horizontal width of the second portion (304), and the horizontal central axis of the first portion (303) of the first bump portion (302) and the horizontal central axis of the second portion (304) may be misaligned.

[0177] The second bump portion (306) may include a first portion (307) disposed on the second pad portion of the first circuit layer (320) and a second portion (308) disposed on the first portion (307). In addition, the horizontal width of the first portion (307) of the second bump portion (306) is larger than the horizontal width of the second portion (308), and the horizontal central axis of the first portion (307) of the second bump portion (306) and the horizontal central axis of the second portion (308) may be misaligned.

[0178] At this time, the misalignment direction of the horizontal central axes of the first part (303) and the second part (304) of the first bump part (302) may be different from the misalignment direction of the horizontal central axes of the first part (307) and the second part (308) of the second bump part (306).

[0179] That is, the central axis of the second part (304) of the first bump part (302) may be misaligned (misalignment 1) in the first horizontal direction with respect to the central axis of the first part (303). For example, the central axis of the second part (304) of the first bump part (302) may be misaligned (misalignment 1) in a direction away from the horizontal central axis (X0) of the build-up layer (301) with respect to the central axis of the first part (303).

[0180] The central axis of the second portion (308) of the second bump portion (306) may be misaligned (misalignment 2) in a second horizontal direction opposite to the first horizontal direction described above with respect to the central axis of the first portion (307). For example, the central axis of the second portion (308) of the second bump portion (306) may be misaligned (misalignment 2) in a direction away from the horizontal central axis (X0) of the build-up layer (301) with respect to the central axis of the first portion (307).

[0181] That is, the horizontal central axis of the second portion (304, 308) of each of the plurality of bump portions (302, 306) can be shifted away from the horizontal central axis (X0) of the build-up layer (301) with respect to the horizontal central axis of the first portion (303, 307), thereby further alleviating the bending of the circuit board in a specific direction.

[0182] According to the embodiment of FIG. 10, the circuit board includes a laminated structure (710) stacked along a vertical direction. The laminated structure (710) may include a core layer (711), an upper build-up layer (712), and a lower build-up layer (713) stacked along the vertical direction. The upper build-up layer (712) may include a first protective layer having a through hole and a recess as described in the previous embodiment. The lower build-up layer (713) may include a second protective layer.

[0183] In addition, the circuit board may further include at least one connecting member (720) embedded within the laminated structure (710). At this time, the basic structure of the laminated structure (710) illustrated in FIG. 10 corresponds to the structure of the circuit board illustrated in FIG. 1, and a detailed description thereof is omitted. The connecting member (720) may function to electrically connect a plurality of semiconductor elements.

[0184] Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices is trending toward larger areas. However, this larger area of ​​semiconductor devices is causing problems in lowering the yield of semiconductor devices. Therefore, there is a trend to divide the pattern size or functional part of semiconductor devices, place chiplets on a circuit board, and embed a connecting member (720) that has the function of electrically connecting them within the circuit board. However, the connecting member (720) is not limited thereto, and can also connect semiconductor devices with other functions, such as memory. In addition, it is advantageous for preventing signal loss to embed the connecting member (720) in the upper build-up layer (712) described with reference to FIG. 1 in the laminated structure (710). That is, the connecting member (720) electrically connects a plurality of semiconductor devices arranged on the circuit board, and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor devices can be advantageous for reducing signal transmission loss. Accordingly, the connecting member (720) can be placed on top of the upper build-up layer (712) of the circuit board. An example embodiment of the connecting member (720) according to the present invention is described in which it is placed on top of the upper build-up layer (712).

[0185] At this time, the upper build-up layer (712) may include a first insulating layer (712-1) and a second insulating layer (712-2), and the first insulating layer (712-1) and the second insulating layer (712-2) may have a through hole (712C), and the through hole (712C) of the first insulating layer (712-1) and the second insulating layer (712-2) may form a cavity.

[0186] The connecting member (720) can be placed in the cavity described above, and the connecting member (720) can be embedded in the third insulating layer (712-3) of the upper build-up layer (712). The connecting member (720) is placed on the upper surface of the core layer (711) that vertically overlaps the cavity, and the third insulating layer (712-3) of the upper build-up layer (712) can be provided to surround the side of the connecting member (720) embedded in the cavity while filling the cavity. At this time, a dummy pattern can be provided on the upper surface of the core layer (711) to ensure the flatness of the connecting member (720) while ensuring that the connecting member (720) is stably placed.

[0187] In the past, only the second insulating layer (712-2) had a through hole and the connecting member (720) was embedded in the third insulating layer (712-3), or only the first insulating layer (712-1) had a through hole and the connecting member (720) was embedded in the second insulating layer (712-2). However, in this case, the flatness of the upper surface of the third insulating layer (712-3) may deteriorate. In addition, when the thickness of the connecting member (720) is thicker than the thickness of the first insulating layer (712-1) and / or the thickness of the second insulating layer (712-2), the flatness of the upper surface of the third insulating layer (712-3) may deteriorate further. Therefore, it is necessary to improve the flatness of the third insulating layer (712-3) and further the flatness of the upper surface of the upper build-up layer (712) by reducing the difference between the thickness of the connecting member (720) and the depth of the cavity.

[0188] At this time, in order to reduce the difference between the depth of the cavity and the thickness of the connecting member (720), it is advantageous to form the cavity across the first insulating layer (712-1) and the second insulating layer (712-2). At this time, the through hole of the second insulating layer (712-2) can be formed to have a second inclination angle higher than the first inclination angle of the inner wall forming the through hole of the first insulating layer (712-1). In this way, in order to increase the positional alignment of the connecting member (720) and prevent the occurrence of voids when filling the cavity with the third insulating layer (712-3), the inclination angle of the inner wall forming the through hole of the first insulating layer (712-1) and the inclination angle of the inner wall forming the through hole of the second insulating layer (712-2) can be arranged differently from each other.

[0189] In addition, the inclination angle of the inner wall forming the through hole of the first insulating layer (712-1) is shown to have a gentler inclination angle than the inclination angle of the inner wall forming the through hole of the second insulating layer (712-2), but is not limited thereto, and the inclination angle of the inner wall forming the through hole of the second insulating layer (712-2) may have a gentler inclination angle than the inclination angle of the inner wall forming the through hole of the first insulating layer (712-1).

[0190] Additionally, when embedding a connecting member (720), a metal member (not shown) may be placed around the cavity to improve the alignment of its position. This can improve the alignment of the position, thereby improving the alignment of the via electrode and circuit layer placed in a subsequent process.

[0191] In addition, the via electrodes provided in the upper build-up layer (712) may have different widths depending on their positions. For example, the upper build-up layer (712) may include a first via electrode (712-4) that vertically overlaps with the connecting member (720), and a second via electrode (712-5) that horizontally overlaps with the first via electrode (712-4) and does not vertically overlap with the connecting member (720). The above-described first via electrode (712-4) may be directly connected to a pad portion (721) provided on the upper surface of the connecting member (720). At this time, the pad portion (721) may have a width smaller than the width of the circuit layer embedded in the lower surface of the first insulating layer (712-1). Therefore, the horizontal width of the first via electrode (712-4) may be smaller than the horizontal width of the second via electrode (712-5).

[0192] Additionally, the circuit board has a bump portion (730) arranged on the upper build-up layer (712). At this time, the bump portion (730) can overlap with the connecting member (720) in the vertical direction. Accordingly, the recess provided in the first protective layer can overlap with the connecting member (720) in the vertical direction.

[0193] The bump portion (730) may be positioned between the pad portion (721) of the connecting member (720) and the terminal of the semiconductor element. Therefore, the embodiment can improve circuit density by using the first portion (731) and the second portion (732) of the bump portion (730), and further, can more stably electrically connect the semiconductor element and the connecting member. Therefore, the embodiment can enable the semiconductor element to operate stably, and thus improve the operational reliability of the semiconductor package.

[0194] According to the embodiment of FIG. 11, the circuit board may include a build-up layer (810). The build-up layer (810) may include an insulating layer (811) formed as a plurality of layers stacked along a vertical direction, a circuit layer (812) disposed on each surface of the plurality of insulating layers (811), and a via electrode (813) electrically connecting the circuit layers (812) disposed on different layers along the vertical direction. At this time, the circuit board of FIG. 11 may have a difference in the structure of the build-up layer (810) compared to the circuit board of the previous embodiment. That is, the insulating layer (811) in the circuit board of FIG. 8 has a structure in which it is stacked only in one direction based on the insulating layer disposed at the uppermost side, unlike the insulating layer of the previous embodiment, and accordingly, it may have a structure in which it is stacked in one direction along a vertical direction based on the bonding portion without having a core layer. In addition, a connecting member (820) may be embedded in the build-up layer (810). Furthermore, the upper circuit layer of the build-up layer (810) may be embedded in the insulating layer (811). In this case, the bump portion (840) may include a first portion and a second portion as described in the previous embodiment, and the first portion of the bump portion (840) may be embedded in the insulating layer (811), and the second portion of the bump portion (840) may protrude above the insulating layer (811).

[0195] Additionally, a connecting portion (830) may be placed between the first portion of the bump portion (840) and the pad portion (821).

[0196] That is, the circuit board of FIG. 1 may be a core board, and the circuit board of FIG. 11 may be a core-less board. Accordingly, the pad portion of the upper circuit layer provided in the circuit board of FIG. 1 may be provided so as to protrude above and below the insulating layer. In contrast, the pad portion of the upper insulating layer provided in the circuit board of FIG. 11 may have a structure in which it is embedded within the insulating layer (811) of the build-up layer (810). For example, the circuit board may have an ETS (Embedded Trace Substrate) structure.

[0197]

[0198] According to the embodiment of FIG. 12, semiconductor elements (930, 940) may be arranged on the circuit board of the embodiment and provided as a semiconductor package.

[0199] For example, semiconductor elements (930, 940) may be arranged on the circuit board illustrated in FIG. 10. That is, the semiconductor package may include a build-up insulating layer (910) in which a connecting member is embedded, and a bump portion (920) arranged on the build-up insulating layer (910). In addition, the bump portion (920) may include a first portion (921) having a first width in a horizontal direction, and a second portion (922) having a second width smaller than the first width in the horizontal direction and arranged on the first portion (921).

[0200] A connection portion (940) may be arranged on the bump portion (920), and semiconductor elements (930, 940) may be arranged on the connection portion (940). At this time, the connection portion (940) may be arranged on the second portion (922) of the bump portion (920), and the semiconductor elements (930, 940) may be attached to the connection portion (940). The connection portion (940) may be provided to surround a side surface of the second portion (922) of the bump portion (920). For example, the connection portion (940) may be in contact with a side surface of the second portion (922) of the bump portion (920). In addition, the connection portion (940) may be in contact with an upper surface of the first portion (921) provided by a step between the first portion (921) and the second portion (922) of the bump portion (920). At this time, the step of the bump portion (920) has different horizontal distances along the circumferential direction of the upper and / or lower surfaces of the bump portion (920), and accordingly, the connection portion (940) may be provided with different widths along the circumferential direction of the bump portion (920) in an area that horizontally overlaps the second portion (922) of the bump portion (920). In addition, the connection portion (940) may not contact the side surface of the first portion (921) through the step between the first portion (921) and the second portion (922) of the bump portion (920). For example, the step described above can prevent the connection portion (940) from overflowing to the side surface of the first portion (921) of the bump portion (920), and thereby enable the volume of the connection portion (940) to be easily adjusted. In addition, an intermetallic compound (IMC) may be formed when the connection portion (940) and the bump portion (920) come into contact. The above-described step can prevent the circuit layer provided in the build-up layer (910) and the connection portion (940) from being connected, and can prevent the interface between different components of the build-up layer (910) from being separated or the electrical characteristics from being deteriorated due to the formation of the intermetallic compound.

[0201] Additionally, the connection portion (940) may be further positioned within a through hole of a first protective layer provided on a circuit board. At this time, the through hole of the first protective layer may expose a pad portion of the circuit board, through which the connection portion (940) may electrically connect the pad portion and the terminal of the semiconductor element.

[0202] In addition, the semiconductor package may further include a buried insulating layer (960) that molds the semiconductor element. The buried insulating layer (960) may bury the semiconductor element. In this case, the buried insulating layer (960) may be provided to fill a recess provided in the protective layer. Through this, the adhesion between the buried insulating layer (960) and the circuit board can be further improved.

[0203] The circuit board according to FIG. 12 described above is used as a semiconductor package board of a semiconductor package, and thus can electrically connect a semiconductor element and a main board.

[0204] In addition, the circuit board described above can be used as an interposer provided between the semiconductor package substrate and the semiconductor elements of the semiconductor package. Referring to the embodiment of FIG. 13, the semiconductor package can include an interposer (1000), a first bonding member (1010), a plurality of semiconductor elements (1020, 1030), a second bonding member (1040), and a semiconductor package substrate (1050).

[0205] The interposer (1000) may include a circuit board described with reference to the previous drawings. That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, the yield of the circuit board may decrease. Therefore, the circuit board may be divided into an interposer (1000) and a semiconductor package board (1050) and used. The circuit board described above may be used as a semiconductor package board as in the embodiment of FIG. 9, and further, may be used as an interposer (1000) as in the embodiment of FIG. 13.

[0206] Semiconductor elements (1020, 1030) are arranged on the interposer (1000). The semiconductor elements (1020, 1030) may be provided in multiple numbers on the interposer (1000) while being spaced apart from each other in the horizontal direction, but the present invention is not limited thereto. For example, the semiconductor elements (1020, 1030) may be arranged to be stacked not only in the horizontal direction but also in the vertical direction on the interposer (1000). A connecting member for electrically connecting the semiconductor elements (1020, 1030) is arranged on the interposer (1000).

[0207] A first bonding member (1010) may be provided between the interposer (1000) and the semiconductor elements (1020, 1030). The first bonding member (1010) may be placed on a bonding portion provided in the interposer (1000), through which the semiconductor elements (1020, 1030) may be attached to the interposer (1000) by a thermocompression bonding method. At this time, the semiconductor elements (1020, 1030) may be provided with terminals (1025, 1035), and the terminals (1025, 1035) may be electrically connected to the bonding portion and circuit layer of the interposer (1000) through the first bonding member (1010).

[0208] A semiconductor package substrate (1750) is placed on the lower surface of the interposer (1000). The semiconductor package substrate (1000) can electrically connect the main board of an electronic device and the interposer (1700).

[0209] At this time, a second bonding member (1040) may be placed between the interposer (1000) and the semiconductor package substrate (1050), through which the interposer (1000) and the semiconductor package substrate (1050) may be electrically bonded.

[0210]

[0211] Below, a method for manufacturing a circuit board according to an embodiment will be described in process order.

[0212] Figures 14a to 14f are cross-sectional views showing a method for manufacturing a circuit board according to one embodiment in process order.

[0213] Referring to FIG. 14A, an embodiment prepares a core member that serves as a basis for manufacturing a circuit board, and may manufacture a core layer (1110) using the core member. The core layer (1110) may include a core insulating layer and a core via electrode, and may include an insulating member penetrating the core via electrode. In addition, when manufacturing the core layer (1110), the embodiment may manufacture a portion of the circuit layer of the upper build-up layer and the lower build-up layer together with the core via electrode.

[0214] Next, referring to FIG. 14b, the embodiment may proceed with a process of manufacturing an upper build-up layer (1120) and a lower build-up layer (1130) on the upper and lower portions of the core layer (1110), respectively. At this time, an upper circuit layer may be formed on the upper surface of the upper build-up layer (1120). The upper circuit layer may include a pad portion (1121), a first portion (1122) of a bump portion, and a wiring portion (1123).

[0215] Next, referring to FIG. 14c, a process of laminating a dry film (not shown) on the upper build-up layer (1120) may be performed. At this time, the dry film may include an opening that opens a location where the second portion (1124) of the bump portion is to be formed. Thereafter, the embodiment may form a bump portion (1125) including the first portion (1122) and the second portion (1124) by filling the opening of the dry film with a conductive material.

[0216] Next, referring to FIG. 14d, a process of forming a first protective layer (1126) on the upper build-up layer (1120) may be performed. At this time, the first protective layer (1126) may be arranged to entirely cover the pad portion (1121), bump portion (1125), and wiring portion (1123) of the upper build-up layer (11120).

[0217] Next, referring to FIG. 14e, exposure and development processes may be performed based on the region where a recess is to be formed and the region where a through hole is to be formed in the first protective layer (1126). Accordingly, the embodiment may perform a process of hardening the remaining region except for the region where a recess is to be formed and the region where a through hole is to be formed. Thereafter, the embodiment may perform a process of thinning the thickness of the unhardened region through etching, thereby performing a process of forming a recess (1128). At this time, the thickness of the region where a through hole is to be formed may also be reduced to correspond to the thickness of the recess (1128).

[0218] Next, referring to FIG. 14f, a process of hardening the area where the recess (1128) is formed can be performed. Thereafter, the embodiment can perform a process of additionally developing the area where the through hole is to be formed to form the through hole (1129).

[0219]

[0220] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0221] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0222] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0223] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up insulating layer including an upper surface and a lower surface, a plurality of insulating layers laminated between the upper surface and the lower surface, and an upper circuit layer disposed on the upper surface; and A protective layer disposed on the upper circuit layer of the above build-up insulating layer; The protective layer includes a through hole having a first depth along a vertical direction, and a recess having a second depth different from the first depth along the vertical direction, A circuit board wherein the above through hole and the above recess are spaced apart from each other in the horizontal direction.

2. In paragraph 1, A circuit board, wherein the first depth of the through hole is greater than the second depth of the recess.

3. In paragraph 1, A circuit board, wherein the upper circuit layer comprises a bump portion disposed in the recess and protruding from the bottom surface of the recess, and a pad portion disposed in the through hole and having at least a portion of the upper surface overlapping the through hole along the vertical direction.

4. In paragraph 3, The upper circuit layer further includes a wiring portion connected to at least one of the pad portion and the bump portion, A circuit board, wherein the above wiring portion is covered with the above protective layer.

5. In paragraph 3, A circuit board, wherein the bottom surface of the above recess includes a concave surface that is concave toward the build-up layer.

6. In paragraph 5, The above bump portion includes a plurality of bumps spaced apart along a horizontal direction, A circuit board, wherein the concave surface is provided between the plurality of bumps.

7. In paragraph 1, A circuit board, wherein the side walls of the recess include a concave trench facing outward of the recess.

8. In paragraph 7, The circuit board, wherein the trench is located at the boundary between the bottom surface of the recess and the side wall of the recess.

9. In paragraph 8, The circuit board, wherein the trench is provided along the circumferential direction of the bottom surface of the recess.

10. In paragraph 3, A circuit board wherein the vertical thickness of the bump portion is greater than the vertical thickness of the pad portion.

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