Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: an insulating layer; a pad disposed on the insulating layer; a protective layer which is disposed on the pad and which has an opening; and a recessed portion disposed on the upper surface of the pad, wherein the recessed portion includes a first recessed portion and a second recessed portion disposed on the first recessed portion, and can include a plating layer disposed in the first recessed portion.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] In addition, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring portion arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring portion connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring portion includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring portion.

[0005] Meanwhile, when surface treatment is performed on the pad on the top layer of the circuit board, the oxidized area of ​​the pad is etched and then a plating layer is formed. However, not only the area where the plating layer is formed, but also the area where the pad and the protective layer come into contact are etched, which causes a problem in that the adhesive strength between the pad and the protective layer is reduced.

[0006] In detail, FIGS. 1 and 2 are drawings illustrating a portion of a circuit board being internally studied. First, referring to FIG. 1, a pad (130) is positioned at the outermost edge of the circuit board, and a protective layer (140) may be disposed on the pad (130). The pad (130) generally includes copper (Cu), and the protective layer (140) may include a thermosetting resin.

[0007] Meanwhile, when the protective layer (140) is heat-cured, the pad (130) is oxidized and an oxide film (138) is formed between the pad (130) and the protective layer (140). Subsequently, when surface treatment is performed on the exposed pad (130), the etchant can penetrate and etch not only the oxide film located at the opening but also the area where the pad (130) and the protective layer (140) come into contact while etching the oxide film (138) covering the pad (130).

[0008] Accordingly, between the pad (130) and the protective layer (140), micro-lifting or haloing (H) may occur due to a decrease in the adhesive strength between the protective layer and the pad, and if the lifting phenomenon worsens, there is a problem that the protective layer (140) may peel off (D).

[0009] Next, referring to FIG. 2, in (a) of FIG. 2, a micro-raised or hollowed (H) region can be formed around the opening (145) of the protective layer for external connection, and can be observed as a ring shape having a white color.

[0010] Accordingly, a color difference occurs on the surface of the circuit board, which causes a design issue, and if the defect worsens, as shown in (b) of Fig. 2, the protective layer (140) partially peels off (D) or peels off from the pad (130), which causes a problem in that the reliability of the pad (130) is reduced.

[0011] One of the technical challenges of the embodiment is to reduce the lifting phenomenon of the protective layer on the circuit board and prevent peeling.

[0012] Additionally, one of the technical challenges of the embodiment is to improve the fixing strength of the connection part such as solder.

[0013] Additionally, one of the technical challenges of the embodiment is to improve the design freedom and aesthetics of the circuit board.

[0014] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0015] A circuit board according to an embodiment includes an insulating layer; a pad disposed on the insulating layer; a protective layer disposed on the pad and having an opening; and a concave portion disposed on an upper surface of the pad; wherein the concave portion includes a first concave portion and a second concave portion disposed on the first concave portion, and may include a plating layer disposed within the first concave portion.

[0016] In addition, in the embodiment, the first concave portion may have a concave shape from the upper surface of the pad to the lower surface, and the second concave portion may have a concave shape from the upper surface of the pad to the side.

[0017] Additionally, in the embodiment, the horizontal width of the first concave portion may be greater than the horizontal width of the opening.

[0018] Additionally, in an embodiment, the plating layer may vertically overlap the protective layer.

[0019] Additionally, in an embodiment, a step may be arranged between the first concave portion and the second concave portion.

[0020] Additionally, in the embodiment, the width of the first region vertically overlapping the first concave portion and the protective layer may be smaller than the width of the second concave portion in the horizontal direction.

[0021] Additionally, in the embodiment, the sum of the width of the first region and the horizontal width of the second concave portion may be smaller than the thickness of the protective layer.

[0022] Additionally, in the embodiment, the sum of the width of the first region and the horizontal width of the second concave portion may be 20% to 80% of the thickness of the protective layer.

[0023] Additionally, the embodiment includes a connection portion connected to the plating layer, wherein the connection portion can be disposed within the second concave portion.

[0024] The circuit board according to the embodiment has a technical effect of reducing the lifting phenomenon or haloing phenomenon of the protective layer and preventing the peeling of the protective layer.

[0025] For example, the embodiment can prevent oxidation of the pad by hardening the protective layer through nitrogen baking (N2baking), thereby reducing the area etched between the protective layer and the pad during the surface treatment process of the pad, thereby preventing lifting or haloing of the protective layer, and further preventing peeling of the protective layer.

[0026] In addition, the embodiment has a technical effect that can improve the design freedom and aesthetics of a circuit board.

[0027] For example, embodiments may improve the design freedom and aesthetics of circuit boards as the width of the hollow area is significantly reduced.

[0028] In addition, the embodiment has a technical effect that can improve the fixing strength of a connection part such as a solder.

[0029] For example, the embodiment may include a second recessed portion disposed between the pad and the protective layer, and a connecting portion disposed within the second recessed portion to enhance the fixing force.

[0030] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0031] Figures 1 and 2 are drawings showing a portion of a circuit board being studied internally.

[0032] Fig. 3 is a cross-sectional view of a circuit board (100) according to an embodiment.

[0033] Figures 4a and 4b are process diagrams showing the manufacturing process of one area (A1) of Figure 3.

[0034] Figures 5 to 6b are drawings observing the haloing area of ​​the circuit board.

[0035] Fig. 7 is a cross-sectional view of a semiconductor package (101) according to an embodiment.

[0036] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0037] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0038] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0039] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0040] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0041] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0042] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0043] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0044] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0045] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0046] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0047]

[0048] (Example)

[0049] Fig. 3 is a cross-sectional view of a circuit board (100) according to an embodiment. Referring to Fig. 3, the circuit board (100) according to the embodiment may include a build-up insulating portion (110), a build-up wiring portion (118), and a protective layer (140). The build-up structure including the build-up insulating portion (110), the build-up wiring portion (118), and the protective layer (140) may be referred to as a build-up structure, but is not limited thereto. The build-up structure may function as a laminated circuit for connecting to electronic components / main boards, etc.

[0050] The build-up insulation (110) includes a single or multiple laminated insulation layers and provides insulation properties between the build-up wiring sections. The build-up insulation (110) may be referred to as a build-up insulator. The build-up insulation (110) may include, but is not limited to, a first insulation layer (111), a second insulation layer (112), and a third insulation layer (113).

[0051] One of the build-up insulation parts (110) may be a core layer. The second insulation layer (112) located at the center of the build-up insulation part (110) may be a core layer, but is not limited thereto.

[0052] The core layer can function to ensure the overall mechanical rigidity of the circuit board, thereby suppressing warpage. Because it can suppress both warpage occurring during processing and during product operation, the core layer can improve circuit board yield and enhance its reliability.

[0053] The core layer may include a reinforcing member such as glass fiber extending horizontally and a resin covering the reinforcing member, and the mechanical rigidity may be controlled according to the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided within the resin layer. According to another embodiment, the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. In addition, it may have an advantage of being able to make the circuit board thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer is not limited to the above-described material in consideration of yield, price, etc., and any material that can secure mechanical rigidity may be freely selected and used.

[0054] The build-up insulation (110) may include an upper build-up insulation disposed on the upper surface of the core layer and a lower build-up insulation disposed on the lower surface of the core layer. For example, the build-up insulation (110) may include a second insulation layer (112) which is the core layer, a first insulation layer (111) which is the upper build-up insulation disposed on the upper surface of the core layer, and a third insulation layer (113) which is the lower build-up insulation disposed on the lower surface of the core layer.

[0055] The upper build-up insulation part and the lower build-up insulation part each have a function to place a wiring layer or via electrode of the build-up wiring part, secure insulation between circuits, and control impedance or insertion loss due to the circuit, and may include an insulation layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into consideration dielectric constant, mechanical rigidity, and processability.

[0056] For example, the insulation layer of the build-up insulation (110) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0057] Also, for example, the insulation layer of the build-up insulation portion (110) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0058] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0059] Additionally, the insulating layer of the build-up insulation (110) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0060] Additionally, the insulation layer of the build-up insulation portion (110) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0061]

[0062] Next, the build-up wiring section (118) of the circuit board (100) includes a wiring layer (130) arranged on the surface of each insulating layer and a via electrode (120) for vertically connecting each wiring layer (130). The wiring layer (130) may have the function of transmitting signals and / or power to semiconductor elements arranged on the circuit board (100) and may have an impedance matching function. The wiring layer (130) may be referred to as a wiring pattern layer, a metal wiring, or a wiring section.

[0063] The via electrode (120) may include a plurality of first via electrodes (121), second via electrodes (122), and third via electrodes (123) formed in through holes penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113), respectively. The via electrode (120) may electrically connect between wiring layers (130) arranged in different layers.

[0064] The via electrode (120) can be formed by forming a through hole penetrating the insulating layers and filling the inside of the formed through hole with a conductive material. Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form the via electrode (120). The metal material forming the via electrode (120) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0065]

[0066] Next, the circuit board (100) according to the embodiment may include a wiring layer (130) electrically connected to a via electrode (120). The wiring layer (130) may include pads and / or traces (or connection patterns) for connecting to the via electrode (120) and / or semiconductor elements and / or capacitors. The traces may be signal wiring lines connecting between a plurality of pads.

[0067] At this time, the pad of the wiring layer (130) may include a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion with a horizontal width greater than that of the trace for alignment margin.

[0068] The wiring layer (130) may include, but is not limited to, a first wiring layer (131) disposed on a first insulating layer (111) and electrically connected to the upper surface of a first via electrode (121), a second wiring layer (132) disposed on a second insulating layer (112) and electrically connected to the lower surface of the first via electrode (121), a third wiring layer (133) electrically connected to the lower surface of the second via electrode (122), and a fourth wiring layer (134) electrically connected to the lower surface of the third via electrode (123).

[0069] The wiring layer (130) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0070] In addition, any one of the above-described build-up wiring sections (118) may have an ETS (Embedded Trace Substrate) structure. The ETS structure may also be referred to as a buried structure. The ETS structure may be advantageous for miniaturization compared to a build-up wiring section having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0071] In addition, the build-up wiring portion may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring portion may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0072]

[0073] Next, the circuit board (100) according to the embodiment may include a protective layer (140) disposed on the wiring layer of the uppermost or lowermost insulating layer. For example, the protective layer may include a first protective layer disposed on the first insulating layer and a second protective layer disposed under the third insulating layer (113).

[0074] The protective layer (140) can prevent problems such as oxidation or peeling of the build-up structure due to penetration of moisture and / or external contaminants. In addition, the protective layer is formed of a material with low solder wettability to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridging short circuits between adjacent solders.

[0075] In addition, the protective layer (140) includes an insulating material, and may include various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. In addition, the protective layer (140) may be a resist layer, and for example, the protective layer (140) may include an epoxy acrylate series resin. In detail, the protective layer (140) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the protective layer (140) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0076] Meanwhile, a plating layer (150) may be disposed on the first wiring layer (131) disposed on the outermost surface of the circuit board. The plating layer (150) may be formed on the first wiring layer (131) through a surface treatment process. For example, the surface treatment process may be, but is not limited to, ENIG (Electroless Nikel Immersion Gold) or ENEPIG (Electroless Nickel Immersion Gold).

[0077] The plating layer (150) can prevent corrosion of the first wiring layer (131) and can improve signal transmission speed by reducing electrical resistance when electrically connected to a connection part (not shown).

[0078] In addition, the plating layer (150) may include a different material from the first wiring layer (131). In addition, the plating layer (150) may include a plurality of layers. For example, the plating layer (150) may include any one of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), but is not limited thereto.

[0079]

[0080] Figures 4a and 4b are process diagrams illustrating the manufacturing process of one area (A1) of Figure 3. First, referring to Figure 4a, a pad (130) may be placed on an insulating layer (110). The pad (130) may be a wiring layer placed on the outermost surface of a circuit board. The pad (130) may include copper (Cu), but is not limited thereto.

[0081] Additionally, a protective layer (140) having an opening (145) may be placed on the pad (130).

[0082] Meanwhile, in the embodiment, N2baking using nitrogen (N2) may be performed during thermal curing of the protective layer (140). Accordingly, the protective layer (140) may be cured, and an oxide film may not be formed on the pad (130).

[0083] Next, in the surface treatment process of the pad (130), a concave portion (160) may be formed by etching a portion of the pad (130). The concave portion (160) may include a first concave portion (162) and a second concave portion (164) disposed on the first concave portion (162).

[0084] In detail, the first concave portion (162) may have a concave shape in a downward direction from the upper surface of the pad (130). In addition, the second concave portion (164) may have a concave shape in a lateral direction from the upper surface of the pad (130). The second concave portion (164) may have a ring shape surrounding the first concave portion (162), but is not limited thereto.

[0085] The first concave portion (162) may overlap vertically with the opening (145) of the protective layer (140). In addition, the second concave portion (164) may not overlap vertically with the opening (145) of the protective layer (140).

[0086] Additionally, the first concave portion (162) and the second concave portion (164) may be positioned at different heights. The first concave portion (162) may be positioned lower than the second concave portion (164). The first concave portion (162) may be closer to the lower surface of the pad (130) or the insulating layer (110) than the second concave portion (164).

[0087] Additionally, a step may be formed between the first concave portion (162) and the second concave portion (164), but is not limited thereto.

[0088] Additionally, the first concave portion (162) may include a first region that vertically overlaps the first concave portion (162) and the protective layer (140).

[0089] Additionally, the second concave portion (164) may be a donut shape or a square ring shape having a horizontal width (L2). Additionally, the second concave portion (164) may be a micro-raised area or a haloing area between the pad (130) and the protective layer (140). The horizontal width (L1) of the first area of ​​the first concave portion (162) may be smaller than the horizontal width (L2) of the second concave portion (164).

[0090] Meanwhile, in the embodiment, as the protective layer (140) is hardened by nitrogen (N2) baking, an oxide film is not formed on the pad (130), and the horizontal width (L2) of the second concave portion (164) formed by etching can be significantly reduced.

[0091] In detail, the sum of the horizontal width (L1) of the first region and the horizontal width (L2) of the second concave portion (164) may be smaller than the first thickness (T1) of the protective layer (140). In this case, the first thickness (T1) of the protective layer (140) may be the length from the upper surface of the protective layer (140) to the upper surface of the insulating layer (110) or the length from the upper surface of the protective layer (140) to the lower surface of the pad (130).

[0092] Additionally, the sum of the horizontal width (L1) of the first region of the first concave portion (162) and the horizontal width (L2) of the second concave portion (164) may be within a range of 20% to 80% of the first thickness (T1) of the protective layer (140).

[0093] Accordingly, the embodiment has a technical effect that the aesthetics can be improved by reducing the micro-raised or haloed area in the circuit board, and the lifting and peeling problems of the protective layer (140) can be prevented.

[0094]

[0095] Next, referring to FIG. 4b, a plating layer (150) can be formed on the pad (130). The plating layer (150) can prevent corrosion of the pad (130) and, when electrically connected to a connecting portion (not shown), can reduce electrical resistance to improve signal transmission speed.

[0096] The plating layer (150) may include a different material from the pad (130). In addition, the plating layer (150) may include multiple layers. For example, the plating layer (150) may include any one of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), but is not limited thereto.

[0097] The plating layer (150) may be disposed on a portion of the concave portion (160). The plating layer (150) may be disposed within the first concave portion (162). In addition, the upper surface of the plating layer (150) may be positioned lower than the lower surface of the second concave portion (164). A portion of the plating layer (150) may vertically overlap the protective layer (140).

[0098] In addition, in the embodiment, when a connecting portion (not shown) such as a solder is placed on the pad (130), the connecting portion (not shown) may be placed so as to be in direct contact with the plating layer (150) placed within the first recess (162) and fill the second recess (164). (See FIG. 7)

[0099] Accordingly, the embodiment has a technical effect that the second concave portion (164) can serve as an anchor and thus improve the fixing force of the connection portion (190) as the connection portion (not shown) is positioned not only in contact with the plating layer (150) but also within the second concave portion (164). In addition, the embodiment has a technical effect that when the connection portion is positioned within the second concave portion (164), the adhesive force between the protective layer (140) and the pad (130) is further improved by the connection portion, thereby improving the mechanical reliability of the circuit board.

[0100]

[0101] Figures 5 to 6b are drawings observing the hollowing area of ​​a circuit board. First, Figure 5 (a) shows the hollowing area (H1) of the circuit board being internally studied, and Figure 5 (b) is a drawing showing the hollowing area (H2) of the circuit board according to an embodiment.

[0102] In (a) of Fig. 5, a protective layer (140) is placed to cover a portion of a pad (not shown), and a plating layer (150) may be placed on the exposed pad. Meanwhile, when etching an oxide film formed on the pad before forming the plating layer, a first hollowing region (H1), which is a micro-lifted region of the protective layer (140) and the pad, may be formed.

[0103] On the other hand, in (b), nitrogen baking (N2baking) is performed during hardening of the protective layer (140) to prevent the formation of an oxide film on the pad, and accordingly, the second hollowing region (H2) formed between the pad and the protective layer (140) can be formed to have a significantly smaller width than the first hollowing region (H1).

[0104] Accordingly, the embodiment has a technical effect of improving the freedom and aesthetics of design by minimizing the micro-raised area or haloing area between the pad and the protective layer, and improving the adhesive strength between the pad and the protective layer.

[0105] Additionally, Fig. 6a shows a hollowing area (H1) in a circuit board being studied internally, and Fig. 6b is a drawing showing a hollowing area (H2) of a circuit board according to an embodiment.

[0106] In FIG. 6a, the area from one end of the protective layer (140) to one area (A2) may be a first hollowing area (H1) where delamination or micro-lifting of the protective layer occurs. In addition, in FIG. 6b, the area from one end of the protective layer (140) to one area (A3) may be a second hollowing area (H2) where delamination or micro-lifting of the protective layer occurs.

[0107] Referring to FIGS. 6a and 6b, the embodiment has a technical effect of minimizing the hollowing area during the surface treatment process by preventing the formation of an oxide film between the pad (130) and the protective layer (140) by curing the protective layer (140) through nitrogen curing (N2baking).

[0108]

[0109] FIG. 7 is a cross-sectional view of a semiconductor package (101) according to an embodiment. Referring to FIG. 7, the semiconductor package (101) according to the embodiment may include a chip (200) placed on a circuit board. In detail, a connection portion (190) may be placed on a first wiring layer (131) exposed by a protective layer (140) on the outermost layer of the circuit board. The connection portion (190) may have a spherical shape. In addition, a cross-section of the connection portion (190) may have a circular shape or a semicircular shape. The connection portion (190) may be a solder ball, but is not limited thereto.

[0110] Meanwhile, in the embodiment, a concave portion (160) is disposed on the first wiring layer (131), and a plating layer may be disposed on a part of the concave portion (160). In detail, the concave portion (160) may include a first concave portion in which a plating layer (150) is disposed, and a second concave portion disposed between the protective layer (140) and the first wiring layer (131).

[0111] Accordingly, when a connecting portion (190) such as a solder is arranged, the connecting portion (190) can be arranged in the second concave portion (164) while in contact with the plating layer (150). Therefore, the embodiment has a technical effect in that the second concave portion (164) can perform an anchor function to improve the fixing force of the connecting portion (190), and the bonding force between the protective layer (140) and the first wiring layer (131) can be improved through the connecting portion (190).

[0112] In addition, a chip (200) or a component may be included on the connection portion (190) of the circuit board. The chip (200) may be a processor chip. For example, the chip (200) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal (205) may be included on the bottom surface of the chip (200), and the terminals (205) may be included in multiple numbers.

[0113] The terminal (205) of the chip (200) can be electrically connected to the connection portion (190) of the circuit board.

[0114] Meanwhile, the semiconductor package (103) of the embodiment may include a plurality of chips that are horizontally spaced apart from each other and arranged on a single circuit board. For example, the chip (200) may also include a first chip and a second chip. The first chip and the second chip may be different types of application processor (AP) chips.

[0115] Additionally, the connection portion located at the bottom of the semiconductor package (101) of the embodiment may be for connecting a main board (or motherboard) of an external device.

[0116] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0117] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0118] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0119] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. Insulating layer; A pad disposed on the above insulating layer; A protective layer disposed on the above pad and having an opening; and A concave portion disposed on the upper surface of the above pad; The above concave portion includes a first concave portion and a second concave portion disposed on the first concave portion, A circuit board comprising a plating layer disposed within the first concave portion.

2. In paragraph 1, The above first concave portion has a concave shape from the upper surface of the pad to the lower surface, A circuit board, wherein the second concave portion has a concave shape laterally from the upper surface of the pad.

3. In paragraph 1, A circuit board wherein the horizontal width of the first concave portion is greater than the horizontal width of the opening.

4. In paragraph 1, A circuit board wherein the plating layer vertically overlaps the protective layer.

5. In paragraph 1, A circuit board in which a step is arranged between the first concave portion and the second concave portion.

6. In paragraph 1, A circuit board, wherein the width of the first region vertically overlapping the first concave portion and the protective layer is smaller than the width of the second concave portion in the horizontal direction.

7. In paragraph 6, A circuit board, wherein the sum of the width of the first region and the horizontal width of the second concave portion is smaller than the thickness of the protective layer.

8. In paragraph 7, A circuit board, wherein the sum of the width of the first region and the horizontal width of the second concave portion is 20% to 80% of the thickness of the protective layer.

9. In paragraph 1, Includes a connection portion connected to the above plating layer, A circuit board, wherein the above connection portion is positioned within the second concave portion.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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