Array substrate, display panel and temperature measurement method therefor, display apparatus and head-up display system

Abstract

An array substrate (1), comprising a display area (AA) and a peripheral area (NA), a binding area (BA) being provided in the peripheral area (NA), and a plurality of temperature measurement areas (TA) being provided in the display area (AA). The array substrate (1) comprises: a base substrate (10); a plurality of temperature sensing coils (20) located on the base substrate (10), the plurality of temperature sensing coils (20) being respectively located in the plurality of temperature measurement areas (TA); and a plurality of signal transmission parts (30) located on the base substrate (10), the plurality of signal transmission parts (30) being respectively and electrically connected to the plurality of temperature sensing coils (20), each signal transmission part (30) comprising a first wire (31) and a second wire (32), the first wires (31) being electrically connected to input ends of the temperature sensing coils (20) and extending to the binding area (BA), and the second wires (32) being electrically connected to output ends of the temperature sensing coils (20) and extending to the binding area (BA). The array substrate (1) further comprises a plurality of signal lines (SL), the orthographic projections of the temperature sensing coils (20) on the base substrate (10) at least partially coinciding with the orthographic projections of the signal lines (SL) on the base substrate (10).

Description

Array substrate, display panel and temperature measurement method thereof, display device and head-up display system Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a temperature measurement method thereof, a display device and a head-up display system. Background Art

[0002] In some usage scenarios, the display area of ​​the display panel will be exposed to a fixed-size solar spot, causing a severe local temperature rise, resulting in display abnormalities or hardware damage. In this case, if the temperature sensor detection area does not pass through the spot or the detection area does not cover the entire panel, the specific temperature of the temperature-rising area cannot be accurately detected, resulting in temperature recognition errors.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, an array substrate is provided.

[0005] The array substrate includes a display area and a peripheral area located around the display area. The display area is provided with a plurality of temperature test areas, and the plurality of temperature test areas are arranged along a first direction and / or a second direction. The peripheral area is provided with a binding area, and the binding area is located on one side of the display area along the second direction. The array substrate includes:

[0006] substrate;

[0007] a plurality of temperature sensing coils located on the substrate, wherein the plurality of temperature sensing coils are respectively located in the plurality of temperature testing areas; and

[0008] a plurality of signal transmission parts located on the substrate, the plurality of signal transmission parts being electrically connected to the plurality of temperature sensing coils, the signal transmission parts comprising a first trace and a second trace, one end of the first trace being electrically connected to the input end of the temperature sensing coil, the other end of the first trace extending to the binding area, one end of the second trace being electrically connected to the output end of the temperature sensing coil, the other end of the second trace extending to the binding area;

[0009] In which, the array substrate also includes a plurality of signal lines located on the array substrate, the plurality of signal lines are arranged along the first direction and extend along the second direction, and the orthographic projection of the temperature sensing coil on the base substrate at least partially overlaps with the orthographic projection of the signal lines on the base substrate.

[0010] According to some exemplary embodiments, the display area includes a plurality of sub-pixel opening areas and non-opening areas located between adjacent sub-pixel opening areas, and the sub-pixel opening areas include a light-transmitting area and a non-light-transmitting area;

[0011] Wherein, at least a portion of the temperature sensing coil is located in the non-opening area, and / or at least a portion of the temperature sensing coil is located in the non-light-transmitting area.

[0012] According to some exemplary embodiments, the temperature sensing coil includes a plurality of sensing traces, a plurality of first connecting segments, and a plurality of second connecting segments, wherein the plurality of sensing traces are arranged along the first direction and extend along the second direction;

[0013] Two adjacent sensing lines whose ends are away from the binding area are electrically connected via the first connecting segment, and two adjacent sensing lines whose ends are close to the binding area are electrically connected via the second connecting segment, and the plurality of first connecting segments and the plurality of second connecting segments are alternately electrically connected to the two adjacent sensing lines; and

[0014] The orthographic projections of the plurality of sensing traces on the substrate at least partially overlap with the orthographic projections of the plurality of signal traces on the substrate.

[0015] According to some exemplary embodiments, the array substrate includes a plurality of scan lines located on the base substrate, the plurality of scan lines are arranged along the second direction and extend along the first direction;

[0016] The orthographic projection of the first connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate; and / or

[0017] The orthographic projection of the second connecting segment on the base substrate is adjacent to and spaced from the orthographic projection of the scanning line on the base substrate.

[0018] According to some exemplary embodiments, at least one first dummy routing segment is further provided between two adjacent sensing routing lines, the first dummy routing segment is spaced apart from the two adjacent sensing routing lines, and the orthographic projection of the first dummy routing segment on the substrate is adjacent to and spaced apart from the orthographic projection of the scanning line on the substrate.

[0019] According to some exemplary embodiments, of the two temperature sensing coils adjacent to each other along the second direction, at least a portion of the signal transmission portion electrically connected to the temperature sensing coil farther from the binding area is located in the temperature testing area where the temperature sensing coil closer to the binding area is located;

[0020] In two temperature testing areas adjacent to each other along the second direction, both temperature testing areas include a dummy area, the temperature sensing coil is located in an area of ​​the temperature testing area other than the dummy area, an extension length of the temperature sensing coil in one temperature testing area is substantially equal to an extension length of the temperature sensing coil in the other temperature testing area, and an area of ​​the dummy area closer to the binding area is smaller than an area of ​​the dummy area farther from the binding area; or

[0021] Among the two temperature testing areas adjacent to each other along the second direction, only the temperature testing area farther away from the binding area includes a dummy area, the temperature sensing coil is located in an area other than the dummy area within the temperature testing area, and an extension length of the temperature sensing coil within one of the temperature testing areas is substantially equal to an extension length of the temperature sensing coil within the other of the temperature testing areas.

[0022] According to some exemplary embodiments, at least one second dummy routing segment and at least one third dummy routing segment are provided in the dummy area;

[0023] The orthographic projection of the second dummy routing segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate, and the orthographic projection of the second dummy routing segment on the substrate is located between the orthographic projections of the two signal routing lines on the substrate;

[0024] The orthographic projection of the third dummy routing segment on the substrate at least partially overlaps with the orthographic projection of the signal routing segment on the substrate, and the orthographic projection of the third dummy routing segment on the substrate is located between the orthographic projections of the two scan lines on the substrate.

[0025] According to some exemplary embodiments, the plurality of temperature sensing coils arranged along the second direction include a distal temperature sensing coil farthest from the binding area and at least one proximal temperature sensing coil located on a side of the distal temperature sensing coil close to the binding area;

[0026] In which, the signal transmission part electrically connected to the proximal temperature sensing coil has a compensation coil located in the peripheral area, and among the two proximal temperature sensing coils adjacent along the second direction, the resistance of the compensation coil electrically connected to the proximal temperature sensing coil farther away from the binding area is smaller than the resistance of the compensation coil electrically connected to the proximal temperature sensing coil closer to the binding area.

[0027] According to some exemplary embodiments, the array substrate further includes a gate metal layer located on the base substrate, a source-drain metal layer located on a side of the gate metal layer away from the base substrate, a common electrode layer located on a side of the source-drain metal layer away from the base substrate, and a sensing metal layer located between the source-drain metal layer and the common electrode layer, and the temperature sensing coil and the signal transmission part are located in the sensing metal layer.

[0028] According to some exemplary embodiments, the common electrode layer includes a common electrode, and an orthographic projection of the common electrode on the base substrate covers at least a portion of an orthographic projection of the temperature sensing coil on the base substrate.

[0029] According to some exemplary embodiments, the plurality of signal lines include a plurality of data lines and a plurality of common electrode lines, and the plurality of data lines and the plurality of common electrode lines are alternately arranged along the first direction;

[0030] The orthographic projection of the sensing trace on the base substrate at least partially overlaps with the orthographic projection of the common electrode line on the base substrate.

[0031] According to some exemplary embodiments, the array substrate further includes a pixel electrode layer located on the base substrate, the pixel electrode layer including a plurality of pixel electrodes; and

[0032] The plurality of scan lines include a plurality of scan line groups, each scan line group includes two scan lines, and an orthographic projection of the scan line group on the base substrate is located between orthographic projections of two adjacent pixel electrodes along the second direction on the base substrate;

[0033] Wherein, at least a portion of the orthographic projection of the first connecting segment on the substrate is located between the orthographic projections of two scanning lines in the scanning line group on the substrate; and / or

[0034] At least a portion of an orthographic projection of the second connecting segment on the substrate is located between orthographic projections of two scanning lines in the scanning line group on the substrate.

[0035] According to some exemplary embodiments, the common electrode line is located in the source / drain metal layer, the array substrate includes a first passivation layer located between the source / drain metal layer and the sensing metal layer, and a second passivation layer located between the sensing metal layer and the common electrode layer, the first passivation layer and the second passivation layer have vias therein, the vias exposing a portion of the common electrode line, the common electrode layer includes a common electrode, and the common electrode is electrically connected to the common electrode line through the vias;

[0036] The sensing trace includes a plurality of sensing segments arranged along the second direction, two adjacent sensing segments are electrically connected via a connecting portion, and an orthographic projection of the connecting portion on the base substrate is spaced apart from an orthographic projection of the via on the base substrate.

[0037] According to some exemplary embodiments, the connecting portion is ring-shaped, and an orthographic projection of the via hole on the base substrate is located within an orthographic projection of the connecting portion on the base substrate.

[0038] According to some exemplary embodiments, the plurality of signal traces include a plurality of data lines, and an orthographic projection of the sensing trace on the substrate at least partially overlaps with an orthographic projection of the data line on the substrate.

[0039] According to some exemplary embodiments, the array substrate further includes a pixel electrode layer located on the base substrate, the pixel electrode layer including a plurality of pixel electrodes; and

[0040] The pixel electrode includes a first electrode portion and a second electrode portion connected along the second direction, the first electrode portion extends along a third direction, the second electrode portion extends along a fourth direction, and the third direction intersects the fourth direction;

[0041] The orthographic projection of the edge where the first electrode portion and the second electrode portion are connected on the base substrate is located within the orthographic projection of the first connecting section on the base substrate; and / or

[0042] An orthographic projection of an edge connecting the first electrode portion and the second electrode portion on the base substrate is located within an orthographic projection of the second connecting segment on the base substrate.

[0043] According to some exemplary embodiments, the first trace includes a first trace segment located in the display area, one end of the first trace segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and

[0044] The second routing segment includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction toward the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

[0045] According to some exemplary embodiments, the first trace includes a first trace segment located in the display area, one end of the first trace segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and

[0046] The second routing segment includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction away from the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

[0047] According to some exemplary embodiments, the first routing segment includes at least two first routing sub-segments, the two first routing sub-segments are electrically connected via at least one third connecting segment, the orthographic projections of the two first routing sub-segments on the substrate at least partially overlap with the orthographic projections of two adjacent signal routing lines on the substrate, respectively, and the orthographic projection of the third connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate; and / or

[0048] The third routing segment includes at least two third routing sub-segments, the two third routing sub-segments are electrically connected via at least one fourth connecting segment, the orthographic projections of the two third routing sub-segments on the substrate at least partially overlap with the orthographic projections of two adjacent signal routing lines on the substrate, respectively, and the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

[0049] According to some exemplary embodiments, the plurality of temperature test areas include at least one special-shaped temperature test area, wherein of the two sides of the special-shaped temperature test area located on both sides of the second direction, an extension direction of one side is parallel to the first direction, and an extension direction of the other side intersects with the first direction or the other side is a curved side.

[0050] The special-shaped temperature test area includes a test area, the test area is rectangular in shape, the temperature sensing coil is located in the test area, and the lengths of the sensing lines along the second direction are substantially equal;

[0051] or

[0052] The sensing coil is located in the special-shaped temperature test area, and the lengths of at least two sensing lines along the second direction are different from each other.

[0053] According to some exemplary embodiments, the array substrate further includes at least one peripheral temperature sensing coil located in the peripheral area, the input end of the peripheral temperature sensing coil being electrically connected to the input terminal in the binding area through an input trace, the input trace being used to connect the driving signal provided by the input terminal to the peripheral temperature sensing coil, the output end of the peripheral temperature sensing coil being electrically connected to the output terminal in the binding area through an output trace, the output trace being used to transmit the sensing signal generated by the peripheral temperature sensing coil to the output terminal.

[0054] In another aspect, a display panel is provided, comprising the array substrate as described above.

[0055] In another aspect, a display device is provided, comprising the display panel as described above.

[0056] In another aspect, a head-up display system is provided, comprising the display panel and the optical path magnifying element as described above.

[0057] According to some exemplary embodiments, the optical path magnifying element includes a concave mirror.

[0058] In another aspect, a method for measuring the temperature of a display panel is provided, which is used for the display panel described above, and the method comprises:

[0059] Inputting a driving signal to an input end of the temperature sensing coil;

[0060] Acquiring a sensing signal outputted from an output end of the temperature sensing coil; and

[0061] The temperature of the temperature test area where the temperature sensing coil is located is obtained according to the sensing signal.

[0062] According to some exemplary embodiments, inputting a driving signal to an input terminal of the temperature sensing coil includes:

[0063] When the display panel is in a display phase, a first drive signal is input to the input end of the temperature sensing coil, wherein the first drive signal is a common electrode voltage signal; and when the display panel is in a non-display phase, a second drive signal is input to the input end of the temperature sensing coil, wherein a voltage value of the second drive signal is greater than a voltage value of the first drive signal; and

[0064] The acquiring of the sensing signal outputted from the output end of the temperature sensing coil comprises:

[0065] When the display panel is in a non-display stage, acquiring the sensing signal output by the temperature sensing coil in response to the second driving signal; or

[0066] The step of inputting a driving signal to the input end of the temperature sensing coil comprises:

[0067] When the display panel is in a display stage and / or a non-display stage, inputting a second driving signal to an input end of the temperature sensing coil; and

[0068] The acquiring of the sensing signal outputted from the output end of the temperature sensing coil comprises:

[0069] When the display panel is in a display stage and / or a non-display stage, the sensing signal output by the temperature sensing coil in response to the second driving signal is acquired. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0071] FIG1A schematically shows a plan view of pixel arrangement of an array substrate according to some embodiments of the present disclosure.

[0072] FIG1B schematically shows a plan view of pixel arrangement of an array substrate according to some other embodiments of the present disclosure.

[0073] FIG2A schematically shows a plan view of an array substrate according to some embodiments of the present disclosure.

[0074] FIG2B schematically shows a plan view of an array substrate according to some other embodiments of the present disclosure.

[0075] FIG2C schematically shows a plan view of an array substrate according to still other embodiments of the present disclosure.

[0076] FIG2D schematically shows a plan view of an array substrate according to some further embodiments of the present disclosure.

[0077] FIG3 schematically shows an enlarged view of the region S1 in FIG2A .

[0078] FIG4 schematically shows an enlarged view of the region S2 in FIG2A .

[0079] FIG. 5 schematically shows an enlarged view of the region S3 in FIG. 4 .

[0080] FIG. 6 schematically shows an enlarged view of the region S10 in FIG. 2A .

[0081] FIG. 7 schematically shows an enlarged view of the region S4 in FIG. 4 .

[0082] FIG. 8 schematically shows an enlarged view of region S5 of the array substrate in FIG. 7 according to an embodiment of the present disclosure.

[0083] FIG. 9 schematically shows a schematic diagram taken along line AA′ in FIG. 8 .

[0084] FIG. 10A schematically shows a schematic diagram taken along line BB′ in FIG. 8 .

[0085] FIG. 10B schematically shows a schematic diagram taken along line CC′ in FIG. 8 .

[0086] FIG. 11 schematically shows an enlarged view of region S6 of the array substrate in FIG. 7 according to an embodiment of the present disclosure.

[0087] FIG. 12 schematically shows an enlarged view of region S7 of the array substrate in FIG. 7 according to an embodiment of the present disclosure.

[0088] FIG. 13A schematically shows an enlarged view of region S8 in FIG. 7 of an array substrate according to another embodiment of the present disclosure.

[0089] FIG13B schematically shows an enlarged view of region S9 in FIG7 .

[0090] FIG. 14 schematically shows an enlarged view of area S11 in FIG. 7 .

[0091] FIG15 schematically shows a plan view of pixel arrangement of an array substrate according to some other embodiments of the present disclosure.

[0092] FIG. 16 schematically shows an enlarged view of region S5 in FIG. 7 of an array substrate according to another embodiment of the present disclosure.

[0093] FIG17 schematically shows an enlarged view of region S5 in FIG7 of an array substrate according to yet another embodiment of the present disclosure.

[0094] FIG. 18 schematically illustrates a distribution diagram of temperature test areas in a display area of ​​an array substrate according to some embodiments of the present disclosure.

[0095] FIG. 19 schematically illustrates a distribution diagram of temperature sensing coils in a special-shaped temperature test area of ​​an array substrate according to some embodiments of the present disclosure.

[0096] FIG. 20 schematically shows a distribution diagram of temperature sensing coils in a special-shaped temperature test area of ​​an array substrate according to some other embodiments of the present disclosure.

[0097] FIG. 21 schematically illustrates a planar area of ​​a peripheral temperature sensing coil of an array substrate according to some embodiments of the present disclosure.

[0098] FIG22 schematically shows a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0099] FIG23 schematically shows a flow chart of a method for measuring the temperature of a display panel according to an embodiment of the present disclosure.

[0100] FIG24 schematically shows a timing diagram of driving signals in a temperature measurement method for a display panel according to an embodiment of the present disclosure.

[0101] FIG25 schematically shows a timing diagram of driving signals in another method for measuring the temperature of a display panel according to an embodiment of the present disclosure.

[0102] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0103] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0104] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0105] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0106] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0107] Figure 1A schematically shows a plan view of pixel arrangement of an array substrate according to some embodiments of the present disclosure. Figure 1B schematically shows a plan view of pixel arrangement of an array substrate according to other embodiments of the present disclosure.

[0108] According to one embodiment of the present disclosure, an array substrate is provided. Referring to FIG. 1A or FIG. 1B , the array substrate may include a base substrate and a plurality of sub-pixels P located on the base substrate. The plurality of sub-pixels P are arranged in an array on the base substrate 10, i.e., including a plurality of rows of sub-pixels P and a plurality of columns of sub-pixels P. For ease of description herein, the horizontal direction in FIG. 1A is referred to as a first direction X, i.e., a row direction, and the vertical direction in FIG. 1A is referred to as a second direction Y, i.e., a column direction.

[0109] For example, the array substrate may include a plurality of scan lines GL extending along a first direction X and arranged along a second direction Y, and a plurality of signal lines SL extending along the second direction Y and arranged along the first direction X. The plurality of signal lines SL and the plurality of scan lines GL respectively intersect to define a plurality of sub-pixels P.

[0110] FIG2A schematically shows a plan view of an array substrate according to some embodiments of the present disclosure.

[0111] Referring to Figure 2A , the array substrate includes a display area AA and a peripheral area NA located around the display area AA. Multiple temperature test areas TA are arrayed within the display area AA. The temperature test areas TA are arranged along a first direction X and a second direction Y. For example, the temperature test areas TA may be rectangular, trapezoidal, triangular, or other shapes. The area of ​​the temperature test areas TA is determined based on the actual required temperature test accuracy. A smaller area of ​​the temperature test areas TA results in higher test accuracy.

[0112] For example, when the array substrate is used in a head-up display device, an optical path amplification element is provided in the head-up display device, and the optical path amplification element may include a concave mirror. The concave mirror also has the property of optical focusing, and the sunlight irradiating the array substrate will be converged by the concave mirror to form a sun spot. Based on this, in order to accurately identify the problem of local overtemperature caused by the sun spot, the area of ​​the temperature test area TA can be set to be approximately equal to the area of ​​the sun spot, or the area of ​​the temperature test area TA can be set to be smaller than the area of ​​the sun spot. For example, the shape of the sun spot is approximately circular with a diameter of 10 mm. Based on the size of this sun spot, the size of the temperature test area TA along the first direction X is set to be less than or equal to 10 mm, and the size of the temperature test area TA along the second direction Y is set to be less than or equal to 10 mm.

[0113] In some embodiments, the array substrate also includes multiple temperature sensing coils 20, and the multiple temperature sensing coils 20 are respectively located in multiple temperature testing areas TA. The multiple temperature sensing coils 20 are respectively used to test the temperature of the parts of the array substrate located in the multiple temperature testing areas TA, thereby realizing regional temperature detection of the array substrate.

[0114] Continuing with reference to Figure 2A, the array substrate includes a plurality of signal transmission units 30. The signal transmission unit 30 includes a first trace 31 and a second trace 32. One end of the first trace 31 is electrically connected to the input end of the temperature sensing coil 20, and the other end of the first trace 31 extends into the binding area BA and is electrically connected to the input terminal located in the binding area BA. The first trace 31 is used to receive the drive signal provided by the input terminal and connect the drive signal to the temperature sensing coil 20. One end of the second trace 32 is electrically connected to the output end of the temperature sensing coil 20, and the other end of the second trace 32 extends into the binding area BA and is electrically connected to the output terminal located in the binding area BA. The second trace 32 is used to receive the sensing signal generated by the temperature sensing coil 20 in response to the driving signal and transmit the sensing signal to the output terminal.

[0115] In some embodiments, the positions of the output end and the input end of the temperature sensing coil 20 can be exchanged according to actual needs, that is, the output end of the temperature sensing coil 20 is electrically connected to the first trace 31, and the input end of the temperature sensing coil 20 is electrically connected to the second trace 32.

[0116] In some embodiments, the binding area BA is located in the peripheral area NA, and the binding area BA is located at one side of the display area AA along the second direction Y.

[0117] In some embodiments, the input terminals and output terminals within the binding region are electrically connected to a flexible printed circuit board (FPC), which is in turn electrically connected to a printed circuit board (PCB). The temperature detection circuit is disposed on the PCB, i.e., the PCB is connected to a temperature sensing coil located within the array substrate via the FPC. The temperature detection circuit disposed within the PCB connects a drive signal to the input terminal of the temperature sensing coil via the FPC, and acquires a sensing signal outputted from the output terminal of the temperature sensing coil via the FPC. Finally, the temperature of the portion of the array substrate corresponding to the temperature test region is determined based on the sensing signal.

[0118] In some embodiments, the flexible circuit board for transmitting temperature detection related signals and the flexible circuit board for transmitting display related signals may be integrated into one flexible circuit board to reduce the layout space of the flexible circuit boards.

[0119] In some embodiments, the temperature detection circuit may also be directly placed in the peripheral area of ​​the array substrate. For example, the input terminals and output terminals in the binding area are electrically connected to a driver chip, and the driver chip is provided with the temperature detection circuit.

[0120] According to some exemplary embodiments, the display area includes a plurality of sub-pixel opening areas and a non-opening area located between adjacent sub-pixel opening areas, and the sub-pixel opening area includes a light-transmitting area and a non-light-transmitting area. Exemplarily, the temperature sensing coil is disposed in the non-opening area, or a portion of the temperature sensing coil is disposed in the non-opening area and another portion is disposed in the non-light-transmitting area, or the temperature sensing coil is disposed in the non-light-transmitting area. That is, the temperature sensing coil is disposed in an area of ​​the array substrate that is not used for display, thereby avoiding the problem of the display effect being affected by the installation of the temperature sensing coil.

[0121] According to some exemplary embodiments, referring to FIG. 2A , a plurality of temperature test areas TA may be arranged in a dense array, with adjacent temperature test areas TA directly connected along a first direction X, and adjacent temperature test areas TA directly connected along a second direction Y. In other words, the display area AA may be divided into a plurality of temperature test areas TA based on actual testing requirements, thereby enabling complete zoned temperature monitoring of the portion of the array substrate located in the display area AA.

[0122] FIG2B schematically shows a plan view of an array substrate according to some other embodiments of the present disclosure.

[0123] According to some exemplary embodiments, it is also possible to use only part of the display area as a temperature test area based on actual needs. For example, only the location where the probability of sun spots appearing is higher can be used as a temperature test area and a temperature sensing coil can be set. For example, referring to Figure 2B, multiple temperature test areas TA are provided in the display area AA, and there is a certain spacing distance between adjacent temperature test areas TA. According to this arrangement, the layout space of the signal transmission unit 30 in the peripheral area NA can be reduced, and the area of ​​the binding area BA for arranging the output terminal and the input terminal can also be reduced. In addition, the processing complexity of calculating the corresponding temperature information based on the sensing signal output by each temperature sensing coil 20 is also reduced.

[0124] According to some exemplary embodiments, referring to FIG. 2B , to ensure wiring uniformity within the display area AA, dummy wiring may be provided in the spacing area between the temperature test areas TA. The manner of providing the dummy wiring will be described in detail below.

[0125] According to some exemplary embodiments, referring to FIG. 2A , two binding areas BA are provided within the peripheral area NA, and the two binding areas BA are arranged along a first direction X. The peripheral area NA includes a first peripheral area NA1 and a second peripheral area NA2, respectively located on either side of the display area AA along the first direction X. Multiple temperature test areas TA closer to the first peripheral area NA1 (e.g., the nine temperature test areas TA arranged in three rows and three columns on the left side of FIG. 2A ) are electrically connected to the input and output terminals within the binding area BA closer to the first peripheral area NA1. Simultaneously, the signal transmission unit 30 is electrically connected to the end of the temperature sensing coil 20 closer to the first peripheral area NA1. Similarly, multiple temperature test areas TA closer to the second peripheral area NA2 (e.g., the nine temperature test areas TA arranged in three rows and three columns on the right side of FIG. 2A ) are electrically connected to the input and output terminals within the binding area BA closer to the second peripheral area NA2. Simultaneously, the signal transmission unit 30 is electrically connected to the end of the temperature sensing coil 20 closer to the second peripheral area NA2.

[0126] FIG2C schematically shows a plan view of an array substrate according to still other embodiments of the present disclosure.

[0127] According to some exemplary embodiments, referring to FIG. 2C , two binding areas BA are provided within the peripheral area NA, and the two binding areas BA are arranged along a first direction X. The peripheral area NA includes a first peripheral area NA1 and a second peripheral area NA2, respectively located on either side of the display area AA along the first direction X. Multiple temperature test areas TA closer to the first peripheral area NA1 (e.g., the nine temperature test areas TA arranged in three rows and three columns on the left side of FIG. 2A ) are electrically connected to the input and output terminals within the binding area BA closer to the first peripheral area NA1. Simultaneously, the signal transmission unit 30 is electrically connected to the end of the temperature sensing coil 20 away from the first peripheral area NA1. Similarly, multiple temperature test areas TA closer to the second peripheral area NA2 (e.g., the nine temperature test areas TA arranged in three rows and three columns on the right side of FIG. 2A ) are electrically connected to the input and output terminals within the binding area BA closer to the second peripheral area NA2. Simultaneously, the signal transmission unit 30 is electrically connected to the end of the temperature sensing coil 20 away from the second peripheral area NA2.

[0128] It should be noted that the connection position of the temperature sensing coil and the signal transmission part can be set in combination with the position of the binding area, and can be set based on the principle of reducing the length of the first and second lines in the signal transmission part as much as possible, thereby reducing the line resistance of the signal transmission part.

[0129] According to some exemplary embodiments, among the multiple temperature sensing coils arranged along the second direction, the connection positions of the multiple temperature sensing coils and the signal transmission unit can also be arranged alternately along the first direction. For example, among the two temperature sensing coils adjacent to each other along the second direction, the outlet end of one temperature sensing coil is located on one side of the first direction, that is, one end of the temperature sensing coil along the first direction is electrically connected to the signal transmission unit, and the outlet end of the other temperature sensing coil is located on the other side of the first direction, that is, the other end of the temperature sensing coil along the first direction is electrically connected to the signal transmission unit. According to some exemplary embodiments, the display area includes an effective display area and a dummy display area located around the effective display area. During actual display, the sub-pixels within the effective display area are used for display, while the sub-pixels located within the dummy display area are not used for display. The temperature test area close to the peripheral area is located within the effective display area, that is, the temperature sensing coil is also located within the effective display area, and the temperature sensing coil is used to test the temperature of the portion of the array substrate actually used for display.

[0130] According to some exemplary embodiments, based on actual temperature testing requirements, the dummy display area can also be used as part of the temperature testing area, a part of the temperature testing area close to the peripheral area is located in the dummy display area, and the remaining part is located in the effective display area, that is, a part of the temperature sensing coil is located in the dummy display area and the remaining part is located in the effective display area.

[0131] According to some exemplary embodiments, a portion of the temperature test area close to the peripheral area is located in the dummy display area, and the remaining portion is located in the effective display area. The temperature sensing coil is only arranged in the effective display area, and the portion of the temperature test area located in the dummy display area is used to set the dummy routing.

[0132] FIG3 schematically shows an enlarged view of the region S1 in FIG2A .

[0133] Referring to Figure 3 , the orthographic projection of the temperature sensing coil 20 on the base substrate at least partially overlaps with the orthographic projection of the signal trace SL on the base substrate. By overlapping the temperature sensing coil 20 with the signal trace SL in the non-aperture area, the area of ​​the non-aperture area is reduced, thereby increasing the aperture ratio of the array substrate.

[0134] According to some exemplary embodiments, referring to FIG. 3 , the temperature sensing coil 20 has a serpentine routing structure and includes a plurality of sensing traces 21, a plurality of first connecting segments 22, and a plurality of second connecting segments 23. The plurality of sensing traces 21 are arranged along a first direction X and extend along a second direction Y. The ends of two adjacent sensing traces 21 that are away from the binding region are electrically connected by the first connecting segment 22, while the ends of two adjacent sensing traces 21 that are closer to the binding region are electrically connected by the second connecting segment 23. The plurality of first connecting segments 22 and the plurality of second connecting segments 23 alternately electrically connect the two adjacent sensing traces 21.

[0135] FIG4 schematically shows an enlarged view of the region S2 in FIG2A .

[0136] For example, referring to Figure 4, the temperature sensing coil 20 has 12 sensing traces arranged in sequence along the first direction X, and the first sensing trace and the second sensing trace, the third sensing trace and the fourth sensing trace, the fifth sensing trace and the sixth sensing trace, the seventh sensing trace and the eighth sensing trace, the ninth sensing trace and the tenth sensing trace, and the eleventh sensing trace and the twelfth sensing trace are respectively electrically connected through the first connecting section; the second sensing trace and the third sensing trace, the fourth sensing trace and the fifth sensing trace, the sixth sensing trace and the seventh sensing trace, the eighth sensing trace and the ninth sensing trace, and the tenth sensing trace and the eleventh sensing trace are respectively electrically connected through the second connecting section.

[0137] It should be understood that the number of sensing lines is related to the area of ​​the temperature test area and the pixel arrangement of the array substrate. Here, only 12 sensing lines are used to exemplify the connection method of each sensing line in the temperature sensing coil. The array substrate provided in the embodiment of the present disclosure does not limit the number of sensing lines.

[0138] 3 , the orthographic projections of the plurality of sensing traces 21 on the substrate at least partially overlap with the orthographic projections of the plurality of signal traces SL on the substrate. For example, the orthographic projections of the plurality of sensing traces 21 on the substrate are located within the orthographic projections of the plurality of signal traces SL on the substrate.

[0139] According to some exemplary embodiments, referring to FIG. 3 , the orthographic projection of the first connecting segment 22 on the substrate is adjacent to and spaced from the orthographic projection of the scan line GL. That is, the first connecting segment 22 and the scan line GL do not overlap, thereby preventing the signal in the first connecting segment 22 from interfering with the scan signal transmitted in the scan line GL. Furthermore, the spacing between the orthographic projection of the first connecting segment 22 on the substrate and the orthographic projection of the scan line GL on the substrate should not be too large to avoid loss of aperture ratio.

[0140] According to some exemplary embodiments, referring to FIG. 3 , the orthographic projection of the second connecting segment 23 on the substrate is adjacent to and spaced from the orthographic projection of the scan line GL. That is, the second connecting segment 23 and the scan line GL do not overlap, thereby preventing the signal in the second connecting segment 23 from interfering with the scan signal transmitted in the scan line GL. Furthermore, the spacing between the orthographic projection of the second connecting segment 23 on the substrate and the orthographic projection of the scan line GL on the substrate should not be too large to avoid loss of aperture ratio.

[0141] According to some exemplary embodiments, referring to FIG3 , at least one first dummy routing segment 24 is further provided between two adjacent sensing routing lines 21. The first dummy routing segment 24 is spaced apart from the two adjacent sensing routing lines 21, and the orthographic projection of the first dummy routing segment 24 on the substrate is adjacent to and spaced apart from the orthographic projection of the scanning line GL on the substrate. The first dummy routing segment 24 is provided at substantially the same position within the corresponding sub-pixel as the first connecting segment 22 and the second connecting segment 23. By adding the first dummy routing segment 24 at the same position in the sub-pixel where the first connecting segment 22 and the second connecting segment 23 are not provided, the wiring within different sub-pixels remains consistent, thereby improving display uniformity.

[0142] For example, in the area where the temperature sensing coil is provided, a first dummy wiring segment 24 is additionally provided in all sub-pixels that are not provided with the first connecting segment 22 and the second connecting segment 23 .

[0143] According to some exemplary embodiments, the distance between the orthographic projection of the first dummy routing segment 24 on the substrate and the orthographic projection of the nearest scan line GL on the substrate is substantially equal to the distance between the orthographic projection of the first connecting segment 22 on the substrate and the orthographic projection of the nearest scan line GL on the substrate.

[0144] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate close to the binding area, and the orthographic projection of the first connecting segment 22 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate close to the binding area.

[0145] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate away from the binding area, and the orthographic projection of the first connecting segment 22 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate away from the binding area.

[0146] According to some exemplary embodiments, the distance between the orthographic projection of the first dummy routing segment 24 on the substrate and the orthographic projection of the nearest scan line GL on the substrate is substantially equal to the distance between the orthographic projection of the second connecting segment 23 on the substrate and the orthographic projection of the nearest scan line GL on the substrate.

[0147] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate close to the binding area, and the orthographic projection of the second connecting segment 23 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate close to the binding area.

[0148] According to some exemplary embodiments, the orthographic projection of the first dummy routing segment 24 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate away from the binding area, and the orthographic projection of the second connecting segment 23 on the substrate is located on a side of the orthographic projection of the nearest scan line GL on the substrate away from the binding area.

[0149] According to some exemplary embodiments, referring to FIG. 2A in conjunction with FIG. 4 , among two temperature sensing coils 20 adjacent along the second direction Y, at least a portion of the signal transmission portion 30 electrically connected to the temperature sensing coil 20 farther from the binding area BA is located in the temperature test area TA where the temperature sensing coil 20 closer to the binding area BA is located. Specifically, among the three temperature sensing coils 20 schematically illustrated in FIG. 4 , a portion of the signal transmission portion 30 electrically connected to the topmost temperature sensing coil 20 is located in the temperature test areas TA where the middle and bottommost temperature sensing coils 20 are located, while a portion of the signal transmission portion 30 electrically connected to the middle temperature sensing coil 20 is located in the temperature test area TA where the bottommost temperature sensing coil 20 is located. Therefore, a portion of the space within the temperature test areas TA is occupied by the signal transmission portion 30, and the area occupied by the signal transmission portion 30 increases in the temperature test areas TA closer to the binding area BA. In order to ensure that the resistance values ​​of the temperature sensing coils 20 in different temperature test areas TA are substantially equal, it is necessary to set a dummy area TA1 in part of the temperature test area TA. The temperature sensing coils 20 are set in the area other than the dummy area TA1 in the temperature test area TA.

[0150] For example, referring to FIG2A and FIG4 , FIG4 schematically illustrates three temperature test areas TA arranged along the second direction Y. For clarity, the temperature test area TA closest to the binding area is designated as the bottommost temperature test area TA, the temperature test area TA farthest from the binding area is designated as the topmost temperature test area TA, and the remaining temperature test areas TA are designated as middle temperature test areas TA. The bottommost temperature test area TA and the middle temperature test area TA in FIG4 are used for schematic illustration. The bottommost temperature test area TA is closer to the binding area than the middle temperature test area TA. In the two temperature test areas TA adjacent to each other along the second direction Y, the extension length of the temperature sensing coil 20 in one temperature test area TA is basically equal to the extension length of the temperature sensing coil 20 in the other temperature test area TA, so the areas occupied by the two temperature sensing coils 20 are also basically equal. However, since the area occupied by the signal transmission part 30 in the lowermost temperature test area TA is larger, a dummy area TA1 is set in the middle temperature test area TA, that is, in the two temperature test areas TA adjacent to each other along the second direction Y (the temperature test area TA located at the lowermost side and the temperature test area TA located in the middle), the dummy area TA1 is only set in the temperature test area TA that is farther away from the binding area BA.

[0151] For example, referring to FIG4 , the uppermost temperature test area TA and the middle temperature test area TA are schematically illustrated. The uppermost temperature test area TA is further away from the binding area than the middle temperature test area TA. In two temperature test areas TA adjacent along the second direction Y, the extension length of the temperature sensing coil 20 in one temperature test area TA is substantially equal to the extension length of the temperature sensing coil 20 in the other temperature test area TA, and thus the areas occupied by the two temperature sensing coils 20 are also substantially equal. However, because a portion of the middle temperature test area TA is occupied by the signal connection portion 30, the uppermost temperature test area TA does not have a signal transmission portion 30. Therefore, a larger dummy area TA1 is required in the upper temperature test area TA. That is, in the two temperature test areas TA adjacent along the second direction Y (the uppermost temperature test area TA and the middle temperature test area TA), both temperature test areas TA include a dummy area TA1, and the area of ​​the dummy area TA1 closer to the binding area BA is smaller than the area of ​​the dummy area TA1 farther away from the binding area BA.

[0152] In some embodiments, referring to FIG. 4 , among a plurality of temperature test areas TA adjacent to each other along the second direction Y, the temperature test area TA closest to the binding area is not provided with a dummy area TA1, while the remaining temperature test areas TA are provided with dummy areas TA1. Furthermore, in the temperature test areas TA other than the temperature test area TA closest to the binding area, the area of ​​the dummy areas TA1 in the temperature test areas TA closer to the binding area is smaller.

[0153] 4 , the signal transmission portion 30 is located on one side of the temperature sensing coil 20 along the first direction X, and the dummy area TA1 is located on the other side of the temperature sensing coil 20 along the first direction X. In some embodiments, referring to FIG.

[0154] FIG. 5 schematically shows an enlarged view of the region S3 in FIG. 4 .

[0155] According to some exemplary embodiments, to ensure wiring consistency between the area where the temperature sensing coil is located and the dummy area, a dummy routing segment is provided in the dummy area. Referring to Figures 4 and 5 , at least one second dummy routing segment 25 and at least one third dummy routing segment 26 are provided within the dummy area TA1. The second dummy routing segment 25 is positioned consistent with the first and second connecting segments, and its orthographic projection on the substrate is adjacent to and spaced from the orthographic projection of the scan line GL. The third dummy routing segment 26 is positioned consistent with the sensing routing, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the signal line SL.

[0156] According to some exemplary embodiments, the lengths of the second dummy routing segment 25 and the third dummy routing segment 26 should not be too long, otherwise there will be a risk of electrostatic damage. For example, the orthographic projection of the second dummy routing segment 25 on the substrate is located between the orthographic projections of two adjacent signal routing lines SL on the substrate, and the orthographic projection of the third dummy routing segment 26 on the substrate is located between the orthographic projections of two adjacent scanning lines GL on the substrate.

[0157] According to some exemplary embodiments, the orthographic projection of the third dummy trace segment on the substrate may be located between the orthographic projections of two non-adjacent scan lines on the substrate, i.e., the orthographic projection of the third dummy trace segment on the substrate overlaps with the orthographic projection of at least one scan line on the substrate. The length of the third dummy trace segment along the second direction is set according to actual needs. For example, the length of the third dummy trace segment along the second direction may be substantially equal to the length of the temperature test region along the second direction.

[0158] According to some exemplary embodiments, among the multiple temperature sensing coils arranged along the second direction, the lengths of the signal transmission parts electrically connected to different temperature sensing coils are different, and thus the resistances of the different signal transmission parts are also different. In order to prevent the resistance differences between different signal transmission parts from affecting the accuracy of temperature detection, a compensation coil is provided in at least a portion of the signal transmission parts for resistance compensation. Referring to Figure 2A, the multiple temperature sensing coils 20 arranged along the second direction Y include a distal temperature sensing coil 20A farthest from the binding area BA and at least one proximal temperature sensing coil 20B located on the side of the distal temperature sensing coil 20A close to the binding area BA. The signal transmission part 30 electrically connected to the proximal temperature sensing coil 20B has a compensation coil located in the peripheral area. The signal transmission part 30 includes a fan-out trace 34 located in the peripheral area NA. The fan-out trace 34 electrically connects the portion of the signal transmission part 30 located in the display area AA to the binding area, and the compensation coil is provided in the fan-out trace 34.

[0159] Furthermore, of two adjacent proximal temperature sensing coils 20B along the second direction, the resistance of the compensation coil electrically connected to the proximal temperature sensing coil 20B farther from the binding area BA is lower than the resistance of the compensation coil electrically connected to the proximal temperature sensing coil 20B closer to the binding area BA. In this way, the compensated resistance of the signal transmission unit 30 electrically connected to each proximal temperature sensing coil 20B is maintained consistent with the resistance of the signal transmission unit 30 electrically connected to the distal temperature sensing coil 20A.

[0160] FIG. 6 schematically shows an enlarged view of the region S10 in FIG. 2A .

[0161] FIG6 schematically illustrates a portion of the structure of five signal transmission units 30 located in the peripheral area. The leftmost signal transmission unit 30 is electrically connected to the distal temperature sensing coil and, therefore, is not provided with a compensation coil. The remaining four signal transmission units 30 are electrically connected to the proximal temperature sensing coils and, therefore, are each provided with a compensation coil 33. Furthermore, the four signal transmission units 30 with compensation coils 33, from left to right, are electrically connected to the four proximal temperature sensing coils located farther from the binding area, respectively. The extension length of the compensation coils 33 in the signal transmission units 30 electrically connected to the proximal temperature sensing coils farther from the binding area is shorter than the extension length of the compensation coils 33 in the signal transmission units 30 electrically connected to the proximal temperature sensing coils closer to the binding area. Consequently, the resistance of the compensation coils 33 in the signal transmission units 30 electrically connected to the proximal temperature sensing coils farther from the binding area is lower than the resistance of the compensation coils 33 in the signal transmission units 30 electrically connected to the proximal temperature sensing coils farther from the binding area.

[0162] According to some exemplary embodiments, referring to FIG6 , the compensation coil 33 includes a first compensation coil 331 and a second compensation coil 332 . The first compensation coil 331 is disposed in the first trace 21 , and the second compensation coil 332 is disposed in the second trace 22 . The first compensation coil 331 and the second compensation coil 332 are disposed adjacent to each other along the first direction X. The extension length of the first compensation coil 331 is substantially equal to the extension length of the second compensation coil 332 .

[0163] According to some exemplary embodiments, referring to FIG. 6 , the first compensation coil 331 and the second compensation coil 332 are of a serpentine structure wound back and forth along the first direction X.

[0164] Figure 7 schematically shows an enlarged view of region S4 in Figure 4. Figure 8 schematically shows an enlarged view of region S5 in Figure 7 of an array substrate according to one embodiment of the present disclosure. Figure 9 schematically shows a schematic diagram taken along line AA' in Figure 8. Figure 10A schematically shows a schematic diagram taken along line BB' in Figure 8. Figure 10B schematically shows a schematic diagram taken along line CC' in Figure 8.

[0165] According to some exemplary embodiments, in combination with reference to Figures 9, 10A and 10B, the array substrate further includes a gate metal layer Gate located on the base substrate 10, a gate insulating layer GI located on the side of the gate metal layer Gate away from the base substrate 10, a source-drain metal layer SD located on the side of the gate insulating layer GI away from the base substrate 10, a first passivation layer PV1 located on the side of the source-drain metal layer SD away from the base substrate, a sensing metal layer METAL located on the side of the first passivation layer PV1 away from the base substrate, a second passivation layer PV2 located on the side of the sensing metal layer METAL away from the base substrate, and a common electrode layer COM located on the side of the second passivation layer PV2 away from the base substrate.

[0166] For example, the temperature sensing coil and the signal transmission portion are located in the sensing metal layer METAL.

[0167] For example, the first dummy trace segment, the second dummy trace segment, and the third dummy trace segment are located in the sensing metal layer METAL.

[0168] According to some exemplary embodiments, referring to FIG9 , the common electrode layer COM includes a common electrode 50, and the orthographic projection of the common electrode 50 on the base substrate 10 covers at least a portion of the orthographic projection of the temperature sensing coil 20 on the base substrate 10. For example, the orthographic projection of the common electrode 50 on the base substrate 10 covers the orthographic projection of the temperature sensing trace on the base substrate 10. In a display panel manufactured by including the array substrate provided by the embodiment of the present disclosure, the array substrate also has a liquid crystal layer and a color filter substrate. Here, the common electrode 50 can serve as a shielding structure for the temperature sensing coil 20 to prevent the signal in the temperature sensing coil 20 from interfering with the electric field that drives the deflection of the liquid crystal molecules, thereby effectively avoiding the occurrence of light leakage caused by abnormal deflection of the liquid crystal molecules.

[0169] According to some exemplary embodiments, referring to FIG. 1A , FIG. 1B , and FIG. 8 , a dual-scan line drive array substrate is shown, wherein the plurality of signal lines SL include a plurality of data lines DL and a plurality of common electrode lines CL. For example, the plurality of data lines DL and the plurality of common electrode lines CL are alternately arranged along a first direction X. Furthermore, the plurality of data lines DL and the plurality of common electrode lines CL both intersect with the plurality of scan lines GL, respectively, to define a plurality of sub-pixels P.

[0170] For example, a scan line group is provided between two adjacent sub-pixels in the second direction Y. The scan line group includes two scan lines GL, which can be represented by a first scan line GL1 and a second scan line GL2, respectively. A first sub-pixel P1 and a second sub-pixel P2 that are adjacent in the first direction X can form a sub-pixel group. A data line DL is provided between the two adjacent sub-pixel groups in the first direction X. A common electrode line CL is provided between the two sub-pixels P1 and P2 within a sub-pixel group.

[0171] Referring to Figure 1A or Figure 1B, in the sub-pixels in the same row, the thin film transistors of the sub-pixels in the odd columns are connected to the same scan line, such as the first scan line GL1, and the thin film transistors of the sub-pixels in the even columns are connected to the same scan line, such as the second scan line GL2. In two adjacent columns of sub-pixels, the thin film transistors of the two adjacent columns of sub-pixels can be connected to the same data line DL. For example, referring to Figure 1A, the data line DL connected to the thin film transistors of the two adjacent columns of sub-pixels is located on the same side of the two columns of sub-pixels along the first direction X. Alternatively, referring to Figure 1B, the data line DL connected to the thin film transistors of the two adjacent columns of sub-pixels is located between the two columns of sub-pixels. The connection method between the data lines and sub-pixels in the array substrate shown in Figure 8 is the connection method illustrated in Figure 1B.

[0172] When the dual-scan line drive array substrate is working, valid signals can be input on the first scan line GL1 and the second scan line GL2 row by row to turn on the corresponding thin film transistors. Specifically, when the thin film transistors in the odd columns of a row are turned on, the pixel voltage is input to the thin film transistors in the odd columns through the data line DL, and the pixel voltage is transmitted to the pixel electrode to display the corresponding grayscale. When the thin film transistors in the even columns of a row are turned on, the pixel voltage is input to the thin film transistors in the even columns through the data line DL, and the pixel voltage is transmitted to the pixel electrode to display the corresponding grayscale. In the dual-scan line drive mode, the number of scan lines is doubled and the number of data lines is reduced by half, which can reduce the cost of the driver IC; at the same time, the charging time is also reduced to half of that in the single-scan line drive mode, and the charging efficiency needs to be improved.

[0173] 8 and 9 , the orthographic projection of the sensing trace 21 on the substrate at least partially overlaps with the orthographic projection of the common electrode line CL on the substrate. The orthographic projection of the sensing trace 21 on the substrate is spaced apart from the orthographic projection of the data line DL on the substrate.

[0174] According to some exemplary embodiments, referring to FIG8 and FIG9 , the array substrate further includes a pixel electrode layer PIX located between the gate insulating layer GI and the first passivation layer PV1. The pixel electrode layer PIX includes a plurality of pixel electrodes 60. The orthographic projection of the scan line group on the substrate is located between the orthographic projections of two adjacent pixel electrodes 60 along the second direction Y. In particular, at least a portion of the orthographic projection of the first connecting segment 22 on the substrate is located between the orthographic projections of two scan lines GL in the scan line group on the substrate. For example, the entire orthographic projection of the first connecting segment 22 on the substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate. Similarly, at least a portion of the orthographic projection of the second connecting segment 23 on the substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate. For example, the entire orthographic projection of the second connecting segment 23 on the substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate.

[0175] According to some exemplary embodiments, referring to Figures 10A and 10B , a common electrode line CL is located in a source / drain metal layer SD. The array substrate further includes a first passivation layer PV1 located between the source / drain metal layer SD and the sensing metal layer METAL, and a second passivation layer PV2 located between the sensing metal layer METAL and the common electrode layer COM. Vias V1 are formed in the first and second passivation layers PV1 and PV2, exposing a portion of the common electrode line CL. The common electrode layer COM includes a common electrode 50, which is electrically connected to the common electrode line CL via the via V1. Referring to Figure 8 , the sensing trace 21 includes a plurality of sensing segments 211 arranged along a second direction Y. The orthographic projections of the sensing segments 211 on the substrate are located between the orthographic projections of two adjacent scan line groups on the substrate. The two adjacent sensing segments 211 are electrically connected by a connecting portion 212. The orthographic projections of the connecting portion 212 on the substrate are spaced apart from the orthographic projections of the via V1 on the substrate, i.e., the connecting portion 212 is arranged to avoid the via V1.

[0176] 8 , the connection portion 212 is ring-shaped, and the orthographic projection of the via V1 on the substrate is located within the orthographic projection of the connection portion 212. For example, the connection portion 212 is circular.

[0177] FIG. 11 schematically shows an enlarged view of region S6 of the array substrate in FIG. 7 according to an embodiment of the present disclosure.

[0178] According to some exemplary embodiments, referring to FIG. 11 , at least one first dummy routing segment 24 is further provided between two adjacent sensing routing lines 21 . The first dummy routing segment 24 is spaced apart from the two adjacent sensing routing lines 21 , and an orthographic projection of the first dummy routing segment 24 on the substrate is located between the orthographic projections of the two scanning lines GL in the scanning line group on the substrate.

[0179] FIG. 12 schematically shows an enlarged view of region S7 of the array substrate in FIG. 7 according to an embodiment of the present disclosure.

[0180] According to some exemplary embodiments, referring to FIG. 12 , to ensure wiring consistency between the area where the temperature sensing coil is provided and the dummy area, at least one second dummy routing segment 25 and at least one third dummy routing segment 26 are provided in the dummy area TA1. At least a portion of the orthographic projection of the second dummy routing segment 25 on the substrate is located between the orthographic projections of two scan lines GL in the scan line group on the substrate. For example, the entire orthographic projection of the second dummy routing segment 25 on the substrate is located between the orthographic projections of the two scan lines GL in the scan line group on the substrate. The orthographic projection of the third dummy routing segment 26 on the substrate at least partially overlaps with the orthographic projection of the common electrode line CL on the substrate.

[0181] According to some exemplary embodiments, the lengths of the second dummy routing segment 25 and the third dummy routing segment 26 should not be too long, otherwise there will be a risk of electrostatic damage. Therefore, the orthographic projection of the second dummy routing segment 25 on the substrate is located between the orthographic projections of two adjacent common electrode lines CL on the substrate, and the orthographic projection of the third dummy routing segment 26 on the substrate is located between the orthographic projections of two adjacent scan line groups on the substrate.

[0182] According to some exemplary embodiments, with reference to FIG. 2A , the first trace 31 includes a first trace segment 311 located in the display area AA, one end of the first trace segment 311 is electrically connected to the input end of the temperature sensing coil 20 and extends along the second direction Y toward the binding area BA.

[0183] The second routing line 32 includes a second routing segment 321 and a third routing segment 322 located in the display area AA. One end of the second routing segment 321 is electrically connected to the output end of the temperature sensing coil 20 and extends along the first direction X toward the first routing segment 311. One end of the third routing segment 322 is electrically connected to the second routing segment 321 and extends along the second direction Y toward the binding area BA.

[0184] FIG2D schematically shows a plan view of an array substrate according to some further embodiments of the present disclosure.

[0185] According to some exemplary embodiments, referring to FIG. 2D , the first trace 31 includes a first trace segment 311 located in the display area AA. One end of the first trace segment 311 is electrically connected to the input end of the temperature sensing coil 20 and extends along the second direction Y toward the binding area BA.

[0186] The second trace 32 includes a second trace segment 321 and a third trace segment 322 located in the display area AA. One end of the second trace segment 321 is electrically connected to the output end of the temperature sensing coil 20 and extends away from the first trace segment 311 along the first direction X. One end of the third trace segment 322 is electrically connected to the second trace segment 321 and extends toward the binding area BA along the second direction Y. In other words, the first trace 31 and the second trace 32 are respectively electrically connected to the ends of the temperature sensing coil 20 along the first direction. The first trace segment 311 and the third trace segment 322, which are electrically connected to the temperature sensing coil 20 farther away from the binding area BA, are located on either side of the temperature sensing coil 20 closer to the binding area BA along the first direction X. This arrangement shortens the length of the second trace segment 321 in the second trace 32, thereby reducing the resistance of the second trace 32. For example, in the second routing line 32 electrically connected to the temperature sensing coil 20 closest to the binding area BA, the portion of the second routing line 32 located in the display area AA may only include a third routing segment 322, that is, one end of the third routing segment 322 is electrically connected to the output end of the temperature sensing coil 20 and extends along the second direction Y to the peripheral area NA.

[0187] Fig. 13A schematically shows an enlarged view of region S8 of an array substrate in Fig. 7 according to another embodiment of the present disclosure. Fig. 13B schematically shows an enlarged view of region S9 in Fig. 7 .

[0188] 13A , on a side of the sensing coil away from the binding area, two adjacent sensing traces 21 are electrically connected via a first connecting segment 22. A first dummy trace segment 24 is further provided between the two adjacent sensing traces 21.

[0189] According to some exemplary embodiments, referring to FIG7 and FIG13B , on a side of the sensing coil near the binding region, two adjacent sensing traces 21 are electrically connected via a second connecting segment 23. A first dummy trace segment 24 is also provided between the two adjacent sensing traces 21. FIG13B also illustrates a portion of a second trace segment 321, where at least a portion of the orthographic projection of the second trace segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate. For example, at least a portion of the orthographic projection of the second trace segment on the substrate is located between the orthographic projections of two scan lines in the scan line group on the substrate.

[0190] FIG. 14 schematically shows an enlarged view of area S11 in FIG. 7 .

[0191] According to some exemplary embodiments, referring to FIG14 , first routing segment 311 includes at least two first routing sub-segments 3111, which are electrically connected via at least one third connecting segment 3112. Third routing segment 322 includes at least two third routing sub-segments 3221, which are electrically connected via at least one fourth connecting segment 3222. This configuration reduces the resistance of the first and third routing segments, thereby improving temperature detection accuracy.

[0192] According to some exemplary embodiments, the orthographic projections of the two first routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate substrate, for example, the orthographic projections of the two first routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent common electrode lines on the substrate substrate. The orthographic projections of the two third routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate substrate, for example, the orthographic projections of the two third routing sub-segments on the substrate substrate at least partially overlap with the orthographic projections of the two adjacent common electrode lines on the substrate substrate.

[0193] According to some exemplary embodiments, at least a portion of the orthographic projection of the third connecting segment on the substrate is adjacent to and spaced apart from the orthographic projection of the scan line on the substrate. For example, at least a portion of the orthographic projection of the third connecting segment on the substrate is located between the orthographic projections of two scan lines in the scan line group on the substrate. At least a portion of the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced apart from the orthographic projection of the scan line on the substrate. For example, at least a portion of the orthographic projection of the fourth connecting segment on the substrate is located between the orthographic projections of two scan lines in the scan line group on the substrate.

[0194] According to some exemplary embodiments, the orthographic projections of the two first routing sub-segments on the substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate, respectively, and at least a portion of the orthographic projection of the third connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

[0195] According to some exemplary embodiments, the orthographic projections of the two third routing sub-segments on the substrate at least partially overlap with the orthographic projections of the two adjacent signal routing lines on the substrate, and the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

[0196] Figure 15 schematically illustrates a plan view of pixel arrangements of array substrates according to other embodiments of the present disclosure. Figure 16 schematically illustrates an enlarged view of region S5 in Figure 7 of an array substrate according to another embodiment of the present disclosure. Figure 17 schematically illustrates an enlarged view of region S5 in Figure 7 of an array substrate according to yet another embodiment of the present disclosure.

[0197] According to some exemplary embodiments, referring to Figures 15, 16 and 17, the array substrate is a single scan line driven array substrate, and the multiple signal lines SL include multiple data lines DL. For example, the multiple data lines DL and the multiple scan lines GL respectively cross to define multiple sub-pixels P.

[0198] According to some exemplary embodiments, referring to FIG. 16 , the orthographic projection of a sensing trace 21 on the substrate at least partially overlaps with the orthographic projection of a data line DL on the substrate. Adjacent sensing traces 21 on the side away from the binding region are electrically connected via a first connecting segment 22. The orthographic projection of the first connecting segment 22 on the substrate is adjacent to and spaced apart from the orthographic projection of a scan line GL on the substrate. Similarly, adjacent sensing traces on the side near the binding region are electrically connected via a second connecting segment. The orthographic projection of the second connecting segment on the substrate is adjacent to and spaced apart from the orthographic projection of the scan line on the substrate.

[0199] According to some exemplary embodiments, referring to FIG. 17 , an orthographic projection of the sensing trace 21 on the base substrate at least partially overlaps with an orthographic projection of the data line DL on the base substrate.

[0200] According to some exemplary embodiments, referring to FIG17 , the pixel electrode 60 includes a first electrode portion 61 and a second electrode portion 62 connected along a second direction Y, the first electrode portion 61 extends along a third direction, the second electrode portion 62 extends along a fourth direction, and the third direction intersects with the fourth direction. That is, the sub-pixel has a dual-domain structure, and the boundary between the two domains is a dark area. Therefore, the first connecting segment and the second connecting segment can be set in this area. Specifically, the side of the adjacent sensing trace 21 away from the binding area is electrically connected through the first connecting segment 22, and the orthographic projection of the edge connected to the first electrode portion 61 and the second electrode portion 62 on the substrate substrate is located within the orthographic projection of the first connecting segment 22 on the substrate substrate. Similarly, the orthographic projection of the edge connected to the first electrode portion and the second electrode portion on the substrate substrate can be located within the orthographic projection of the second connecting segment on the substrate substrate.

[0201] According to some exemplary embodiments, based on the structure of the array substrate illustrated in FIG. 17 , a first dummy trace can be provided in the temperature sensing coil. The first dummy trace is provided in substantially the same manner as the first connecting segment and the second connecting segment to ensure uniform routing within the temperature test area. Specifically, in the temperature sensing coil, at least one first dummy trace segment is provided between two adjacent sensing traces. The orthographic projection of the first dummy trace segment on the base substrate overlaps the edge where the first electrode portion and the second electrode portion connect.

[0202] FIG. 18 schematically illustrates a distribution diagram of temperature test areas in a display area of ​​an array substrate according to some embodiments of the present disclosure.

[0203] According to some exemplary embodiments, the display area is irregularly shaped, and at least one temperature test area in the display area is irregularly shaped. For example, referring to FIG. 18 , the upper edge of the display area is a curved edge. The temperature test area TA located at the lower side is rectangular, and the temperature test area TA located at the uppermost side is an irregularly shaped temperature test area TAA. Of the two sides of the irregularly shaped temperature test area TAA located on both sides of the second direction Y, one side extends in a direction parallel to the first direction X, and the other side extends in a direction intersecting with the first direction X, or the other side is a curved side.

[0204] FIG. 19 schematically illustrates a distribution diagram of temperature sensing coils in a special-shaped temperature test area of ​​an array substrate according to some embodiments of the present disclosure.

[0205] According to some exemplary embodiments, referring to FIG. 19 , the special-shaped temperature test area TAA includes a rectangular test area TAA1. The temperature sensing coil 20 is located within the test area. The sensing traces 21 have substantially equal lengths along the second direction Y. Dummy trace segments may be provided in areas of the special-shaped temperature test area TAA other than the test area TAA1 to ensure routing consistency.

[0206] FIG. 20 schematically shows a distribution diagram of temperature sensing coils in a special-shaped temperature test area of ​​an array substrate according to some other embodiments of the present disclosure.

[0207] 20 , the sensing coil is located in the special-shaped temperature test area TAA, and at least two sensing traces 21 have different lengths along the second direction Y. That is, the contour shape of the sensing trace 21 is consistent with the special-shaped temperature test area TAA.

[0208] According to some exemplary embodiments, referring to Figure 2A, the array substrate also includes at least one peripheral temperature sensing coil 20N located in the peripheral area NA, and the input end of the peripheral temperature sensing coil 20N is electrically connected to the binding area BA through an input trace, and the input trace is used to connect the driving signal provided by the binding area BA to the peripheral temperature sensing coil 20N, and the output end of the peripheral temperature sensing coil 20N is electrically connected to the binding area BA through an output trace, and the output trace is used to transmit the sensing signal generated by the peripheral temperature sensing coil 20N to the binding area BA.

[0209] FIG. 21 schematically illustrates a planar area of ​​a peripheral temperature sensing coil of an array substrate according to some embodiments of the present disclosure.

[0210] According to some exemplary embodiments, referring to FIG. 21 , the ambient temperature sensing coil 20N includes a first portion 20N1 and a second portion 20N2 adjacent to each other along a first direction, and the first portion 20N1 and the second portion 20N2 are electrically connected. The first portion 20N1 has a serpentine structure wound back and forth along the first direction X, and the second portion 20N2 has a serpentine structure wound back and forth along the first direction X.

[0211] In some embodiments, the structure of the peripheral temperature sensing coil located in the peripheral area can be consistent with the structure of the temperature sensing coil located in the display area, so that the resistance of the peripheral temperature sensing coil is substantially equal to the resistance of the temperature sensing coil. This allows the same processing procedure to be used to obtain corresponding temperature information based on the sensing signals output by the peripheral temperature sensing coil and the sensing signals output by the temperature sensing coil. This reduces the processing complexity of calculating the corresponding temperature information based on the sensing signals. Figure 22 schematically illustrates a display panel according to an embodiment of the present disclosure.

[0212] The display panel may include an array substrate 1 and an opposing substrate 2 disposed opposite the array substrate 1. The display panel may further include a liquid crystal layer 3 located between the array substrate 1 and the opposing substrate 2. The array substrate 1 may be the array substrate described above, i.e., the array substrate may include a temperature sensing coil.

[0213] For example, the counter substrate 2 may be a color filter substrate. Specifically, it may include a black matrix BM, wherein the orthographic projection of the black matrix BM on the base substrate 10 covers at least a portion of the orthographic projection of the temperature sensing coil 20 on the base substrate 10. Exemplarily, the orthographic projection of the black matrix BM on the base substrate 10 covers the orthographic projection of the sensing trace 21 on the base substrate 10.

[0214] According to an embodiment of the present disclosure, a display device is further provided, which may include the display panel described above. For example, the display device may be any product or component with a display function, such as a smartphone, a wearable smartwatch, smart glasses, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, an in-vehicle display, an e-book, or the like.

[0215] According to an embodiment of the present disclosure, a head-up display system is also provided, comprising the display panel described above and an optical path magnifying element. For example, the head-up display system can be used in a car, with the display panel used to generate graphics and control brightness. The optical path magnifying element is used to amplify the display image and eliminate distortion caused by the car's windshield. Because the virtual image of the display panel is reflected from the windshield, it can create a visual experience of the image floating outside the windshield, presenting a holographic image effect. According to some exemplary embodiments, the optical path magnifying element may include a concave mirror.

[0216] FIG23 schematically shows a flow chart of a method for measuring the temperature of a display panel according to an embodiment of the present disclosure.

[0217] According to an embodiment of the present disclosure, a temperature measurement method for the display panel as described above is also provided. Referring to FIG. 23 , the temperature measurement method includes the following steps:

[0218] In step S10 , a driving signal is input to the input end of the temperature sensing coil.

[0219] In step S20 , a sensing signal outputted from an output terminal of the temperature sensing coil is acquired.

[0220] In step S30 , the temperature of the temperature test area where the temperature sensing coil is located is obtained according to the sensing signal.

[0221] According to some exemplary embodiments, before the display panel is officially used, the display panel is placed in environments with different temperatures, and a driving signal is input to the input end of a temperature sensing coil in the display panel to measure sensing signals corresponding to the different temperatures and generate a standard temperature curve. Determining the temperature of the temperature test area where the temperature sensing coil is located based on the sensing signal includes determining the temperature of the temperature test area where the temperature sensing coil is located based on the standard temperature curve and the sensing signal.

[0222] Figure 24 schematically shows a timing diagram of driving signals in a method for measuring the temperature of a display panel according to an embodiment of the present disclosure. Figure 25 schematically shows a timing diagram of driving signals in another method for measuring the temperature of a display panel according to an embodiment of the present disclosure.

[0223] According to some exemplary embodiments, referring to FIG. 25 , inputting a drive signal to the input end of the temperature sensing coil includes: when the display panel is in a display phase t1, the data signal Source switches between a high-level signal and a low-level signal, and at this time, inputting a first drive signal DS1 to the input end of the temperature sensing coil, the first drive signal DS1 being a common electrode voltage signal; when the display panel is in a non-display phase t2, the data signal Source is a low-level signal, and at this time, inputting a second drive signal DS2 to the input end of the temperature sensing coil, the voltage value of the second drive signal DS2 being greater than the voltage value of the first drive signal DS1; and obtaining a sensed signal output from the output end of the temperature sensing coil includes: when the display panel is in the non-display phase t2, obtaining a sensed signal output by the temperature sensing coil in response to the second drive signal DS2. In this temperature measurement method, since a common electrode voltage signal with a lower voltage value is input to the temperature sensing coil during the display phase t1, the voltage signal of the temperature sensing coil can be effectively prevented from affecting other display signals in the display panel, thereby causing display defects.

[0224] According to some exemplary embodiments, referring to FIG. 24 , inputting a drive signal to the input terminal of the temperature sensing coil includes inputting a second drive signal DS2 to the input terminal of the temperature sensing coil regardless of whether the display panel is in a display phase t1 or a non-display phase t2 ; and obtaining a sensing signal output by the output terminal of the temperature sensing coil includes obtaining a sensing signal output by the temperature sensing coil in response to the second drive signal DS2 when temperature data is required. For example, the sensing signal output by the temperature sensing coil in response to the second drive signal DS2 may be obtained during the display phase t1 , or the sensing signal output by the temperature sensing coil in response to the second drive signal DS2 may be obtained during the non-display phase t2 .

[0225] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0226] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0227] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, wherein: The array substrate includes a display area and a peripheral area located around the display area. The display area is provided with a plurality of temperature test areas, and the plurality of temperature test areas are arranged along a first direction and / or a second direction. The peripheral area is provided with a binding area, and the binding area is located on one side of the display area along the second direction. The array substrate includes: substrate; a plurality of temperature sensing coils located on the substrate, wherein the plurality of temperature sensing coils are respectively located in the plurality of temperature testing areas; and a plurality of signal transmission parts located on the substrate, the plurality of signal transmission parts being electrically connected to the plurality of temperature sensing coils, the signal transmission parts comprising a first trace and a second trace, one end of the first trace being electrically connected to the input end of the temperature sensing coil, the other end of the first trace extending to the binding area, one end of the second trace being electrically connected to the output end of the temperature sensing coil, the other end of the second trace extending to the binding area; In which, the array substrate also includes a plurality of signal lines located on the array substrate, the plurality of signal lines are arranged along the first direction and extend along the second direction, and the orthographic projection of the temperature sensing coil on the base substrate at least partially overlaps with the orthographic projection of the signal lines on the base substrate.

2. The array substrate according to claim 1, wherein: The display area includes a plurality of sub-pixel opening areas and a non-opening area located between adjacent sub-pixel opening areas, and the sub-pixel opening area includes a light-transmitting area and a non-light-transmitting area; Wherein, at least a portion of the temperature sensing coil is located in the non-opening area, and / or at least a portion of the temperature sensing coil is located in the non-light-transmitting area.

3. The array substrate according to claim 1 or 2, wherein: The temperature sensing coil includes a plurality of sensing traces, a plurality of first connecting segments, and a plurality of second connecting segments, wherein the plurality of sensing traces are arranged along the first direction and extend along the second direction; Two adjacent sensing traces whose ends are away from the binding area are electrically connected via the first connecting segment, and two adjacent sensing traces whose ends are close to the binding area are electrically connected via the second connecting segment, and the plurality of first connecting segments and the plurality of second connecting segments are alternately electrically connected to the two adjacent sensing traces; as well as The orthographic projections of the plurality of sensing traces on the substrate at least partially overlap with the orthographic projections of the plurality of signal traces on the substrate.

4. The array substrate according to claim 3, wherein: The array substrate comprises a plurality of scan lines located on the base substrate, the plurality of scan lines are arranged along the second direction and extend along the first direction; The orthographic projection of the first connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scanning line on the substrate; and / or The orthographic projection of the second connecting segment on the base substrate is adjacent to and spaced from the orthographic projection of the scanning line on the base substrate.

5. The array substrate according to claim 4, wherein: At least one first dummy routing segment is further provided between two adjacent sensing routing lines. The first dummy routing segment is spaced apart from the two adjacent sensing routing lines, and the orthographic projection of the first dummy routing segment on the base substrate is adjacent to and spaced apart from the orthographic projection of the scanning line on the base substrate.

6. The array substrate according to claim 4 or 5, wherein: Of the two temperature sensing coils adjacent to each other along the second direction, at least a portion of the signal transmission portion electrically connected to the temperature sensing coil farther from the binding area is located in the temperature testing area where the temperature sensing coil closer to the binding area is located; In two temperature testing areas adjacent to each other along the second direction, both temperature testing areas include a dummy area, the temperature sensing coil is located in an area of ​​the temperature testing area other than the dummy area, an extension length of the temperature sensing coil in one temperature testing area is substantially equal to an extension length of the temperature sensing coil in the other temperature testing area, and an area of ​​the dummy area closer to the binding area is smaller than an area of ​​the dummy area farther from the binding area; or Among the two temperature testing areas adjacent to each other along the second direction, only the temperature testing area farther away from the binding area includes a dummy area, the temperature sensing coil is located in an area other than the dummy area within the temperature testing area, and an extension length of the temperature sensing coil within one of the temperature testing areas is substantially equal to an extension length of the temperature sensing coil within the other of the temperature testing areas.

7. The array substrate according to claim 6, wherein: At least one second dummy routing segment and at least one third dummy routing segment are provided in the dummy area; The orthographic projection of the second dummy routing segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate, and the orthographic projection of the second dummy routing segment on the substrate is located between the orthographic projections of the two signal routing lines on the substrate; The orthographic projection of the third dummy routing segment on the substrate at least partially overlaps with the orthographic projection of the signal routing segment on the substrate, and the orthographic projection of the third dummy routing segment on the substrate is located between the orthographic projections of the two scan lines on the substrate.

8. The array substrate according to any one of claims 1 to 7, wherein: The plurality of temperature sensing coils arranged along the second direction include a distal temperature sensing coil farthest from the binding area and at least one proximal temperature sensing coil located on a side of the distal temperature sensing coil close to the binding area; In which, the signal transmission part electrically connected to the proximal temperature sensing coil has a compensation coil located in the peripheral area, and among the two proximal temperature sensing coils adjacent along the second direction, the resistance of the compensation coil electrically connected to the proximal temperature sensing coil farther away from the binding area is smaller than the resistance of the compensation coil electrically connected to the proximal temperature sensing coil closer to the binding area.

9. The array substrate according to any one of claims 4 to 7, wherein: The array substrate also includes a gate metal layer located on the base substrate, a source-drain metal layer located on a side of the gate metal layer away from the base substrate, a common electrode layer located on a side of the source-drain metal layer away from the base substrate, and a sensing metal layer located between the source-drain metal layer and the common electrode layer, wherein the temperature sensing coil and the signal transmission unit are located in the sensing metal layer.

10. The array substrate according to claim 9, wherein: The common electrode layer includes a common electrode, and an orthographic projection of the common electrode on the base substrate covers at least a portion of an orthographic projection of the temperature sensing coil on the base substrate.

11. The array substrate according to any one of claims 9 or 10, wherein: The plurality of signal lines include a plurality of data lines and a plurality of common electrode lines, and the plurality of data lines and the plurality of common electrode lines are alternately arranged along the first direction; The orthographic projection of the sensing trace on the base substrate at least partially overlaps with the orthographic projection of the common electrode line on the base substrate.

12. The array substrate according to claim 11, wherein: The array substrate further includes a pixel electrode layer located on the base substrate, wherein the pixel electrode layer includes a plurality of pixel electrodes; and The plurality of scan lines include a plurality of scan line groups, each scan line group includes two scan lines, and an orthographic projection of the scan line group on the base substrate is located between orthographic projections of two adjacent pixel electrodes along the second direction on the base substrate; Wherein, at least a portion of the orthographic projection of the first connecting segment on the substrate is located between the orthographic projections of two scanning lines in the scanning line group on the substrate; and / or At least a portion of an orthographic projection of the second connecting segment on the substrate is located between orthographic projections of two scanning lines in the scanning line group on the substrate.

13. The array substrate according to claim 11 or 12, wherein: The common electrode line is located in the source / drain metal layer, the array substrate includes a first passivation layer located between the source / drain metal layer and the sensing metal layer, and a second passivation layer located between the sensing metal layer and the common electrode layer, the first passivation layer and the second passivation layer have via holes therein, the via holes exposing a portion of the common electrode line, the common electrode layer includes a common electrode, and the common electrode is electrically connected to the common electrode line through the via holes; The sensing trace includes a plurality of sensing segments arranged along the second direction, two adjacent sensing segments are electrically connected via a connecting portion, and an orthographic projection of the connecting portion on the base substrate is spaced apart from an orthographic projection of the via on the base substrate.

14. The array substrate according to claim 13, wherein: The connecting portion is ring-shaped, and the orthographic projection of the via hole on the base substrate is located within the orthographic projection of the connecting portion on the base substrate.

15. The array substrate according to any one of claims 9 or 10, wherein: The plurality of signal lines include a plurality of data lines, and an orthographic projection of the sensing line on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate.

16. The array substrate according to any one of claims 1 to 3, wherein: The array substrate further includes a pixel electrode layer located on the base substrate, wherein the pixel electrode layer includes a plurality of pixel electrodes; and The pixel electrode includes a first electrode portion and a second electrode portion connected along the second direction, the first electrode portion extends along a third direction, the second electrode portion extends along a fourth direction, and the third direction intersects the fourth direction; The orthographic projection of the edge where the first electrode portion and the second electrode portion are connected on the base substrate is located within the orthographic projection of the first connecting segment on the base substrate; and / or An orthographic projection of an edge connecting the first electrode portion and the second electrode portion on the base substrate is located within an orthographic projection of the second connecting segment on the base substrate.

17. The array substrate according to any one of claims 4 to 7 and 9 to 15, wherein: The first wiring includes a first wiring segment located in the display area, one end of the first wiring segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and The second routing segment includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction toward the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

18. The array substrate according to any one of claims 4 to 7 and 9 to 15, wherein: The first wiring includes a first wiring segment located in the display area, one end of the first wiring segment is electrically connected to the input end of the temperature sensing coil and extends along the second direction toward the binding area; and The second routing segment includes a second routing segment and a third routing segment located in the display area, one end of the second routing segment is electrically connected to the output end of the temperature sensing coil and extends along the first direction away from the first routing segment, and one end of the third routing segment is electrically connected to the second routing segment and extends along the second direction toward the binding area.

19. The array substrate according to claim 17 or 18, wherein: The first routing segment includes at least two first routing sub-segments, the two first routing sub-segments are electrically connected via at least one third connecting segment, the orthographic projections of the two first routing sub-segments on the substrate at least partially overlap with the orthographic projections of two adjacent signal routing lines on the substrate, and the orthographic projection of the third connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate; and / or The third routing segment includes at least two third routing sub-segments, the two third routing sub-segments are electrically connected via at least one fourth connecting segment, the orthographic projections of the two third routing sub-segments on the substrate at least partially overlap with the orthographic projections of two adjacent signal routing lines on the substrate, respectively, and the orthographic projection of the fourth connecting segment on the substrate is adjacent to and spaced from the orthographic projection of the scan line on the substrate.

20. The array substrate according to any one of claims 3 to 7, 9 to 15, and 17 to 19, wherein: The plurality of temperature test areas include at least one special-shaped temperature test area, wherein of the two sides of the special-shaped temperature test area located on both sides of the second direction, an extension direction of one side is parallel to the first direction, and an extension direction of the other side intersects with the first direction or the other side is a curved side; The special-shaped temperature test area includes a test area, the test area is rectangular in shape, the temperature sensing coil is located in the test area, and the lengths of the sensing lines along the second direction are substantially equal; or The sensing coil is located in the special-shaped temperature test area, and the lengths of at least two sensing lines along the second direction are different from each other.

21. The array substrate according to any one of claims 1 to 20, wherein: The array substrate also includes at least one peripheral temperature sensing coil located in the peripheral area, the input end of the peripheral temperature sensing coil is electrically connected to the input terminal in the binding area through an input trace, and the input trace is used to connect the driving signal provided by the input terminal to the peripheral temperature sensing coil. The output end of the peripheral temperature sensing coil is electrically connected to the output terminal in the binding area through an output trace, and the output trace is used to transmit the sensing signal generated by the peripheral temperature sensing coil to the output terminal.

22. A display panel, wherein: The display panel includes the array substrate according to any one of claims 1-21.

23. A display device, wherein: The display device includes the display panel according to claim 22.

24. A head-up display system, wherein: The head-up display system includes the display panel according to claim 22 and an optical path amplifying element.

25. The head-up display system according to claim 24, wherein: The optical path magnifying element includes a concave mirror.

26. A method for measuring the temperature of a display panel, wherein: For the display panel according to claim 22, the temperature measurement method comprises: Inputting a driving signal to an input end of the temperature sensing coil; Acquiring a sensing signal outputted from an output end of the temperature sensing coil; and The temperature of the temperature test area where the temperature sensing coil is located is obtained according to the sensing signal.

27. The method for measuring the temperature of a display panel according to claim 26, wherein: The step of inputting a driving signal to the input end of the temperature sensing coil comprises: When the display panel is in a display phase, a first drive signal is input to the input end of the temperature sensing coil, wherein the first drive signal is a common electrode voltage signal; and when the display panel is in a non-display phase, a second drive signal is input to the input end of the temperature sensing coil, wherein a voltage value of the second drive signal is greater than a voltage value of the first drive signal; and The acquiring of the sensing signal outputted from the output end of the temperature sensing coil comprises: When the display panel is in a non-display stage, acquiring the sensing signal output by the temperature sensing coil in response to the second driving signal; or The step of inputting a driving signal to the input end of the temperature sensing coil comprises: When the display panel is in a display stage and / or a non-display stage, inputting a second driving signal to an input end of the temperature sensing coil; and The acquiring of the sensing signal outputted from the output end of the temperature sensing coil comprises: When the display panel is in a display stage and / or a non-display stage, the sensing signal output by the temperature sensing coil in response to the second driving signal is acquired.

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