Semiconductor integrated circuit device

Abstract

An inverter cell (C1) is provided with active regions (2P1, 2N1) and nanosheets (21, 22). A filler cell (C3) that has no logic function and is disposed adjacent to the inverter cell (C1) is provided with active regions (2P3, 2N3) and nanosheets (121, 124). First-side surfaces of the nanosheets (21, 22) are exposed from gate wiring (31). First-side surfaces of the nanosheets (121, 124) are exposed from dummy gate wiring (131). In plan view, the first-side end of the nanosheet (21) and the first-side end of the nanosheet (121) are disposed at the same position with respect to a second direction.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, also simply referred to as cells, as appropriate) that include CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Standard cells include cells with logic functions such as NAND gates and NOR gates (hereinafter referred to as logic cells, as appropriate), as well as cells without logic functions. An example of a cell without logic functions is a "filler cell." A "filler cell" is a cell that does not have a logic function, does not contribute to the logic function of a circuit block, and is placed between logic cells.

[0005] Patent Document 1 discloses a filler cell that uses a CFET (Complementary FET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate in order to reduce the area of ​​a semiconductor integrated circuit device.

[0006] Patent Document 2 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a fork-shaped gate electrode, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 2 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0007] International Publication No. 2020 / 137660 U.S. Patent Application Publication No. 2022 / 0246644

[0008] However, regarding filler cells using CFETs, no specific consideration has yet been given to the layout structure of filler cells using fork-sheet transistors as transistors.

[0009] The present disclosure aims to provide a layout structure of a filler cell using a fork-sheet transistor as a transistor, in relation to a filler cell using a CFET.

[0010] In a first aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a first standard cell having a logic function and a second standard cell arranged adjacent to the first standard cell and not having a logic function, wherein the first standard cell includes: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; a first power supply wiring extending in the first direction and supplying a first power supply voltage; and a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage. and a power supply wiring, wherein the first power supply wiring is connected to the source of the first transistor in the first active region, and the second power supply wiring is connected to the source of the second transistor in the second active region. The second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, and constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, and constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and a dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction, wherein the first and second nanosheets have first side surfaces, which are one side in the second direction, exposed from the first gate wiring, and the third and fourth nanosheets areThe first side surface is exposed from the dummy gate wiring, and in a plan view, the first side end of the first nanosheet and the first side end of the third nanosheet are arranged at the same position in the second direction.

[0011] According to the present disclosure, the first-side end of the first nanosheet in the first active region of the first standard cell and the first-side end of the third nanosheet in the third active region of the second standard cell are aligned in the second direction. Furthermore, the first-side surface of the first nanosheet is exposed from the first gate wiring, and the first-side surface of the third nanosheet is exposed from the dummy gate wiring. That is, in the first and second standard cells, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the second direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, by aligning the positions of the nanosheet surfaces exposed from the gate wiring in the second direction, the shape of the structure, i.e., the size and layout area in the second direction, can be made constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0012] In a second aspect of the present disclosure, there is provided a semiconductor integrated circuit device including a first standard cell having a logic function and a second standard cell arranged adjacent to the first standard cell and not having a logic function, wherein the first standard cell includes: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in a first direction; a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the outer periphery of the first and second nanosheets in the second direction and the depth direction; a first power supply wiring extending in the first direction and supplying a first power supply voltage; and a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage. and a power supply wiring, wherein the first power supply wiring is connected to the source of the first transistor in the first active region, and the second power supply wiring is connected to the source of the second transistor in the second active region. The second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, and constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, and constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and a dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction, wherein the first and second nanosheets have first side surfaces, which are one side in the second direction, exposed from the first gate wiring, and the third and fourth nanosheets areThe first side surface is exposed from the dummy gate wiring, and the first side end and the second side end of the first active region are arranged between the first side end and the second side end of the third active region, which is the other side in the second direction, of the third active region.

[0013] According to the present disclosure, in the second direction, the first and second ends of the first active region of the first standard cell having a logic function are arranged between the first and second ends of the third active region of the second standard cell not having a logic function. By arranging the second standard cell adjacent to the first standard cell, the third active region of the second standard cell can be arranged along the entire side surface of the first active region of the first standard cell in the first direction. Therefore, the distance from the first active region of the first standard cell to the third active region of the second standard cell is set to a predetermined value. This improves the accuracy of estimating the transistor performance of standard cells having a logic function.

[0014] According to the present disclosure, with respect to filler cells using CFETs, a layout of filler cells using fork-sheet transistors as transistors facilitates the manufacture of semiconductor integrated circuit devices and improves the accuracy of estimating the transistor performance of standard cells having logic functions.

[0015] 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment. FIG. 2 is a plan view showing an example of the layout structure of an inverter cell according to the first embodiment. FIG. 3 is a circuit diagram of an inverter cell. FIG. 4 is a plan view showing an example of the layout structure of a filler cell according to the first embodiment. FIG. 5 is a cross-sectional view of the filler cell of FIG. 4. FIG. 6 is another configuration example of a semiconductor integrated circuit device according to the first embodiment. FIG. 7 is a plan view showing an example of the layout structure of an inverter cell according to a modification of the first embodiment. FIG. 8 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. FIG. 9 is a plan view showing an example of the layout structure of an inverter cell according to the second embodiment. FIG. 10 is a plan view showing an example of the layout structure of a filler cell according to the second embodiment. FIG. 11 is a plan view showing an example of the layout structure of a circuit block included in a semiconductor integrated circuit device according to a third embodiment. FIG. 12 is a plan view showing an example of the layout structure of an inverter cell according to the third embodiment. FIG. 13 is a plan view showing an example of the layout structure of a filler cell according to the third embodiment. FIG. 14 is a plan view showing an example of the layout structure of a circuit block included in a semiconductor integrated circuit device according to a fourth embodiment. FIG. 15 is a plan view showing an example of the layout structure of an inverter cell according to the fourth embodiment. FIG. 16 is a plan view showing an example of the layout structure of a filler cell according to the fourth embodiment.

[0016] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells. At least some of the plurality of standard cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0017] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0018] 1 is a plan view showing an example of the layout of a circuit block provided in a semiconductor integrated circuit device according to the first embodiment. Specifically, Fig. 1(a) shows the lower part of the cell, i.e., the part including the nanosheet transistor formed on the side closer to the substrate, and Fig. 1(b) shows the upper part of the cell, i.e., the part including the nanosheet transistor formed on the side farther from the substrate.

[0019] 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed, and in an M0 wiring layer, which is a metal wiring layer above the transistors.

[0020] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0021] 1 and other plan views, the solid lines surrounding the cells indicate the cell frames (outer edges of the standard cells). A standard cell is arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

[0022] In the layout of FIG. 1, a plurality of cells arranged in the X direction constitute a cell row. The plurality of cells include inverter cells C1 and C2 having a logic function and a filler cell C3. In the layout of FIG. 1, the filler cell C3 is arranged between the inverter cells C1 and C2. Note that a "filler cell" refers to a cell that does not have a logic function, does not contribute to the logic function of the circuit block, and is arranged between logic cells.

[0023] In each cell, power supply wiring is formed in the BM0 wiring layer and the M0 wiring layer in the center of the drawing in the Y direction. Specifically, power supply wiring (power supply wiring 11 described later) that supplies power supply voltage VDD is formed in the BM0 wiring layer, and power supply wiring (power supply wiring 51 described later) that supplies power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 1, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column.

[0024] Additionally, the active region 2P3 (2N3) of the filler cell C3 is arranged to the right of the active region 2P1 (2N1) of the inverter cell C1 in the X direction in the drawing. The active region 2P3 (2N3) of the filler cell C3 is arranged to the left of the active region 2P2 (2N2) of the inverter cell C2 in the X direction in the drawing. In other words, the active regions of the filler cells without logic functions are arranged adjacent to the active regions of the standard cells with logic functions in the X direction.

[0025] (Configuration of inverter cell C1) Fig. 2 is a plan view showing an example of the layout structure of inverter cells C1 and C2 according to the first embodiment, and Fig. 3 is a circuit diagram of the inverter cell. Specifically, Fig. 2(a) shows the lower part of inverter cell C1, Fig. 2(b) shows the upper part of inverter cell C1, Fig. 2(c) shows the lower part of inverter cell C2, and Fig. 2(d) shows the upper part of inverter cell C2.

[0026] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 2 and the dashed lines running vertically in cross-sectional views such as FIG. 5 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0027] As shown in FIG. 3, the inverter cell C1 has transistors P1 and N1, and an inverter circuit with an input A and an output Y is configured.

[0028] 2A, a BM0 wiring layer, which is a wiring layer, is formed on the back surface of a semiconductor chip on which transistors are formed. In the BM0 wiring layer, a power supply wiring 11 extending in the X direction is formed at the center of the cell in the Y direction of the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0029] An active region that forms the channel, source, and drain of the P-type transistor is formed in the P-type transistor region at the bottom of the cell. Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0030] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheet structures (not shown) in a plan view and extends in the X direction. In the active region 2P1, the portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P1 overlap in a plan view.

[0031] As shown in FIG. 2B, an active region that forms the channel, source, and drain of the N-type transistor is formed in the N-type transistor region in the upper part of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 is disposed above the active region 2P1 in the Z direction. The active region 2N1 overlaps with the active region 2P1 in a plan view.

[0032] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has a nanosheet 22 as a channel, which is made of three overlapping sheets (not shown) in a plan view and extends in the X direction.

[0033] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0034] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0035] Similar to the dummy gate wirings 131 to 133 described later, the gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower sides of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper sides of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0036] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0037] 2A, local interconnects (LI) 41 and 42 extending in the Y direction are formed below the cell. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the source of the transistor P1. The local interconnect 42 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1.

[0038] 2B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N1 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N1 that will become the drain of the transistor N1.

[0039] In the M0 wiring layer, which is a metal wiring layer above the active region 2N1, a power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0040] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N1 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N1 that will become the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N1 overlap in plan view.

[0041] The wiring 52 is disposed on the lower side in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N1 overlap in a plan view.

[0042] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 42, 44.

[0043] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0044] As shown in FIGS. 2A and 2B, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0045] In the inverter cell C1 shown in FIG. 2, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P1 and 2N1 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0046] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P1 (2N1) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P1 (2N1) is positioned closer to the lower end of the cell frame in the Y direction, based on the center of the cell frame in the Y direction. That is, in a planar view, the center of the active region 2P1 (2N1) in the Y direction is lower than the center of the cell frame in the Y direction.

[0047] Furthermore, the power supply wiring 11, 51 is formed in the center of the cell in the Y direction in plan view. That is, the center of the active region 2P1 (2N1) in the Y direction is located below the center of the power supply wiring 11 (51) in the Y direction. By arranging the inverter cell C1 in the circuit block of FIG. 1, the power supply wiring that supplies the power supply voltages VDD and VSS is uniformly arranged in the Y direction, which makes it possible to suppress a drop in the power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0048] Furthermore, the via 61 connects the power supply wiring 11 and a portion of the active region 2P1 that serves as the source of the transistor P1. In plan view, the center of the via 61 in the Y direction is located at the same position as the center of the power supply wiring 11 in the Y direction. That is, when the center of the active region 2P1 in the Y direction is used as a reference, the via 61 is located closer to the upper end of the active region 2P1 in the Y direction (the side where the nanosheet 21 is not exposed from the gate wiring 31). In other words, the center of the via 61 in the Y direction is located above the center of the active region 2P1 in the Y direction.

[0049] Furthermore, the via 62 connects the power supply wiring 51 and a portion of the active region 2N1 that serves as the source of the transistor N1. In plan view, the center of the via 62 in the Y direction is located at the same position as the center of the power supply wiring 51 in the Y direction. That is, when the center of the active region 2N1 in the Y direction is used as a reference, the via 62 is located closer to the upper end of the active region 2N1 in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31). In other words, the center of the via 62 in the Y direction is located above the center of the active region 2N1 in the Y direction.

[0050] Furthermore, the via 63 connecting the wiring 52 and the gate wiring 31 is formed lower in the Y direction than the power wiring 51 in plan view (the side where the nanosheet 22 is exposed from the gate wiring 31 and where the active region 2N1 is positioned closer to the cell frame). The via 63 is formed in the area where the wiring 52 and the active region 2N1 overlap in plan view. That is, the via 63 is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as the reference point. This reduces the distance from the wiring 52 (input A) to the portion of the gate wiring 31 that overlaps the nanosheets 21 and 22 in plan view and covers the nanosheets 21 and 22, thereby reducing the resistance from the wiring 52 to the gate wiring 31 and increasing the speed of the semiconductor integrated circuit device.

[0051] Furthermore, the wiring 53 is disposed on the upper side of the drawing in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N1 is disposed close to the cell frame). The via 64 connecting the wiring 53 to the local wiring 44 and the via 65 connecting the local wirings 42 and 44 are formed on the upper side of the drawing in the Y direction. This reduces the distance from the wiring 53 to the portion of the active region 2P1 that serves as the drain of the transistor P1 and the portion of the active region 2N1 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P1 (2N1) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0052] (Configuration of Inverter Cell C2) The inverter cell C2 has almost the same configuration as the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C2 is a standard cell having a logic function.

[0053] As shown in Figures 2(c) and (d), compared to the inverter cell C1 shown in Figures 2(a) and (b), the inverter cell C2 has active regions 2P2 and 2N2, each having a different width in the Y direction, arranged in place of the active regions 2P1 and 2N1.

[0054] Specifically, the active regions 2P2 and 2N2 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0055] 2, the bottom edge of the active region 2P2 (2N2) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P1 (2N1) in the Y direction. That is, the bottom edge of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the bottom edge of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction are aligned in the Y direction.

[0056] (Configuration of filler cell C3) Fig. 4 is a plan view showing an example of the layout structure of the filler cell according to the first embodiment, and Fig. 5 is a cross-sectional view showing an example of the layout structure of the filler cell according to the first embodiment. Specifically, Fig. 4(a) shows the lower part of the cell, Fig. 4(b) shows the upper part of the cell, Fig. 5(a) is a cross-section taken along X1-X1' in Fig. 4, Fig. 5(b) is a cross-section taken along Y1-Y1' in Fig. 4, and Fig. 5(c) is a cross-section taken along Y2-Y2' in Fig. 4.

[0057] 4A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0058] An active region 2P3 is formed in the P-type transistor region. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0059] P-type dummy transistors DP1 to DP3 are formed in the active region 2P3. The dummy transistors DP1 to DP3 each have a channel made of three overlapping sheets in a plan view, and have nanosheets 121 to 123 extending in the X direction.

[0060] 4B, an active region 2N3 is formed in the N-type transistor region. The active region 2N3 overlaps with the active region 2P3 in plan view.

[0061] N-type dummy transistors DN1 to DN3 are formed in the active region 2N3. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0062] Dummy gate wirings 131 to 133 are formed extending in the Y and Z directions. Nanosheets 121 and 124 overlap with dummy gate wiring 131 in a planar view. Nanosheets 122 and 125 overlap with dummy gate wiring 132 in a planar view. Nanosheets 123 and 126 overlap with dummy gate wiring 133 in a planar view. Dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 132 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 133 corresponds to the gates of dummy transistors DP3 and DN3.

[0063] As shown in FIG. 5C, the dummy gate wiring 131 covers the outer peripheries of the nanosheets 121 and 124 in the Y and Z directions so that part of the outer peripheries of the nanosheets 121 and 124 are exposed. Specifically, the right-hand side surfaces of the nanosheets 121 and 124 in the drawing are not covered by the dummy gate wiring 131, and the left-hand side surfaces of the nanosheets 121 and 124 in the drawing are covered by the dummy gate wiring 131. Therefore, in FIG. 4, the lower sides of the nanosheets 121 and 124 in the Y direction are exposed from the dummy gate wiring 131, and the upper sides of the nanosheets 121 and 124 in the Y direction are covered by the dummy gate wiring 131. Similarly, the dummy gate wiring 132 covers the outer peripheries of the nanosheets 122 and 125 in the Y and Z directions so that part of the outer peripheries of the nanosheets 122 and 125 are exposed. Dummy gate wiring 133 covers the outer peripheries of nanosheets 123 and 126 in the Y and Z directions so as to expose a portion of the outer peripheries of nanosheets 123 and 126. In Fig. 4, the lower sides of nanosheets 122 and 125 in the Y direction are exposed from dummy gate wiring 132, and the upper sides of nanosheets 122 and 125 in the Y direction are covered by dummy gate wiring 132. The lower sides of nanosheets 123 and 126 in the Y direction are exposed from dummy gate wiring 133, and the upper sides of nanosheets 123 and 126 in the Y direction are covered by dummy gate wiring 133.

[0064] Dummy gate wiring 134, 135 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 134 is shared with another cell (inverter cell C1 in FIG. 1) located on the left side of the drawing. The dummy gate wiring 135 is shared with another cell (inverter cell C2 in FIG. 1) located on the right side of the drawing.

[0065] As shown in FIG. 4A, local interconnections 141 to 144 extending in the Y direction are formed below the cell. Local interconnection 141 is connected to a portion in active region 2P3 that will become the source of dummy transistor DP1. Local interconnection 142 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP1 and a portion in active region 2P3 that will become the source of dummy transistor DP2. Local interconnection 143 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP2 and a portion in active region 2P3 that will become the source of dummy transistor DP3. Local interconnection 144 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP3.

[0066] As shown in FIG. 4B, local interconnections 145 to 148 extending in the Y direction are formed above the cell. Local interconnection 145 is connected to a portion of active region 2N3 that will become the source of dummy transistor DN1. Local interconnection 146 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN1 and a portion of active region 2N3 that will become the source of dummy transistor DN2. Local interconnection 147 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN2 and a portion of active region 2N3 that will become the source of dummy transistor DN3. Local interconnection 148 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN3.

[0067] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The power supply wiring 51 overlaps with the active region 2N3 in plan view.

[0068] 4, unlike the inverter cells C1 and C2, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the filler cell C3 is a standard cell that does not have a logic function.

[0069] In the block layout of FIG. 1 , a filler cell C3 without a logic function is arranged adjacent to an inverter cell C1 with a logic function. The inverter cell C1 includes an active region 2P1 and an active region 2N1. The filler cell C3 includes an active region 2P3 and an active region 2N3. The nanosheets 121-123 (124-126) of the filler cell C3 are arranged in the same position in the Y direction as the nanosheet 21 (22) of the inverter cell C1. The active region 2P3 (2N3) is arranged in the same position in the Y direction as the active region 2P1 (2N1). In other words, by arranging the active region in the filler cell C3, it is possible to suppress variations in the density of transistor arrangement. This reduces manufacturing variations in semiconductor integrated circuit devices and improves yield.

[0070] Furthermore, in the X direction, the active area closest to the active area 2P1 (2N1) of the inverter cell C1 is the active area 2P3 (2N3) of the filler cell C3. Therefore, the presence of the active area 2P3 (2N3) determines the distance of the active area 2P1 (2N1) to the adjacent transistor to a predetermined value. In other words, the presence of the active area in the filler cell C3 allows the distance from the active area closest to the cell edge of the logic cell (inverter cell C1) to the active area adjacent to that active area to be estimated to a predetermined value. This improves the accuracy of estimating the transistor performance of the logic cell.

[0071] Furthermore, the gate wiring 31 and dummy gate wiring 32, 33 (134) of the inverter cell C1, the gate wiring 31 and dummy gate wiring 32 (135), 33 of the inverter cell C2, and the dummy gate wiring 131 to 133 of the filler cell C3 are arranged at the same pitch Pg in the X direction. That is, the gate wiring (including the dummy gate wiring) of the inverter cells C1, C2 and filler cell C3 is arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yield.

[0072] Furthermore, the local wirings 41 and 42 of the inverter cell C1 (C2) and the local wirings 141 to 144 of the filler cell C3 are arranged at the same pitch P1 in the X direction. The local wirings 43 and 44 of the inverter cell C1 (C2) and the local wirings 145 to 148 of the filler cell C3 are arranged at the same pitch P1 in the X direction. That is, the local wirings of the inverter cells C1 and C2 and the filler cell C3 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0073] Furthermore, the bottom ends of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction, the bottom ends of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction, and the bottom ends of the active region 2P3 (2N3) of the filler cell C3 in the Y direction are arranged at the same position in the Y direction. That is, the bottom ends of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction, the bottom ends of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction, and the bottom ends of the active region 2P3 (2N3) of the filler cell C3 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C1 and C2 and the nanosheets 121 to 123 (124 to 126) of the filler cell C3 have their lower surfaces in the Y direction exposed from the gate wiring 31 and the dummy gate wiring 131 to 133, respectively. That is, in the inverter cells C1, C2, and filler cell C3, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row in which standard cells are arranged in the X direction, as in the configuration of Figure 1, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction, thereby making the shape of the structure, i.e., its size and layout area in the Y direction, uniform. This facilitates the manufacture of semiconductor integrated circuit devices.

[0074] The Y-direction width of the active region 2P1 (2N1) in the inverter cell C1 and the Y-direction width of the active region 2P3 (2N3) in the filler cell C3 are w1. The Y-direction width of the active region 2P2 (2N2) in the inverter cell C2 is w2, which is smaller than w1. The Y-direction bottom ends of the active region 2P1 (2N1) in the inverter cell C1, the Y-direction bottom ends of the active region 2P2 (2N2) in the inverter cell C2, and the Y-direction bottom ends of the active region 2P3 (2N3) in the filler cell C3 are aligned in the Y-direction. By disposing the filler cell C3 between the inverter cells C1 and C2, which have active regions with different Y-direction widths, the active region of the filler cell C3 can be positioned along the entire right side of the active region of the inverter cell C1 and the entire left side of the active region of the inverter cell C2. Therefore, the distances from the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2 to the active region 2P3 (2N3) of the filler cell C3 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0075] In this embodiment, the size of the filler cell C3 in the X direction is set to four grids, but is not limited to this.

[0076] In addition, in this embodiment, the filler cell C3 includes the local wirings 141 to 148, but it is not necessary to include some or all of these.

[0077] In this embodiment, the Y-direction widths of the active regions at the top and bottom of the inverter cells C1, C2, and filler cell C3 are equal, but they may be different. In this case, it is sufficient that the Y-direction width of the active region 2P3 of filler cell C3 is the same as the Y-direction width of the active region 2P1 of inverter cell C1 and is larger than the Y-direction width of the active region 2P3 of inverter cell C2. Similarly, it is sufficient that the Y-direction width of the active region 2N3 of filler cell C3 is the same as the Y-direction width of the active region 2N1 of inverter cell C1 and is larger than the Y-direction width of the active region 2N2 of inverter cell C2.

[0078] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of filler cell C3 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0079] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0080] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0081] Fig. 6(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 6(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0082] 6B shows a cross section of filler cell C3 of FIG. 4 taken along line Y1-Y1' in this configuration example. As shown in FIG. 6B, power supply wiring 11 for supplying VDD is formed in a wiring layer provided on the surface of chip B. Although not shown, in inverter cell C1 (C2), power supply wiring 11 is connected to active region 2P1 (2P2) of chip A through via 61.

[0083] This configuration example also provides the same effects as those of FIG.

[0084] 7A and 7B are plan views showing another example of the layout structure of filler cell C3 according to the first embodiment. Specifically, FIG. 7A shows the lower part of filler cell C3, and FIG. 7B shows the upper part of filler cell C3. In FIG. 7, compared to FIG. 4, the source and drain of each dummy transistor configured in active regions 2P3 and 2N3 are connected to the power supply wiring via vias.

[0085] 7A, the portion of the active region 2P3 that will become the source of the dummy transistor DP1 is connected to the power supply wiring 11 via a via 161. The portions of the active region 2P3 that will become the drain of the dummy transistor DP1 and the source of the dummy transistor DP2 are connected to the power supply wiring 11 via a via 162. The portions of the active region 2P3 that will become the drain of the dummy transistor DP2 and the source of the dummy transistor DP3 are connected to the power supply wiring 11 via a via 163. The portion of the active region 2P3 that will become the drain of the dummy transistor DP3 is connected to the power supply wiring 11 via a via 164. The vias 161 to 164 are formed in a region where the power supply wiring 11 and the active region 2P3 overlap in a planar view.

[0086] 7B, the portion that will become the source of dummy transistor DN1 in active region 2N3 is connected to power supply wiring 51 via via 165 and local wiring 145. The portions that will become the drain of dummy transistor DN1 and the source of dummy transistor DN2 in active region 2N3 are connected to power supply wiring 51 via via 166 and local wiring 146. The portions that will become the drain of dummy transistor DN2 and the source of dummy transistor DN3 in active region 2N3 are connected to power supply wiring 51 via via 167 and local wiring 147. The portion that will become the drain of dummy transistor DN3 in active region 2N3 is connected to power supply wiring 51 via via 168 and local wiring 148.

[0087] 7, the sources and drains of dummy transistors DP1 to DP3 configured in active region 2P3 are fixed to power supply voltage VDD. The sources and drains of dummy transistors DN1 to DN3 configured in active region 2N3 are fixed to power supply voltage VSS. This makes it possible to reduce the floating nodes of the dummy transistors configured in the active region, thereby stabilizing the operation of the circuit block.

[0088] In addition, the same effects as those in FIG. 4 can be obtained.

[0089] 8A and 8B are plan views showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. Specifically, Fig. 8A shows a lower part of a cell, and Fig. 8B shows an upper part of a cell.

[0090] In the layout of Fig. 8, a plurality of cells arranged in the X direction constitute a cell column. The plurality of cells includes inverter cells C4 and C5 having a logic function and a filler cell C6 having no logic function. In the layout of Fig. 8, the filler cell C6 is arranged between the inverter cells C4 and C5.

[0091] In each cell, power supply wiring is formed at the bottom of the drawing in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, power supply wiring (power supply wiring 11) that supplies power supply voltage VDD is formed in the BM0 wiring layer, and power supply wiring (power supply wiring 51) that supplies power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. Each cell column is arranged in a reversed manner in the Y direction for every other column. That is, in the block layout of FIG. 8, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column.

[0092] As will be described in detail later, the active region 2P6 (2N6) of the filler cell C6 is arranged to the right of the active region 2P4 (2N4) of the inverter cell C4 in the X direction of the drawing. The active region 2P6 (2N6) of the filler cell C6 is arranged to the left of the active region 2P5 (2N5) of the inverter cell C5 in the X direction of the drawing. In other words, the active regions of the filler cells that do not have a logic function are arranged adjacent to the active regions of the standard cells that have a logic function in the X direction.

[0093] (Configuration of inverter cell C4) Figure 9 is a plan view showing an example of the layout structure of inverter cells C4 and C5 according to the second embodiment. Specifically, Figure 9(a) shows the lower part of inverter cell C4, Figure 9(b) shows the upper part of inverter cell C4, Figure 9(c) shows the lower part of inverter cell C5, and Figure 9(d) shows the upper part of inverter cell C5. Note that the inverter circuits shown in Figure 3 are configured in the inverter cells C4 and C5 in Figure 9, respectively.

[0094] 9A, the BM0 wiring layer has a power supply wiring 11 formed at the bottom end of the cell in the Y direction in the drawing, the power supply wiring 11 extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD.

[0095] An active region 2P4 is formed in the P-type transistor region below the cell. The active region 2P4 overlaps with the power supply wiring 11 in plan view.

[0096] A transistor P1 is formed in the active region 2P4. The transistor P1 has a nanosheet 21 extending in the X direction. In the active region 2P4, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 through a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P4 overlap in a plan view.

[0097] 9B, an active region 2N4 is formed in the N-type transistor region in the upper part of the cell. The active region 2N4 is arranged higher in the Z direction than the active region 2P4. The active region 2N4 overlaps with the active region 2P4 in plan view.

[0098] The active region 2N4 has a transistor N1 formed therein. The transistor N1 has a nanosheet 22 extending in the X direction.

[0099] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0100] The gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower sides of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper sides of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0101] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0102] 9A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P4 that will become the source of the transistor P1. The local wiring 42 is connected to a portion of the active region 2P4 that will become the drain of the transistor P1.

[0103] 9B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N4 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N4 that will become the drain of the transistor N1.

[0104] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction and wirings 52 and 53. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0105] The power supply wiring 51 is formed at the bottom end of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N4 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N4 that will become the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N4 overlap in plan view.

[0106] The wiring 52 is disposed near the center of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N4 overlap in a plan view.

[0107] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 42, 44.

[0108] As described above, the inverter cell C4 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0109] As shown in FIGS. 9A and 9B, the active regions 2P4 and 2N4 in the inverter cell C4 have a width w1 in the Y direction in plan view.

[0110] In the inverter cell C4 shown in FIG. 9 , the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P4 (2N4) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P4 and 2N4 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0111] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P4 (2N4) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P4 (2N4) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P4 (2N4) is positioned closer to the lower end of the cell frame in the Y direction when the center of the cell frame in the Y direction is used as the reference. That is, in a planar view, the center of the active region 2P4 (2N4) in the Y direction is lower than the center of the cell frame in the Y direction.

[0112] Furthermore, power supply wiring 11, 51 is formed at the lower end of the cell in the Y direction in plan view, and is shared with the standard cell arranged below inverter cell C4 in the Y direction in the drawing. Thus, by placing inverter cell C4 in the circuit block of Figure 8, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and suppressing the occurrence of electromigration due to current concentration.

[0113] Furthermore, the via 61 connecting the power supply wiring 11 and the portion of the active region 2P4 that serves as the source of the transistor P1 is formed in the region where the power supply wiring 11 and the active region 2P4 overlap in a planar view. In planar view, the via 61 is disposed toward the upper side of the region where the power supply wiring 11 and the active region 2P4 overlap in a planar view. In other words, in planar view, the distance d4 in the Y direction from the center of the via 61 to the upper end of the power supply wiring 11 is smaller than the distance d5 in the Y direction from the center of the via 61 to the lower end of the active region 2P4. As a result, since the via 61 is disposed toward the center of the active region 2P4 in the Y direction, the difference in resistance between the via 61 to the upper end of the nanosheet 21 of the transistor P1 in the active region 2P4 and the via 61 to the lower end of the nanosheet 21 of the transistor P1 in the active region 2P4 is reduced. Therefore, the current flowing through the transistor P1 is equalized in the Y direction (up and down in the drawing), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0114] Furthermore, the via 62 connecting the power supply wiring 51 and the portion of the active region 2N4 that serves as the source of the transistor N1 is formed in the area where the power supply wiring 51 and the active region 2N4 overlap in a planar view. In planar view, the via 62 is disposed toward the upper side of the area where the power supply wiring 51 and the active region 2N4 overlap in a planar view. In other words, in planar view, the distance d4 in the Y direction from the center of the via 62 to the upper end of the power supply wiring 51 is smaller than the distance d5 in the Y direction from the center of the via 62 to the lower end of the active region 2N4. As a result, since the via 62 is disposed toward the center of the active region 2N4 in the Y direction, the difference in resistance between the via 62 to the upper end of the nanosheet 22 of the transistor N1 in the active region 2N4 and the via 62 to the lower end of the nanosheet 22 of the transistor N1 in the active region 2N4 is reduced. Therefore, the current flowing through the transistor N1 is equalized in the Y direction (up and down in the drawing), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0115] Furthermore, via 63 connecting wiring 52 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N4 and gate wiring 31. This makes it possible to reduce the distance from wiring 52 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance value from wiring 52 and enabling the speed of the semiconductor integrated circuit device to be increased.

[0116] Furthermore, the wiring 53 is disposed above the wiring 52 in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31, opposite the side where the active region 2N4 is disposed closer to the cell frame). The via 64 connecting the wiring 53 to the local wiring 44 and the via 65 connecting the local wirings 42 and 44 are formed above the wiring 52 in the Y direction in plan view. This reduces the distance from the wiring 53 to the portion of the active region 2P4 that serves as the drain of the transistor P1 and the portion of the active region 2N4 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P4 (2N4) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0117] (Configuration of Inverter Cell C5) The inverter cell C5 has a configuration similar to that of the inverter cell C4. Specifically, the inverter cell C5 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C5 is a standard cell having a logic function.

[0118] As shown in Figures 9(c) and (d), compared to the inverter cell C4 shown in Figures 9(a) and (b), the inverter cell C5 has active regions 2P5 and 2N5, each having a different width in the Y direction, instead of the active regions 2P4 and 2N4.

[0119] Specifically, the active regions 2P5 and 2N5 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C4 is greater than the drive capability of the inverter cell C5.

[0120] 9, the bottom edge of the active region 2P5 (2N5) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P4 (2N4) in the Y direction. That is, the bottom edge of the active region 2P4 (2N4) of the inverter cell C4 in the Y direction and the bottom edge of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction are aligned.

[0121] (Configuration of filler cell C6) Figure 10 is a plan view showing an example of the layout structure of a filler cell according to the second embodiment. Specifically, Figure 10(a) shows the lower part of the cell, and Figure 10(b) shows the upper part of the cell. In filler cell C6 of Figure 10, the arrangement of power supply wiring 11, 51 is different from that of filler cell C3 of Figure 4. Active regions 2P6, 2N6 are formed instead of active regions 2P3, 2N3.

[0122] 10A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0123] An active region 2P6 is formed in the P-type transistor region. Dummy transistors DP1 to DP3 are formed in the active region 2P6. The active region 2P6 overlaps with the power supply wiring 11 in plan view.

[0124] 10B, an active region 2N6 is formed in the N-type transistor region. The active region 2N6 is disposed above the active region 2P6 in the Z direction. The active region 2N6 overlaps with the active region 2P6 in plan view. Dummy transistors DN1 to DN3 are formed in the active region 2N6.

[0125] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The power supply wiring 51 overlaps with the active region 2N6 in plan view.

[0126] 10, unlike the inverter cells C4 and C5, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the filler cell C6 is a standard cell that does not have a logic function.

[0127] In the block layout of FIG. 8, filler cell C6, which does not have a logic function, is arranged adjacent to inverter cell C4, which has a logic function. Inverter cell C4 has active region 2P4 and active region 2N4. Filler cell C6 has active region 2P6 and active region 2N6. Nanosheets 121-123 (124-126) of filler cell C6 are arranged in the same position in the Y direction as nanosheet 21 (22) of inverter cell C4. Active region 2P6 (2N6) is arranged in the same position in the Y direction as active region 2P4 (2N4). In other words, by arranging an active region in filler cell C6, it is possible to suppress variations in the density of transistor arrangement. This reduces manufacturing variations in semiconductor integrated circuit devices and improves yield.

[0128] Furthermore, in the X direction, the active area closest to the active area 2P4 (2N4) of the inverter cell C4 is the active area 2P6 (2N6) of the filler cell C6. Therefore, the presence of the active area 2P6 (2N6) determines the distance of the active area 2P4 (2N4) to the adjacent transistor to a predetermined value. That is, the presence of the active area in the filler cell C6 allows the distance from the active area closest to the cell edge of the logic cell (inverter cell C4) to the active area adjacent to that active area to be estimated to a predetermined value. This improves the accuracy of estimating the transistor performance of the logic cell.

[0129] Furthermore, the gate wiring 31 and dummy gate wiring 32, 33 (134) of inverter cell C4, the gate wiring 31 and dummy gate wiring 32 (135), 33 of inverter cell C5, and the dummy gate wiring 131 to 133 of filler cell C6 are arranged at the same pitch Pg in the X direction. That is, the gate wiring (including the dummy gate wiring) of inverter cells C4, C5 and filler cell C6 is arranged regularly. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices and improve yields.

[0130] Furthermore, the local wirings 41 and 42 of the inverter cell C4 (C5) and the local wirings 141 to 144 of the filler cell C6 are arranged at the same pitch P1 in the X direction. The local wirings 43 and 44 of the inverter cell C4 (C5) and the local wirings 145 to 148 of the filler cell C6 are arranged at the same pitch P1 in the X direction. That is, the local wirings of the inverter cells C4 and C5 and the filler cell C6 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0131] Furthermore, the bottom edges of the active region 2P4 (2N4) of the inverter cell C4 in the Y direction, the bottom edges of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction, and the bottom edges of the active region 2P6 (2N6) of the filler cell C6 in the Y direction are arranged at the same position in the Y direction. That is, the bottom edges of the active region 2P4 (2N4) of the inverter cell C4 in the Y direction, the bottom edges of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction, and the bottom edges of the active region 2P6 (2N6) of the filler cell C6 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C4 and C5 and the nanosheets 121 to 123 (124 to 126) of the filler cell C6 have their lower surfaces exposed from the gate wiring 31 and the dummy gate wiring 131 to 133, respectively. That is, in inverter cells C4 and C5 and filler cell C6, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and placement area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0132] The Y-direction width of the active region 2P4 (2N4) in the inverter cell C4 and the Y-direction width of the active region 2P6 (2N6) in the filler cell C6 are w1. The Y-direction width of the active region 2P5 (2N5) in the inverter cell C5 is w2, which is smaller than w1. The Y-direction bottom ends of the active region 2P4 (2N4) in the drawing of the inverter cell C4, the Y-direction bottom ends of the active region 2P5 (2N5) in the drawing of the inverter cell C5, and the Y-direction bottom ends of the active region 2P6 (2N6) in the drawing of the filler cell C6 are aligned in the Y-direction. By disposing the filler cell C6 between the inverter cells C4 and C5, which have active regions with different Y-direction widths, the active region of the filler cell C6 can be positioned along the entire right side surface of the active region of the inverter cell C4 and the entire left side surface of the active region of the inverter cell C5. Therefore, the distances from the active region 2P4 (2N4) of the inverter cell C4 and the active region 2P5 (2N5) of the inverter cell C5 to the active region 2P6 (2N6) of the filler cell C6 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0133] In this embodiment, the size of the filler cell C6 in the X direction is set to four grids, but is not limited to this.

[0134] In addition, in this embodiment, the filler cell C6 includes the local interconnections 141 to 148, but it is not necessary to include some or all of these.

[0135] In this embodiment, the Y-direction widths of the active regions at the top and bottom of the inverter cells C4, C5, and filler cell C6 are equal, but they may be different. In this case, it is sufficient that the Y-direction width of the active region 2P6 of filler cell C6 is the same as the Y-direction width of the active region 2P4 of inverter cell C4 and is larger than the Y-direction width of the active region 2P5 of inverter cell C5. Similarly, it is sufficient that the Y-direction width of the active region 2N6 of filler cell C6 is the same as the Y-direction width of the active region 2N4 of inverter cell C4 and is larger than the Y-direction width of the active region 2N5 of inverter cell C5.

[0136] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of filler cell C6 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0137] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0138] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P6 and 2N6 of the filler cell C6 may be connected to the power supply wirings 11 and 51 through vias.

[0139] 11A and 11B are plan views showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a third embodiment. Specifically, FIG. 11A shows a lower part of a cell, and FIG. 11B shows an upper part of a cell.

[0140] 11, a plurality of cells arranged in the X direction constitute a cell column. The plurality of cells includes inverter cells C7 and C8 having a logic function and a filler cell C9 having no logic function. In the layout of FIG. 11, the filler cell C9 is disposed between the inverter cells C7 and C8.

[0141] In each cell, power supply wiring is formed at the top end of the drawing in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, power supply wiring (power supply wiring 11) that supplies power supply voltage VDD is formed in the BM0 wiring layer, and power supply wiring (power supply wiring 51) that supplies power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. Each cell column is arranged in a reversed manner in the Y direction for every other column. That is, in the block layout of FIG. 11, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column.

[0142] As will be described in detail later, the active region 2P9 (2N9) of the filler cell C9 is arranged to the right of the active region 2P7 (2N7) of the inverter cell C7 in the X direction of the drawing. The active region 2P9 (2N9) of the filler cell C9 is arranged to the left of the active region 2P8 (2N8) of the inverter cell C8 in the X direction of the drawing. In other words, the active regions of the filler cells that do not have a logic function are arranged adjacent to the active regions of the standard cells that have a logic function in the X direction.

[0143] (Configuration of inverter cell C7) Figure 12 is a plan view showing an example of the layout structure of inverter cells C7 and C8 according to the third embodiment. Specifically, Figure 12(a) shows the lower part of inverter cell C7, Figure 12(b) shows the upper part of inverter cell C7, Figure 12(c) shows the lower part of inverter cell C8, and Figure 12(d) shows the upper part of inverter cell C8. Note that the inverter circuits shown in Figure 3 are configured in the inverter cells C7 and C8 in Figure 12, respectively.

[0144] 12A, the BM0 wiring layer has a power supply wiring 11 formed at the upper end of the cell in the Y direction in the drawing, the power supply wiring 11 extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD.

[0145] An active region 2P7 is formed in the P-type transistor region at the bottom of the cell. A transistor P1 is formed in the active region 2P7. The transistor P1 has a nanosheet 21 extending in the X direction.

[0146] 12B, an active region 2N7 is formed in the N-type transistor region in the upper part of the cell. The active region 2N7 is arranged higher in the Z direction than the active region 2P7. The active region 2N7 overlaps with the active region 2P7 in plan view.

[0147] The active region 2N7 includes a transistor N1. The transistor N1 includes a nanosheet 22.

[0148] A gate wiring 31 extending in the Y direction is formed in the center of the cell in the X direction in the drawing. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of the transistors P1 and N1.

[0149] The gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower surfaces of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper surfaces of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0150] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0151] 12A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P7 that will become the source of the transistor P1. The local wiring 41 is connected to the power supply wiring 11 through a via 61. The via 61 is formed in a region where the local wiring 41 and the power supply wiring 11 overlap in a planar view. That is, the power supply wiring 11 is connected to a portion of the active region 2P7 that will become the source of the transistor P1 through the via 61 and the local wiring 41. The local wiring 42 is connected to a portion of the active region 2P7 that will become the drain of the transistor P1.

[0152] 12B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N7 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N7 that will become the drain of the transistor N1.

[0153] In the M0 wiring layer, a power supply wiring 51 extending in the X direction and wirings 52 and 53 are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0154] The power supply wiring 51 is formed at the upper end of the cell in the Y direction in the drawing. The power supply wiring 51 is connected to a portion of the active region 2N7 that serves as the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in a region where the power supply wiring 51 and the local wiring 43 overlap in a plan view.

[0155] The wiring 52 is disposed near the center of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N7 overlap in a plan view.

[0156] In a plan view, the wiring 53 is disposed between the power supply wiring 51 and the wiring 52. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and the local wirings 42, 44.

[0157] As described above, the inverter cell C7 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C7 is a standard cell having a logic function.

[0158] As shown in FIGS. 12A and 12B, the active regions 2P7 and 2N7 in the inverter cell C7 have a width of w1 in the Y direction in plan view.

[0159] In the inverter cell C7 shown in FIG. 12, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P7 (2N7) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P7 and 2N7 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0160] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P7 (2N7) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P7 (2N7) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P7 (2N7) is positioned closer to the lower end of the cell frame in the Y direction when the center of the cell frame in the Y direction is used as the reference. That is, in a planar view, the center of the active region 2P7 (2N7) in the Y direction is lower than the center of the cell frame in the Y direction.

[0161] Furthermore, power supply wiring 11, 51 is formed at the upper end of the cell in the Y direction in plan view, and is shared with the standard cell arranged above inverter cell C7 in the Y direction in the drawing. Thus, by placing inverter cell C7 in the circuit block of Fig. 11, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and suppressing the occurrence of electromigration due to current concentration.

[0162] Furthermore, in a plan view, the power supply wiring 11 (51) does not overlap with the active region 2P7 (2N7). This reduces the load capacitance of the power supply wiring 11 (51) that supplies the power supply voltage VDD (VSS) to the transistor P1 (N1) configured in the active region 2P7 (2N7), thereby enabling the semiconductor integrated circuit device to operate at a higher speed. Note that, in a plan view, the power supply wiring 11 (51) may overlap with the active region 2P7 (2N7). In this case, the overlapping area between the power supply wiring 11 (51) and the active region 2P7 (2N7) can be made smaller than in the inverter cell C4 of FIG. 9, enabling the semiconductor integrated circuit device to operate at a higher speed.

[0163] Furthermore, via 63 connecting wiring 52 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N7 and gate wiring 31. This reduces the distance from wiring 52 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance from wiring 52 and enabling the semiconductor integrated circuit device to operate at a higher speed.

[0164] Furthermore, the wiring 53 is disposed higher in the Y direction than the wiring 52 in the drawing (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N7 is disposed closer to the cell frame). The via 64 connecting the wiring 53 and the local wiring 44 and the via 65 connecting the local wirings 42 and 44 are formed higher in the Y direction than the wiring 52 in a plan view. This reduces the distance from the wiring 53 to the portion of the active region 2P7 that serves as the drain of the transistor P1 and the portion of the active region 2N7 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P7 (2N7) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0165] Furthermore, the via 61 connecting the power supply wiring 11 and the local wiring 41 connected to the portion of the active region 2P7 that serves as the source of the transistor P1 is formed in a region where the power supply wiring 11 and the local wiring 41 overlap in a planar view. In a planar view, the via 61 is disposed toward the lower side of the region where the power supply wiring 11 and the local wiring 41 overlap in a planar view. In other words, in a planar view, the distance d6 in the Y direction from the center of the via 61 to the bottom edge of the power supply wiring 11 is smaller than the distance d7 in the Y direction from the center of the via 61 to the top edge of the local wiring 41. This positions the via 61 closer to the active region 2P7, thereby reducing the resistance from the via 61 to the nanosheet 21 and increasing the speed of the semiconductor integrated circuit device.

[0166] Furthermore, the via 62 connecting the power supply wiring 51 and the local wiring 43 connected to the portion of the active region 2N7 that serves as the source of the transistor N1 is formed in a region where the power supply wiring 51 and the local wiring 43 overlap in a planar view. In a planar view, the via 62 is disposed toward the lower side of the region where the power supply wiring 51 and the local wiring 43 overlap in a planar view. In other words, in a planar view, the distance d6 in the Y direction from the center of the via 62 to the bottom edge of the power supply wiring 51 is smaller than the distance d7 in the Y direction from the center of the via 62 to the top edge of the local wiring 43. This positions the via 62 closer to the active region 2N7, thereby reducing the resistance from the via 62 to the nanosheet 22 and increasing the speed of the semiconductor integrated circuit device.

[0167] (Configuration of Inverter Cell C8) The inverter cell C8 has a configuration similar to that of the inverter cell C7. Specifically, the inverter cell C8 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C8 is a standard cell having a logic function.

[0168] As shown in Figures 12(c) and (d), compared to inverter cell C7 shown in Figures 12(a) and (b), inverter cell C8 has active regions 2P8 and 2N8 with different widths in the Y direction arranged therein instead of active regions 2P7 and 2N7.

[0169] Specifically, the active regions 2P8 and 2N8 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C7 is greater than the drive capability of the inverter cell C8.

[0170] 12, the bottom edge of the active region 2P8 (2N8) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2N7 (2N7). That is, the bottom edge of the active region 2P7 (2N7) of the inverter cell C7 in the Y direction and the bottom edge of the active region 2P8 (2N8) of the inverter cell C8 in the Y direction are aligned.

[0171] (Configuration of filler cell C9) Figure 13 is a plan view showing an example of the layout structure of a filler cell according to the third embodiment. Specifically, Figure 13(a) shows the lower part of the cell, and Figure 13(b) shows the upper part of the cell. In filler cell C9 of Figure 13, the arrangement of power supply wiring 11, 51 is different from that of filler cell C3 of Figure 4. Active regions 2P9, 2N9 are formed instead of active regions 2P3, 2N3.

[0172] 13A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0173] An active region 2P9 is formed in the P-type transistor region, and dummy transistors DP1 to DP3 are formed in the active region 2P9.

[0174] 13B, an active region 2N9 is formed in the N-type transistor region. The active region 2N9 is disposed above the active region 2P9 in the Z direction. The active region 2N9 overlaps with the active region 2P9 in plan view. Dummy transistors DN1 to DN3 are formed in the active region 2N9.

[0175] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0176] 13, unlike the inverter cells C7 and C8, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the filler cell C9 is a standard cell that does not have a logic function.

[0177] In the block layout of FIG. 11 , a filler cell C9 without a logic function is arranged adjacent to an inverter cell C7 with a logic function. The inverter cell C7 includes an active region 2P7 and an active region 2N7. The filler cell C9 includes an active region 2P9 and an active region 2N9. Nanosheets 121-123 (124-126) of the filler cell C9 are arranged in the same position in the Y direction as nanosheet 21 (22) of the inverter cell C7. The active region 2P9 (2N9) is arranged in the same position in the Y direction as the active region 2P7 (2N7). In other words, by arranging an active region in the filler cell C9, it is possible to suppress variations in the density of transistor arrangement. This reduces manufacturing variations in semiconductor integrated circuit devices and improves yield.

[0178] Furthermore, in the X direction, the active area closest to the active area 2P7 (2N7) of the inverter cell C7 is the active area 2P9 (2N9) of the filler cell C9. Therefore, the presence of the active area 2P9 (2N9) determines the distance of the active area 2P7 (2N7) to the adjacent transistor to a predetermined value. In other words, the presence of the active area in the filler cell C9 allows the distance from the active area closest to the cell edge of the logic cell (inverter cell C7) to the active area adjacent to that active area to be estimated to a predetermined value. This improves the accuracy of estimating the transistor performance of the logic cell.

[0179] Furthermore, the gate wiring 31 and dummy gate wiring 32, 33 (134) of inverter cell C7, the gate wiring 31 and dummy gate wiring 32 (135), 33 of inverter cell C8, and the dummy gate wiring 131 to 133 of filler cell C9 are arranged at the same pitch Pg in the X direction. That is, the gate wiring (including the dummy gate wiring) of inverter cells C7, C8 and filler cell C9 is arranged regularly. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices and improve yields.

[0180] Furthermore, local wirings 41 and 42 of inverter cell C7 (C8) and local wirings 141 to 144 of filler cell C9 are arranged at the same pitch P1 in the X direction. Local wirings 43 and 44 of inverter cell C7 (C8) and local wirings 145 to 148 of filler cell C9 are arranged at the same pitch P1 in the X direction. That is, the local wirings of inverter cells C7 and C8 and filler cell C9 are arranged regularly. This makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices and improve yields.

[0181] Furthermore, the bottom end of the active region 2P7 (2N7) of the inverter cell C7 in the Y direction, the bottom end of the active region 2P8 (2N8) of the inverter cell C8 in the Y direction, and the bottom end of the active region 2P9 (2N9) of the filler cell C9 in the Y direction are arranged at the same position in the Y direction. That is, the bottom end of the active region 2P7 (2N7) of the inverter cell C7 in the Y direction, the bottom end of the active region 2P8 (2N8) of the inverter cell C8 in the Y direction, and the bottom end of the active region 2P9 (2N9) of the filler cell C9 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C7 and C8 and the nanosheets 121 to 123 (124 to 126) of the filler cell C9 have their lower surfaces in the Y direction exposed from the gate wiring 31 and the dummy gate wiring 131 to 133, respectively. That is, in inverter cells C7 and C8 and filler cell C9, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., the size and placement area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0182] The Y-direction width of the active region 2P7 (2N7) in the inverter cell C7 and the Y-direction width of the active region 2P9 (2N9) in the filler cell C9 are w1. The Y-direction width of the active region 2P8 (2N8) in the inverter cell C8 is w2, which is smaller than w1. The Y-direction bottom edges of the active region 2P7 (2N7) in the inverter cell C7, the Y-direction bottom edges of the active region 2P8 (2N8) in the inverter cell C8, and the Y-direction bottom edges of the active region 2P9 (2N9) in the filler cell C9 are aligned in the Y-direction. By disposing the filler cell C9 between the inverter cells C7 and C8, which have active regions with different Y-direction widths, the active region of the filler cell C9 can be positioned along the entire right side of the active region of the inverter cell C7 and the entire left side of the active region of the inverter cell C8. Therefore, the distances from the active region 2P7 (2N7) of the inverter cell C7 and the active region 2P8 (2N8) of the inverter cell C8 to the active region 2P9 (2N9) of the filler cell C9 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0183] In this embodiment, the size of the filler cell C9 in the X direction is set to four grids, but is not limited to this.

[0184] In addition, in this embodiment, the filler cell C9 includes the local interconnections 141 to 148, but it may not include some or all of these.

[0185] In this embodiment, the Y-direction widths of the active regions at the top and bottom of the inverter cells C7, C8, and filler cell C9 are equal, but they may be different. In this case, it is sufficient that the Y-direction width of the active region 2P9 of filler cell C9 is the same as the Y-direction width of the active region 2P7 of inverter cell C7 and is larger than the Y-direction width of the active region 2P8 of inverter cell C8. Similarly, it is sufficient that the Y-direction width of the active region 2N9 of filler cell C9 is the same as the Y-direction width of the active region 2N7 of inverter cell C7 and is larger than the Y-direction width of the active region 2N8 of inverter cell C8.

[0186] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of filler cell C9 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0187] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0188] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P9 and 2N9 of the filler cell C9 may be connected to the power supply wirings 11 and 51 through vias.

[0189] 14A and 14B are plan views showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a fourth embodiment. Specifically, FIG. 14A shows a lower part of a cell, and FIG. 14B shows an upper part of a cell.

[0190] In the layout of Fig. 14, a plurality of cells arranged in the X direction constitute a cell column. The plurality of cells include inverter cells C10 and C11 having a logic function and a filler cell C12 having no logic function. In the layout of Fig. 14, the filler cell C12 is arranged between the inverter cells C10 and C11.

[0191] In each cell, power supply wiring is formed in the BM0 wiring layer at both the top and bottom ends in the Y direction in the drawing. Each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row is arranged inverted in the Y direction. At the boundary between adjacent cell rows, the power supply wiring (power supply wiring 11) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0192] As will be described in detail later, the active region 2P12 (2N12) of the filler cell C12 is arranged on the right side of the active region 2P10 (2N10) of the inverter cell C10 in the X direction of the drawing. The active region 2P12 (2N12) of the filler cell C12 is arranged on the left side of the active region 2P11 (2N11) of the inverter cell C11 in the X direction of the drawing. In other words, the active regions of filler cells that do not have a logic function are arranged adjacent to the active regions of the standard cells that have a logic function in the X direction.

[0193] (Configuration of inverter cell C10) Figure 15 is a plan view showing an example of the layout structure of inverter cells C10 and C11 according to the fourth embodiment. Specifically, Figure 15(a) shows the lower part of inverter cell C10, Figure 15(b) shows the upper part of inverter cell C10, Figure 15(c) shows the lower part of inverter cell C11, and Figure 15(d) shows the upper part of inverter cell C11. Note that the inverter cells C10 and C11 in Figure 15 each have the inverter circuit of Figure 3 configured therein.

[0194] 15A, a BM0 wiring layer is formed. Power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0195] An active region 2P10 is formed in the P-type transistor region below the cell. The active region 2P10 overlaps with the power supply wiring 11 in plan view.

[0196] A transistor P1 is formed in the active region 2P10. The transistor P1 has a nanosheet 21 extending in the X direction. In the active region 2P10, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 through a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P10 overlap in a plan view.

[0197] 15B, an active region 2N10 is formed in the N-type transistor region in the upper part of the cell. The active region 2N10 is arranged higher in the Z direction than the active region 2P10. The active region 2N10 overlaps with the active region 2P10 in a plan view.

[0198] The active region 2N10 includes a transistor N1. The transistor N1 has a nanosheet 22 extending in the X direction.

[0199] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0200] The gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower surfaces of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper surfaces of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0201] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0202] 15A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P10 that will become the source of the transistor P1. The local wiring 42 is connected to a portion of the active region 2P10 that will become the drain of the transistor P1.

[0203] As shown in FIG. 15B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N10 that will become the source of the transistor N1. The local wiring 43 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in a region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. That is, the power supply wiring 12 is connected to a portion of the active region 2N10 that will become the source of the transistor N1 via the via 62 and the local wiring 43. The local wiring 44 is connected to a portion of the active region 2N10 that will become the drain of the transistor N1.

[0204] In the M0 wiring layer, wirings 52 and 53 extending in the X direction are formed. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0205] The wiring 52 is disposed near the center of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N10 overlap in a plan view.

[0206] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 42, 44.

[0207] As described above, the inverter cell C10 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C10 is a standard cell having a logic function.

[0208] As shown in FIGS. 15A and 15B, the active regions 2P10 and 2N10 in the inverter cell C10 have a width w1 in the Y direction in plan view.

[0209] In the inverter cell C10 shown in FIG. 15, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in adjacent cells in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P10 (2N10) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P10 and 2N10 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0210] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P10 (2N10) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P10 (2N10) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P10 (2N10) is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as a reference. That is, in plan view, the center of the active region 2P10 (2N10) in the Y direction is located below the center of the cell frame in the Y direction.

[0211] Furthermore, power supply wiring 11 is formed at the bottom end of the cell in the Y direction in plan view, and is shared with the standard cell arranged below inverter cell C10 in the Y direction in the drawing. Power supply wiring 12 is formed at the top end of the cell in the Y direction in plan view, and is shared with the standard cell arranged above inverter cell C10 in the Y direction in the drawing. Thus, by placing inverter cell C10 in the circuit block of Figure 14, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and preventing electromigration due to current concentration.

[0212] Furthermore, the via 61 connecting the power supply wiring 11 and the portion of the active region 2P10 that serves as the source of the transistor P1 is formed in the area where the power supply wiring 11 and the active region 2P10 overlap in a planar view. In planar view, the via 61 is disposed toward the upper side of the area where the power supply wiring 11 and the active region 2P10 overlap in a planar view. In other words, in planar view, the distance d4 in the Y direction from the center of the via 61 to the upper end of the power supply wiring 11 is smaller than the distance d5 in the Y direction from the center of the via 61 to the lower end of the active region 2P10. As a result, since the via 61 is disposed toward the center of the active region 2P10 in the Y direction, the difference in resistance between the via 61 to the upper end of the nanosheet 21 of the transistor P1 in the active region 2P10 and the via 61 to the lower end of the nanosheet 21 of the transistor P1 in the active region 2P10 is reduced. Therefore, the current flowing through the transistor P1 is equalized in the Y direction (up and down in the drawing), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0213] Furthermore, the power supply wiring 12 is connected to the portion of the active region 2N10 that serves as the source of the transistor N1 via the via 62 and the local wiring 43. The via 62 connects the power supply wiring 12 formed in the BM0 wiring layer to the local wiring 43 formed above the cell, and therefore has a long length in the Z direction. As described above, the distance d1 from the bottom edge of the active region 2P10 (2N10) in the Y direction to the bottom edge of the cell frame in the Y direction is smaller than the distance d2 from the top edge of the active region 2P10 (2N10) in the Y direction to the top edge of the cell frame in the Y direction. This allows for a larger area from the top edge of the active region 2P10 (2N10) in the Y direction to the top edge of the cell frame in the Y direction, making it easier to form the via 62 in that area. This facilitates the manufacture of semiconductor integrated circuit devices, and improves yield and reliability.

[0214] Furthermore, the via 62 is formed in a region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. In a planar view, the via 62 is disposed toward the lower side of the region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. In other words, in a planar view, a distance d8 in the Y direction from the center of the via 62 to the bottom end of the power supply wiring 12 is smaller than a distance d9 in the Y direction from the center of the via 62 to the top end of the local wiring 43. This positions the via 62 closer to the active region 2N10, thereby reducing the resistance from the power supply wiring 12 to the portion of the active region 2N10 that serves as the source of the transistor N1, thereby enabling an increase in the speed of the semiconductor integrated circuit device.

[0215] Furthermore, via 63 connecting wiring 52 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N10 and gate wiring 31. This makes it possible to reduce the distance from wiring 52 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance value from wiring 52 and enabling the speed of the semiconductor integrated circuit device to be increased.

[0216] Furthermore, the wiring 53 is disposed above the wiring 52 in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31, and opposite the side where the active region 2N10 is disposed closer to the cell frame). The via 64 connecting the wiring 53 and the local wiring 44 and the via 65 connecting the local wirings 44 and 42 are formed above the wiring 52 in the Y direction in plan view. This reduces the distance from the wiring 53 to the portion of the active region 2P10 that serves as the drain of the transistor P1 and the portion of the active region 2N10 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P10 (2N10) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0217] (Configuration of Inverter Cell C11) The inverter cell C11 has a configuration similar to that of the inverter cell C10. Specifically, the inverter cell C10 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C10 is a standard cell having a logic function.

[0218] As shown in Figures 15(c) and (d), compared to the inverter cell C10 shown in Figures 15(a) and (b), the inverter cell C11 has active regions 2P11 and 2N11 with different widths in the Y direction arranged therein instead of the active regions 2P10 and 2N10.

[0219] Specifically, the active regions 2P11 and 2N11 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C10 is greater than the drive capability of the inverter cell C11.

[0220] 15, the bottom edge of the active region 2P11 (2N11) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P10 (2N10) in the Y direction. That is, the bottom edge of the active region 2P10 (2N10) of the inverter cell C10 in the Y direction and the bottom edge of the active region 2P11 (2N11) of the inverter cell C11 in the Y direction are aligned.

[0221] (Configuration of filler cell C12) Figure 16 is a plan view showing an example of the layout structure of a filler cell according to the fourth embodiment. Specifically, Figure 16(a) shows the lower part of the cell, and Figure 16(b) shows the upper part of the cell. In the filler cell C12 of Figure 16, compared to the filler cell C3 of Figure 4, power supply wirings 11 and 12 are formed in the BM0 wiring layer, and the power supply wiring 51 in the M0 wiring layer is omitted.

[0222] 16A, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0223] An active region 2P12 is formed in the P-type transistor region. Dummy transistors DP1 to DP3 are formed in the active region 2P12. The active region 2P12 overlaps with the power supply wiring 11 in a plan view.

[0224] 16B, an active region 2N12 is formed in the N-type transistor region. The active region 2N12 is arranged higher in the Z direction than the active region 2P12. The active region 2N12 overlaps with the active region 2P12 in a plan view. Dummy transistors DN1 to DN3 are formed in the active region 2N12.

[0225] 16, unlike the inverter cells C10 and C11, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the filler cell C12 is a standard cell that does not have a logic function.

[0226] In the block layout of FIG. 14, a filler cell C12 without a logic function is arranged adjacent to an inverter cell C10 with a logic function. The inverter cell C10 includes an active region 2P10 and an active region 2N10. The filler cell C12 includes an active region 2P12 and an active region 2N12. The nanosheets 121-123 (124-126) of the filler cell C12 are arranged in the same position in the Y direction as the nanosheet 21 (22) of the inverter cell C10. The active region 2P12 (2N12) is arranged in the same position in the Y direction as the active region 2P10 (2N10). In other words, by arranging the active region in the filler cell C12, it is possible to suppress variations in the density of transistor arrangement. This reduces manufacturing variations in semiconductor integrated circuit devices and improves yield.

[0227] Furthermore, in the X direction, the active area closest to the active area 2P10 (2N10) of the inverter cell C10 is the active area 2P12 (2N12) of the filler cell C12. Therefore, the presence of the active area 2P12 (2N12) determines the distance of the active area 2P10 (2N10) to the adjacent transistor to a predetermined value. In other words, the presence of the active area in the filler cell C12 allows the distance from the active area closest to the cell edge of the logic cell (inverter cell C10) to the active area adjacent to that active area to be estimated to a predetermined value. This improves the accuracy of estimating the transistor performance of the logic cell.

[0228] Furthermore, the gate wiring 31 and dummy gate wiring 32, 33 (134) of the inverter cell C10, the gate wiring 31 and dummy gate wiring 32 (135), 33 of the inverter cell C11, and the dummy gate wiring 131 to 133 of the filler cell C12 are arranged at the same pitch Pg in the X direction. That is, the gate wiring (including the dummy gate wiring) of the inverter cells C10, C11 and the filler cell C12 is arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yield.

[0229] Furthermore, the local wirings 41 and 42 of the inverter cell C10 (C11) and the local wirings 141 to 144 of the filler cell C12 are arranged at the same pitch P1 in the X direction. The local wirings 43 and 44 of the inverter cell C10 (C11) and the local wirings 145 to 148 of the filler cell C12 are arranged at the same pitch P1 in the X direction. That is, the local wirings of the inverter cells C10 and C11 and the filler cell C12 are arranged regularly. This makes it possible to suppress manufacturing variations in the semiconductor integrated circuit device and improve yields.

[0230] Furthermore, the bottom ends of the active regions 2P10 (2N10) of the inverter cells C10, 2P11 (2N11) of the inverter cells C11, and 2P12 (2N12) of the filler cells C12 in the Y direction are all located at the same position in the Y direction. That is, the bottom ends of the active regions 2P10 (2N10) of the inverter cells C10, 2P11 (2N11) of the inverter cells C11, and 2P12 (2N12) of the filler cells C12 are all aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C10 and C11 and the nanosheets 121 to 123 (124 to 126) of the filler cell C12 have their lower surfaces in the Y direction exposed from the gate wiring 31 and dummy gate wiring 131 to 133, respectively. That is, in the inverter cells C10 and C11 and the filler cell C12, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structure provided between the opposing nanosheets exposed from the gate wiring, i.e., its size and installation area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0231] The Y-direction width of the active region 2P10 (2N10) of the inverter cell C10 and the Y-direction width of the active region 2P12 (2N12) of the filler cell C12 are w1. The Y-direction width of the active region 2P11 (2N11) of the inverter cell C11 is w2, which is smaller than w1. The Y-direction bottom edge of the active region 2P10 (2N10) of the inverter cell C10, the Y-direction bottom edge of the active region 2P11 (2N11) of the inverter cell C11, and the Y-direction bottom edge of the active region 2P12 (2N12) of the filler cell C12 are aligned in the Y-direction. By placing the filler cell C12 between the inverter cells C10 and C11, each having an active area with a different width in the Y direction, the active area of ​​the filler cell C12 can be positioned along the entire right side of the active area of ​​the inverter cell C10 and the entire left side of the active area of ​​the inverter cell C11. Therefore, the distances from the active area 2P10 (2N10) of the inverter cell C10 and the active area 2P11 (2N11) of the inverter cell C11 to the active area 2P12 (2N12) of the filler cell C12 are set to predetermined values. This improves the accuracy of estimating the transistor performance of the logic cell.

[0232] In this embodiment, the size of the filler cell C12 in the X direction is set to four grids, but this is not limitative.

[0233] In addition, in this embodiment, the filler cell C12 includes the local interconnections 141 to 148, but it is not necessary to include some or all of these.

[0234] In this embodiment, the inverter cells C10, C11, and filler cell C12 have the same Y-direction width in the active regions at the top and bottom of the cells, but these widths may be different. In this case, it is sufficient that the Y-direction width of the active region 2P12 of filler cell C12 is the same as the Y-direction width of the active region 2P10 of inverter cell C10 and is larger than the Y-direction width of the active region 2P11 of inverter cell C11. Similarly, it is sufficient that the Y-direction width of the active region 2N12 of filler cell C12 is the same as the Y-direction width of the active region 2N10 of inverter cell C10 and is larger than the Y-direction width of the active region 2N11 of inverter cell C11.

[0235] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of filler cell C12 in the Y direction may be adjusted to the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0236] In addition, in this embodiment, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same wiring width, but the power supply wirings 11 and 12 may have different wiring widths.

[0237] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P12 and 2N12 of the filler cell C12 may be connected to the power supply wirings 11 and 12 through vias.

[0238] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0239] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0240] Furthermore, in each of the above-described embodiments and variants, a P-type transistor is formed at the bottom of the cell and an N-type transistor is formed at the top of the cell, but this is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor may be formed at the bottom of the cell.

[0241] Furthermore, in each of the above-described embodiments and variants, the standard cells having logic functions are described as inverter cells, but the standard cells having logic functions may also be other cells (NAND, NOR, flip-flops, etc.).

[0242] In the present disclosure, with respect to filler cells using CFETs, a layout of filler cells using fork-sheet transistors as transistors facilitates the manufacture of semiconductor integrated circuit devices and improves the accuracy of estimating the transistor performance of standard cells having logic functions.

[0243] 11, 12, 51 Power supply wiring 21, 22, 121 to 126 Nanosheet 31 Gate wiring 32, 33, 131 to 135 Dummy gate wiring 41 to 44, 141 to 148 Local wiring 61 to 65, 161 to 168 Via 2P1 to 2P12, 2N1 to 2N12 Active area P1, N1 Transistor DP1 to DP3, DN1 to DN3 Dummy transistor C1, C2, C4, C5, C7, C8, C10, C11 Inverter cell C3, C6, C9, C12 Filler cell

Claims

1. A semiconductor integrated circuit device comprising a first standard cell having a logic function and a second standard cell arranged adjacent to the first standard cell and not having a logic function, wherein the first standard cell comprises: a first active region constituting a channel, source, and drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, the second active region constituting a channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; and a first power supply wiring extending in the first direction, for supplying a first power supply voltage. and a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage, wherein the first power supply wiring is connected to a source of the first transistor in the first active region, and the second power supply wiring is connected to a source of the second transistor in the second active region, and the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, and including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, and including a fourth nanosheet extending in the first direction as the channel; and dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction,A semiconductor integrated circuit device, wherein the first and second nanosheets have a first side surface, which is one side in the second direction, exposed from the first gate wiring, the third and fourth nanosheets have a first side surface exposed from the dummy gate wiring, and in a planar view, the first side end of the first nanosheet and the first side end of the third nanosheet are arranged at the same position in the second direction.

2. A semiconductor integrated circuit device according to claim 1, wherein, in a plan view, the first side end of the second nanosheet and the first side end of the fourth nanosheet are arranged at the same position in the second direction.

3. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed on the back surface side of the first transistor, and the second power supply wiring is formed above the second transistor in the depth direction.

4. A semiconductor integrated circuit device according to claim 3, wherein the first standard cell is formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, and further comprises a first via connecting the source of the first transistor in the first active region with the first power supply wiring, and the first and second power supply wirings are arranged in the center of the first standard cell in the second direction.

5. A semiconductor integrated circuit device according to claim 3, wherein the first standard cell is formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, and further comprises a second via connecting the source of the first transistor in the first active region with the first power supply wiring, and the first and second power supply wirings are arranged at the first end of the first standard cell.

6. A semiconductor integrated circuit device according to claim 3, wherein the first and second power supply wirings are arranged at the end of the first standard cell on the second side, which is the other side in the second direction.

7. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first standard cell on the first side; the second power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first standard cell on the second side, which is the other side in the second direction; the first standard cell is formed in a region in the first active region where the region that becomes the source of the first transistor and the first power supply wiring overlap, and further comprising a third via that connects the source of the first transistor in the first active region and the first power supply wiring.

8. A semiconductor integrated circuit device according to claim 1, further comprising a third standard cell having a logic function, wherein the third standard cell comprises: a fifth active region formed in the same layer as the first active region in the depth direction, constituting the channel, source, and drain of the third transistor of the first conductivity type, the fifth active region including a fifth nanosheet extending in the first direction as the channel; a sixth active region formed in the same layer as the second active region in the depth direction, constituting the channel, source, and drain of the fourth transistor of the second conductivity type, the sixth nanosheet extending in the first direction as the channel; a second gate wiring extending in the second direction and surrounding the peripheries of the fifth and sixth nanosheets in the second direction and the depth direction; a third power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring; and a fourth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring. a semiconductor integrated circuit device, wherein the third power supply wiring is connected to the source of the third transistor in the fifth active region; the fourth power supply wiring is connected to the source of the fourth transistor in the sixth active region; the fifth and sixth nanosheets have their first side surfaces exposed from the second gate wiring; and in a planar view, the width of the fifth active region in the second direction is smaller than the width of the first active region in the second direction.

9. A semiconductor integrated circuit device according to claim 8, wherein, in a plan view, the first side end of the first active region, the first side end of the third active region, and the first side end of the fifth active region are arranged at the same position in the second direction.

10. A semiconductor integrated circuit device according to claim 1, wherein the second standard cell further comprises: a fifth power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring; and a sixth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring, wherein the fifth power supply wiring is connected to the source and drain of the first dummy transistor, and the sixth power supply wiring is connected to the source and drain of the second dummy transistor.

11. A semiconductor integrated circuit device comprising a first standard cell having a logic function and a second standard cell arranged adjacent to the first standard cell and not having a logic function, wherein the first standard cell comprises: a first active region constituting a channel, source, and drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in a first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, the second active region constituting a channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; and a first power supply wiring extending in the first direction, for supplying a first power supply voltage. and a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage, wherein the first power supply wiring is connected to a source of the first transistor in the first active region, and the second power supply wiring is connected to a source of the second transistor in the second active region, and the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, and including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, and including a fourth nanosheet extending in the first direction as the channel; and dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction,a semiconductor integrated circuit device, wherein the first and second nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first gate wiring; the third and fourth nanosheets have first-side surfaces, which are exposed from the dummy gate wiring; and the first-side end and the second-side end of the first active region are arranged between the first-side end and the second-side end of the third active region in the second direction.

12. A semiconductor integrated circuit device according to claim 11, wherein the first end and the second end of the second active region are arranged between the first end and the second end of the fourth active region in the second direction.

13. A semiconductor integrated circuit device according to claim 11, wherein the first power supply wiring is formed on the back surface side of the first transistor, and the second power supply wiring is formed above the second transistor in the depth direction.

14. A semiconductor integrated circuit device according to claim 13, wherein the first standard cell is formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, and further comprises a first via connecting the source of the first transistor in the first active region with the first power supply wiring, and the first and second power supply wirings are arranged in the center of the first standard cell in the second direction.

15. A semiconductor integrated circuit device according to claim 13, wherein the first standard cell is formed in a region in the first active region where a region serving as the source of the first transistor overlaps with the first power supply wiring, and further comprises a second via connecting the source of the first transistor in the first active region with the first power supply wiring, and the first and second power supply wirings are arranged at the first end of the first standard cell.

16. A semiconductor integrated circuit device according to claim 13, wherein the first and second power supply wirings are arranged at the second end of the first standard cell.

17. A semiconductor integrated circuit device according to claim 11, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first side of the first standard cell; the second power supply wiring is formed on the back side of the first transistor and is arranged at the end of the second side of the first standard cell; the first standard cell is formed in a region in the first active region where the region that serves as the source of the first transistor and the first power supply wiring overlap, and further comprising a third via that connects the source of the first transistor in the first active region and the first power supply wiring.

18. A semiconductor integrated circuit device according to claim 11, further comprising a third standard cell having a logic function, wherein the third standard cell comprises: a fifth active region formed in the same layer as the first active region in the depth direction, constituting the channel, source, and drain of the third transistor of the first conductivity type, the fifth active region including a fifth nanosheet extending in the first direction as the channel; a sixth active region formed in the same layer as the second active region in the depth direction, constituting the channel, source, and drain of the fourth transistor of the second conductivity type, the sixth nanosheet extending in the first direction as the channel; a second gate wiring extending in the second direction and surrounding the outer peripheries of the fifth and sixth nanosheets in the second direction and the depth direction; a third power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring; and a fourth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring. a semiconductor integrated circuit device, wherein the third power supply wiring is connected to the source of the third transistor in the fifth active region; the fourth power supply wiring is connected to the source of the fourth transistor in the sixth active region; the fifth and sixth nanosheets have their first side surfaces exposed from the second gate wiring; and in a planar view, the width of the fifth active region in the second direction is smaller than the width of the first active region in the second direction.

19. A semiconductor integrated circuit device according to claim 18, wherein, in a plan view, the first side end of the first active region, the first side end of the third active region, and the first side end of the fifth active region are arranged at the same position in the second direction.

20. A semiconductor integrated circuit device according to claim 1, wherein the second standard cell further comprises: a fifth power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring; and a sixth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring, wherein the fifth power supply wiring is connected to the source and drain of the first dummy transistor, and the sixth power supply wiring is connected to the source and drain of the second dummy transistor.

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