Semiconductor integrated circuit device

Abstract

In the present invention, an inverter cell (C1) includes active regions (2P1, 2N1) and nanosheets (21, 22). A terminus cell (C3) is disposed on one or both ends of a cell column (CR) and does not have a logical function, and the terminus cell includes active regions (2P3, 2N3) and nanosheets (121, 124). The nanosheets (21, 22) have a first-side surface exposed from a gate wiring (31). The nanosheets (121, 124) have a first-side surface exposed from a dummy gate wiring (131). In a plan view, a first-side end part of the nanosheet (21) and a first-side end part of the nanosheet (121) are disposed at the same position in a second direction.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, also simply referred to as cells, as appropriate) that include CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Standard cells include cells with logic functions such as NAND gates and NOR gates (hereinafter referred to as logic cells, as appropriate), as well as cells without logic functions. An example of a cell without logic functions is a "termination cell." A "termination cell" is a cell that does not contribute to the logic function of a circuit block and is used to terminate the circuit block. By placing a termination cell, it is possible to suppress variations in the finished shape of the layout pattern of cells located inside the termination cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0005] Patent Document 1 discloses a termination cell using a CFET (Complementary FET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate.

[0006] Patent Document 2 discloses a standard cell using a fork sheet transistor, which is a nanosheet FET and has a fork-shaped gate electrode, for reducing the area of ​​a semiconductor integrated circuit device. Patent Document 2 also discloses the structure of a terminal cell among standard cells using the fork sheet transistor.

[0007] International Publication No. 2020 / 170715 U.S. Patent Application Publication No. 2022 / 0246644

[0008] However, regarding termination cells using CFETs, no specific consideration has yet been given to the layout structure of termination cells using fork-sheet transistors as transistors.

[0009] The present disclosure aims to provide a layout structure for a termination cell using a fork-sheet transistor as a transistor for a termination cell using a CFET.

[0010] In a first aspect of the present disclosure, there is provided a semiconductor device comprising a plurality of cell rows each including a plurality of standard cells arranged side by side in a first direction, wherein a first cell row being one of the plurality of cell rows comprises a first standard cell having a logic function and a second standard cell arranged on at least one end of the first cell row and not having a logic function, wherein the first standard cell comprises: a first active region including a first nanosheet extending in the first direction as the channel; a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view; a second gate wiring extending in the first direction and surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; the second power supply wiring is connected to a source of the first transistor in the first active region, and the second power supply wiring is connected to a source of the second transistor in the second active region; the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction and constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction and constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction;A first side surface, which is one side in the second direction, is exposed from the first gate wiring, and the third and fourth nanosheets have first side surfaces exposed from the dummy gate wiring, and in a plan view, the first side end of the first nanosheet and the first side end of the third nanosheet are arranged at the same position in the second direction.

[0011] According to the present disclosure, the first-side end of the first nanosheet in the first active region of the first standard cell and the first-side end of the third nanosheet in the third active region of the second standard cell are aligned in the second direction. Furthermore, the first-side surface of the first nanosheet is exposed from the first gate wiring, and the first-side surface of the third nanosheet is exposed from the dummy gate wiring. That is, in the first and second standard cells, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the second direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, by aligning the positions of the nanosheet surfaces exposed from the gate wiring in the second direction, the shape of the structure, i.e., the size and layout area in the second direction, can be made constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0012] In a second aspect of the present disclosure, there is provided a semiconductor device comprising a plurality of cell rows each including a plurality of standard cells arranged side by side in a first direction, wherein a first cell row being one of the plurality of cell rows comprises a first standard cell having a logic function and a second standard cell arranged on at least one end of the first cell row and not having a logic function, wherein the first standard cell comprises: a first active region including a first nanosheet extending in the first direction as the channel; a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view; a second gate wiring extending in the first direction and surrounding the periphery of the first and second nanosheets in the second direction and the depth direction; the second power supply wiring is connected to a source of the first transistor in the first active region, and the second power supply wiring is connected to a source of the second transistor in the second active region; the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction and constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction and constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction;A first side surface, which is one side in the second direction, is exposed from the first gate wiring, and the third and fourth nanosheets have first side surfaces exposed from the dummy gate wiring, and the first side end and the second side end of the first active region are arranged between the first side end and the second side end of the third active region, which is the other side in the second direction, in the second direction.

[0013] According to the present disclosure, in the second direction, the first and second ends of the first active region of the first standard cell having a logic function are arranged between the first and second ends of the third active region of the second standard cell not having a logic function. By arranging the second standard cell adjacent to the first standard cell, the third active region of the second standard cell can be arranged along the entire side surface of the first active region of the first standard cell in the first direction. Therefore, the distance from the first active region of the first standard cell to the third active region of the second standard cell is set to a predetermined value. This improves the accuracy of estimating the transistor performance of standard cells having a logic function.

[0014] In a third aspect of the present disclosure, there is provided a semiconductor device including a plurality of standard cells arranged side by side in a first direction, and a plurality of cell rows arranged side by side in a second direction perpendicular to the first direction, the plurality of cell rows including a first cell row including first and third standard cells having a logic function, and a second cell row arranged at either end of the plurality of cell rows in the second direction and including a second standard cell having no logic function, the first standard cell constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being formed by a first active region including a first nanosheet extending in the first direction, a second active region formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second active region including a second nanosheet extending in the first direction, the second active region extending in the second direction and surrounding the outer peripheries of the first and second nanosheets in the second direction and the depth direction. a first power supply wiring extending in the first direction and supplying a first power supply voltage; and a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage, wherein the first power supply wiring is connected to a source of the first transistor in the first active region, and the second power supply wiring is connected to a source of the second transistor in the second active region. The second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction and constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction and constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and dummy gate wiring extending in the second direction and surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction.The third standard cell includes: a fifth active region formed in the same layer as the first active region in the depth direction, constituting a channel, a source, and a drain of a third transistor of the first conductivity type, the fifth active region including a fifth nanosheet extending in the first direction as the channel; a sixth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a fourth transistor of the second conductivity type, the sixth nanosheet extending in the first direction as the channel; a second gate wiring extending in the second direction and surrounding the outer peripheries of the fifth and sixth nanosheets in the second direction and the depth direction; a third power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring; and a fourth power supply wiring formed in the same layer, extending in the first direction, and connected to the second power supply wiring, wherein the third power supply wiring is connected to the source of the third transistor in the fifth active region, and the fourth power supply wiring is connected to the source of the fourth transistor in the sixth active region, the first and second nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first gate wiring, the third and fourth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the dummy gate wiring, and the fifth and sixth nanosheets have first-side surfaces exposed from the second gate wiring, and in a plan view, the width of the first active region in the second direction is the same as the width of the third active region in the second direction and is larger than the width of the fifth active region in the second direction.

[0015] According to the present disclosure, in the case of a termination cell using a CFET, a layout of the termination cell using a fork-sheet transistor as the transistor makes it easier to manufacture a semiconductor integrated circuit device, and improves the accuracy of estimating the transistor performance of a standard cell having a logic function.

[0016] 11. A plan view showing an example of the layout of circuit blocks included in a semiconductor integrated circuit device according to the first embodiment. A plan view of portion A1 in FIG. 1. A cross-sectional view of FIG. 2. A circuit diagram of an inverter cell. A plan view of portion A2 in FIG. 1. Another configuration example of the semiconductor integrated circuit device according to the first embodiment. A plan view showing another example of portion A1 in FIG. 1. A plan view of portion A3 in FIG. 1. A plan view showing another example of portion A3 in FIG. 1. A plan view showing another example of portion A3 in FIG. 1. A plan view showing an example of the layout of circuit blocks included in a semiconductor integrated circuit device according to a second embodiment. A plan view of portion A4 in FIG. 11. A plan view of portion A5 in FIG. 11. A plan view of portion A6 in FIG. 11. A plan view showing an example of the layout of circuit blocks included in a semiconductor integrated circuit device according to a third embodiment. A plan view of portion A7 in FIG. 15. A plan view of portion A8 in FIG. 16. A plan view of portion A9 in FIG. 17. A plan view showing an example of the layout of circuit blocks included in a semiconductor integrated circuit device according to a fourth embodiment. A plan view of portion A10 in FIG. 19. 19A and 19B are plan views of a portion A11 and a portion A12 in FIG.

[0017] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells. At least some of the plurality of standard cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0018] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0019] 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a first embodiment. Note that in FIG. 1, only power supply wiring formed in a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed is shown, and other components are omitted.

[0020] 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed, and in an M0 wiring layer, which is a metal wiring layer above the transistors.

[0021] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0022] 1 and other plan views, the solid lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0023] 1, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The cells include standard cells with logic functions such as NAND gates and NOR gates, and termination cells with no logic functions.

[0024] Here, a "terminal cell" refers to a cell that does not contribute to the logical function of the circuit block and is arranged at the end of the circuit block. Here, the "end of the circuit block" refers to both ends of the cell row that constitutes the circuit block (here, both ends in the X direction), as well as the top and bottom rows of the circuit block (here, both end cell rows in the Y direction). In other words, a "terminal cell" is arranged at the end of the cell row, which is the end of the circuit block, such as both ends in the X direction or both end cell rows in the Y direction. By arranging the terminal cell, it is possible to suppress variation in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variation in semiconductor integrated circuit devices and improving yield and reliability.

[0025] In the layout of FIG. 1 , a rectangular logic unit LC, which includes logic cells having logic functions and realizes the circuit functions, is arranged in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C1 and C2 are arranged in the logic unit LC. Termination cells C3 and C4 are arranged in the termination cell unit. Specifically, termination cells C3 are arranged on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C4 are arranged in the cell rows CR arranged in the top and bottom rows of the circuit block in the Y direction.

[0026] In each cell, power supply wiring is formed in the center in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, power supply wiring (power supply wiring 11 described later) that supplies power supply voltage VDD is formed in the BM0 wiring layer, and power supply wiring (power supply wiring 51 described later) that supplies power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 1, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column CR.

[0027] (Configuration of inverter cell C1) Fig. 2 is a plan view of portion A1 in Fig. 1, Fig. 3 is a cross-sectional view in Fig. 2, and Fig. 4 is a circuit diagram configured in the inverter cell. Specifically, Fig. 2(a) shows the lower part of the cell, Fig. 2(b) shows the upper part of the cell, Fig. 3(a) is a cross-section taken along line X1-X1' in Fig. 2, Fig. 3(b) is a cross-section taken along line Y1-Y1' in Fig. 2, and Fig. 3(c) is a cross-section taken along line Y2-Y2' in Fig. 2.

[0028] As shown in FIG. 4, the inverter cell C1 has transistors P1 and N1, and an inverter circuit with an input A and an output Y is configured.

[0029] As shown in FIGS. 1 and 2, the inverter cell C1 is arranged at the left end of the logic section LC in the drawing, and the termination cell C3 is arranged adjacent to it on the left side.

[0030] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 2 and the dashed lines running vertically in cross-sectional views such as FIG. 3 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0031] 2A, a BM0 wiring layer, which is a wiring layer, is formed on the back surface of a semiconductor chip on which transistors are formed. In the BM0 wiring layer, a power supply wiring 11 extending in the X direction is formed at the center of the cell in the Y direction of the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0032] An active region that forms the channel, source, and drain of the P-type transistor is formed in the P-type transistor region at the bottom of the cell. Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0033] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheet structures (not shown) in a plan view and extends in the X direction. In the active region 2P1, the portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P1 overlap in a plan view.

[0034] As shown in FIG. 2B, an active region that forms the channel, source, and drain of the N-type transistor is formed in the N-type transistor region in the upper part of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 is disposed above the active region 2P1 in the Z direction. The active region 2N1 overlaps with the active region 2P1 in a plan view.

[0035] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has a nanosheet 22 as a channel, which is made of three overlapping sheets (not shown) in a plan view and extends in the X direction.

[0036] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0037] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0038] Similar to the dummy gate wirings 131 to 133 described later, the gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower sides of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper sides of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0039] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0040] 2A, local interconnects (LI) 41 and 42 extending in the Y direction are formed below the cell. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the source of the transistor P1. The local interconnect 42 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1.

[0041] 2B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N1 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N1 that will become the drain of the transistor N1.

[0042] In the M0 wiring layer, which is a metal wiring layer above the active region 2N1, a power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0043] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N1 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N1 that will become the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N1 overlap in plan view.

[0044] The wiring 52 is disposed on the lower side in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N1 overlap in a plan view.

[0045] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 42, 44.

[0046] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0047] As shown in FIGS. 2A and 2B, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0048] In the inverter cell C1 shown in FIG. 2, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P1 and 2N1 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0049] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P1 (2N1) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P1 (2N1) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P1 (2N1) is positioned closer to the lower end of the cell frame in the Y direction, based on the center of the cell frame in the Y direction. That is, in a planar view, the center of the active region 2P1 (2N1) in the Y direction is lower than the center of the cell frame in the Y direction.

[0050] Furthermore, the power supply wiring 11, 51 is formed in the center of the cell in the Y direction in plan view. That is, the center of the active region 2P1 (2N1) in the Y direction is located below the center of the power supply wiring 11 (51) in the Y direction. By arranging the inverter cell C1 in the circuit block of FIG. 1, the power supply wiring that supplies the power supply voltages VDD and VSS is uniformly arranged in the Y direction, which makes it possible to suppress a drop in the power supply voltage and to suppress the occurrence of electromigration due to current concentration.

[0051] Furthermore, the via 61 connects the power supply wiring 11 and a portion of the active region 2P1 that serves as the source of the transistor P1. In plan view, the center of the via 61 in the Y direction is located at the same position as the center of the power supply wiring 11 in the Y direction. That is, when the center of the active region 2P1 in the Y direction is used as a reference, the via 61 is located closer to the upper end of the active region 2P1 in the Y direction (the side where the nanosheet 21 is not exposed from the gate wiring 31). In other words, the center of the via 61 in the Y direction is located above the center of the active region 2P1 in the Y direction.

[0052] Furthermore, the via 62 connects the power supply wiring 51 and a portion of the active region 2N1 that serves as the source of the transistor N1. In plan view, the center of the via 62 in the Y direction is located at the same position as the center of the power supply wiring 51 in the Y direction. That is, when the center of the active region 2N1 in the Y direction is used as a reference, the via 62 is located closer to the upper end of the active region 2N1 in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31). In other words, the center of the via 62 in the Y direction is located above the center of the active region 2N1 in the Y direction.

[0053] Furthermore, the via 63 connecting the wiring 52 and the gate wiring 31 is formed lower in the Y direction than the power wiring 51 in plan view (the side where the nanosheet 22 is exposed from the gate wiring 31 and where the active region 2N1 is positioned closer to the cell frame). The via 63 is formed in the area where the wiring 52 and the active region 2N1 overlap in plan view. That is, the via 63 is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as the reference point. This reduces the distance from the wiring 52 (input A) to the portion of the gate wiring 31 that overlaps the nanosheets 21 and 22 in plan view and covers the nanosheets 21 and 22, thereby reducing the resistance from the wiring 52 to the gate wiring 31 and increasing the speed of the semiconductor integrated circuit device.

[0054] Furthermore, the wiring 53 is disposed on the upper side of the drawing in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N1 is disposed close to the cell frame). The via 64 connecting the wiring 53 to the local wiring 44 and the via 65 connecting the local wirings 42 and 44 are formed on the upper side of the drawing in the Y direction. This reduces the distance from the wiring 53 to the portion of the active region 2P1 that serves as the drain of the transistor P1 and the portion of the active region 2N1 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P1 (2N1) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0055] (Configuration of inverter cell C2) Fig. 5 is a plan view of portion A2 in Fig. 1. Specifically, Fig. 5(a) shows the lower part of the cell, and Fig. 5(b) shows the upper part of the cell.

[0056] As shown in FIGS. 1 and 5, the inverter cell C2 is arranged at the left end of the logic section LC in the drawing, and the termination cell C3 is arranged adjacent to it on the left side.

[0057] The inverter cell C2 has a configuration similar to that of the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C2 is a standard cell having a logic function.

[0058] As shown in FIG. 5, the inverter cell C2 is different from the inverter cell C1 shown in FIG. 2 in that active regions 2P2 and 2N2 having different widths in the Y direction are arranged in place of the active regions 2P1 and 2N1.

[0059] Specifically, the active regions 2P2 and 2N2 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0060] 2 and 5, the bottom edge of the active region 2P2 (2N2) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P1 (2N1) in the Y direction. That is, the bottom edge of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the bottom edge of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction are aligned in the Y direction.

[0061] (Configuration of Terminating Cell C3) As shown in FIG. 1, the terminating cells C3 are arranged on both the left and right ends of the cell row CR in the X direction.

[0062] 2A and 5A, an active region 2P3 is formed in the P-type transistor region. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0063] P-type dummy transistors DP1 to DP3 are formed in the active region 2P3. The dummy transistors DP1 to DP3 each have a channel made of three overlapping sheets in a plan view, and have nanosheets 121 to 123 extending in the X direction.

[0064] 2B and 5B, an active region 2N3 is formed in the N-type transistor region in the upper part of the cell. The active region 2N3 overlaps with the active region 2P3 in plan view.

[0065] N-type dummy transistors DN1 to DN3 are formed in the active region 2N3. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0066] Dummy gate wirings 131 to 133 are formed extending in the Y and Z directions. Nanosheets 121 and 124 overlap with dummy gate wiring 131 in a planar view. Nanosheets 122 and 125 overlap with dummy gate wiring 132 in a planar view. Nanosheets 123 and 126 overlap with dummy gate wiring 133 in a planar view. Dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 132 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 133 corresponds to the gates of dummy transistors DP3 and DN3.

[0067] As shown in FIG. 3C, the dummy gate wiring 131 covers the outer peripheries of the nanosheets 121 and 124 in the Y and Z directions so that a portion of the outer peripheries of the nanosheets 121 and 124 is exposed. Specifically, the right-hand side surfaces of the nanosheets 121 and 124 in the drawing are not covered by the dummy gate wiring 131, and the left-hand side surfaces of the nanosheets 121 and 124 in the drawing are covered by the dummy gate wiring 131. Therefore, in FIGS. 2 and 5, the lower sides of the nanosheets 121 and 124 in the Y direction are exposed from the dummy gate wiring 131, and the upper sides of the nanosheets 121 and 124 in the Y direction are covered by the dummy gate wiring 131. Similarly, the dummy gate wiring 132 covers the outer peripheries of the nanosheets 122 and 125 in the Y and Z directions so that a portion of the outer peripheries of the nanosheets 122 and 125 is exposed. Dummy gate wiring 133 covers the outer peripheries of nanosheets 123, 126 in the Y and Z directions so that part of the outer peripheries of nanosheets 123, 126 are exposed. In Figures 2 and 5, the lower sides of nanosheets 122, 125 in the Y direction are exposed from dummy gate wiring 132, and the upper sides of nanosheets 122, 125 in the Y direction are covered by dummy gate wiring 132. The lower sides of nanosheets 123, 126 in the Y direction are exposed from dummy gate wiring 133, and the upper sides of nanosheets 123, 126 in the Y direction are covered by dummy gate wiring 133.

[0068] Dummy gate wiring 134, 135 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 134 is shared with another cell arranged on the left side of the drawing. The dummy gate wiring 135 is shared with another cell arranged on the right side of the drawing (inverter cell C1 in FIG. 2 and inverter cell C2 in FIG. 5).

[0069] As shown in FIGS. 2A and 5A, local interconnections 141 to 144 extending in the Y direction are formed below the cell. Local interconnection 141 is connected to a portion in active region 2P3 that will become the source of dummy transistor DP1. Local interconnection 142 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP1 and a portion in active region 2P3 that will become the source of dummy transistor DP2. Local interconnection 143 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP2 and a portion in active region 2P3 that will become the source of dummy transistor DP3. Local interconnection 144 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP3.

[0070] As shown in FIGS. 2B and 5B, local interconnections 145 to 148 extending in the Y direction are formed above the cell. Local interconnection 145 is connected to a portion of active region 2N3 that will become the source of dummy transistor DN1. Local interconnection 146 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN1 and a portion of active region 2N3 that will become the source of dummy transistor DN2. Local interconnection 147 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN2 and a portion of active region 2N3 that will become the source of dummy transistor DN3. Local interconnection 148 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN3.

[0071] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The power supply wiring 51 overlaps with the active region 2P3 in plan view.

[0072] 2 and 5, unlike the inverter cells C1 and C2, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to other wirings. In other words, the termination cell C3 is a standard cell that does not have a logic function.

[0073] 2 and 5, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0074] The local wirings 41, 42, and 141 to 144 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction. The local wirings 43, 44, and 145 to 148 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction.

[0075] The local wirings 41 to 44 and 141 to 148 are arranged so that their upper ends in the Y direction are at the same position on the drawing. The local wirings 41 to 44 and 141 to 148 are arranged so that their lower ends in the Y direction are at the same position on the drawing.

[0076] 2 and 5, inverter cells C1 and C2 having a logic function and a terminal cell C3 having no logic function are arranged in a cell row CR. The terminal cell C3 is arranged at the left end of the cell row CR in the X direction of the drawing. Dummy gate wirings 131-135 of the terminal cell C3 are arranged in the same layer in the Z direction as the gate wiring 31 of the inverter cells C1 and C2. Local wirings 141-144 of the terminal cell C3 are arranged in the same layer in the Z direction as the local wirings 41 and 42 of the inverter cells C1 and C2. Local wirings 145-148 of the terminal cell C3 are arranged in the same layer in the Z direction as the local wirings 43 and 44 of the inverter cells C1 and C2. In other words, by providing dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings including the dummy gate wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0077] Furthermore, the dummy gate wirings 131 to 135 of the terminal cell C3 are formed with the same length Lg in the Y direction as the gate wiring 31 and dummy gate wirings 32 and 33 of the inverter cells C1 and C2, thereby suppressing variations in the finished shape of the layout pattern and suppressing manufacturing variations in the semiconductor integrated circuit device.

[0078] Furthermore, the local wirings 141 to 148 of the terminal cell C3 are arranged so that their upper ends in the Y direction are at the same position as the upper ends in the Y direction of the local wirings 41 to 44 of the inverter cells C1 and C2. The local wirings 141 to 148 of the terminal cell C3 are arranged so that their lower ends in the Y direction are at the same position as the lower ends in the Y direction of the local wirings 41 to 44 of the inverter cells C1 and C2. In other words, the upper and lower ends in the Y direction of the local wirings arranged in the terminal cells are aligned with the upper and lower ends in the Y direction of the local wirings arranged in the cells that constitute the logic unit LC, respectively. This makes it possible to constant the distance from the logic unit LC to the nearest local wiring, thereby improving the performance predictability of the cells arranged in the logic unit LC.

[0079] In addition, the active region 2P3 (2N3) of the termination cell C3 is arranged in the same layer as the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2 in the Z direction, which makes it possible to uniformize the layout pattern of the active regions where the transistors are configured, and suppress manufacturing variations.

[0080] Furthermore, the active regions 2P3 and 2N3 of the termination cell C3 are located close to the dummy gate wiring 32 (135) located at the boundary between the termination cell C3 and the inverter cells C1 and C2. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0081] Furthermore, the bottom ends of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction, the bottom ends of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction, and the bottom ends of the active region 2P3 (2N3) of the terminal cell C3 in the Y direction are arranged at the same position in the Y direction. That is, the bottom ends of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction, the bottom ends of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction, and the bottom ends of the active region 2P3 (2N3) of the terminal cell C3 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C1 and C2 and the nanosheets 121 to 123 (124 to 126) of the terminal cell C3 have their lower surfaces in the Y direction exposed from the gate wiring 31 and the dummy gate wiring 131 to 133, respectively. That is, in the inverter cells C1, C2, and the terminal cell C3, the positions of the nanosheet surfaces exposed from the gate wiring are aligned in the Y direction. Here, in a fork-sheet FET, the opposing nanosheets exposed from the gate wiring are formed by providing an insulating structure between them. Therefore, in a cell row CR in which standard cells are arranged in the X direction, as in the configurations of Figures 2 and 5, by aligning the positions of the nanosheet surfaces exposed from the gate wiring in the Y direction, the shape of the structure, i.e., its size and layout area in the Y direction, can be made constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0082] The Y-direction width of the active region 2P1 (2N1) in the inverter cell C1 and the Y-direction width of the active region 2P3 (2N3) in the termination cell C3 are w1. The Y-direction width of the active region 2P2 (2N2) in the inverter cell C2 is w2, which is smaller than w1. The Y-direction bottom ends of the active region 2P1 (2N1) in the inverter cell C1, the Y-direction bottom ends of the active region 2P2 (2N2) in the inverter cell C2, and the Y-direction bottom ends of the active region 2P3 (2N3) in the termination cell C3 are aligned in the Y-direction. By arranging the termination cell C3 adjacent to the inverter cells C1 and C2, which have active regions with different Y-direction widths, the active region of the termination cell C3 can be positioned along the entire left side surface of the active region of the inverter cell C1 and the entire left side surface of the active region of the inverter cell C2. Therefore, the distances from the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2 to the active region 2P3 (2N3) of the termination cell C3 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0083] Although five dummy gate wirings (dummy gate wirings 131 to 135) and eight local wirings (local wirings 141 to 148) are arranged in the termination cell C3, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C3 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C3 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C3 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C3.

[0084] In this embodiment, the active regions of the inverter cells C1, C2, and the termination cell C3 have the same Y-direction width at the top and bottom of the cells, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P3 of the termination cell C3 is the same as the Y-direction width of the active region 2P1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2P2 of the inverter cell C2. Similarly, it is sufficient that the Y-direction width of the active region 2N3 of the termination cell C3 is the same as the Y-direction width of the active region 2N1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2N2 of the inverter cell C2.

[0085] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of the termination cell C3 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0086] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0087] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0088] Fig. 6(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 6(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0089] 6B shows a cross section of this configuration example taken along line Y1-Y1' in FIG. 2. As shown in FIG. 6B, a power supply wiring 11 that supplies VDD is formed in a wiring layer provided on the surface of chip B. Although not shown, in inverter cell C1 (C2), power supply wiring 11 is connected to active region 2P1 (2P2) of chip A through via 61.

[0090] This configuration example also provides the same effects as those of FIG.

[0091] (Modification of Termination Cell C3) Figure 7 is a plan view showing another example of portion A1 in Figure 1. Specifically, Figure 7(a) shows the lower part of the cell, and Figure 7(b) shows the upper part of the cell. In Figure 7, compared to Figure 2, the source and drain of each dummy transistor configured in active regions 2P3 and 2N3 are connected to the power supply wiring through vias.

[0092] 7A, the portion of the active region 2P3 that will become the source of the dummy transistor DP1 is connected to the power supply wiring 11 via a via 161. The portions of the active region 2P3 that will become the drain of the dummy transistor DP1 and the source of the dummy transistor DP2 are connected to the power supply wiring 11 via a via 162. The portions of the active region 2P3 that will become the drain of the dummy transistor DP2 and the source of the dummy transistor DP3 are connected to the power supply wiring 11 via a via 163. The portion of the active region 2P3 that will become the drain of the dummy transistor DP3 is connected to the power supply wiring 11 via a via 164. The vias 161 to 164 are formed in a region where the power supply wiring 11 and the active region 2P3 overlap in a planar view.

[0093] 7B, the portion that will become the source of dummy transistor DN1 in active region 2N3 is connected to power supply wiring 51 via via 165 and local wiring 145. The portions that will become the drain of dummy transistor DN1 and the source of dummy transistor DN2 in active region 2N3 are connected to power supply wiring 51 via via 166 and local wiring 146. The portions that will become the drain of dummy transistor DN2 and the source of dummy transistor DN3 in active region 2N3 are connected to power supply wiring 51 via via 167 and local wiring 147. The portion that will become the drain of dummy transistor DN3 in active region 2N3 is connected to power supply wiring 51 via via 168 and local wiring 148.

[0094] 7, the sources and drains of dummy transistors DP1 to DP3 configured in active region 2P3 are fixed to power supply voltage VDD. The sources and drains of dummy transistors DN1 to DN3 configured in active region 2N3 are fixed to power supply voltage VSS. This reduces the floating nodes of the dummy transistors configured in the active region, thereby stabilizing the operation of the circuit block.

[0095] In addition, the same effects as those in FIGS. 2 and 5 can be obtained.

[0096] (Configuration of Termination Cell C4) Figure 8 is a plan view of portion A3 in Figure 1. Specifically, Figure 8(a) shows the lower part of the cell, and Figure 8(b) shows the upper part of the cell. In Figure 8, inverter cells C1 and C2 are arranged inverted in the Y direction.

[0097] 1, the terminal cell C4 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C1 and C2 arranged at the top end of the logic unit LC in the drawing.

[0098] 8A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0099] An active region 2P4 is formed in the P-type transistor region. The active region 2P4 overlaps with the power supply wiring 11 in plan view.

[0100] P-type dummy transistors DP4 to DP6 are formed in the active region 2P4. The dummy transistors DP4 to DP6 have nanosheets 221 to 223 extending in the X direction.

[0101] 8B, an active region 2N4 is formed in the N-type transistor region. The active region 2N4 overlaps with the active region 2P4 in plan view.

[0102] N-type dummy transistors DN4 to DN6 are formed in the active region 2N4. The dummy transistors DN4 to DN6 have nanosheets 224 to 226 extending in the X direction.

[0103] Dummy gate wirings 231 to 233 are formed extending in the Y and Z directions. Nanosheets 221 and 224 overlap with dummy gate wiring 231 in a planar view. Nanosheets 222 and 225 overlap with dummy gate wiring 232 in a planar view. Nanosheets 223 and 226 overlap with dummy gate wiring 233 in a planar view. Dummy gate wiring 231 corresponds to the gates of dummy transistors DP4 and DN4. Dummy gate wiring 232 corresponds to the gates of dummy transistors DP5 and DN5. Dummy gate wiring 233 corresponds to the gates of dummy transistors DP6 and DN6.

[0104] The dummy gate wiring 231 covers the outer peripheries of the nanosheets 221 and 224 in the Y and Z directions so that portions of the outer peripheries of the nanosheets 221 and 224 are exposed. The dummy gate wiring 232 covers the outer peripheries of the nanosheets 222 and 225 in the Y and Z directions so that portions of the outer peripheries of the nanosheets 222 and 225 are exposed. The dummy gate wiring 233 covers the outer peripheries of the nanosheets 223 and 226 in the Y and Z directions so that portions of the outer peripheries of the nanosheets 223 and 226 are exposed. Specifically, the lower sides of the nanosheets 221 and 224 in the Y direction are exposed from the dummy gate wiring 231, and the upper sides of the nanosheets 221 and 224 in the Y direction are covered by the dummy gate wiring 231. The lower sides of the nanosheets 222 and 225 in the Y direction are exposed from the dummy gate wiring 232, and the upper sides of the nanosheets 222 and 225 in the Y direction are covered by the dummy gate wiring 232. The nanosheets 223 and 226 are each exposed at their lower sides in the Y direction from the dummy gate wiring 233 and are each covered at their upper sides in the Y direction with the dummy gate wiring 233 .

[0105] Dummy gate wiring 234, 235 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 234 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 235 is shared with other cells arranged on the right side of the drawing.

[0106] As shown in FIG. 8A, local wirings 241 to 244 extending in the Y direction are formed below the cell. Local wiring 241 is connected to a portion in the active region 2P4 that will become the source of dummy transistor DP4. Local wiring 242 is connected to a portion in the active region 2P4 that will become the drain of dummy transistor DP4 and a portion in the active region 2P4 that will become the source of dummy transistor DP5. Local wiring 243 is connected to a portion in the active region 2P4 that will become the drain of dummy transistor DP5 and a portion in the active region 2P4 that will become the source of dummy transistor DP6. Local wiring 244 is connected to a portion in the active region 2P4 that will become the drain of dummy transistor DP6.

[0107] As shown in FIG. 8B, local interconnections 245 to 248 extending in the Y direction are formed above the cell. Local interconnection 245 is connected to a portion of active region 2N4 that will become the source of dummy transistor DN4. Local interconnection 246 is connected to a portion of active region 2N4 that will become the drain of dummy transistor DN4 and a portion of active region 2N4 that will become the source of dummy transistor DN5. Local interconnection 247 is connected to a portion of active region 2N4 that will become the drain of dummy transistor DN5 and a portion of active region 2N4 that will become the source of dummy transistor DN6. Local interconnection 248 is connected to a portion of active region 2N4 that will become the drain of dummy transistor DN6.

[0108] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0109] 8, unlike the inverter cells C1 and C2, the dummy gate wirings 231 to 235 and the local wirings 241 to 248 are not connected to any other wirings. In other words, the termination cell C4 is a standard cell that does not have a logic function.

[0110] 8, nanosheets 221 and 224 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C1, respectively, and are arranged in the same layer in the Z direction. Nanosheets 223 and 226 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C2, respectively, and are arranged in the same layer in the Z direction.

[0111] The gate wiring 31 and the dummy gate wirings 32, 33, 231 to 235 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. The dummy gate wirings 231 to 235 are also arranged at the same pitch Pg in the X direction and in the same layer in the Z direction.

[0112] The local wirings 241 to 244 are arranged at the same pitch P1 in the X direction. The local wirings 41, 42, and 241 to 244 are arranged in the same layer in the Z direction. The local wirings 245 to 248 are arranged at the same pitch P1 in the X direction. The local wirings 43, 44, and 245 to 248 are arranged in the same layer in the Z direction.

[0113] The local wirings 241 to 248 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 241 to 248 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0114] In FIG. 8 , a termination cell C4 having no logic function is arranged adjacent to inverter cells C1 and C2 having logic functions in the cell column CR at the top row in the Y direction of the circuit block. The active region 2P4 (2N4) of the termination cell C4 is arranged in the same layer as the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2. The local wirings 241-244 of the termination cell C4 are arranged in the same layer as the local wirings 41 and 42 of the inverter cells C1 and C2. The local wirings 245-248 of the termination cell C4 are arranged in the same layer as the local wirings 43 and 44 of the inverter cells C1 and C2. In other words, by providing dummy transistors, dummy gate wiring, and local wiring in the termination cell, transistors including dummy transistors, gate wiring including dummy gate wiring, and local wiring are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0115] Furthermore, nanosheets 221 and 224 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C1, respectively. Nanosheets 223 and 226 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C2, respectively. Dummy gate wirings 231 to 235 of terminal cell C4 are arranged in the same positions in the X direction as gate wiring 31 of inverter cell C1, dummy gate wiring 33 of inverter cell C1 (dummy gate wiring 32 of inverter cell C2), gate wiring 31 of inverter cell C2, dummy gate wiring 32 of inverter cell C1, and dummy gate wiring 33 of inverter cell C2, respectively. Local wirings 241, 242, 245, and 246 of terminal cell C4 are arranged in the same positions in the X direction as local wirings 41 to 44 of inverter cell C1, respectively. The local interconnects 243, 244, 247, and 248 of the terminal cell C4 are arranged in the same positions in the X direction as the local interconnects 41 to 44 of the inverter cell C2. That is, the terminal cell C4 has dummy transistors, dummy gate interconnects, and local interconnects formed across the entire cell width. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0116] Furthermore, the upper end of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the upper end of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction are arranged at the same position in the Y direction. The lower end of the active region 2P4 (2N4) of the terminal cell C4 in the Y direction are arranged at the same position in the Y direction. That is, the upper end of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the upper end of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction are aligned in the Y direction. The lower end of the active region 2P4 (2N4) of the terminal cell C4 in the Y direction are aligned in the Y direction. Furthermore, the upper surface of the nanosheets 21 (22) of the inverter cells C1 and C2 in the Y direction is exposed from the gate wiring 31. The nanosheets 221-223 (224-226) of the terminal cell C4 have their lower surfaces in the Y direction exposed from the dummy gate wirings 231-233, respectively. That is, the opposing surfaces of the nanosheets of the inverter cell C1 (C2) and the terminal cell C4 are exposed from the gate wiring. This allows the shape of the structure made of an insulator formed between the opposing nanosheets exposed from the gate wiring, i.e., the size and layout range of the structure in the Y direction, to be constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0117] Although five dummy gate wirings (dummy gate wirings 231 to 235) and eight local wirings (local wirings 241 to 248) are arranged in the termination cell C4, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C4 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C4 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C4 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C4.

[0118] In this embodiment, the active regions of the inverter cells C1, C2, and the termination cell C4 have the same Y-direction width at the top and bottom of the cells, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P4 of the termination cell C4 is the same as the Y-direction width of the active region 2P1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2P2 of the inverter cell C2. Similarly, it is sufficient that the Y-direction width of the active region 2N4 of the termination cell C4 is the same as the Y-direction width of the active region 2N1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2N2 of the inverter cell C2.

[0119] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C4 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0120] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0121] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P4 and 2N4 of the termination cell C4 may be connected to the power supply wirings 11 and 51 through vias.

[0122] (First Modification of Termination Cell C4) Figure 9 is a plan view showing another example of portion A3 in Figure 1. Specifically, Figure 9(a) shows the lower part of the cell, and Figure 9(b) shows the upper part of the cell. Note that in Figure 9, inverter cells C1 and C2 are arranged without being inverted in the Y direction.

[0123] In FIG. 9, compared with FIG. 8, in the inverter cells C1 and C2 and the terminal cell C4, the surface of each nanosheet opposite in the Y direction is exposed from the gate wiring.

[0124] Specifically, the nanosheets 21 and 22 in the inverter cell C1 (C2) are each exposed from the gate wiring 31 on the lower side in the Y direction in the drawing, and are covered by the gate wiring 31 on the upper side in the Y direction in the drawing.

[0125] The nanosheets 221 and 224 of the terminal cell C4 are each exposed at their upper Y-direction sides from the dummy gate wiring 231, and are covered at their lower Y-direction sides by the dummy gate wiring 231. The nanosheets 222 and 225 are each exposed at their upper Y-direction sides from the dummy gate wiring 232, and are covered at their lower Y-direction sides by the dummy gate wiring 232. The nanosheets 223 and 226 are each exposed at their upper Y-direction sides from the dummy gate wiring 233, and are covered at their lower Y-direction sides by the dummy gate wiring 233.

[0126] That is, in the inverter cell C1 (C2) and the terminal cell C4, the opposing surfaces of the nanosheets are not exposed from the gate wiring.

[0127] The configuration of FIG. 9 can also provide the same effect as that of FIG.

[0128] In the terminal cell C4, the upper sides of the nanosheets 221 and 224 in the Y direction may not be exposed from the dummy gate wiring 231. The upper sides of the nanosheets 222 and 225 in the Y direction may not be exposed from the dummy gate wiring 232. The upper sides of the nanosheets 223 and 226 in the Y direction may not be exposed from the dummy gate wiring 233.

[0129] (Second Modification of Termination Cell C4) FIG. 10 is a plan view showing another example of portion A3 in FIG. 1. Specifically, FIG. 10(a) shows the lower part of the cell, and FIG. 10(b) shows the upper part of the cell. In termination cell C4 in FIG. 10, the cell height (width of the cell in the Y direction) is half that of termination cell C4 in FIG. 8, and the power supply wiring and active region formed in the BM0 wiring layer and M0 wiring layer are omitted. Specifically, power supply wiring 11, 51 and active regions 2P4, 2N4 are omitted in FIG. 10. The lengths of local wiring 241-248 and dummy gate wiring 231-235 in the Y direction are halved.

[0130] The configuration of FIG. 10 also provides the same effect as that of the termination cell C4 of FIG.

[0131] Furthermore, with the configuration of FIG. 10, the width of the terminal cell C4 in the Y direction is halved, thereby enabling the area of ​​the semiconductor integrated circuit device to be reduced.

[0132] Second Embodiment (Circuit Block Configuration) Fig. 11 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. Specifically, Fig. 11 shows the lower part of the cell. Note that Fig. 11 only shows the power supply wiring arranged in the standard cell, and the rest is omitted.

[0133] 11 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0134] 11, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The cells include inverter cells C5 and C6 having logic functions and termination cells C7 and C8.

[0135] In each cell, power supply wiring is formed at the cell boundary in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, a power supply wiring (power supply wiring 11) that supplies a power supply voltage VDD is formed in the BM0 wiring layer, and a power supply wiring (power supply wiring 51) that supplies a power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 11, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column CR.

[0136] In the layout of Figure 11, similar to the layout of Figure 1, a rectangular logic unit LC that includes logic cells having logic functions and realizes the circuit function is placed in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C5 and C6 are placed in the logic unit LC. Termination cells C7 and C8 are placed in the termination cell unit. Specifically, termination cells C7 are placed on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C8 are placed in the cell rows CR placed in the top and bottom rows of the circuit block in the Y direction.

[0137] (Configuration of inverter cell C5) Figure 12 is a plan view of portion A4 in Figure 11. Specifically, Figure 12(a) shows the lower part of the cell, and Figure 12(b) shows the upper part of the cell. Note that inverter cells C5 and C6 each have the inverter circuit of Figure 4 configured therein.

[0138] As shown in FIGS. 11 and 12, the inverter cell C5 is arranged at the left end of the logic section LC in the drawing, and the termination cell C7 is arranged adjacent to it on the left side.

[0139] 12A, the BM0 wiring layer has a power supply wiring 11 formed at the bottom end of the cell in the Y direction in the drawing, the power supply wiring 11 extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD.

[0140] An active region 2P5 is formed in the P-type transistor region below the cell. The active region 2P5 overlaps with the power supply wiring 11 in plan view.

[0141] A transistor P1 is formed in the active region 2P5. The transistor P1 has a nanosheet 21 extending in the X direction. In the active region 2P5, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 through a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P5 overlap in a plan view.

[0142] 12B, an active region 2N5 is formed in the N-type transistor region in the upper part of the cell. The active region 2N5 is arranged higher in the Z direction than the active region 2P5. The active region 2N5 overlaps with the active region 2P5 in plan view.

[0143] The active region 2N5 has a transistor N1 formed therein. The transistor N1 has a nanosheet 22 extending in the X direction.

[0144] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0145] The gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower sides of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper sides of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0146] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0147] 12A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P5 that will become the source of the transistor P1. The local wiring 42 is connected to a portion of the active region 2P5 that will become the drain of the transistor P1.

[0148] 12B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N5 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N5 that will become the drain of the transistor N1.

[0149] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction and wirings 52 and 53. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0150] The power supply wiring 51 is formed at the bottom end of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N5 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N5 that will become the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N5 overlap in plan view.

[0151] The wiring 52 is disposed near the center of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N5 overlap in a plan view.

[0152] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 42, 44.

[0153] As described above, the inverter cell C5 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C5 is a standard cell having a logic function.

[0154] As shown in FIGS. 12A and 12B, the active regions 2P5 and 2N5 in the inverter cell C5 have a width of w1 in the Y direction in plan view.

[0155] In the inverter cell C5 shown in FIG. 12, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in adjacent cells in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P5 (2N5) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P5 and 2N5 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0156] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P5 (2N5) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P5 (2N5) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P5 (2N5) is positioned closer to the lower end of the cell frame in the Y direction when the center of the cell frame in the Y direction is used as the reference. That is, in a planar view, the center of the active region 2P5 (2N5) in the Y direction is lower than the center of the cell frame in the Y direction.

[0157] Furthermore, power supply wiring 11, 51 is formed at the lower end of the cell in the Y direction in plan view, and is shared with the standard cell arranged below inverter cell C5 in the Y direction in the drawing. Thus, by placing inverter cell C5 in the circuit block of Figure 11, the power supply wiring that supplies power supply voltages VDD and VSS can be strengthened, thereby suppressing a drop in power supply voltage and suppressing the occurrence of electromigration due to current concentration.

[0158] Furthermore, the via 61 connecting the power supply wiring 11 and the portion of the active region 2P5 that serves as the source of the transistor P1 is formed in the area where the power supply wiring 11 and the active region 2P5 overlap in a planar view. In planar view, the via 61 is disposed toward the upper side of the area where the power supply wiring 11 and the active region 2P5 overlap in a planar view. In other words, in planar view, the distance d4 in the Y direction from the center of the via 61 to the upper end of the power supply wiring 11 is smaller than the distance d5 in the Y direction from the center of the via 61 to the lower end of the active region 2P5. As a result, since the via 61 is disposed toward the center of the active region 2P5 in the Y direction, the difference in resistance between the via 61 to the upper end of the nanosheet 21 of the transistor P1 in the active region 2P5 and the via 61 to the lower end of the nanosheet 21 of the transistor P1 in the active region 2P5 is reduced. Therefore, the current flowing through the transistor P1 is equalized in the Y direction (up and down in the drawing), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0159] Furthermore, the via 62 connecting the power supply wiring 51 and the portion of the active region 2N5 that serves as the source of the transistor N1 is formed in the area where the power supply wiring 51 and the active region 2N5 overlap in a planar view. In planar view, the via 62 is disposed toward the upper side of the area where the power supply wiring 51 and the active region 2N5 overlap in a planar view. In other words, in planar view, the distance d4 in the Y direction from the center of the via 62 to the upper end of the power supply wiring 51 is smaller than the distance d5 in the Y direction from the center of the via 62 to the lower end of the active region 2N5. As a result, since the via 62 is disposed toward the center of the active region 2N5 in the Y direction, the difference in resistance between the via 62 to the upper end of the nanosheet 22 of the transistor N1 in the active region 2N5 and the via 62 to the lower end of the nanosheet 22 of the transistor N1 in the active region 2N5 is reduced. Therefore, the current flowing through the transistor N1 is equalized in the Y direction (up and down in the drawing), thereby enabling the semiconductor integrated circuit device to operate at a higher speed.

[0160] Furthermore, via 63 connecting wiring 52 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N5 and gate wiring 31. This makes it possible to reduce the distance from wiring 52 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance from wiring 52 and enabling the speed of the semiconductor integrated circuit device to be increased.

[0161] Furthermore, the wiring 53 is disposed above the wiring 52 in the Y direction (the side where the nanosheet 22 is not exposed from the gate wiring 31, and opposite the side where the active region 2N5 is disposed closer to the cell frame). The via 64 connecting the wiring 53 and the local wiring 44 and the via 65 connecting the local wirings 42 and 44 are formed above the wiring 52 in the Y direction in plan view. This reduces the distance from the wiring 53 to the portion of the active region 2P5 that serves as the drain of the transistor P1 and the portion of the active region 2N5 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P5 (2N5) that serves as the drain of the transistor P1 (N1), and increasing the speed of the semiconductor integrated circuit device.

[0162] (Configuration of inverter cell C6) Figure 13 is a plan view of portion A5 in Figure 11. Specifically, Figure 13(a) shows the lower part of the cell, and Figure 13(b) shows the upper part of the cell.

[0163] As shown in FIGS. 11 and 13, the inverter cell C6 is arranged at the left end of the logic section LC in the drawing, and the termination cell C7 is arranged adjacent to it on the left side.

[0164] The inverter cell C6 has a configuration similar to that of the inverter cell C5. Specifically, the inverter cell C6 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C6 is a standard cell having a logic function.

[0165] As shown in FIG. 13, the inverter cell C6 is different from the inverter cell C5 shown in FIG. 11 in that active regions 2P6 and 2N6 having different widths in the Y direction are arranged in place of the active regions 2P5 and 2N5.

[0166] Specifically, the active regions 2P6 and 2N6 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C5 is greater than the drive capability of the inverter cell C6.

[0167] 12 and 13, the bottom edge of the active region 2P5 (2N5) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P6 (2N6) in the Y direction. That is, the bottom edge of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction and the bottom edge of the active region 2P6 (2N6) of the inverter cell C6 in the Y direction are aligned.

[0168] 12 and 13 differs from the termination cell C3 of Fig. 2 and 5 in the arrangement of the power supply wirings 11 and 51. Active regions 2P7 and 2N7 are formed in place of the active regions 2P3 and 2N3.

[0169] As shown in FIG. 11, the terminal cells C7 are arranged on both the left and right ends of the cell row CR in the X direction.

[0170] 12A and 13A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0171] An active region 2P7 is formed in the P-type transistor region. Dummy transistors DP1 to DP3 are formed in the active region 2P7. The active region 2P7 overlaps with the power supply wiring 11 in plan view.

[0172] As shown in Figures 12(b) and 13(b), an active region 2N7 is formed in the N-type transistor region. The active region 2N7 is arranged higher in the Z direction than the active region 2P7. The active region 2N7 overlaps with the active region 2P7 in a plan view. Dummy transistors DN1 to DN3 are formed in the active region 2N7.

[0173] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The power supply wiring 51 overlaps with the active region 2N7 in plan view.

[0174] 12 and 13, unlike the inverter cells C5 and C6, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the termination cell C7 is a standard cell that does not have a logic function.

[0175] 12 and 13, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0176] The local wirings 41, 42, and 141 to 144 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction. The local wirings 43, 44, and 145 to 148 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction.

[0177] The local wirings 41 to 44 and 141 to 148 are arranged so that their upper ends in the Y direction are at the same position on the drawing. The local wirings 41 to 44 and 141 to 148 are arranged so that their lower ends in the Y direction are at the same position on the drawing.

[0178] 12 and 13 , inverter cells C5 and C6 having logic functions and a terminal cell C7 having no logic function are arranged in a cell column CR. The terminal cell C7 is arranged at the left end of the cell column CR in the X direction of the drawing. Dummy gate wirings 131-135 of the terminal cell C7 are arranged in the same layer in the Z direction as the gate wiring 31 of the inverter cells C5 and C6. Local wirings 141-144 of the terminal cell C7 are arranged in the same layer in the Z direction as the local wirings 41 and 42 of the inverter cells C5 and C6. Local wirings 145-148 of the terminal cell C7 are arranged in the same layer in the Z direction as the local wirings 43 and 44 of the inverter cells C5 and C6. In other words, by providing dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings including the dummy gate wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0179] Furthermore, the dummy gate wirings 131 to 135 of the terminal cell C7 are formed to have the same length Lg in the Y direction as the gate wiring 31 and dummy gate wirings 32 and 33 of the inverter cells C5 and C6, thereby suppressing variations in the finished shape of the layout pattern and suppressing manufacturing variations in the semiconductor integrated circuit device.

[0180] Furthermore, the local wirings 141 to 148 of the terminal cell C7 are arranged so that their upper ends in the Y direction are at the same position as the upper ends in the Y direction of the local wirings 41 to 44 of the inverter cells C5 and C6. The local wirings 141 to 148 of the terminal cell C7 are arranged so that their lower ends in the Y direction are at the same position as the lower ends in the Y direction of the local wirings 41 to 44 of the inverter cells C5 and C6. In other words, the upper and lower ends in the Y direction of the local wirings arranged in the terminal cells are aligned with the upper and lower ends in the Y direction of the local wirings arranged in the cells that constitute the logic unit LC, respectively. This makes it possible to constant the distance from the logic unit LC to the nearest local wiring, thereby improving the performance predictability of the cells arranged in the logic unit LC.

[0181] In addition, the active region 2P7 (2N7) of the termination cell C7 is arranged in the same layer as the active region 2P5 (2N5) of the inverter cell C5 and the active region 2P6 (2N6) of the inverter cell C6 in the Z direction, which makes it possible to standardize the layout pattern of the active regions where the transistors are configured, and suppress manufacturing variations.

[0182] Furthermore, the active regions 2P7 and 2N7 of the termination cell C7 are located close to the dummy gate wiring 32 (135) located at the boundary between the termination cell C7 and the inverter cells C5 and C6. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0183] Furthermore, the bottom ends of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction, the bottom ends of the active region 2P6 (2N6) of the inverter cell C6 in the Y direction, and the bottom ends of the active region 2P7 (2N7) of the terminal cell C7 in the Y direction are arranged at the same position in the Y direction. That is, the bottom ends of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction, the bottom ends of the active region 2P6 (2N6) of the inverter cell C6 in the Y direction, and the bottom ends of the active region 2P7 (2N7) of the terminal cell C7 in the Y direction are aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C5 and C6 and the nanosheets 121 to 123 (124 to 126) of the terminal cell C7 have their lower surfaces in the Y direction exposed from the gate wiring 31 and the dummy gate wiring 131 to 133, respectively. That is, in inverter cells C5 and C6 and terminal cell C7, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structures provided between the nanosheets exposed from the gate wiring, i.e., their size and placement area in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0184] The Y-direction width of the active region 2P5 (2N5) in the inverter cell C5 and the Y-direction width of the active region 2P7 (2N7) in the termination cell C7 are w1. The Y-direction width of the active region 2P6 (2N6) in the inverter cell C6 is w2, which is smaller than w1. The Y-direction bottom ends of the active region 2P5 (2N5) in the inverter cell C5, the Y-direction bottom ends of the active region 2P6 (2N6) in the inverter cell C6, and the Y-direction bottom ends of the active region 2P7 (2N7) in the termination cell C7 are aligned in the Y-direction. By arranging the termination cell C7 adjacent to the inverter cells C5 and C6, which have active regions with different Y-direction widths, the active region of the termination cell C7 can be positioned along the entire left side of the active region of the inverter cell C5 and the entire left side of the active region of the inverter cell C6. Therefore, the distances from the active region 2P5 (2N5) of the inverter cell C5 and the active region 2P6 (2N6) of the inverter cell C6 to the active region 2P7 (2N7) of the termination cell C7 are set to predetermined values, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0185] Although five dummy gate wirings (dummy gate wirings 131 to 135) and eight local wirings (local wirings 141 to 148) are arranged in the termination cell C7, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C7 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C7 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C7 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C7.

[0186] In this embodiment, the active regions of the upper and lower parts of the inverter cells C5 and C6 and the termination cell C7 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P7 of the termination cell C7 is the same as the Y-direction width of the active region 2P5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2P6 of the inverter cell C6. Similarly, it is sufficient that the Y-direction width of the active region 2N7 of the termination cell C7 is the same as the Y-direction width of the active region 2N5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2N6 of the inverter cell C6.

[0187] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C7 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0188] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0189] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P7 and 2N7 of the termination cell C7 may be connected to the power supply wirings 11 and 51 through vias.

[0190] (Configuration of Termination Cell C8) Figure 14 is a plan view of portion A6 in Figure 11. Specifically, Figure 14(a) shows the lower part of the cell, and Figure 14(b) shows the upper part of the cell. In Figure 14, inverter cells C5 and C6 are arranged inverted in the Y direction.

[0191] The termination cell C8 in Fig. 14 differs from the termination cell C4 in Fig. 6 in the arrangement of the power supply wirings 11 and 51. Active regions 2P8 and 2N8 are formed in place of the active regions 2P4 and 2N4.

[0192] 14, the terminal cell C8 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C5 and C6 arranged at the top end of the logic unit LC in the drawing.

[0193] 14A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0194] An active region 2P8 is formed in the P-type transistor region. Dummy transistors DP4 to DP6 are formed in the active region 2P8. The active region 2P8 overlaps with the power supply wiring 11 in plan view.

[0195] As shown in Figure 14(b), an active region 2N8 is formed in the N-type transistor region. The active region 2N8 is arranged higher in the Z direction than the active region 2P8. The active region 2N8 overlaps with the active region 2P8 in plan view. Dummy transistors DN4 to DN6 are formed in the active region 2N8.

[0196] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The power supply wiring 51 overlaps with the active region 2N8 in plan view.

[0197] 14, unlike the inverter cells C5 and C6, the dummy gate wirings 231 to 235 and the local wirings 241 to 248 are not connected to any other wirings. In other words, the termination cell C8 is a standard cell that does not have a logic function.

[0198] 14, nanosheets 221 and 224 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C5, respectively, and are arranged in the same layer in the Z direction. Nanosheets 223 and 226 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C6, respectively, and are arranged in the same layer in the Z direction.

[0199] The gate wiring 31 and the dummy gate wirings 32, 33, 231 to 235 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. The dummy gate wirings 231 to 235 are also arranged at the same pitch Pg in the X direction and in the same layer in the Z direction.

[0200] The local wirings 241 to 244 are arranged at the same pitch P1 in the X direction. The local wirings 41, 42, and 241 to 244 are arranged in the same layer in the Z direction. The local wirings 245 to 248 are arranged at the same pitch P1 in the X direction. The local wirings 43, 44, and 245 to 248 are arranged in the same layer in the Z direction.

[0201] The local wirings 241 to 248 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 241 to 248 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0202] 14, a termination cell C8 having no logic function is arranged adjacent to inverter cells C5 and C6 having logic functions in the cell column CR at the top row in the Y direction of the circuit block. The active region 2P8 (2N8) of the termination cell C8 is arranged in the same layer as the active region 2P5 (2N5) of the inverter cell C5 and the active region 2P6 (2N6) of the inverter cell C6. The local wirings 241-244 of the termination cell C8 are arranged in the same layer as the local wirings 41 and 42 of the inverter cells C5 and C6. The local wirings 245-248 of the termination cell C8 are arranged in the same layer as the local wirings 43 and 44 of the inverter cells C5 and C6. In other words, by providing dummy transistors, dummy gate wiring, and local wiring in the termination cell, transistors including dummy transistors, gate wiring including dummy gate wiring, and local wiring are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0203] Furthermore, nanosheets 221 and 224 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C5, respectively. Nanosheets 223 and 226 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C6, respectively. Dummy gate wirings 231 to 235 of terminal cell C8 are arranged in the same positions in the X direction as gate wiring 31 of inverter cell C5, dummy gate wiring 33 of inverter cell C5 (dummy gate wiring 32 of inverter cell C6), gate wiring 31 of inverter cell C6, dummy gate wiring 32 of inverter cell C5, and dummy gate wiring 33 of inverter cell C6, respectively. Local wirings 241, 242, 245, and 246 of terminal cell C8 are arranged in the same positions in the X direction as local wirings 41 to 44 of inverter cell C5, respectively. The local interconnects 243, 244, 247, and 248 of the terminal cell C8 are arranged in the same positions in the X direction as the local interconnects 41 to 44 of the inverter cell C6. That is, the terminal cell C8 has dummy transistors, dummy gate interconnects, and local interconnects formed across the entire cell width. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0204] Furthermore, the upper end of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction and the upper end of the active region 2P6 (2N6) of the inverter cell C6 in the Y direction are arranged at the same position in the Y direction. The lower end of the active region 2P8 (2N8) of the terminal cell C8 in the Y direction are arranged at the same position in the Y direction. That is, the upper end of the active region 2P5 (2N5) of the inverter cell C5 in the Y direction and the upper end of the active region 2P6 (2N6) of the inverter cell C6 in the Y direction are aligned in the Y direction. The lower end of the active region 2P8 (2N8) of the terminal cell C8 in the Y direction are aligned in the Y direction. Furthermore, the upper surface of the nanosheets 21 (22) of the inverter cells C5 and C6 in the Y direction is exposed from the gate wiring 31. The nanosheets 121-123 (124-126) of the terminal cell C8 have their lower surfaces in the Y direction exposed from the dummy gate wirings 131-133, respectively. That is, the opposing surfaces of the nanosheets of the inverter cell C5 (C6) and the terminal cell C8 are exposed from the gate wiring. This allows the shape of the structure made of an insulator formed between the opposing nanosheets exposed from the gate wiring, i.e., the size and layout range of the structure in the Y direction, to be constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0205] Although five dummy gate wirings (dummy gate wirings 231 to 235) and eight local wirings (local wirings 241 to 248) are arranged in the termination cell C8, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C8 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C8 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C8 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C8.

[0206] In this embodiment, the active regions of the upper and lower parts of the inverter cells C5 and C6 and the termination cell C8 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P8 of the termination cell C8 is the same as the Y-direction width of the active region 2P5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2P6 of the inverter cell C6. Similarly, it is sufficient that the Y-direction width of the active region 2N8 of the termination cell C8 is the same as the Y-direction width of the active region 2N5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2N6 of the inverter cell C6.

[0207] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C8 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0208] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0209] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P8 and 2N8 of the termination cell C8 may be connected to the power supply wirings 11 and 51 through vias.

[0210] 9, in the present embodiment, in the inverter cells C5 and C6 and the terminal cell C8, the surfaces of each nanosheet on the opposite side in the Y direction may be exposed from the gate wiring. That is, the surfaces of the nanosheets of the inverter cells C5 and C6 and the nanosheet of the terminal cell C8 facing each other may be covered by the gate wiring.

[0211] (Third Embodiment) (Circuit Block Configuration) Fig. 15 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a third embodiment. Specifically, Fig. 15 shows the lower part of the cell. Note that Fig. 15 shows only the power supply wiring arranged in the standard cell, and the rest is omitted.

[0212] 15 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0213] 15, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The plurality of cells includes inverter cells C9 and C10 having logic functions and termination cells C11 and C12.

[0214] In each cell, power supply wiring is formed at the cell boundary in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, a power supply wiring (power supply wiring 11) that supplies a power supply voltage VDD is formed in the BM0 wiring layer, and a power supply wiring (power supply wiring 51) that supplies a power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 15, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column CR.

[0215] In the layout of FIG. 15 , similar to the layout of FIG. 1 , a rectangular logic unit LC that includes logic cells having logic functions and realizes the circuit function is arranged in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C9 and C10 are arranged in the logic unit LC. Termination cells C11 and C12 are arranged in the termination cell unit. Specifically, in each cell row CR, termination cells C11 are arranged on both the left and right ends of the drawing in the X direction. Termination cells C12 are arranged in the cell rows CR arranged in the top and bottom rows of the circuit block in the Y direction.

[0216] (Configuration of inverter cell C9) Fig. 16 is a plan view of portion A7 in Fig. 15. Specifically, Fig. 16(a) shows the lower part of the cell, and Fig. 16(b) shows the upper part of the cell. Note that inverter cells C9 and C10 each have the inverter circuit of Fig. 4 configured therein.

[0217] As shown in FIGS. 15 and 16, the inverter cell C9 is arranged at the left end of the logic unit LC in the drawing, and the termination cell C11 is arranged adjacent to it on the left side.

[0218] 16A, the BM0 wiring layer has a power supply wiring 11 formed at the upper end of the cell in the Y direction in the drawing, the power supply wiring 11 extending in the X direction. The power supply wiring 11 supplies a power supply voltage VDD.

[0219] An active region 2P9 is formed in the P-type transistor region at the bottom of the cell. A transistor P1 is formed in the active region 2P9. The transistor P1 has a nanosheet 21 extending in the X direction.

[0220] 16B, an active region 2N9 is formed in the N-type transistor region in the upper part of the cell. The active region 2N9 is arranged higher in the Z direction than the active region 2P9. The active region 2N9 overlaps with the active region 2P9 in plan view.

[0221] The active region 2N9 includes a transistor N1. The transistor N1 includes a nanosheet 22.

[0222] A gate wiring 31 extending in the Y direction is formed in the center of the cell in the X direction in the drawing. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of the transistors P1 and N1.

[0223] The gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower surfaces of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper surfaces of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0224] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0225] As shown in FIG. 16A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P9 that will become the source of the transistor P1. The local wiring 41 is connected to the power supply wiring 11 through a via 61. The via 61 is formed in a region where the local wiring 41 and the power supply wiring 11 overlap in a planar view. That is, the power supply wiring 11 is connected to a portion of the active region 2P9 that will become the source of the transistor P1 through the via 61 and the local wiring 41. The local wiring 42 is connected to a portion of the active region 2P9 that will become the drain of the transistor P1.

[0226] 16B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N9 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N9 that will become the drain of the transistor N1.

[0227] In the M0 wiring layer, a power supply wiring 51 extending in the X direction and wirings 52 and 53 are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0228] The power supply wiring 51 is formed at the upper end of the cell in the Y direction in the drawing. The power supply wiring 51 is connected to a portion of the active region 2N9 that serves as the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in a region where the power supply wiring 51 and the local wiring 43 overlap in a plan view.

[0229] The wiring 52 is disposed near the center of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N9 overlap in plan view.

[0230] In a plan view, the wiring 53 is disposed between the power supply wiring 51 and the wiring 52. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and the local wirings 42, 44.

[0231] As described above, the inverter cell C9 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C9 is a standard cell having a logic function.

[0232] As shown in FIGS. 16A and 16B, the active regions 2P9 and 2N9 in the inverter cell C9 have a width of w1 in the Y direction in plan view.

[0233] In the inverter cell C9 shown in FIG. 16, the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in adjacent cells in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P9 (2N9) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P9 and 2N9 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0234] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P9 (2N9) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P9 (2N9) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P9 (2N9) is positioned closer to the lower end of the cell frame in the Y direction when the center of the cell frame in the Y direction is used as the reference. That is, in a planar view, the center of the active region 2P9 (2N9) in the Y direction is lower than the center of the cell frame in the Y direction.

[0235] Furthermore, power supply wiring 11, 51 is formed at the upper end of the cell in the Y direction in plan view, and is shared with the standard cell arranged above inverter cell C9 in the Y direction in the drawing. Thus, by arranging inverter cell C9 in the circuit block of Fig. 15, it is possible to strengthen the power supply wiring that supplies power supply voltages VDD and VSS, thereby suppressing a drop in power supply voltage and suppressing the occurrence of electromigration due to current concentration.

[0236] Furthermore, in a plan view, the power supply wiring 11 (51) does not overlap with the active region 2P9 (2N9). This reduces the load capacitance of the power supply wiring 11 (51) that supplies the power supply voltage VDD (VSS) to the transistor P1 (N1) configured in the active region 2P9 (2N9), thereby enabling the semiconductor integrated circuit device to operate at a higher speed. Note that, in a plan view, the power supply wiring 11 (51) may overlap with the active region 2P9 (2N9). In this case, the overlapping area between the power supply wiring 11 (51) and the active region 2P9 (2N9) can be made smaller than in the inverter cell C5 of FIG. 12, enabling the semiconductor integrated circuit device to operate at a higher speed.

[0237] Furthermore, via 63 connecting wiring 52 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N9 and gate wiring 31. This reduces the distance from wiring 52 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance from wiring 52 and enabling the speed of the semiconductor integrated circuit device to be increased.

[0238] Furthermore, the wiring 53 is disposed higher in the Y direction than the wiring 52 in the drawing (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N9 is disposed closer to the cell frame). The via 64 connecting the wiring 53 and the local wiring 44 and the via 65 connecting the local wirings 42 and 44 are formed higher in the Y direction than the wiring 52 in a plan view. This reduces the distance from the wiring 53 to the portion of the active region 2P9 that serves as the drain of the transistor P1 and the portion of the active region 2N9 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P9 (2N9) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0239] Furthermore, the via 61 connecting the power supply wiring 11 and the local wiring 41 connected to the portion of the active region 2P9 that serves as the source of the transistor P1 is formed in a region where the power supply wiring 11 and the local wiring 41 overlap in a planar view. In a planar view, the via 61 is disposed toward the lower side of the region where the power supply wiring 11 and the local wiring 41 overlap in a planar view. In other words, in a planar view, the distance d6 in the Y direction from the center of the via 61 to the bottom edge of the power supply wiring 11 is smaller than the distance d7 in the Y direction from the center of the via 61 to the top edge of the local wiring 41. This positions the via 61 closer to the active region 2P9, thereby reducing the resistance from the via 61 to the nanosheet 21 and increasing the speed of the semiconductor integrated circuit device.

[0240] Furthermore, via 62, which connects power supply wiring 51 and local wiring 43 connected to a portion of active region 2N9 that serves as the source of transistor N1, is formed in a region where power supply wiring 11 and local wiring 43 overlap in a planar view. In a planar view, via 62 is disposed toward the lower side of the region where power supply wiring 51 and local wiring 43 overlap in a planar view. In other words, in a planar view, distance d6 in the Y direction from the center of via 62 to the bottom edge of power supply wiring 51 is smaller than distance d7 in the Y direction from the center of via 62 to the top edge of local wiring 43. This positions via 62 closer to active region 2N9, thereby reducing the resistance from via 62 to nanosheet 22 and increasing the speed of the semiconductor integrated circuit device.

[0241] (Configuration of inverter cell C10) Figure 17 is a plan view of portion A8 in Figure 16. Specifically, Figure 17(a) shows the lower part of the cell, and Figure 17(b) shows the upper part of the cell.

[0242] As shown in FIGS. 15 and 17, the inverter cell C10 is arranged at the left end of the logic unit LC in the drawing, and the termination cell C11 is arranged adjacent to it on the left side.

[0243] The inverter cell C10 has a configuration similar to that of the inverter cell C9. Specifically, the inverter cell C10 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C10 is a standard cell having a logic function.

[0244] As shown in FIG. 17, the inverter cell C10 is different from the inverter cell C9 shown in FIG. 16 in that active regions 2P10 and 2N10 having different widths in the Y direction are arranged in place of the active regions 2P9 and 2N9.

[0245] Specifically, the active regions 2P10 and 2N10 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C9 is greater than the drive capability of the inverter cell C10.

[0246] 16 and 17, the bottom edge of the active region 2P9 (2N9) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P10 (2N10) in the Y direction. That is, the bottom edge of the active region 2P9 (2N9) of the inverter cell C9 in the Y direction and the bottom edge of the active region 2P10 (2N10) of the inverter cell C10 in the Y direction are aligned in the Y direction.

[0247] 16 and 17 differs from the termination cell C3 of Figures 2 and 5 in the arrangement of the power supply wirings 11 and 51. Active regions 2P11 and 2N11 are formed instead of the active regions 2P3 and 2N3.

[0248] As shown in FIG. 15, the terminal cells C11 are arranged on both the left and right ends of the cell row CR in the X direction.

[0249] 16A and 17A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0250] An active region 2P11 is formed in the P-type transistor region, and dummy transistors DP1 to DP3 are formed in the active region 2P11.

[0251] As shown in Figures 16(b) and 17(b), an active region 2N11 is formed in the N-type transistor region. The active region 2N11 is arranged higher in the Z direction than the active region 2P11. The active region 2N11 overlaps with the active region 2P11 in a plan view. Dummy transistors DN1 to DN3 are formed in the active region 2N11.

[0252] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0253] 16 and 17, unlike the inverter cells C9 and C10, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the termination cell C11 is a standard cell that does not have a logic function.

[0254] 16 and 17, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0255] The local wirings 41, 42, and 141 to 144 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction. The local wirings 43, 44, and 145 to 148 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction.

[0256] The local wirings 41 to 44 and 141 to 148 are arranged so that their upper ends in the Y direction are at the same position on the drawing. The local wirings 41 to 44 and 141 to 148 are arranged so that their lower ends in the Y direction are at the same position on the drawing.

[0257] 16 and 17 , inverter cells C9 and C10 having logic functions and a terminal cell C11 having no logic function are arranged in a cell column CR. The terminal cell C11 is arranged at the left end of the cell column CR in the X direction of the drawing. Dummy gate wirings 131-135 of the terminal cell C11 are arranged in the same layer in the Z direction as the gate wiring 31 of the inverter cells C9 and C10. Local wirings 141-144 of the terminal cell C11 are arranged in the same layer in the Z direction as the local wirings 41 and 42 of the inverter cells C9 and C10. Local wirings 145-148 of the terminal cell C11 are arranged in the same layer in the Z direction as the local wirings 43 and 44 of the inverter cells C9 and C10. In other words, by providing dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings including the dummy gate wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0258] Furthermore, the dummy gate wirings 131 to 135 of the terminal cell C11 are formed with the same length Lg in the Y direction as the gate wiring 31 and dummy gate wirings 32 and 33 of the inverter cells C9 and C10, thereby suppressing variations in the finished shape of the layout pattern and suppressing manufacturing variations in the semiconductor integrated circuit device.

[0259] Furthermore, the local wirings 141 to 148 of the terminal cell C11 are arranged so that their upper ends in the Y direction are at the same position as the upper ends in the Y direction of the local wirings 41 to 44 of the inverter cells C9 and C10. The local wirings 141 to 148 of the terminal cell C11 are arranged so that their lower ends in the Y direction are at the same position as the lower ends in the Y direction of the local wirings 41 to 44 of the inverter cells C9 and C10. In other words, the upper and lower ends in the Y direction of the local wirings arranged in the terminal cells are aligned with the upper and lower ends in the Y direction of the local wirings arranged in the cells that constitute the logic unit LC, respectively. This makes it possible to constant the distance from the logic unit LC to the nearest local wiring, thereby improving the performance predictability of the cells arranged in the logic unit LC.

[0260] In addition, the active region 2P11 (2N11) of the termination cell C11 is arranged in the same layer as the active region 2P9 (2N9) of the inverter cell C9 and the active region 2P10 (2N10) of the inverter cell C10 in the Z direction, which makes it possible to standardize the layout pattern of the active regions where the transistors are configured, and suppress manufacturing variations.

[0261] Furthermore, the active regions 2P11 and 2N11 of the termination cell C11 are located close to the dummy gate wiring 32 (135) located at the boundary between the termination cell C11 and the inverter cells C9 and C10. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0262] Furthermore, the bottom end in the Y direction of the active region 2P9 (2N9) of the inverter cell C9, the bottom end in the Y direction of the active region 2P10 (2N10) of the inverter cell C10, and the bottom end in the Y direction of the active region 2P11 (2N11) of the termination cell C11 are all located at the same position in the Y direction. That is, the bottom end in the Y direction of the active region 2P9 (2N9) of the inverter cell C9, the bottom end in the Y direction of the active region 2P10 (2N10) of the inverter cell C10, and the bottom end in the Y direction of the active region 2P11 (2N11) of the termination cell C11 are all aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C9 and C10 and the nanosheets 121 to 123 (124 to 126) of the terminal cell C11 have their lower surfaces in the Y direction exposed from the gate wiring 31 and dummy gate wiring 131 to 133, respectively. That is, in the inverter cells C9 and C10 and the terminal cell C11, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structures provided between the nanosheets exposed from the gate wiring, i.e., their size and installation range in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0263] The Y-direction width of the active region 2P9 (2N9) in the inverter cell C9 and the Y-direction width of the active region 2P11 (2N11) in the termination cell C11 are w1. The Y-direction width of the active region 2P10 (2N10) in the inverter cell C10 is w2, which is smaller than w1. The Y-direction bottom edges of the active region 2P9 (2N9) in the inverter cell C9, the Y-direction bottom edges of the active region 2P10 (2N10) in the inverter cell C10, and the Y-direction bottom edges of the active region 2P11 (2N11) in the termination cell C11 are aligned in the Y-direction. By disposing the termination cell C11 in the inverter cells C9 and C10, which have active regions with different Y-direction widths, the active region of the termination cell C11 can be positioned along the entire left side surface of the active region of the inverter cell C9 and the entire left side surface of the active region of the inverter cell C10. Therefore, the distances from the active region 2P9 (2N9) of the inverter cell C9 and the active region 2P10 (2N10) of the inverter cell C10 to the active region 2P11 (2N11) of the termination cell C11 are set to a predetermined value, thereby improving the accuracy of estimating the transistor performance of the logic cells.

[0264] Although the termination cell C11 has five dummy gate wirings (dummy gate wirings 131 to 135) and eight local wirings (local wirings 141 to 148), the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C11 is provided with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end portion of the logic unit. The number of local wirings arranged at the upper and lower portions of the termination cell C11 may differ. The cell width (dimension in the X direction) of the termination cell C11 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C11.

[0265] In this embodiment, the inverter cells C9, C10, and the termination cell C11 have the same Y-direction width in the active regions at the top and bottom of the cells, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P11 of the termination cell C11 is the same as the Y-direction width of the active region 2P9 of the inverter cell C9 and is larger than the Y-direction width of the active region 2P10 of the inverter cell C10. Similarly, it is sufficient that the Y-direction width of the active region 2N11 of the termination cell C11 is the same as the Y-direction width of the active region 2N9 of the inverter cell C9 and is larger than the Y-direction width of the active region 2N10 of the inverter cell C10.

[0266] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C11 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0267] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0268] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P11 and 2N11 of the termination cell C11 may be connected to the power supply wirings 11 and 51 through vias.

[0269] (Configuration of Termination Cell C12) Figure 18 is a plan view of portion A9 in Figure 15. Specifically, Figure 18(a) shows the lower part of the cell, and Figure 18(b) shows the upper part of the cell. In Figure 18, inverter cells C9 and C10 are arranged inverted in the Y direction.

[0270] The termination cell C12 of Fig. 18 differs from the termination cell C4 of Fig. 6 in the arrangement of the power supply lines 11 and 51. Active regions 2P12 and 2N12 are formed in place of the active regions 2P4 and 2N4.

[0271] 18, the terminal cell C12 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C9 and C10 arranged at the top end of the logic unit LC in the drawing.

[0272] 18A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD.

[0273] An active region 2P12 is formed in the P-type transistor region, and dummy transistors DP4 to DP6 are formed in the active region 2P12.

[0274] 18B, an active region 2N12 is formed in the N-type transistor region. The active region 2N12 is arranged higher in the Z direction than the active region 2P12. The active region 2N12 overlaps with the active region 2P12 in a plan view. Dummy transistors DN4 to DN6 are formed in the active region 2N12.

[0275] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction. The power supply wiring 51 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0276] 18, unlike the inverter cells C9 and C10, the dummy gate wirings 231 to 235 and the local wirings 241 to 248 are not connected to any other wirings. In other words, the termination cell C12 is a standard cell that does not have a logic function.

[0277] 18, nanosheets 221 and 224 of terminal cell C12 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C9, respectively, and are arranged in the same layer in the Z direction. Nanosheets 223 and 226 of terminal cell C12 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C10, respectively, and are arranged in the same layer in the Z direction.

[0278] The gate wiring 31 and the dummy gate wirings 32, 33, 231 to 235 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. The dummy gate wirings 231 to 235 are also arranged at the same pitch Pg in the X direction and in the same layer in the Z direction.

[0279] The local wirings 241 to 244 are arranged at the same pitch P1 in the X direction. The local wirings 41, 42, and 241 to 244 are arranged in the same layer in the Z direction. The local wirings 245 to 248 are arranged at the same pitch P1 in the X direction. The local wirings 43, 44, and 245 to 248 are arranged in the same layer in the Z direction.

[0280] The local wirings 241 to 248 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 241 to 248 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0281] 18, a termination cell C12 having no logic function is arranged adjacent to inverter cells C9 and C10 having logic functions in the cell column CR at the top row in the Y direction of the circuit block. The active region 2P12 (2N12) of the termination cell C12 is arranged in the same layer as the active region 2P9 (2N9) of the inverter cell C9 and the active region 2P10 (2N10) of the inverter cell C10. The local wirings 241-244 of the termination cell C12 are arranged in the same layer as the local wirings 41 and 42 of the inverter cells C9 and C10. The local wirings 245-248 of the termination cell C12 are arranged in the same layer as the local wirings 43 and 44 of the inverter cells C9 and C10. In other words, by providing dummy transistors, dummy gate wiring, and local wiring in the termination cell, transistors including dummy transistors, gate wiring including dummy gate wiring, and local wiring are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0282] Furthermore, nanosheets 221 and 224 of terminal cell C12 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C9, respectively. Nanosheets 223 and 226 of terminal cell C12 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C10, respectively. Dummy gate wirings 231 to 235 of terminal cell C12 are arranged in the same positions in the X direction as gate wiring 31 of inverter cell C9, dummy gate wiring 33 of inverter cell C9 (dummy gate wiring 32 of inverter cell C10), gate wiring 31 of inverter cell C10, dummy gate wiring 32 of inverter cell C9, and dummy gate wiring 33 of inverter cell C10, respectively. Local wirings 241, 242, 245, and 246 of terminal cell C12 are arranged in the same positions in the X direction as local wirings 41 to 44 of inverter cell C9, respectively. The local interconnects 243, 244, 247, and 248 of the terminal cell C12 are arranged in the same positions in the X direction as the local interconnects 41 to 44 of the inverter cell C10. That is, the terminal cell C12 has dummy transistors, dummy gate interconnects, and local interconnects formed across the entire cell width. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0283] Furthermore, the upper end of the active region 2P9 (2N9) of the inverter cell C9 in the Y direction and the upper end of the active region 2P10 (2N10) of the inverter cell C10 in the Y direction are arranged at the same position in the Y direction. The lower end of the active region 2P12 (2N12) of the terminal cell C12 in the Y direction are arranged at the same position in the Y direction. That is, the upper end of the active region 2P9 (2N9) of the inverter cell C9 in the Y direction and the upper end of the active region 2P10 (2N10) of the inverter cell C10 in the Y direction are aligned in the Y direction. The lower end of the active region 2P12 (2N12) of the terminal cell C12 in the Y direction are aligned in the Y direction. Furthermore, the upper surface of the nanosheet 21 (22) of the inverter cells C9 and C10 in the Y direction is exposed from the gate wiring 31. The nanosheets 221-223 (224-226) of the terminal cell C12 have their lower surfaces in the Y direction exposed from the dummy gate wirings 231-233, respectively. That is, the opposing surfaces of the nanosheets of the inverter cell C9 (C10) and the terminal cell C12 are exposed from the gate wiring. This allows the shape of the structure made of an insulator formed between the opposing nanosheets exposed from the gate wiring, i.e., the size and layout range of the structure in the Y direction, to be constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0284] Although five dummy gate wirings (dummy gate wirings 231 to 235) and eight local wirings (local wirings 241 to 248) are arranged in the termination cell C12, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C12 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end portion of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C12 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C12 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C12.

[0285] In this embodiment, the active regions of the upper and lower parts of the inverter cells C9 and C10 and the termination cell C12 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P12 of the termination cell C12 is the same as the Y-direction width of the active region 2P9 of the inverter cell C9 and is larger than the Y-direction width of the active region 2P10 of the inverter cell C10. Similarly, it is sufficient that the Y-direction width of the active region 2N12 of the termination cell C12 is the same as the Y-direction width of the active region 2N9 of the inverter cell C9 and is larger than the Y-direction width of the active region 2N10 of the inverter cell C10.

[0286] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C12 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0287] In addition, in this embodiment, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0288] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P12 and 2N12 of the termination cell C12 may be connected to the power supply wirings 11 and 51 through vias.

[0289] 9, in the present embodiment, in the inverter cells C9, C10 and the terminal cell C12, the surfaces of each nanosheet on the opposite side in the Y direction may be exposed from the gate wiring. That is, the surfaces of the nanosheets of the inverter cells C9, C10 and the nanosheet of the terminal cell C12 facing each other may be covered by the gate wiring.

[0290] (Fourth Embodiment) (Circuit Block Configuration) Fig. 19 is a plan view showing an example of the layout of a circuit block provided in a semiconductor integrated circuit device according to a fourth embodiment. Specifically, Fig. 19 shows the lower part of the cell. Note that Fig. 19 shows only the power supply wiring arranged in the standard cell, and the rest is omitted.

[0291] 19 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0292] 19, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The plurality of cells includes inverter cells C13 and C14 having logic functions and termination cells C15 and C16.

[0293] In each cell, power supply wiring is formed in the BM0 wiring layer at both the top and bottom ends in the Y direction of the drawing. Each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0294] In the layout of Figure 19, similar to the layout of Figure 1, a rectangular logic unit LC that includes logic cells having logic functions and realizes the circuit function is placed in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C13 and C14 are placed in the logic unit LC. Termination cells C15 and C16 are placed in the termination cell unit. Specifically, termination cells C15 are placed on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C16 are placed in the cell rows CR placed in the top and bottom rows of the circuit block in the Y direction.

[0295] (Configuration of inverter cell C13) Fig. 20 is a plan view of portion A10 in Fig. 19. Specifically, Fig. 20(a) shows the lower part of the cell, and Fig. 20(b) shows the upper part of the cell. Note that inverter cells C13 and C14 each have the inverter circuit of Fig. 4 configured therein.

[0296] As shown in FIGS. 19 and 20, the inverter cell C13 is arranged at the left end of the logic unit LC in the drawing, and the termination cell C15 is arranged adjacent to it on the left side.

[0297] As shown in Figure 20(a), a BM0 wiring layer is formed. Power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0298] An active region 2P13 is formed in the P-type transistor region below the cell. The active region 2P13 overlaps with the power supply wiring 11 in plan view.

[0299] A transistor P1 is formed in the active region 2P13. The transistor P1 has a nanosheet 21 extending in the X direction. In the active region 2P13, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 through a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P13 overlap in a plan view.

[0300] 20B, an active region 2N13 is formed in the N-type transistor region in the upper part of the cell. The active region 2N13 is arranged higher in the Z direction than the active region 2P13. The active region 2N13 overlaps with the active region 2P13 in a plan view.

[0301] The active region 2N13 includes a transistor N1. The transistor N1 has a nanosheet 22 extending in the X direction.

[0302] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0303] The gate wiring 31 covers the outer peripheries of the nanosheets 21 and 22 in the Y and Z directions so as to expose part of the outer peripheries of the nanosheets 21 and 22. Specifically, the lower surfaces of the nanosheets 21 and 22 in the Y direction are exposed from the gate wiring 31, and the upper surfaces of the nanosheets 21 and 22 in the Y direction are covered by the gate wiring 31.

[0304] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0305] 20A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P13 that will become the source of the transistor P1. The local wiring 42 is connected to a portion of the active region 2P13 that will become the drain of the transistor P1.

[0306] As shown in FIG. 20B , local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N13 that will become the source of the transistor N1. The local wiring 43 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in a region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. That is, the power supply wiring 12 is connected to a portion of the active region 2N13 that will become the source of the transistor N1 via the via 62 and the local wiring 43. The local wiring 44 is connected to a portion of the active region 2N13 that will become the drain of the transistor N1.

[0307] In the M0 wiring layer, wirings 52 and 53 extending in the X direction are formed. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0308] The wiring 52 is disposed near the center of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the active region 2N13 overlap in a plan view.

[0309] The wiring 53 is disposed on the upper side in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64, 65 and local wirings 42, 44.

[0310] As described above, the inverter cell C13 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C13 is a standard cell having a logic function.

[0311] As shown in FIGS. 20A and 20B, the active regions 2P13 and 2N13 in the inverter cell C13 have a width w1 in the Y direction in plan view.

[0312] In the inverter cell C13 shown in FIG. 20 , the nanosheets 21 and 22 have their lower surfaces exposed from the gate wiring 31 in the Y direction. Each cell row is arranged in a reversed orientation in the Y direction. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction. This reduces the distance d1 from the lower end of the active region 2P13 (2N13) in the Y direction to the lower end of the cell frame in the Y direction. In other words, the active regions 2P13 and 2N13 (nanosheets 21 and 22) can be positioned close to the lower end of the cell frame in the Y direction. This allows for a reduction in the area of ​​the semiconductor integrated circuit device.

[0313] Furthermore, the upper surfaces of the nanosheets 21 and 22 in the Y direction are not exposed from the gate wiring 31. That is, in cells adjacent to each other in the Y direction, the nanosheets in the active regions facing each other in the Y direction have their surfaces exposed from the gate wiring (lower surfaces) facing each other in the Y direction, and their surfaces not exposed from the gate wiring (upper surfaces) facing each other in the Y direction. Therefore, the distance d1 from the lower end of the active region 2P13 (2N13) in the Y direction to the lower end of the cell frame in the Y direction is smaller than the distance d2 from the upper end of the active region 2P13 (2N13) in the Y direction to the upper end of the cell frame in the Y direction. In other words, in a planar view, the active region 2P13 (2N13) is positioned closer to the lower end of the cell frame when the center of the cell frame in the Y direction is used as a reference. That is, in plan view, the center of the active region 2P13 (2N13) in the Y direction is located below the center of the cell frame in the Y direction.

[0314] In addition, in a plan view, the power supply wiring 11 is formed at the lower end of the drawing in the Y direction of the cell, and is shared with the standard cell disposed on the lower side in the Y direction of the inverter cell C13. The power supply wiring 12 is formed at the upper end of the drawing in the Y direction of the cell in a plan view, and is shared with the standard cell disposed on the upper side in the Y direction of the inverter cell C13. Thus, by disposing the inverter cell C13 in the circuit block of FIG. 19, the power supply wiring for supplying the power supply voltages VDD and VSS can be strengthened, so that the drop of the power supply voltage can be suppressed and the occurrence of electromigration due to current concentration can be suppressed.

[0315] Also, the via 61 that connects the power supply wiring 11 and the portion that becomes the source of the transistor P1 in the active region 2P13 is formed in a region where the power supply wiring 11 and the active region 2P13 overlap in a plan view. In a plan view, the via 61 is disposed closer to the upper side of the drawing in a region where the power supply wiring 11 and the active region 2P13 overlap in a plan view. In other words, in a plan view, the distance d4 in the Y direction from the center of the drawing of the via 61 to the upper end of the drawing of the power supply wiring 11 is smaller than the distance d5 in the Y direction from the center of the drawing of the via 61 to the lower end of the drawing of the active region 2P13. Thus, since the via 61 is disposed closer to the center of the drawing in the Y direction of the active region 2P13, the difference between the resistance value from the via 61 to the upper end of the drawing of the nano sheet 21 of the transistor P1 in the active region 2P13 and the resistance value from the via 61 to the lower end of the drawing of the nano sheet 21 of the transistor P1 in the active region 2P13 becomes small. Therefore, the current flowing through the transistor P1 is equalized with respect to the vertical direction of the drawing in the Y direction, and the semiconductor integrated circuit device can be made faster.

[0316] Furthermore, the power supply wiring 12 is connected to the portion of the active region 2N13 that serves as the source of the transistor N1 via the via 62 and the local wiring 43. The via 62 connects the power supply wiring 12 formed in the BM0 wiring layer to the local wiring 43 formed above the cell, and therefore has a long length in the Z direction. As described above, the distance d1 from the bottom edge of the active region 2P13 (2N13) in the Y direction to the bottom edge of the cell frame in the Y direction is smaller than the distance d2 from the top edge of the active region 2P13 (2N13) in the Y direction to the top edge of the cell frame in the Y direction. This allows for a larger area from the top edge of the active region 2P13 (2N13) in the Y direction to the top edge of the cell frame in the Y direction, making it easier to form the via 62 in that area. This facilitates the manufacture of semiconductor integrated circuit devices, and improves yield and reliability.

[0317] Furthermore, the via 62 is formed in a region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. In a planar view, the via 62 is disposed toward the lower side of the region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. In other words, in a planar view, a distance d8 in the Y direction from the center of the via 62 to the bottom end of the power supply wiring 12 is smaller than a distance d9 in the Y direction from the center of the via 62 to the top end of the local wiring 43. This positions the via 62 closer to the active region 2N13, thereby reducing the resistance from the power supply wiring 12 to the portion of the active region 2N13 that serves as the source of the transistor N1, thereby enabling an increase in the speed of the semiconductor integrated circuit device.

[0318] Furthermore, via 63 connecting wiring 52 and gate wiring 31 is formed in a region that overlaps, in plan view, with active region 2N13 and gate wiring 31. This makes it possible to reduce the distance from wiring 52 (input A) to the portion of gate wiring 31 that overlaps with nanosheets 21 and 22 in plan view and covers nanosheets 21 and 22, thereby reducing the resistance from wiring 52 and enabling the speed of the semiconductor integrated circuit device to be increased.

[0319] Furthermore, the wiring 53 is disposed higher in the Y direction than the wiring 52 in the drawing (the side where the nanosheet 22 is not exposed from the gate wiring 31 and opposite the side where the active region 2N13 is disposed closer to the cell frame). The via 64 connecting the wiring 53 and the local wiring 44 and the via 65 connecting the local wirings 44 and 42 are formed higher in the Y direction than the wiring 52 in a plan view. This reduces the distance from the wiring 53 to the portion of the active region 2P13 that serves as the drain of the transistor P1 and the portion of the active region 2N13 that serves as the drain of the transistor N1, thereby reducing the resistance from the wiring 53 to the portion of the active region 2P13 (2N13) that serves as the drain of the transistor P1 (N1), thereby enabling the speed of the semiconductor integrated circuit device to be increased.

[0320] (Configuration of inverter cell C14) Fig. 21 is a plan view of portion A11 in Fig. 19. Specifically, Fig. 21(a) shows the lower part of the cell, and Fig. 21(b) shows the upper part of the cell.

[0321] As shown in FIGS. 19 and 21, the inverter cell C14 is arranged at the left end of the logic unit LC in the drawing, and the termination cell C15 is arranged adjacent to it on the left side.

[0322] The inverter cell C14 has a configuration similar to that of the inverter cell C13. Specifically, the inverter cell C13 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C13 is a standard cell having a logic function.

[0323] As shown in FIG. 21, in comparison with the inverter cell C13 shown in FIG. 20, the inverter cell C14 has active regions 2P14 and 2N14 having different widths in the Y direction arranged therein instead of the active regions 2P13 and 2N13.

[0324] Specifically, the active regions 2P14 and 2N14 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C13 is greater than the drive capability of the inverter cell C14.

[0325] 20 and 21, the bottom edge of the active region 2P14 (2N14) in the Y direction is located at the same position in the Y direction as the bottom edge of the active region 2P13 (2N13) in the Y direction. That is, the bottom edge of the active region 2P13 (2N13) of the inverter cell C13 in the Y direction and the bottom edge of the active region 2P14 (2N14) of the inverter cell C14 are aligned in the Y direction.

[0326] (Configuration of Termination Cell C15) In the termination cell C15 of FIGS. 20 and 21, compared to the termination cell C3 of FIGS. 2 and 5, power supply wirings 11 and 12 are formed in the BM0 wiring layer, and the power supply wiring 51 in the M0 wiring layer is omitted.

[0327] As shown in FIG. 19, the terminal cells C15 are arranged on both the left and right ends of the cell row CR in the X direction.

[0328] 20(a) and 21(a), the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0329] An active region 2P15 is formed in the P-type transistor region. Dummy transistors DP1 to DP3 are formed in the active region 2P15. The active region 2P15 overlaps with the power supply wiring 11 in plan view.

[0330] As shown in Figures 20(b) and 21(b), an active region 2N15 is formed in the N-type transistor region. The active region 2N15 is arranged higher in the Z direction than the active region 2P15. The active region 2N15 overlaps with the active region 2P15 in a plan view. Dummy transistors DN1 to DN3 are formed in the active region 2N15.

[0331] 20 and 21, unlike the inverter cells C13 and C14, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to any other wirings. In other words, the termination cell C15 is a standard cell that does not have a logic function.

[0332] 20 and 21, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0333] The local wirings 41, 42, and 141 to 144 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction. The local wirings 43, 44, and 145 to 148 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction.

[0334] The local wirings 42 to 44 and 141 to 148 are arranged so that their upper ends in the Y direction are at the same position in the drawing. The local wirings 41 to 44 and 141 to 148 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0335] 20 and 21 , inverter cells C13 and C14 having logic functions and a terminal cell C15 having no logic function are arranged in a cell column CR. The terminal cell C15 is arranged at the left end of the cell column CR in the X direction of the drawing. Dummy gate wirings 131-135 of the terminal cell C15 are arranged in the same layer in the Z direction as the gate wiring 31 of the inverter cells C13 and C14. Local wirings 141-144 of the terminal cell C15 are arranged in the same layer in the Z direction as the local wirings 41 and 42 of the inverter cells C13 and C14. Local wirings 145-148 of the terminal cell C15 are arranged in the same layer in the Z direction as the local wirings 43 and 44 of the inverter cells C13 and C14. In other words, by providing dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings including the dummy gate wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0336] Furthermore, the dummy gate wirings 131 to 135 of the terminal cell C15 are formed with the same length Lg in the Y direction as the gate wiring 31 and dummy gate wirings 32 and 33 of the inverter cells C13 and C14. This makes it possible to suppress variations in the finished shape of the layout pattern, and to suppress manufacturing variations in semiconductor integrated circuit devices.

[0337] Furthermore, the local wirings 141 to 148 of the terminal cell C15 are arranged so that their upper ends in the Y direction are at the same position as the upper ends in the Y direction of the local wirings 42 to 44 of the inverter cells C13 and C14. The local wirings 141 to 148 of the terminal cell C15 are arranged so that their lower ends in the Y direction are at the same position as the lower ends in the Y direction of the local wirings 41 to 44 of the inverter cells C13 and C14. In other words, the upper and lower ends in the Y direction of the local wirings arranged in the terminal cell are aligned with the upper and lower ends in the Y direction of the local wirings arranged in the cells that constitute the logic unit LC, respectively. This makes it possible to constant the distance from the logic unit LC to the nearest local wiring, thereby improving the performance predictability of the cells arranged in the logic unit LC.

[0338] In addition, the active region 2P15 (2N15) of the termination cell C15 is arranged in the same layer in the Z direction as the active region 2P13 (2N13) of the inverter cell C13 and the active region 2P14 (2N14) of the inverter cell C14. This makes it possible to standardize the layout pattern for the active regions in which the transistors are configured, thereby suppressing manufacturing variations.

[0339] Furthermore, the active regions 2P15 and 2N15 of the termination cell C15 are located close to the dummy gate wiring 32 (135) located at the boundary between the termination cell C15 and the inverter cells C13 and C14. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0340] Furthermore, the bottom end in the Y direction of the active region 2P13 (2N13) of the inverter cell C13, the bottom end in the Y direction of the active region 2P14 (2N14) of the inverter cell C14, and the bottom end in the Y direction of the active region 2P15 (2N15) of the termination cell C15 are all located at the same position in the Y direction. That is, the bottom end in the Y direction of the active region 2P13 (2N13) of the inverter cell C13, the bottom end in the Y direction of the active region 2P14 (2N14) of the inverter cell C14, and the bottom end in the Y direction of the active region 2P15 (2N15) of the termination cell C15 are all aligned in the Y direction. Furthermore, the nanosheets 21 (22) of the inverter cells C13 and C14 and the nanosheets 121 to 123 (124 to 126) of the terminal cell C15 have their lower surfaces in the Y direction exposed from the gate wiring 31 and dummy gate wiring 131 to 133, respectively. That is, in the inverter cells C13 and C14 and the terminal cell C15, the positions of the surfaces of the nanosheets exposed from the gate wiring are aligned in the Y direction. This allows the shape of the insulator structures provided between the nanosheets exposed from the gate wiring, i.e., their size and installation range in the Y direction, to be consistent. This facilitates the manufacture of semiconductor integrated circuit devices.

[0341] The Y-direction width of the active region 2P13 (2N13) of the inverter cell C13 and the Y-direction width of the active region 2P15 (2N15) of the termination cell C15 are w1. The Y-direction width of the active region 2P14 (2N14) of the inverter cell C14 is w2, which is smaller than w1. The Y-direction bottom edge of the active region 2P13 (2N13) of the inverter cell C13, the Y-direction bottom edge of the active region 2P14 (2N14) of the inverter cell C14, and the Y-direction bottom edge of the active region 2P15 (2N15) of the termination cell C15 are aligned in the Y-direction. By arranging the termination cell C15 adjacent to the inverter cells C13 and C14, each having an active area with a different width in the Y direction, the active area of ​​the termination cell C15 can be positioned along the entire left side of the active area of ​​the inverter cell C13 and the entire left side of the active area of ​​the inverter cell C14. Therefore, the distances from the active area 2P13 (2N13) of the inverter cell C13 and the active area 2P14 (2N14) of the inverter cell C14 to the active area 2P15 (2N15) of the termination cell C15 are set to predetermined values. This improves the accuracy of estimating the transistor performance of the logic cells.

[0342] Although the termination cell C15 has five dummy gate wirings (dummy gate wirings 131 to 135) and eight local wirings (local wirings 141 to 148), the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C15 is provided with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end portion of the logic unit. The number of local wirings arranged at the upper and lower portions of the termination cell C15 may differ. The cell width (dimension in the X direction) of the termination cell C15 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C15.

[0343] In this embodiment, the active regions of the upper and lower parts of the inverter cells C13, C14, and the termination cell C15 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P15 of the termination cell C15 is the same as the Y-direction width of the active region 2P13 of the inverter cell C13 and is larger than the Y-direction width of the active region 2P14 of the inverter cell C14. Similarly, it is sufficient that the Y-direction width of the active region 2N15 of the termination cell C15 is the same as the Y-direction width of the active region 2N13 of the inverter cell C13 and is larger than the Y-direction width of the active region 2N14 of the inverter cell C14.

[0344] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C15 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0345] In addition, in this embodiment, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same wiring width, but the power supply wirings 11 and 12 may have different wiring widths.

[0346] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P15 and 2N15 of the termination cell C15 may be connected to the power supply wirings 11 and 12 through vias.

[0347] (Configuration of Termination Cell C16) Fig. 22 is a plan view of portion A12 in Fig. 19. Specifically, Fig. 22(a) shows the lower part of the cell, and Fig. 22(b) shows the upper part of the cell. In Fig. 22, inverter cells C13 and C14 are arranged inverted in the Y direction.

[0348] In the terminal cell C16 of FIG. 22, compared to the terminal cell C4 of FIG. 6, power supply wirings 11 and 12 are formed in the BM0 wiring layer, and the power supply wiring 51 in the M0 wiring layer is omitted.

[0349] 22, the terminal cell C16 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C13 and C14 arranged at the top end of the logic unit LC in the drawing.

[0350] 22A, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0351] An active region 2P16 is formed in the P-type transistor region. Dummy transistors DP4 to DP6 are formed in the active region 2P16. The active region 2P16 overlaps with the power supply wiring 11 in a plan view.

[0352] As shown in Figure 22(b), an active region 2N16 is formed in the N-type transistor region. The active region 2N16 is arranged higher in the Z direction than the active region 2P16. The active region 2N16 overlaps with the active region 2P16 in plan view. Dummy transistors DN4 to DN6 are formed in the active region 2N16.

[0353] 22, unlike the inverter cells C13 and C14, the dummy gate wirings 231 to 235 and the local wirings 241 to 248 are not connected to any other wirings. In other words, the termination cell C16 is a standard cell that does not have a logic function.

[0354] 22, nanosheets 221 and 224 of terminal cell C16 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C13, respectively, and are arranged in the same layer in the Z direction. Nanosheets 223 and 226 of terminal cell C16 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C14, respectively, and are arranged in the same layer in the Z direction.

[0355] The gate wiring 31 and the dummy gate wirings 32, 33, 231 to 235 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. The dummy gate wirings 231 to 235 are also arranged at the same pitch Pg in the X direction and in the same layer in the Z direction.

[0356] The local wirings 241 to 244 are arranged at the same pitch P1 in the X direction. The local wirings 41, 42, and 241 to 244 are arranged in the same layer in the Z direction. The local wirings 245 to 248 are arranged at the same pitch P1 in the X direction. The local wirings 43, 44, and 245 to 248 are arranged in the same layer in the Z direction.

[0357] The local wirings 241 to 248 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 241 to 248 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0358] 22, a termination cell C16 having no logic function is arranged adjacent to inverter cells C13 and C14 having logic functions in the topmost cell column CR in the Y direction of the circuit block. The active region 2P16 (2N16) of the termination cell C16 is arranged in the same layer as the active region 2P13 (2N13) of the inverter cell C13 and the active region 2P14 (2N14) of the inverter cell C14. The local wirings 241-244 of the termination cell C16 are arranged in the same layer as the local wirings 41 and 42 of the inverter cells C13 and C14. The local wirings 245-248 of the termination cell C16 are arranged in the same layer as the local wirings 43 and 44 of the inverter cells C13 and C14. In other words, by providing dummy transistors, dummy gate wiring, and local wiring in the termination cell, transistors including dummy transistors, gate wiring including dummy gate wiring, and local wiring are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0359] Furthermore, nanosheets 221 and 224 of terminal cell C16 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C13, respectively. Nanosheets 223 and 226 of terminal cell C16 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C14, respectively. Dummy gate wirings 231 to 235 of terminal cell C16 are arranged in the same positions in the X direction as gate wiring 31 of inverter cell C13, dummy gate wiring 33 of inverter cell C13 (dummy gate wiring 32 of inverter cell C14), gate wiring 31 of inverter cell C14, dummy gate wiring 32 of inverter cell C13, and dummy gate wiring 33 of inverter cell C14, respectively. Local wirings 241, 242, 245, and 246 of terminal cell C16 are arranged in the same positions in the X direction as local wirings 41 to 44 of inverter cell C13, respectively. The local interconnects 243, 244, 247, and 248 of the terminal cell C16 are arranged in the same positions in the X direction as the local interconnects 41 to 44 of the inverter cell C14. That is, the terminal cell C16 has dummy transistors, dummy gate interconnects, and local interconnects formed across the entire cell width. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0360] Furthermore, the upper end of the active region 2P13 (2N13) of the inverter cell C13 in the Y direction and the upper end of the active region 2P14 (2N14) of the inverter cell C14 in the Y direction are arranged at the same position in the Y direction. The lower end of the active region 2P16 (2N16) of the terminal cell C16 in the Y direction are arranged at the same position in the Y direction. That is, the upper end of the active region 2P13 (2N13) of the inverter cell C13 in the Y direction and the upper end of the active region 2P14 (2N14) of the inverter cell C14 in the Y direction are aligned in the Y direction. The lower end of the active region 2P16 (2N16) of the terminal cell C16 in the Y direction are aligned in the Y direction. Furthermore, the upper surface of the nanosheets 21 (22) of the inverter cells C13 and C14 in the Y direction is exposed from the gate wiring 31. The nanosheets 221 to 233 (224 to 226) of the terminal cell C16 have their lower surfaces in the Y direction exposed from the dummy gate wirings 231 to 233, respectively. That is, the opposing surfaces of the nanosheets of the inverter cell C13 (C14) and the terminal cell C16 are exposed from the gate wiring. This allows the shape of the structure made of an insulator formed between the opposing nanosheets exposed from the gate wiring, i.e., the size and layout range of the structure in the Y direction, to be constant. This facilitates the manufacture of semiconductor integrated circuit devices.

[0361] Although five dummy gate wirings (dummy gate wirings 231 to 235) and eight local wirings (local wirings 241 to 248) are arranged in the termination cell C16, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C16 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C16 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C16 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C16.

[0362] In this embodiment, the active regions of the upper and lower parts of the inverter cells C13, C14, and the termination cell C16 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P16 of the termination cell C16 is the same as the Y-direction width of the active region 2P13 of the inverter cell C13 and is larger than the Y-direction width of the active region 2P14 of the inverter cell C14. Similarly, it is sufficient that the Y-direction width of the active region 2N16 of the termination cell C16 is the same as the Y-direction width of the active region 2N13 of the inverter cell C13 and is larger than the Y-direction width of the active region 2N14 of the inverter cell C14.

[0363] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C16 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0364] In addition, in this embodiment, the power supply wirings 11 and 12 formed in the BM0 wiring layer are illustrated as having the same wiring width, but the power supply wirings 11 and 12 may have different wiring widths.

[0365] In this embodiment, similarly to FIG. 7, the source and drain of each dummy transistor formed in the active regions 2P16 and 2N16 of the termination cell C16 may be connected to the power supply wirings 11 and 12 through vias.

[0366] 9, in the present embodiment, in the inverter cells C13, C14 and the terminal cell C16, the surfaces of each nanosheet on the opposite side in the Y direction may be exposed from the gate wiring. That is, the surfaces of the nanosheets of the inverter cells C13, C14 and the nanosheet of the terminal cell C16 facing each other may be covered by the gate wiring.

[0367] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0368] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0369] Furthermore, in each of the above-described embodiments and variants, a P-type transistor is formed at the bottom of the cell and an N-type transistor is formed at the top of the cell, but this is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor may be formed at the bottom of the cell.

[0370] Furthermore, in each of the above-described embodiments and variants, the standard cells having logic functions are described as inverter cells, but the standard cells having logic functions may also be other cells (NAND, NOR, flip-flops, etc.).

[0371] In the present disclosure, with respect to termination cells using CFETs, the layout of termination cells using fork-sheet transistors as transistors facilitates the manufacture of semiconductor integrated circuit devices and improves the accuracy of estimating the transistor performance of standard cells having logic functions.

[0372] 11, 12, 51 Power supply wiring 21, 22, 121-126, 221-226 Nanosheet 31 Gate wiring 32, 33, 131-135, 231-235 Dummy gate wiring 41-44, 141-148, 241-248 Local wiring 61-65, 161-168 Via 2P1-2P16, 2N1-2N16 Active area P1, N1 Transistor DP1-DP6, DN1-DN6 Dummy transistor C1, C2, C5, C6, C9, C10, C13, C14 Inverter cell C3, C4, C7, C8, C11, C12, C15, C16 Termination cell

Claims

1. A semiconductor device comprising a plurality of cell rows, each of which comprises a plurality of standard cells arranged side by side in a first direction, wherein a first cell row, which is one of the plurality of cell rows, comprises a first standard cell having a logic function, and a second standard cell arranged on at least one end of the first cell row and having no logic function, wherein the first standard cell comprises: a first active region constituting the channel, source, and drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in the first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, the second active region constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, the first gate wiring surrounding the first and second nanosheets in the second direction and the depth direction; the second active region is connected to the source of the second transistor in the second active region; and the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, the third active region constituting the channel, source, and drain of a first dummy transistor of the first conductivity type, the third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, the fourth active region constituting the channel, source, and drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and dummy gate wiring extending in the second direction, surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction.a first side surface of each of the first and second nanosheets, which is one side in the second direction, exposed from the first gate wiring; a first side surface of each of the third and fourth nanosheets, which is exposed from the dummy gate wiring; and an end of the first side of each of the first nanosheets and an end of the first side of each of the third nanosheets are arranged at the same position in the second direction in a plan view.

2. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed on the back side of the first transistor and is located in the center of the first standard cell in the second direction; the second power supply wiring is formed higher than the second transistor in the depth direction and is located in the center of the first standard cell in the second direction; the first standard cell is formed in a region in the first active region where a region that serves as the source of the first transistor and the first power supply wiring overlap, and the device further comprises a first via that connects the source of the first transistor in the first active region and the first power supply wiring.

3. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first side of the first standard cell; the second power supply wiring is formed higher than the second transistor in the depth direction and is arranged at the end of the first side of the first standard cell; the first standard cell is formed in a region in the first active region where a region that serves as the source of the first transistor and the first power supply wiring overlap, and the device further comprises a second via that connects the source of the first transistor in the first active region and the first power supply wiring.

4. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed on the back surface side of the first transistor and is arranged at the end of the first standard cell on the second side, which is the other side in the second direction, and the second power supply wiring is formed higher than the second transistor in the depth direction and is arranged at the end of the first standard cell on the second side.

5. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed on the back surface side of the first transistor and is arranged at the end of the first standard cell on the first side; the second power supply wiring is formed on the back surface side of the first transistor and is arranged at the end of the first standard cell on the second side, which is the other side in the second direction; the first standard cell is formed in a region in the first active region where the region that becomes the source of the first transistor and the first power supply wiring overlap, and the device further comprises a third via that connects the source of the first transistor in the first active region and the first power supply wiring.

6. A semiconductor integrated circuit device according to claim 1, wherein a second cell row, which is one of the plurality of cell rows, comprises a third standard cell having a logic function and the second standard cell arranged on at least one of both ends of the second cell row, the third standard cell comprising: a fifth active region formed in the same layer as the first active region in the depth direction, constituting the channel, source, and drain of the third transistor of the first conductivity type, the channel including a fifth nanosheet extending in the first direction; a sixth active region formed in the same layer as the second active region in the depth direction, constituting the channel, source, and drain of the fourth transistor of the second conductivity type, the channel including a sixth nanosheet extending in the first direction; a second gate wiring extending in the second direction and surrounding the periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and a third power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring. a fourth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring; the third power supply wiring connected to a source of the third transistor in the fifth active region; the fourth power supply wiring connected to a source of the fourth transistor in the sixth active region; the fifth and sixth nanosheets have their first side surfaces exposed from the second gate wiring; and in a planar view, the width of the fifth active region in the second direction is smaller than the width of the first active region in the second direction.

7. A semiconductor integrated circuit device according to claim 1, wherein the second standard cell further comprises: a fifth power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring; and a sixth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring, wherein the fifth power supply wiring is connected to the source and drain of the first dummy transistor, and the sixth power supply wiring is connected to the source and drain of the second dummy transistor.

8. A semiconductor device comprising a plurality of cell rows, each of which comprises a plurality of standard cells arranged side by side in a first direction, wherein a first cell row, which is one of the plurality of cell rows, comprises a first standard cell having a logic function and a second standard cell arranged on at least one end of the first cell row and having no logic function, wherein the first standard cell comprises: a first active region constituting the channel, source, and drain of a first transistor of a first conductivity type, the channel being a first nanosheet extending in the first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, the second active region constituting the channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in a second direction perpendicular to the first direction and the depth direction, the first gate wiring surrounding the peripheries of the first and second nanosheets in the second direction and the depth direction; the second active region is connected to the source of the second transistor in the second active region; and the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, source, and drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, source, and drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel; and a dummy gate wiring extending in the second direction, surrounding the outer peripheries of the third and fourth nanosheets in the second direction and the depth direction;a first-side surface of the first and second nanosheets, which is one side in the second direction, exposed from the first gate wiring; a first-side surface of the third and fourth nanosheets, which is exposed from the dummy gate wiring; and a first-side end and a second-side end of the first active region are disposed between a first-side end and a second-side end of the third active region, which is the other side in the second direction, in the second direction.

9. A semiconductor integrated circuit device according to claim 8, wherein the first power supply wiring is formed on the back side of the first transistor and is located in the center of the first standard cell in the second direction; the second power supply wiring is formed higher than the second transistor in the depth direction and is located in the center of the first standard cell in the second direction; the first standard cell is formed in a region in the first active region where a region that serves as the source of the first transistor and the first power supply wiring overlap, and the device further comprises a first via that connects the source of the first transistor in the first active region and the first power supply wiring.

10. A semiconductor integrated circuit device according to claim 8, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first side of the first standard cell; the second power supply wiring is formed higher than the second transistor in the depth direction and is arranged at the end of the first side of the first standard cell; the first standard cell is formed in a region in the first active region where a region that serves as the source of the first transistor and the first power supply wiring overlap, and the device further comprises a second via that connects the source of the first transistor in the first active region and the first power supply wiring.

11. A semiconductor integrated circuit device according to claim 8, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first standard cell on the second side, and the second power supply wiring is formed higher than the second transistor in the depth direction and is arranged at the end of the first standard cell on the second side.

12. A semiconductor integrated circuit device according to claim 8, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first side of the first standard cell; the second power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first standard cell on the second side; the first standard cell is formed in a region in the first active region where the region that serves as the source of the first transistor and the first power supply wiring overlap, and the semiconductor integrated circuit device further comprises a third via that connects the source of the first transistor in the first active region and the first power supply wiring.

13. A semiconductor integrated circuit device according to claim 8, wherein a second cell row, which is one of the plurality of cell rows, comprises a third standard cell having a logic function and the second standard cell arranged on at least one of both ends of the second cell row, the third standard cell comprising: a fifth active region formed in the same layer as the first active region in the depth direction, constituting the channel, source, and drain of the third transistor of the first conductivity type, the channel including a fifth nanosheet extending in the first direction; a sixth active region formed in the same layer as the second active region in the depth direction, constituting the channel, source, and drain of the fourth transistor of the second conductivity type, the channel including a sixth nanosheet extending in the first direction; a second gate wiring extending in the second direction and surrounding the outer periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and a third power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring. a fourth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring; the third power supply wiring connected to a source of the third transistor in the fifth active region; the fourth power supply wiring connected to a source of the fourth transistor in the sixth active region; the fifth and sixth nanosheets have their first side surfaces exposed from the second gate wiring; and in a planar view, the width of the fifth active region in the second direction is smaller than the width of the first active region in the second direction.

14. A semiconductor device comprising a plurality of standard cells arranged side by side in a first direction, and a plurality of cell rows arranged side by side in a second direction perpendicular to the first direction, wherein the plurality of cell rows include a first cell row including first and third standard cells having a logic function, and a second cell row arranged at either end of the plurality of cell rows in the second direction and including second standard cells having no logic function, wherein the first standard cells each include: a first active region constituting a channel, source, and drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in the first direction; a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, the second active region constituting a channel, source, and drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction; a first gate wiring extending in the second direction and surrounding the outer periphery of the first and second nanosheets in the second direction and the depth direction; the second power supply wiring is connected to the source of the second transistor in the second active region; and the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, source, and drain of a first dummy transistor of the first conductivity type, the third active region including a third nanosheet extending in the first direction as the channel; and a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, source, and drain of a second dummy transistor of the second conductivity type, the fourth nanosheet extending in the first direction as the channel.a dummy gate wiring extending in the second direction and surrounding the periphery of the third and fourth nanosheets in the second direction and the depth direction, wherein the third standard cell comprises: a fifth active region formed in the same layer as the first active region in the depth direction and constituting the channel, source, and drain of the third transistor of the first conductivity type, the fifth active region including a fifth nanosheet extending in the first direction as the channel; a sixth active region formed in the same layer as the second active region in the depth direction and constituting the channel, source, and drain of the fourth transistor of the second conductivity type, the sixth active region including a sixth nanosheet extending in the first direction as the channel; a second gate wiring extending in the second direction and surrounding the periphery of the fifth and sixth nanosheets in the second direction and the depth direction; and a third power supply wiring formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring. a fourth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring; the third power supply wiring is connected to a source of the third transistor in the fifth active region; the fourth power supply wiring is connected to a source of the fourth transistor in the sixth active region; a first side surface of each of the first and second nanosheets, which is one side in the second direction, is exposed from the first gate wiring; a second side surface of each of the third and fourth nanosheets, which is the other side in the second direction, is exposed from the dummy gate wiring; and a first side surface of each of the fifth and sixth nanosheets, which is exposed from the second gate wiring; and in a plan view, a width of the first active region in the second direction is the same as a width of the third active region in the second direction and is larger than a width of the fifth active region in the second direction.

15. A semiconductor integrated circuit device according to claim 14, wherein the first power supply wiring is formed on the back side of the first transistor and is located in the center of the first standard cell in the second direction; the second power supply wiring is formed higher than the second transistor in the depth direction and is located in the center of the first standard cell in the second direction; the first standard cell is formed in a region in the first active region where a region that serves as the source of the first transistor and the first power supply wiring overlap, and the device further comprises a first via that connects the source of the first transistor in the first active region and the first power supply wiring.

16. A semiconductor integrated circuit device according to claim 14, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first side of the first standard cell; the second power supply wiring is formed higher than the second transistor in the depth direction and is arranged at the end of the first side of the first standard cell; the first standard cell is formed in a region in the first active region where the region that serves as the source of the first transistor and the first power supply wiring overlap, and the device further comprises a second via that connects the source of the first transistor in the first active region and the first power supply wiring.

17. A semiconductor integrated circuit device according to claim 14, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first standard cell on the second side, and the second power supply wiring is formed above the second transistor in the depth direction and is arranged at the end of the first standard cell on the second side.

18. A semiconductor integrated circuit device according to claim 14, wherein the first power supply wiring is formed on the back side of the first transistor and is arranged at the end of the first side of the first standard cell; the second power supply wiring is formed on the back side of the first transistor and is arranged at the end of the second side of the first standard cell; the first standard cell is formed in a region in the first active region where the region that serves as the source of the first transistor and the first power supply wiring overlap, and the semiconductor integrated circuit device further comprises a third via that connects the source of the first transistor in the first active region and the first power supply wiring.

19. A semiconductor integrated circuit device according to claim 14, wherein the width of the second standard cell in the second direction is half the width of the first standard cell in the second direction.

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