Electronic device

Abstract

This electronic device comprises: a substrate in which a display region and a non-display region are defined; a plurality of pixels which are arranged on the substrate and each of which includes a transistor and a light-emitting element connected to the transistor; an encapsulation layer that covers the pixels and has an end defined in the non-display region; a crack sensing circuit that is disposed, in the non-display region, along at least a portion of an edge of the display region, and includes a first end and a second end; and a static electricity prevention circuit that is disposed in the non-display region and connected to the crack sensing circuit, wherein the static electricity prevention circuit is spaced apart from the end of the encapsulation layer in a plan view.

Description

electronic devices

[0001] The present invention relates to an electronic device for displaying an image.

[0002] Electronic devices that typically provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates images and presents them to the user through a display screen.

[0003] An electronic device for displaying an image includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0004] The purpose of the present invention is to provide an electronic device with improved reliability.

[0005] An electronic device according to one embodiment of the present invention includes a substrate having a display area and a non-display area adjacent to the display area defined therein, a plurality of pixels disposed on the substrate, each pixel including a transistor and a light-emitting element connected to the transistor, an encapsulation layer covering the pixels and having an end defined in the non-display area, a crack detection circuit disposed along at least a portion of an edge of the display area in the non-display area and including one end and the other end, and an anti-static circuit disposed in the non-display area and connected to the crack detection circuit, wherein the anti-static circuit is spaced apart from the end of the encapsulation layer in a plane.

[0006] The crack detection circuit includes a crack detection line extending along at least three sides of the display area and including one end and the other end, a first pad connected to the one end of the crack detection line, and a second pad connected to the other end of the crack detection line, and the anti-static circuit can be disposed adjacent to the first pad or the second pad.

[0007] The above-described anti-static circuit may include a first anti-static circuit connected to a portion of the crack detection line adjacent to the first pad and a second anti-static circuit connected to a portion adjacent to the first pad.

[0008] An electronic device according to one embodiment of the present invention further includes a data driver disposed in the non-display area and connected to the pixels, and the one end and the other end of the crack detection line may be disposed spaced apart from each other with the data driver interposed therebetween.

[0009] An electronic device according to one embodiment of the present invention further includes a data driving unit disposed in the non-display area and connected to the pixels, and the one end and the other end of the crack detection line may be disposed on the same side with respect to the data driving unit.

[0010] The above-mentioned anti-static circuit may not overlap with the sealing layer on a plane.

[0011] The above-mentioned anti-static circuit can overlap the first pad or the second pad when viewed from one direction.

[0012] The above-mentioned anti-static circuit can overlap the above-mentioned sealing layer on a plane.

[0013] The above-mentioned anti-static circuit may be placed between the crack detection line and the display area.

[0014] The above crack detection line includes at least one bend, and the bend may be concave or convex toward the display area.

[0015] An electronic device according to one embodiment of the present invention further includes an alignment mark arranged in the non-display area, and the curved portion may be concave with respect to the alignment mark.

[0016] The crack detection line includes a first line extending along one direction, and a second line extending along the one direction and disposed on the same layer as the first line and overlapping in a plane at least in a portion of the area, wherein the first line and the second line can be in contact at least in the portion of the area.

[0017] Each of the first line and the second line includes at least one bend, and the first line and the second line can overlap in the entire area.

[0018] The encapsulating layer may include at least one inorganic film and at least one organic film, and the end of the encapsulating layer may be defined by the inorganic film.

[0019] The encapsulating layer comprises a plurality of inorganic membranes, and the ends of the encapsulating layer may be aligned ends of at least two inorganic membranes.

[0020] An electronic device according to one embodiment of the present invention includes a substrate having a display area and a non-display area adjacent to the display area defined therein, a plurality of pixels disposed on the substrate, each pixel including a transistor and a light-emitting element connected to the transistor, an encapsulation layer covering the pixels and having an end defined in the non-display area, a crack detection line disposed along at least a portion of an edge of the display area in the non-display area and including one end and the other end, and an anti-static circuit disposed in the non-display area and connected to the one end or the other end of the crack detection line, wherein the anti-static circuit does not overlap the end of the encapsulation layer in a plane.

[0021] The sealing layer includes a first inorganic film, a second inorganic film, and an organic film disposed between the first inorganic film and the second inorganic film, and the ends of the sealing layer may be aligned ends of the first inorganic film and the second inorganic film.

[0022] The above-mentioned anti-static circuit can overlap the first inorganic film and the second inorganic film on a plane.

[0023] The above-mentioned anti-static circuit can be non-overlapping on a plane with the first inorganic film and the second inorganic film.

[0024] The crack detection circuit may include at least one bend, wherein the bend may have a concave or convex shape toward the display area.

[0025] According to the present invention, it is possible to reliably measure whether a crack occurs due to an external impact.

[0026] In addition, according to the present invention, the problem of the circuit for measuring whether a crack has occurred being damaged by static electricity or the like can be prevented.

[0027] FIG. 1 is a perspective view of an electronic device according to an embodiment of the present invention.

[0028] FIG. 2 is a drawing illustrating an example of a cross-section of the electronic device illustrated in FIG. 1.

[0029] FIG. 3 is a drawing illustrating an example of a cross-section of the display panel illustrated in FIG. 2.

[0030] Figure 4 is a block diagram of the electronic device illustrated in Figure 1.

[0031] FIG. 5 is a drawing illustrating a cross-section of a display panel corresponding to a portion of a pixel area illustrated in FIG. 4.

[0032] Figure 6 is a plan view of the display panel illustrated in Figure 1.

[0033] FIG. 7 is a drawing showing some configurations of the display panel illustrated in FIG. 6.

[0034] Figure 8 is a drawing showing an enlarged portion of a portion of Figure 7.

[0035] Figures 9a to 9c are cross-sectional views schematically illustrating an area cut along line I-I' of Figure 8a.

[0036] Figure 10a is a circuit diagram of an anti-static circuit according to one embodiment of the present invention.

[0037] FIG. 10b is a diagram illustrating a layout of an anti-static circuit according to one embodiment of the present invention.

[0038] FIGS. 11A to 11C are plan views illustrating a portion of a crack detection line according to one embodiment of the present invention.

[0039] Figure 12a is a cross-sectional view schematically illustrating the crack detection line illustrated in Figure 11b.

[0040] Figure 12b is a cross-sectional view schematically illustrating the crack detection line illustrated in Figure 11c.

[0041] FIG. 13a is a plan view of a display panel according to one embodiment of the present invention.

[0042] Figure 13b is a drawing showing an enlarged portion of a portion of Figure 13a.

[0043] Figure 14 is a plan view of a display panel according to one embodiment of the present invention.

[0044] Fig. 15a is a plan view of a crack detection line according to a comparative example.

[0045] FIG. 15b is a plan view of a crack detection line according to one embodiment of the present invention.

[0046] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0047] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content.

[0048] “And / or” includes any combination of one or more of the associated constructs that can be defined.

[0049] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0050] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and may be explicitly defined herein, unless interpreted in an idealized or overly formal sense.

[0052] Terms such as "include" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0053] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0054] FIG. 1 is a perspective view of an electronic device according to an embodiment of the present invention. As illustrated in FIG. 1, the electronic device (DD) may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1).

[0055] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0056] The front surface of the electronic device (DD) may be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) may be provided to a user through the display surface (DS).

[0057] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may be an area where an image is displayed, and the non-display area (NDA) may be an area where an image is not displayed. The non-display area (NDA) may be adjacent to at least one side of the display area (DA). In the present embodiment, the non-display area (NDA) may have a frame shape surrounding the display area (DA).

[0058] An electronic device (DD) can detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) can detect a first input by a touch pen (PEN) and a second input by a touch (TC). In this case, the touch pen (PEN) can be defined as an input device, and the display area (DA) can provide the user with a detection area capable of detecting inputs in addition to displaying an image.

[0059] The touch pen (PEN) may be an active pen or an electromagnetic pen. The second input by the touch (TC) may include various forms of external input, such as a part of the user's body, light, heat, or pressure. The touch pen (PEN) includes an active pen, a passive pen, an electromagnetic pen, and the like, and is not limited to any one embodiment.

[0060] The electronic device (DD) may be a large electronic device, such as a television, monitor, or outdoor billboard. Furthermore, the electronic device (DD) may be a small or medium-sized electronic device, such as a personal computer, laptop computer, personal digital assistant, car navigation system, game console, smartphone, tablet, or camera. However, this is merely an example, and the electronic device (DD) according to an embodiment of the present invention may be utilized in various forms and is not limited to any one embodiment.

[0061]

[0062] FIG. 2 is an exemplary cross-sectional view of the electronic device illustrated in FIG. 1. FIG. 3 is an exemplary cross-sectional view of the display panel illustrated in FIG. 2. The present invention will be described with reference to FIGS. 2 and 3.

[0063] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensing portion (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2).

[0064] A display panel (DP) according to an embodiment of the present invention may be an emissive display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel (DP) will be described as an organic light-emitting display panel by way of example.

[0065] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0066] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A display element layer (DP-OLED) may be disposed on the display area (DA).

[0067] A plurality of pixels may be arranged on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor arranged on the circuit element layer (DP-CL) and a light-emitting element arranged on the display element layer (DP-OLED) and connected to the transistor.

[0068] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) may protect pixels from moisture, oxygen, and external foreign substances. Meanwhile, in the present embodiment, the thin film encapsulation layer (TFE) is illustrated as covering the entire area of ​​the substrate (SUB), but according to an embodiment of the present invention, the substrate (SUB) may include a portion exposed from the thin film encapsulation layer (TFE). Alternatively, the area exposed from the thin film encapsulation layer (TFE) may be formed along the edge of the substrate (SUB), and is not limited to any one embodiment.

[0069] An input sensing unit (ISP) may be arranged on a display panel (DP). The input sensing unit (ISP) may include a plurality of sensing units (not shown) for sensing an external input in a capacitive manner. The input sensing unit (ISP) may be formed directly on the display panel (DP) during the manufacturing of the electronic device (DD). Specifically, a conductive pattern or an insulating layer constituting the input sensing unit (ISP) may be directly deposited or patterned on the display panel (DP). However, the present invention is not limited thereto, and the input sensing unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) via an adhesive layer, and is not limited to any one embodiment.

[0070] An anti-reflection layer (RPL) may be disposed on an input sensing unit (ISP). The anti-reflection layer (RPL) may reduce external light reflectance of the electronic device (DD) to improve the visibility of an image displayed on the electronic device (DD). The anti-reflection layer (RPL) may include a phase retarder, a polarizer, a black matrix, a color filter, and the like, and is not limited to any one embodiment. The anti-reflection layer (RPL) may be directly formed on the input sensing unit (ISP) through a coating or deposition process, or may be provided in a film form and attached to the input sensing unit (ISP) through an adhesive layer, and is not limited to any one embodiment.

[0071] The window (WIN) can be placed on an anti-reflection layer (RPL). The window (WIN) can protect the display panel (DP), the input sensor (ISP), and the anti-reflection layer (RPL) from external scratches and impacts.

[0072] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may support the display panel (DP) and protect the lower portion of the display panel (DP). The panel protection film (PPF) may have insulating properties. For example, the panel protection film (PPF) may include, but is not limited to, a plastic such as polyethylene terephthalate (PET), polyimide (PI), or polypropylene (PP).

[0073] A first adhesive layer (AL1) is disposed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded to each other by the first adhesive layer (AL1). A second adhesive layer (AL2) is disposed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded to each other by the second adhesive layer (AL2).

[0074]

[0075] Fig. 4 is a block diagram of the electronic device illustrated in Fig. 1. Referring to Fig. 4, the electronic device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG).

[0076] The display panel (DP) may include a plurality of scanning lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), a plurality of light emitting lines (EML1 to EMLm), a plurality of data lines (DL1 to DLn), and a plurality of pixels (PX). m and n are natural numbers greater than 1.

[0077] The pixels (PX) can be electrically connected to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), emission lines (EML1 to EMLm), and data lines (DL1 to DLn), respectively. Each of the pixels (PX) can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission line.

[0078] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) may include a plurality of initialization scan lines (GIL1 to GILm), a plurality of compensation scan lines (GCL1 to GCLm), a plurality of write scan lines (GWL1 to GWLm), and a plurality of bias scan lines (GBL1 to GBLm).

[0079] Each of the pixels (PX) can be connected to a corresponding one of the initialization scan lines (GIL1 to GILm), a corresponding one of the compensation scan lines (GCL1 to GCLm), a corresponding one of the write scan lines (GWL1 to GWLm), and a corresponding one of the bias scan lines (GBL1 to GBLm).

[0080] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) are connected to the scan driver (SDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The light emitting lines (EML1 to EMLm) are connected to the light emitting driver (EDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The data lines (DL1 to DLn) are connected to the data driver (DDV), extend in a second direction (DR2), and can be arranged in the first direction (DR1).

[0081] The scanning driver (SDV), the emission driver (EDV), and the data driver (DDV) can be substantially arranged on the display panel (DP), and this configuration will be illustrated in FIG. 6 below.

[0082] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to meet the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0083] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0084] The scan driver (SDV) can receive a scan control signal (SCS) from a timing controller (TC). The scan driver (SDV) can output scan signals to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm).

[0085] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from a timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to the pixels (PX) through data lines (DL1 to DLn).

[0086] The emission driver (EDV) can receive an emission control signal (ECS) from a timing controller (TC). The emission driver (EDV) can output emission signals to the emission lines (EML1 to EMLm) in response to the emission control signal (ECS). The emission signals can be applied to the pixels (PX) through the emission lines (EML1 to EMLm).

[0087] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission signals.

[0088] Each pixel (PX) may include a light-emitting element and a pixel circuit for driving the light-emitting element. The light-emitting element may be an organic light-emitting element, but in one embodiment of the present invention, the light-emitting element may be an inorganic light-emitting element and is not limited to any one embodiment.

[0089] The pixel circuit may include a transistor and a capacitor. The transistors may be provided in multiple numbers. The plurality of transistors and capacitors can control the amount of current flowing to the light-emitting element, and the light-emitting element can generate light having a predetermined brightness depending on the amount of current provided.

[0090]

[0091] FIG. 5 is a drawing exemplarily showing a cross-section of a display panel corresponding to a portion of a pixel illustrated in FIG. 4. In this embodiment, an area in which three transistors (TR1, TR2, TR3) and a light-emitting element (OLED) are arranged among the components of a pixel (PXij) is shown. According to FIG. 5, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL), a display element layer (DP-OLED), and an encapsulation layer (TFE).

[0092] The substrate (SUB) may include a glass substrate, a sapphire substrate, a plastic film, or an organic / inorganic laminated film. The substrate (SUB) may have a multilayer or single-layer structure. For example, the substrate (SUB) may have a laminated structure of a plurality of plastic films bonded with an adhesive, or may have a laminated structure of a glass substrate and a plastic film bonded with an adhesive. The substrate (SUB) may have flexibility. For example, the substrate (SUB) may include polyimide (PI). However, this is described as an example, and the substrate (SUB) may be provided in a rigid state and is not limited to any one embodiment.

[0093] A circuit element layer (DP-CL) is disposed on a substrate (SUB). The circuit element layer (DP-CL) may include a driving element and a plurality of insulating layers. The three transistors (TR1, TR2, TR3) described above may be elements constituting the circuit element layer (DP-CL). The insulating layers may include a secondary layer (BFL) and first to seventh insulating layers (INS1 to INS7) sequentially stacked on the substrate (SUB), but this is merely an example and the number of insulating layers constituting the circuit element layer (DP-CL) may vary and is not limited to any one embodiment.

[0094] Three transistors (TR1, TR2, TR3) are arranged on a substrate (SUB). The three transistors (TR1, TR2, TR3) include a first transistor (TR1), a second transistor (TR2), and a third transistor (TR3). In the present embodiment, a lower metal layer (BML) and a secondary layer (BFL) may be further arranged between the three transistors (TR1, TR2, TR3) and the substrate (SUB).

[0095] The lower blocking layer (BML) can block light incident on the first transistor (TR1) from below the lower blocking layer (BML). The lower blocking layer (BML) can be a light-shielding pattern and can include a black matrix or a reflective conductive material. When the lower blocking layer (BML) includes a conductive material, the lower blocking layer (BML) can be electrically floated or connected to the first transistor (TR1). For example, the lower blocking layer (BML) can be connected to any one of a source, a gate, and a drain of the first transistor (TR1). Meanwhile, this is merely an example, and in the display panel according to an embodiment of the present invention, the lower blocking layer (BML) can be omitted and is not limited to any one embodiment.

[0096] A secondary layer (BFL) is disposed on a substrate (SUB) and covers a lower barrier layer (BML). The secondary layer (BFL) can completely cover the substrate (SUB). The secondary layer (BFL) can include a barrier layer and / or a buffer layer. Accordingly, the secondary layer (BFL) can prevent oxygen or moisture flowing through the substrate (SUB) from penetrating into the pixel (PXij) or reduce the surface energy of the substrate (SUB) so that the pixel (PXij) is stably formed on the substrate (SUB). Meanwhile, at least one of the barrier layer and the buffer layer may be provided in multiple forms or may be omitted. In addition, in the display panel according to an embodiment of the present invention, the secondary layer (BFL) may be omitted and is not limited to any one embodiment.

[0097] A first transistor (TR1) may include a semiconductor pattern and a first gate (G1). The first transistor (TR1) may be a driving transistor that is arranged on a current path between the first power line described above and the light-emitting element (OLED) to control the amount of current flowing to the light-emitting element (OLED), but is not limited thereto. The first power line may be any one of a plurality of power lines connected to a voltage generator (VG). For example, the first power line may be a line that transmits a first driving voltage (ELVDD). The semiconductor pattern includes a first source (S1), a first drain (D1), and a first channel (A1).

[0098] In this embodiment, the semiconductor pattern of the first transistor (TR1) may include silicon. Specifically, the semiconductor pattern of the first transistor (TR1) may be polycrystalline silicon. However, this is merely an example, and the semiconductor pattern of the first transistor (TR1) may include amorphous silicon or an oxide semiconductor, and is not limited to any one embodiment.

[0099] The first source (S1) and the first drain (D1) may be highly doped regions having a relatively high dopant concentration compared to the first channel (A1). The conductivity of the highly doped region is greater than the conductivity of the first panel (A1), which is a low doped region, and thus may function as source / drain electrodes. That is, the source and drain of the first transistor (TR1) may be formed on a semiconductor pattern. However, this is merely an example, and the source / drain of the first transistor (TR1) may be provided as a separate conductive pattern connected to the semiconductor pattern and is not limited to any one embodiment.

[0100] A first gate (G1) may be disposed on a semiconductor pattern of a first transistor (TR1). The first gate (G1) may overlap a first channel (A1). A first insulating layer (INS1) may be disposed between the first gate (G1) and the semiconductor pattern. The first insulating layer (INS1) may be a gate insulating layer, and the first transistor (TR1) is illustrated as having a top-gate structure. However, this is merely an example, and the first transistor (TR1) may also have a bottom-gate structure and is not limited to any one embodiment.

[0101] Meanwhile, an upper electrode (DME) may be placed on the first transistor (TR1). The upper electrode (DME) is placed to overlap the first gate (G1) with a second insulating layer (INS2) therebetween. The second insulating layer (INS2) is placed on the first insulating layer (INS1) to cover the first transistor (TR1).

[0102] The portion where the upper electrode (DME) and the first gate (G1) overlap on a plane can function as a capacitor constituting a pixel circuit. According to the present invention, by forming the capacitor together with the first gate (G1) of the first transistor (TR1), a high-resolution pixel circuit can be designed while securing the area of ​​the capacitor. However, this is merely an example, and the upper electrode (DME) may be omitted or the capacitor may be formed in a different location, and the present invention is not limited to any one embodiment.

[0103] The second transistor (TR2) may include a second gate (G2) and a semiconductor pattern. The second transistor (TR2) may be an initialization transistor that is turned on through a corresponding initialization scan line among the aforementioned initialization scan lines (GIL1 to GILm) and provides a first initialization voltage (VINT) transmitted through the first initialization line to the pixel circuit, but is not limited thereto.

[0104] The semiconductor pattern of the second transistor (TR2) may be arranged on a different layer from the semiconductor pattern of the first transistor (TR1). In the present embodiment, the semiconductor pattern of the second transistor (TR2) is arranged on the third insulating layer (INS3). The third insulating layer (INS3) is arranged on the second insulating layer (INS2) to cover the upper electrode (DME). The semiconductor pattern of the second transistor (TR2) may include a metal oxide semiconductor. The metal oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0105] The semiconductor pattern of the second transistor (TR2) may include a plurality of regions that are distinguished depending on whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as a reduced region) may have greater conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as a non-reduced region). The reduced region may substantially function as a source electrode or a drain electrode of the second transistor (TR2). The non-reduced region may substantially correspond to the active (or channel) of the second transistor (TR2). That is, the source and drain of the second transistor (TR2) may be formed on the semiconductor pattern. However, this is merely an example, and the source / drain of the second transistor (TR2) may be provided as a separate conductive pattern connected to the semiconductor pattern and is not limited to any one embodiment.

[0106] The second gate (G2) may be disposed on the semiconductor pattern of the second transistor (TR2). The second gate (G2) may overlap the second channel (A2). When the second transistor (TR2) is an initialization transistor, the second gate (G2) may be connected to a corresponding initialization scan line among the aforementioned initialization scan lines (GIL1 to GILm). A fourth insulating layer (INS4) may be disposed between the second gate (G2) and the semiconductor pattern. A fifth insulating layer (INS5) is disposed on the fourth insulating layer (INS4) to cover the second transistor (TR2). The fourth insulating layer (INS4) may be a gate insulating layer, and the second transistor (TR2) is illustrated as having a top-gate structure. However, this is merely an example, and the second transistor (TR2) may have a bottom-gate structure and is not limited to any one embodiment.

[0107] The third transistor (TR3) may include a third gate (G3) and a semiconductor pattern. The third transistor (TR3) may be a light-emitting control transistor that is arranged on a current path between the first transistor (TR1) and the light-emitting element (OLED) and provides a driving current transmitted by the first transistor (TR1) to the light-emitting element (OLED) in response to a signal transmitted through a corresponding light-emitting line among the above-described light-emitting lines (EML1 to EMLm), but is not limited thereto.

[0108] The third transistor (TR3) may be provided with the same structure as the first transistor (TR1). Specifically, the third transistor (TR3) may have a top-gate structure, include a semiconductor pattern disposed on the same layer as the first transistor (TR1), and include a third source (S3), a second drain (D3), and a third channel (A3) formed on the semiconductor pattern. The semiconductor pattern of the first transistor (TR1) and the semiconductor pattern (TR3) of the third transistor may include the same material and be patterned simultaneously. However, this is merely an example, and the semiconductor pattern (TR3) of the third transistor may include a different material from the semiconductor pattern of the first transistor (TR1) and is not limited to any one embodiment.

[0109] In the present embodiment, the auxiliary layer (BFL) and the first to fifth insulating layers (INS1 to INS5) may each include an inorganic layer. For example, the auxiliary layer (BFL), the first insulating layer (INS1), and the fourth insulating layer (INS4) may include a silicon oxide layer, and the second insulating layer (INS2) may include a silicon nitride layer.

[0110] Meanwhile, each of the third and fifth insulating layers (INS3, INS5) may include a plurality of inorganic insulating layers including different materials and stacked on each other. For example, the third insulating layer (INS3) may include a silicon nitride layer and a silicon oxide layer stacked sequentially, and the fifth insulating layer (INS5) may include a silicon oxide layer and a silicon nitride layer stacked sequentially. The thickness of each of the third and fifth insulating layers (INS3, INS5) may be greater than the thickness of each of the auxiliary layer (BFL) and the first, second, and fourth insulating layers (INS1, INS2, INS4). However, this is merely an example, and the material or stacking form of each of the auxiliary layer (BFL) and the first to fifth insulating layers (INS1 to INS5) may be variously changed and is not limited to any one embodiment.

[0111] The third transistor (TR3) can be connected to the light-emitting element (OLED) via a connection electrode (CNE). The connection electrode (CNE) can include a first connection electrode (CNE1) and a second connection electrode (CNE2).

[0112] A first connection electrode (CNE1) may be disposed on a fifth insulating layer (INS5) and connected to a third drain region (D3) through a first contact hole (CH1) defined in the first to fifth insulating layers (INS1 to INS5). A sixth insulating layer (INS6) may be disposed on the fifth insulating layer (INS5) to cover the first connection electrode (CNE1).

[0113] The second connection electrode (CNE2) may be disposed on the sixth insulating layer (INS6). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a second contact hole (CH2) defined in the sixth insulating layer (INS6). A seventh insulating layer (INS7) may be disposed on the sixth insulating layer (INS6) to cover the second connection electrode (CNE2). The sixth and seventh insulating layers (INS6, INS7) may include an inorganic layer or an organic layer.

[0114] A first electrode (AE) may be disposed on the seventh insulating layer (INS7). The first electrode (AE) may be electrically connected to the second connection electrode (CNE2) through a third contact hole (CH3) defined in the seventh insulating layer (INS7). Meanwhile, this is merely an example, and the connection electrode (CNE) may be provided as a single connection electrode or as three or more connection electrodes, as long as it can connect the third transistor (TR3) and the light-emitting element (OLED), and is not limited to any one embodiment.

[0115] A display element layer (DP-OLED) may be disposed on a circuit element layer (DP-CL). The display element layer (DP-OLED) may include a light-emitting element (OLED) and a pixel defining layer (PDL). The light-emitting element (OLED) may include a first electrode (AE), a hole control layer (HCL), an emission layer (EML), an electron control layer (ECL), and a second electrode (CE).

[0116] A pixel defining layer (PDL) exposing a predetermined portion of the first electrode (AE) may be disposed on the first electrode (AE) and the seventh insulating layer (INS7). An opening (PX_OP) for exposing a predetermined portion of the first electrode (AE) may be defined in the pixel defining layer (PDL).

[0117] A hole control layer (HCL) may be disposed on a first electrode (AE) and a pixel defining layer (PDL). The hole control layer (HCL) may be disposed commonly in an emission area (LEA) and a non-emission area (NLEA). The hole control layer (HCL) may include a layer having high hole mobility to facilitate movement of holes from the first electrode (AE) to the emission layer (EML). For example, the hole control layer (HCL) may include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0118] The emission layer (EML) may be disposed on the hole control layer (HCL). The emission layer (EML) may be disposed in an area corresponding to the opening (PX_OP). The emission layer (EML) may include an organic material and / or an inorganic material. The emission layer (EML) may generate light of any one of red, green, and blue.

[0119] An electron control layer (ECL) may be disposed on the light emitting layer (EML) and the hole control layer (HCL). The electron control layer (ECL) may be disposed commonly in the light emitting area (LEA) and the non-light emitting area (NLEA). The electron control layer (ECL) may include a layer having high electron mobility to facilitate the movement of electrons from the second electrode (CE) to the light emitting layer (EML). For example, the electron control layer (ECL) may include at least one of an electron transport layer, an electron injection layer, and a hole blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0120] The second electrode (CE) may be disposed on the electronic control layer (ECL). The second electrode (CE) may be commonly disposed on the pixels (PX). That is, the second electrode (CE) may be formed in an integral shape on the light-emitting layers (EML) of the pixels (PX). However, this is merely an example, and the second electrode (CE) may be provided in a separate pattern for each pixel (PX) and is not limited to any one embodiment. The second electrode (CE) may be semi-transparent or transparent. The second electrode (CE) may be provided in various forms, such as a transparent conductive oxide layer, a thin-film metal layer having transparency, or a layer having a stacked structure of a metal layer / oxide layer. Meanwhile, when the light-emitting element (OLED) has a bottom-emitting structure, the second electrode (CE) may be a reflective electrode.

[0121] An encapsulation layer (TFE) may be disposed on the display element layer (DD-OLED). The encapsulation layer (TFE) may include an inorganic layer and an organic layer. In the present embodiment, the first inorganic layer (IL1), the organic layer (OL), and the second inorganic layer (IL2) are sequentially laminated, but the laminated structure of the layers constituting the encapsulation layer (TFE) may be varied.

[0122] The first inorganic layer (IL1) and the second inorganic layer (IL2) contain inorganic materials and can protect pixels from moisture / oxygen. The first inorganic layer (IL1) and the second inorganic layer (IL2) may contain the same material or different materials. The organic layer (OL) contains organic materials and can protect the light-emitting element layer (DD-OLED) or the circuit element layer (DP-CL) from foreign substances.

[0123]

[0124] Fig. 6 is a plan view of the display panel illustrated in Fig. 1. Referring to Fig. 6, the electronic device (DD) may include a display panel (DP), a scan driver (SDV), a plurality of data drivers (DDV), an emission driver (EDV), and a plurality of pads (PD).

[0125] In the present embodiment, the display area (DA) may have a rectangular shape with corners of a curved shape. For example, the display area (DA) may include rectangular sides extending in the first direction (DR1) and the second direction (DR2) and rounded corners connecting the sides. In the present embodiment, the border of the display area (DA) may include long sides (SI1, SI2) extending in the first direction (DR1), short sides (S3, S4) extending in the second direction (DR2), and corner parts (CR1, CR2, CR3, CR4) connected thereto. However, this is merely an example, and the display area (DA) may have a rectangular shape with angled corners different from the shape of the electronic device (DD), and is not limited to any one embodiment.

[0126] A display panel (DP) may include a plurality of pixels (PX), a plurality of scan lines (SL1 to SLm), a plurality of data lines (DL1 to DLn), and a plurality of emission lines (EML1 to EMLm). The pixels (PX) may be arranged within a display area (DA). The pixels (PX) may be connected to the scan lines (SL1 to SLm), the data lines (DL1 to DLn), and the emission lines (EML1 to EMLm).

[0127] The scan lines (SL1 to SLm) may include the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) illustrated in FIG. 4. For example, the ith scan line among the scan lines (SL1 to SLm) may include the ith write scan line among the aforementioned write scan lines (GWL1 to GWLm), the ith compensation scan line among the compensation scan lines (GCL1 to GCLm), the ith initialization scan line among the initialization scan lines (GIL1 to GILm), and the ith bias scan line among the bias scan lines (GBL1 to GBLm). Accordingly, the aforementioned scan signals may be applied to the pixels (PX) through the scan lines (SL1 to SLm). The data lines (DL1 to DLn) and the light emitting lines (EML1 to EMLm) may be the same as the data lines (DL1 to DLn) and the light emitting lines (EML1 to EMLm) illustrated in FIG. 4.

[0128] The scanning driver (SDV) and the emission driver (EDV) may be arranged in adjacent non-display areas (NDAs) on opposite sides of the display panel (DP) in the first direction (DR1). Each of the scanning driver (SDV) and the emission driver (EDV) is illustrated as having a curved upper and lower side corresponding to the shape of the curved corners (CR1 to CR4) of the display area (DA), but the shape of each of the scanning driver (SDV) and the emission driver (EDV) is not limited thereto.

[0129] A plurality of data drivers (DDVs) may be provided on the display panel (DP). The data drivers (DDVs) may be arranged in a non-display area (NDA) adjacent to one of the two sides of the display panel (DP) that are opposite to each other in the second direction (DR2). When viewed in a plan view, the data drivers (DDVs) may be adjacent to the bottom of the display panel (DP). However, this is merely an example, and the data drivers (DDVs) may be provided singly, or may be provided on a separate circuit board and bonded to the display panel (DP) to thereby be connected to the pixels (PX), and the present invention is not limited to any one embodiment.

[0130] The scan lines (SL1 to SLm) may extend in a first direction (DR1) and be connected to the pixels (PX) and the scan driver (SDV). The data lines (DL1 to DLn) may extend in a second direction (DR2) and be connected to the pixels (PX) and the data driver (DDV). The emission lines (EML1 to EMLm) may extend in the first direction (DR1) and be connected to the pixels (PX) and the emission driver (EDV).

[0131] The data driving units (DDV) may be spaced apart from each other in the first direction (DR1). A predetermined number of data lines may be connected to each of the data driving units (DDV). By way of example, two data driving units (DDV) are illustrated, but the number of data driving units (DDV) is not limited thereto. For example, as the left and right areas of the display panel (DP) increase, the number of data driving units (DDV) may also increase.

[0132] The pads (PD) are arranged in a non-display area (NDA) adjacent to the bottom of the display panel (DP) and may be closer to the bottom of the display panel (DP) than the data drivers (DDV). The data drivers (DDV) may be connected to the pads (PD). The data lines (DL1 to DLn) may be connected to the data drivers (DDV), and the data drivers (DDV) may be connected to the pads (PD) corresponding to the data lines (DL1 to DLn).

[0133] Meanwhile, although not shown, the timing controller (TC) and voltage generator (VG) shown in FIG. 4 may be mounted on a printed circuit board and connected to pads (PD) through the printed circuit board.

[0134] As illustrated in FIG. 6, a display panel (DP) according to one embodiment of the present invention may include a crack detection circuit (PCD) and an electrostatic discharge prevention circuit (ESCa, ESCb). The crack detection circuit (PCD) and the electrostatic discharge prevention circuit (ESCa, ESCb) are arranged in a non-display area (NDA).

[0135] A crack detection circuit (PCD) may include a crack detection line (CDL), a first pad (CDPa), and a second pad (CDPb). The crack detection line (CDL) may be a conductive line having an integral shape. That is, the crack detection line (CDL) has one end and one end. The first pad (CDPa) and the second pad (CDPb) may be connected to both ends of the crack detection line (CDL), respectively.

[0136] When a crack occurs in a display panel (DP), a crack detection line (CDL) positioned in the corresponding area may be short-circuited or damaged, and the resistance of the crack detection line (CDL) may increase. By measuring the voltage or current between a first pad (CDPa) and a second pad (CDPb), it is possible to check whether the resistance of the crack detection line (CDL) increases. The crack detection line (CDL) extends along the shape of the edge of the display panel (DP). Therefore, the crack detection line (CDL) and the crack detection circuit (PCD) can detect whether a crack occurs in the edge of the display panel (DP) due to external impact, etc.

[0137] Cracks occurring at the edge of a display panel (DP) can cause defects in pixels (PX) of a display area (DA) by providing a path for moisture or foreign matter to penetrate. Furthermore, even if the crack is small enough to not cause immediate damage to the display area (DA), it can grow into the display area (DA) later, thereby reducing the reliability of the display panel (DP). The display panel (DP) according to the present invention includes a crack detection circuit (PCD), thereby enabling inspection and management of damage such as cracks at the edge of the display panel (DP).

[0138] The electrostatic discharge prevention circuit (ESCa, ESCb) is connected to the crack detection circuit (PCD). The electrostatic discharge prevention circuit (ESCa, ESCb) prevents the crack detection circuit (PCD) from being damaged due to static electricity generation, etc. As described above, the crack detection line (CDL) has an integral line shape with one end and the other end, and has a shape that extends long along the edge of the display panel (DP), so that when static electricity is generated in any area of ​​the display panel (DP), there is a high possibility that the crack detection circuit (PCD) will be damaged. According to the present invention, by connecting the electrostatic discharge prevention circuit (ESCa, ESCb) to the crack detection circuit (PCD), damage to the crack detection circuit (PCD) due to static electricity generation can be prevented, and an increase in resistance measured by the crack detection circuit (PCD) can be unified as being caused only by a crack generated in the display panel (DP), so that the occurrence of errors in the detection result of the crack detection circuit (PCD) can be reduced.

[0139] In the present embodiment, the electrostatic protection circuit (ESCa, ESCb) may include a first electrostatic protection circuit (ESCa) and a second electrostatic protection circuit (ESCb). The first electrostatic protection circuit (ESCa) may be disposed in an area close to the first pad (CDPa). For example, the first electrostatic protection circuit (ESCa) may overlap the first pad (CDPa) when viewed in the first direction (DR1). In addition, the second electrostatic protection circuit (ESCb) may be disposed in an area close to the second pad (CDPb). For example, the second electrostatic protection circuit (ESCb) may overlap the second pad (CDPb) when viewed in the first direction (DR1). According to the present invention, by providing a plurality of electrostatic discharge prevention circuits (ESCa, ESCb), the electrostatic flow in each of the first pad (CDPa) and the second pad (CDPb) corresponding to both ends of the crack detection circuit (PCD) can be stably absorbed by the electrostatic discharge prevention circuits (ESCa, ESCb). Accordingly, the electrical reliability of the crack detection circuit (PCD) can be improved.

[0140]

[0141] FIG. 7 is a drawing showing some components of the display panel shown in FIG. 6. FIG. 8 is an enlarged view of some areas of FIG. 7. FIGS. 9a to 9c are cross-sectional views schematically showing areas cut along line I-I' of FIG. 8a. For ease of explanation, FIG. 7 shows only a substrate (SUB), a thin film encapsulation layer (TFE), a crack detection circuit (PCD), and an anti-static circuit (ESCa, ESCb), and the thin film encapsulation layer (TFE) is shaded. Hereinafter, the present invention will be described with reference to FIGS. 7 to 9c.

[0142] As illustrated in FIGS. 7 and 8, the thin film encapsulation layer (TFE) covers the entire display area (DA) and extends to the outside of the display area (DA). An end (TFE_E) of the thin film encapsulation layer (TFE) is defined in the non-display area (NDA) and is located inside the edge (SUB_E) of the substrate (SUB). Meanwhile, the end (TFE_E) of the thin film encapsulation layer (TFE) may be the ends of the first inorganic layer (IL1) and / or the second inorganic layer (IL2) described above. The organic layer (OL) may overlap most of the display area (DA) and may not cover most of the non-display area (NDA). Therefore, in the area outside the display area (DA), the thin film encapsulation layer (TFE) may be provided in a form in which the second inorganic layer (IL2) is arranged in direct contact with the first inorganic layer (IL1). Accordingly, the end (TFE_E) of the thin film encapsulation layer (TFE) may be the end of the first inorganic layer (IL1), the end of the second inorganic layer (IL2), or the ends of the first inorganic layer (IL1) and the second inorganic layer (IL2) aligned with each other.

[0143] At least a portion of a crack detection line (CDL) in a crack detection circuit (PCD) may be covered by a thin film encapsulation layer (TFE). In the present embodiment, most of the crack detection line (CDL) extending along three sides (SI2, SI3, SI4) of the display area (DA) may be covered by the thin film encapsulation layer (TFE). The structure covering the crack detection line (CDL) may be a first inorganic layer (IL1) or a second inorganic layer (IL2) of the thin film encapsulation layer (TFE), and the organic layer (OL) of the thin film encapsulation layer (TFE) may not overlap with the crack detection line (CDL) in a plane.

[0144] Among the crack detection circuits (PCD), the first pad (CDPa) and the second pad (CDPb) are exposed from the thin film encapsulation layer (TFE). In other words, the first pad (CDPa) and the second pad (CDPb) can be planarly non-overlapping with the thin film encapsulation layer (TFE). Accordingly, connection between an external inspection device for crack inspection and the pads (CDPa, CDPb) can be easily achieved.

[0145] The electrostatic discharge protection circuit (ESCa, ESCb) is arranged so as not to overlap the end (TFE_E) of the thin film encapsulation layer (TFE) on a plane. The electrostatic discharge protection circuit (ESCa, ESCb) may be arranged at a position where it does not overlap the thin film encapsulation layer (TFE) by being spaced apart from the end (TFE_E) of the thin film encapsulation layer (TFE) by a predetermined gap (GA). The gap (GA) may be the minimum value of the distance between the electrostatic discharge protection circuit (ESCa, ESCb) and the end (TFE_E) of the thin film encapsulation layer (TFE), and may be greater than 0.

[0146] Referring to FIGS. 9A to 9C, the end (TFE_E) of the thin film encapsulation layer (TFE) can be defined by the end of the inorganic layer. For ease of explanation, FIGS. 9A to 9C only illustrate the substrate (SUB), the crack detection line (CDL), the insulating layer (INL), the first inorganic layer (IL1), and the second inorganic layer (IL2), and other components are omitted. The insulating layer (INL) may be an insulating layer disposed between the crack detection line (CDL) and the encapsulation layer (TFE) and may include an organic layer and / or an inorganic layer. For example, the insulating layer (INL) may include at least one of the sixth insulating layer (INS6, see FIG. 5), the seventh insulating layer (INS7, see FIG. 5), and the pixel definition layer (PDL, see FIG. 5). Alternatively, the insulating layer (INL) may include a layer positioned on the crack detection line (CDL) among the first to fifth insulating layers (INS1, INS2, INS3, INS4, INS5). This is illustrated as an example, and the layers constituting the insulating layer (INL) are not limited to any one embodiment.

[0147] Referring to FIG. 9a, the end (TFE_E) of the thin film encapsulation layer (TFE) may be defined by the end portions of the first inorganic layer (IL1) and the second inorganic layer (IL2). At this time, the end portions of the first inorganic layer (IL1) and the second inorganic layer (IL2) may be aligned. Alternatively, referring to FIG. 9b, the end (TFE_E1) of the thin film encapsulation layer (TFE) may be defined by the end portion of the first inorganic layer (IL1). Alternatively, referring to FIG. 9c, the end (TFE_E2) of the thin film encapsulation layer (TFE) may be defined by the end portion of the second inorganic layer (IL2). The end portions (TFE_E, TFE_E1, TFE_E2) of the thin film encapsulation layer (TFE) according to an embodiment of the present invention may be provided in various embodiments and are not limited to any one embodiment.

[0148] Hereinafter, for easy explanation, the description will be made based on Fig. 9a. The inorganic layers (IL1, IL2) of the thin film encapsulation layer (TFE) are formed through a deposition process (chemical vapor deposition, CVD) using an open mask, and a shadow phenomenon may occur due to the mask between the outer side of the display area (DA) and the end (TFE_E) of the thin film encapsulation layer (TFE). Accordingly, the closer to the end (TFE_E) of the thin film encapsulation layer (TFE), the more areas (hereinafter, shadow areas) in which the inorganic layers (IL1, IL2) are not deposited or are deposited thinly may be formed. These shadow areas can become moisture permeation paths through which moisture or oxygen can penetrate. The permeated oxygen or moisture can oxidize the inorganic layers (IL1, IL2) and damage the inorganic layers (IL1, IL2). In addition, when the inorganic layers (IL1, IL2) are insulating layers containing nitride, gases such as ammonia may be generated from the inorganic layers (IL1, IL2) or may flow in from the outside during the formation of the inorganic layers (IL1, IL2) and damage the metal patterns disposed thereunder. This is likely to occur at the end (TFE_E) of the thin film encapsulation layer (TFE) defined by the end of the inorganic layers (IL1, IL2). According to the present invention, by arranging the electrostatic protection circuit (ESCa, ESCb) so as not to overlap with the end (TFE_E) of the thin film encapsulation layer (TFE), a design can be achieved in which the electrostatic protection circuit (ESCa, ESCb) is not disposed in an area vulnerable to moisture permeation. Therefore, damage to the electrostatic protection circuit (ESCa, ESCb) can be prevented, and the reliability of the display panel (DP) can be improved.

[0149]

[0150] FIG. 10A is a circuit diagram of an anti-static circuit according to one embodiment of the present invention. FIG. 10B is a diagram illustrating the layout of an anti-static circuit according to one embodiment of the present invention. The present invention will be described with reference to FIGS. 10A and 10B.

[0151] As illustrated in FIG. 10A, the electrostatic discharge protection circuit (ESC) may include a plurality of transistors. In the present embodiment, each of the transistors may be a PMOS and may include a first element (DV1) connected to a first voltage terminal (VGH) and a second element (DV2) connected to a second voltage terminal (VGL).

[0152] The first element (DV1) is connected between a line connected to the sense line (CDL) and a first voltage terminal (VGH), and includes a gate connected to the source or drain. That is, the first element (DV1) can perform substantially the same operation as a diode. The first element (DV1) can discharge static electricity supplied to the crack sense line (CDL) through the first voltage terminal (VGH).

[0153] The second element (DV2) is connected between a line connected to the sense line (CDL) and a second voltage terminal (VGL), and includes a gate connected to the source or drain. That is, the second element (DV2) can perform substantially the same operation as a diode. The second element (DV2) can discharge static electricity supplied to the crack detection line (CDL) through the second voltage terminal (VGL).

[0154] The first voltage terminal (VGH) can provide a first voltage, and the second voltage terminal (VGL) can provide a second voltage lower than the first voltage, and each can be a constant voltage. Each of the first voltage and the second voltage can be one of the scan control signals (SCS, see Fig. 4). That is, some of the signal lines supplied to the scan driver (SDV, see Fig. 4) can be branched off and function as the first and second voltage terminals (VGH, VGL) of the static electricity prevention circuit.

[0155] Referring to FIG. 10b, an embodiment of a specific layout of an electrostatic discharge protection circuit (ESC) is illustrated. A first voltage transmission line (VTL1) and a second voltage transmission line (VTL2) extending along the first direction (DR1) are respectively connected to opposite ends of five semiconductor patterns (SMP1 to SMP5) arranged along the first direction (DR1). The first voltage transmission line (VTL1) and the second voltage transmission line (VTL2) are respectively connected to a first voltage line (VHL) and a second voltage line (VLL), so that the first voltage terminal (VGH) can form the second voltage terminal (VGL), respectively. In the present embodiment, the first voltage line (VHL) and the second voltage line (VLL) may be arranged on the same layer as the first connection electrode (CNE1, see FIG. 5) described above and may include the same material, but are not limited thereto.

[0156] In the present embodiment, the first voltage transmission line (VTL1) and the second voltage transmission line (VTL2) may insulate and intersect the signal lines (SGL1, SGL2) extending along the second direction (DR2). In addition, the first voltage line (VHL) and the second voltage line (VLL) may overlap with predetermined conductive patterns (CVP1, CVP2) arranged on different layers in a plane. The signal lines (SGL1, SGL2) or the conductive patterns (CVP1, CVP2) may be configurations that transmit electrical signals to elements other than the electrostatic discharge protection circuit (ESC). Meanwhile, this is merely an example, and the first voltage transmission line (VTL1), the second voltage transmission line (VTL2), the first voltage line (VHL), and the second voltage line (VLL) may be arranged so as not to overlap with the signal lines (SGL1, SGL2) or the conductive patterns (CVP1, CVP2), and are not limited to any one embodiment.

[0157] A branch line (BRL) that runs across the center of five semiconductor patterns (SMP1 to SMP5) and is connected to each of the semiconductor patterns (SMP1 to SMP5) is connected to a crack detection line (CDL). In the present embodiment, the branch line (BRL) is illustrated as including a first portion that extends along a second direction (DR2) and is connected to the crack detection line (CDL), and a second portion that has an integral shape with the first portion and extends along the first direction (DR1) and is connected to each of the semiconductor patterns (SMP1 to SMP5). However, the branch line (BRL) may have various shapes as long as it can connect the crack detection line (CDL) and an electrostatic discharge (ESD) protection circuit, and is not limited to any one embodiment.

[0158] A plurality of PMOS transistors that perform the same operation as a diode may be formed on each of the semiconductor patterns (SMP1 to SMP5). Each of the PMOS transistors may be a first element (DV1) or a second element (DV2). Each of the first element (DV1) and the second element (DV2) may have the same layer structure as the first transistor (TR1, see FIG. 5). That is, each of the first element (DV1) and the second element (DV2) may include a semiconductor pattern and a gate that are arranged on the same layer as the first transistor (TR1) and include the same material, but are not limited thereto.

[0159] Meanwhile, the components constituting the electrostatic discharge protection circuit (ESC) according to one embodiment of the present invention may be NMOS transistors or may include diodes. The electrostatic discharge protection circuit (ESC) may be provided in various forms as long as it can stably discharge static electricity from the crack detection line (CDL), and is not limited to any one embodiment.

[0160]

[0161] FIGS. 11A to 11C are plan views illustrating a portion of a crack detection line according to an embodiment of the present invention. FIG. 12A is a cross-sectional view schematically illustrating the crack detection line illustrated in FIG. 11B, and FIG. 12B is a cross-sectional view schematically illustrating the crack detection line illustrated in FIG. 11C. Hereinafter, the present invention will be described with reference to FIGS. 11A to 12B.

[0162] Referring to Fig. 11a, the crack detection line (CDL1) may include a plurality of bends along the extension direction. Fig. 11a illustrates an area in which the extension direction of the crack detection line (CDL1) is the second direction (DR2). The crack detection line (CDL1) may have a shape that is concave or convex in the first direction (DR1). For example, the crack detection line (CDL1) may be concave or convex toward the display area (DA). According to the present invention, since the crack detection line has a shape that includes bends, the length of the path that the crack detection line passes through for the same area can be increased. In addition, by reducing the width of the crack detection line, the defect in which the resistance of the crack detection line does not decrease even when a micro-sized crack occurs can be resolved. Therefore, the crack occurrence sensitivity of the crack detection circuit can be improved, and a display panel with improved reliability can be provided.

[0163] Referring to FIGS. 11b and 12a, the crack detection line (CDL2) may include a plurality of lines that are in contact with each other. In FIG. 11b, the crack detection line (CDL2) is illustrated as an embodiment including a first line (L1) and a second line (L2). The first detection line (L1) and the second detection line (L2) may be arranged on the same layer and may be in physical contact by overlapping at least a portion thereof. Accordingly, the crack detection line (CDL2) may have at least a portion of an overlapping region (OVR).

[0164] According to the present invention, when provided as a plurality of lines having a narrow width, the crack detection probability is improved and it is easier to detect cracks of a fine size, compared to when provided as a single line having a thick width. Meanwhile, the number of lines constituting the crack detection line (CDL2) can be further increased, and as the number of lines increases, the width of each line can be reduced. As long as it is possible to detect fine cracks of a size that can affect the display panel, the number and width of the lines can be designed in various ways and are not limited to any one embodiment.

[0165] Referring to FIGS. 11C and 12B, the crack detection line (CDL3) may include a plurality of lines that are physically in contact with each other and overlap each other while including a plurality of bends along the extension direction. The crack detection line (CDL3) may include a first line (L1) having a plurality of bends and a second line (L2) having a plurality of bends, and the first line (L1) and the second line (L2) may have shapes that correspond to each other. The first line (L1) and the second line (L2) may overlap on a plane. That is, the crack detection line (CDL3) may be provided in a form in which the first line (L1) and the second line (L2) are directly stacked.

[0166] According to the present invention, by forming bends in the crack detection line, sensitivity to microcracks can be improved. Furthermore, since the crack detection line (CDL3) has a structure in which multiple lines are stacked, the resistance of the crack detection line (CDL3) itself can be prevented from increasing excessively due to its narrow width. Therefore, a crack detection circuit with enhanced electrical reliability and sensitivity can be provided.

[0167]

[0168] Fig. 13a is a plan view of a display panel according to an embodiment of the present invention. Fig. 13b is an enlarged view of a portion of Fig. 13a. Fig. 13a illustrates an area corresponding to Fig. 7, and Fig. 13b illustrates an area corresponding to Fig. 8. Hereinafter, the present invention will be described with reference to Figs. 13a and 13b. Meanwhile, the same reference numerals are given to the same components as those described in Figs. 1 to 12b, and redundant descriptions are omitted.

[0169] As illustrated in FIGS. 13a and 13b, the electrostatic protection circuits (ESCa1, ESCb1) may be arranged in an area overlapping with the thin film encapsulation layer (TFE). The electrostatic protection circuits (ESCa1, ESCb1) may be spaced apart from the end (TFE_E) of the thin film encapsulation layer (TFE) by a predetermined distance (GA1), but may be arranged inside the end (TFE_E) of the thin film encapsulation layer (TFE) so as to overlap with the thin film encapsulation layer (TFE) in a plane. Each of the electrostatic protection circuits (ESCa1, ESCb1) may be arranged between the crack detection line (CDL) and the display area (DA).

[0170] By arranging the electrostatic discharge prevention circuits (ESCa1, ESCb1) at a location away from the end (TFE_E) of the thin film encapsulation layer (TFE) where non-deposition or insufficient deposition may occur, damage to the electrostatic discharge prevention circuits (ESCa1, ESCb1) due to moisture penetration, etc. can be prevented. In addition, by arranging the electrostatic discharge prevention circuits (ESCa1, ESCb1) at a location overlapping the encapsulation layer (TFE), the area of ​​the non-display area (NDA) can be prevented from increasing excessively.

[0171]

[0172] Fig. 14 is a plan view of a display panel according to one embodiment of the present invention. Fig. 14 illustrates an area corresponding to Fig. 7. The present invention will now be described with reference to Fig. 14. Components identical to those described in Figs. 1 to 13b are assigned the same reference numerals, and redundant descriptions thereof will be omitted.

[0173] Referring to FIG. 14, the crack detection circuit (PCDc) may be designed such that a first pad (CDPa) and a second pad (CDPb) are arranged adjacent to each other. The crack detection line (CDLc) of the crack detection circuit (PCDc) may include a first portion (CDLa) connected to the first pad (CDPa) and extending to an opposite edge of the display area (DA), and a second portion (CDLb) connected to the first portion (CDLa) and arranged parallel to the first portion (CDLa) and connected to the second pad (CDPb). The first portion (CDLa) and the second portion (CDLa) may extend parallel to each side of the display area (DA). That is, the crack detection line (CDLc) may have a shape in which two lines of the first portion (CDLa) and the second portion (CDLb) extend parallel to each other along the non-display area (NDA). Therefore, the sensitivity to micro-cracks may be improved.

[0174] The electrostatic discharge prevention circuits (ESCa, ESCb) are arranged adjacent to the first pad (CDPa) and the second pad (CDPb) but not overlapping with the ends of the thin film encapsulation layer (TFE), and are respectively connected to both ends of the crack detection line (CDLc). Therefore, according to the present embodiment, the electrostatic discharge prevention circuits (ESCa, ESCb) can be arranged on the same side (e.g., the left side) with respect to the center of the display area (DA). Accordingly, the design of the electrostatic discharge prevention circuits (ESCa, ESCb) and the crack detection circuit (PCDc) can be simplified.

[0175]

[0176] Fig. 15a is a plan view of a crack detection line according to a comparative example, and Fig. 15b is a plan view of a crack detection line according to an embodiment of the present invention. Corresponding areas are illustrated in Figs. 15a and 15b. Hereinafter, the present invention will be described with reference to Figs. 15a and 15b.

[0177] As illustrated in Fig. 15a, the crack detection line (CDL-C, hereinafter referred to as the comparative example) of the comparative example may be positioned in an area adjacent to the alignment mark (ALK). The comparative example (CDL-C) may have a straight line shape. Accordingly, if the gap (GAK) with the alignment mark (ALK) is narrow, static electricity may be generated, which may cause damage to the comparative example (CDL-C).

[0178] As illustrated in FIG. 15b, the crack detection line (CDL-K) according to one embodiment of the present invention may have a curved shape in an area adjacent to the alignment mark (ALK). For example, the crack detection line (CDL-K) may be concave with respect to the alignment mark (ALK). The crack detection line (CDL-K) may extend from a position spaced sufficiently apart (GAK1, GAK2) from the alignment mark (ALK) through the curved shape, thereby avoiding a path where static electricity may be generated between the alignment marks (ALK). Accordingly, the electrical stability of the crack detection circuit may be improved.

[0179] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0180] According to the present invention, an electronic device with improved electrical stability can be provided. Therefore, the present invention has industrial applicability.

Claims

1. A substrate having a display area and a non-display area adjacent to the display area defined; A plurality of pixels arranged on the substrate, each pixel including a transistor and a light-emitting element connected to the transistor; An encapsulating layer covering the above pixels and having an end defined in the non-display area; A crack detection circuit disposed along at least a portion of an edge of the display area in the non-display area and including one end and the other end; and An anti-static circuit disposed in the non-display area and connected to the crack detection circuit, The above anti-static circuit is an electronic device spaced apart from the end of the sealing layer on a plane.

2. In paragraph 1, The above crack detection circuit, A crack detection line extending along at least three sides of the above display area and including one end and the other end; a first pad connected to the above-described end of the above-described crack detection line; and including a second pad connected to the other end of the crack detection line; An electronic device wherein the anti-static circuit is disposed adjacent to the first pad or the second pad.

3. In paragraph 2, An electronic device in which the anti-static circuit includes a first anti-static circuit connected to a portion of the crack detection line adjacent to the first pad and a second anti-static circuit connected to a portion adjacent to the first pad.

4. In paragraph 2, Further comprising a data driver arranged in the non-display area and connected to the pixels, An electronic device in which the first and second ends of the crack detection line are spaced apart from each other with the data drive unit interposed therebetween.

5. In paragraph 2, Further comprising a data driver arranged in the non-display area and connected to the pixels, An electronic device wherein the first and second ends of the crack detection line are arranged on the same side with respect to the data driving unit.

6. In paragraph 2, The above-mentioned anti-static circuit is an electronic device that does not overlap with the sealing layer on a plane.

7. In paragraph 6, An electronic device wherein the above-mentioned anti-static circuit overlaps the first pad or the second pad when viewed from one direction.

8. In paragraph 2, The above-mentioned anti-static circuit is an electronic device that overlaps the above-mentioned sealing layer on a plane.

9. In paragraph 8, The above-mentioned anti-static circuit is an electronic device disposed between the crack detection line and the display area.

10. In paragraph 2, An electronic device wherein the crack detection line comprises at least one bend, the bend being concave or convex toward the display area.

11. In paragraph 10, Further comprising alignment marks placed in the above non-displayed area, The above-mentioned bending portion is an electronic device concave with respect to the above-mentioned alignment mark.

12. In paragraph 2, The above crack detection line is, a first line extending along one direction; and A second line extending along the above direction and disposed on the same layer as the first line and overlapping in the plane at least in a portion thereof, An electronic device in which the first line and the second line are in contact with each other in at least a portion of the area.

13. In paragraph 12, Each of the first line and the second line includes at least one bend. The above first line and the above second line are an electronic device that overlaps in the entire area.

14. In paragraph 1, The above encapsulating layer comprises at least one inorganic film and at least one organic film, An electronic device wherein the end of the above-mentioned sealing layer is defined by the above-mentioned inorganic film.

15. In paragraph 14, The above-mentioned encapsulating layer comprises a plurality of inorganic films, An electronic device wherein the ends of the above encapsulating layer are aligned ends of at least two inorganic membranes.

16. A substrate having a display area and a non-display area adjacent to the display area defined; A plurality of pixels arranged on the substrate, each pixel including a transistor and a light-emitting element connected to the transistor; An encapsulating layer covering the above pixels and having an end defined in the non-display area; A crack detection line disposed along at least a portion of an edge of the display area in the non-display area and including one end and the other end; An anti-static circuit disposed in the non-display area and connected to one end or the other end of the crack detection line, The above-mentioned anti-static circuit is an electronic device that does not overlap on a plane with the above-mentioned end of the above-mentioned sealing layer.

17. In paragraph 16, The above-mentioned sealing layer includes a first inorganic film, a second inorganic film, and an organic film disposed between the first inorganic film and the second inorganic film, An electronic device wherein the ends of the above-mentioned sealing layer are aligned ends of the first inorganic film and the second inorganic film.

18. In paragraph 17, The above-mentioned anti-static circuit is an electronic device that overlaps the first inorganic film and the second inorganic film on a plane.

19. In paragraph 17, The above-mentioned anti-static circuit is an electronic device that does not overlap on a plane with the first inorganic film and the second inorganic film.

20. In paragraph 17, An electronic device wherein the crack detection circuit comprises at least one bend, the bend having a concave or convex shape toward the display area.

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