Method for manufacturing FMM and FMM manufactured thereby

Abstract

The present invention relates to a method for manufacturing an FMM and an FMM manufactured thereby. The manufacturing method is characterized by comprising: step (a), depositing protective thin films on the upper surface and the lower surface of a silicon substrate; step (b), depositing a conductive layer on the upper surface of the silicon substrate having the protective thin films deposited on the upper surface and the lower surface thereof; step (c), depositing an invar alloy plating layer on the conductive layer deposited on the upper surface; step (d), removing a portion of the protective thin film on the lower surface, performing back etching on the lower surface of the silicon substrate, removing a central region of the silicon substrate on the basis of the surface shape to form an open portion, and removing a peripheral region of the silicon substrate on the basis of a hole shape while a supporting part is formed by using the silicon substrate in the non-removed peripheral region to form an alignment hole; and step (e), performing dry etching on the invar alloy plating layer, the conductive layer, and the protective thin film, which are exposed in the open portion, to form a cluster of patterned holes in the central portion of the open portion and a cluster of dummy holes surrounding the cluster of the patterned holes, resulting in penetration through the alignment hole.

Description

Method for manufacturing FMM and FMM manufactured by the same TECHNICAL FIELD

[0001] The present invention relates to a method for manufacturing FMM and FMM manufactured by the same, and more particularly to a method for manufacturing FMM in which an invar mask is formed on a silicon wafer in an electroplating manner, the silicon wafer is used as a frame of the mask, and compared to a press method of an invar sheet, the mask can be manufactured in a thin thickness while reducing thickness deviation, a process of welding the mask and an additional frame or a stretching process of the mask can be omitted, thereby simplifying a manufacturing process and reducing manufacturing costs. BACKGROUND

[0002] When an organic light-emitting diode (OLED) panel is currently manufactured, a fine metal mask (FMM) as a necessary component plays a role of a mask in RGB deposition. The FMM is in the form of a thin iron plate formed of an invar raw material, and in order to be used inside a depositor, needs to be combined with a strong frame. For this reason, a method of combining the mask and the frame in a physical stretching and laser welding manner has been used in the past.

[0003] That is, the conventional stretching and welding method is a method of stretching the FMM using a stretcher or the like while welding using a laser, and a large-area mask has a problem of alignment deviation. Also, the mask is large in area and thin in thickness, and thus the mask is sagged or twisted due to physical stretching force and load, and there is a problem that pixel positioning accuracy (PPA) is deviated.

[0004] In an ultra-high-definition OLED manufacturing process, a slight alignment error of several μm can also cause pixel deposition to fail, and thus a technology of preventing deformation such as sagging or bending of the mask and accurately aligning is required.

[0005] On the other hand, a micro display for an augmented reality (AR) device or a virtual reality (VR) device has recently attracted attention.

[0006] A micro display needs to have a smaller screen size than existing displays and achieve high definition in a smaller screen in order to directly display an image in front of a user's eyes in an AR / VR device. Accordingly, the pattern hole size and pitch are reduced compared to a mask used in an existing ultra-high definition OLED manufacturing process, and thus a smaller alignment of the mask is urgently required before a pixel deposition process.

[0007] SUMMARY

[0008] The present application has been made to solve the problems as described above, and aims to provide a manufacturing method of an FMM in which a mask of a Invar alloy material is formed by electroplating on a silicon wafer, the silicon wafer is used as a frame of the mask, and a mask can be manufactured in a thin thickness while reducing thickness deviation compared to a calendering method of an Invar alloy sheet, and a process of welding the mask and an additional frame or a stretching process of the mask can be omitted, thereby simplifying a manufacturing process and reducing manufacturing costs.

[0009] According to the present application, there is provided a manufacturing method of an FMM, characterized by comprising: a step (a) of depositing a protective film on both upper and lower surfaces of a silicon substrate; a step (b) of depositing a conductive layer on the upper surface of the silicon substrate on which the protective film is deposited on both upper and lower surfaces; a step (c) of depositing an Invar plating layer on the conductive layer deposited on the upper surface; a step (d) of removing a part of the protective film on the lower surface, performing back etching on the lower surface of the silicon substrate, removing a central region of the silicon substrate by a surface shape, forming an open portion, forming a support portion using the silicon substrate of a peripheral region which is not removed while removing the peripheral region of the silicon substrate by a hole shape, and forming an alignment hole; and a step (e) of performing dry etching on the Invar plating layer, the conductive layer, and the protective film exposed in the open portion, forming a pattern hole which is clustered in a central portion of the open portion and a virtual hole which surrounds the clustered pattern hole, and penetrating a position of the alignment hole.

[0010] According to another aspect of the present application, there is provided a method of manufacturing an FMM, characterized by comprising: step (A) of depositing a protective film on both upper and lower surfaces of a silicon substrate; step (B) of depositing a conductive layer on the upper surface of the silicon substrate on which the protective film is deposited on both upper and lower surfaces; step (C) of forming a photo pattern layer on the conductive layer deposited on the upper surface at positions of pattern holes clustered in a central portion and dummy holes surrounding the clustered pattern holes; step (D) of depositing an invar plating layer on the conductive layer on which the photo pattern layer is formed on the upper surface; step (E) of removing a portion of the protective film on the lower surface, performing back etching on the lower surface of the silicon substrate, removing a central region of the silicon substrate by a surface shape, forming an open portion, and removing a peripheral region of the silicon substrate by a hole shape to form an alignment hole while forming a support portion using the silicon substrate of the peripheral region which is not removed; and step (F) of performing dry etching on the conductive layer and the protective film exposed in the open portion, perforating the invar plating layer, the conductive layer, and the protective film in the support portion while perforating the pattern holes and the dummy holes at positions of the open portion, and perforating the alignment hole.

[0011] Preferably, the present application is characterized in that the silicon substrate is a silicon wafer or a quartz wafer formed in a thickness of 50 to 700 μm.

[0012] Preferably, the present application is characterized in that the protective film is a SiNx inorganic film deposited in a thickness of 10 to 50 nm.

[0013] Preferably, the present application is characterized in that the conductive layer is formed of TiN or Ti-Cu and deposited in a thickness of 100 to 400 nm.

[0014] Preferably, the present application is characterized in that the invar plating layer is formed of an invar alloy (Ni-Fe) or a super invar alloy (Ni-Fe-Co) having a coefficient of thermal expansion (CTE) of 3 PPM / °C or less and electroplated in a thickness of 2 to 5 μm.

[0015] Preferably, the present application is characterized in that the inside of the support portion dividing the open portion is tapered.

[0016] Preferably, the present application is characterized in that the pattern holes have a diameter of 3 μm or less and are processed in a pitch of 8 μm or less.

[0017] Preferably, the present application is characterized in that the dummy holes are perforated in an elliptical shape having a long axis and a short axis, individual dummy holes are arranged apart from adjacent dummy holes in a direction of the long axis, a plurality of dummy hole rows are arranged in a radial direction of the silicon substrate, and the individual dummy holes of each dummy hole row are arranged apart from adjacent individual dummy holes in the radial direction.

[0018] Preferably, the present application is characterized in that the virtual holes and the pattern holes are formed simultaneously or the virtual holes are formed first and then the pattern holes are formed.

[0019] Preferably, the present application is characterized in that the inconel plating layer formed on the conductive layer is heat-treated before the back etching process.

[0020] On the other hand, according to another aspect of the present application, there is provided an FMM manufactured by the manufacturing method of the FMM according to any one of the above-described features, characterized by comprising: a silicon substrate; a protective film deposited on the upper and lower surfaces of the silicon substrate; a conductive layer deposited on the upper surface of the silicon substrate on which the protective film is deposited on both surfaces; an inconel plating layer deposited on the conductive layer deposited on the upper surface, the central region of the lower surface of the silicon substrate is removed by a surface shape to form an open portion, the silicon substrate of the peripheral region which is not removed forms a support portion, a plurality of pattern holes are formed by a through shape in the central portion of the open portion, and a plurality of virtual holes are formed by a through shape in the region from the outermost portion of the pattern holes which are clustered in a surrounding shape to the support portion.

[0021] Preferably, the present application is characterized in that the inside of the support portion in the silicon substrate is formed in a tapered shape.

[0022] Preferably, the present application is characterized in that an alignment hole is formed in the support portion of the silicon substrate, and the alignment hole penetrates the protective film, the conductive layer, and the inconel plating layer including the support portion in the upper and lower directions.

[0023] According to the present application, the following effects can be obtained. An inconel mask is formed on a silicon wafer by electroplating, and the silicon wafer is used as a frame of the mask. Compared to a calendering method of inconel sheets, the mask can be manufactured in a thin thickness while reducing thickness deviation.

[0024] Also, the following effects can be obtained. The process of welding the mask and an additional frame or the stretching process of the mask can be omitted, thereby simplifying the manufacturing process and reducing manufacturing costs. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a diagram for explaining a manufacturing method of an OLED using an FMM according to the related art.

[0026] FIGS. 2 and 3 are diagrams for explaining a manufacturing method of an FMM according to the related art.

[0027] FIG. 4 is a diagram for explaining a manufacturing method of an FMM according to a first embodiment of the present application.

[0028] FIG. 5 is a diagram for explaining a manufacturing method of an FMM according to a second embodiment of the present application.

[0029] FIG. 6 is a diagram for explaining a virtual hole structure of an FMM according to an embodiment of the present application.

[0030] FIG. 7 is a diagram for explaining an outer shape structure of an FMM according to an embodiment of the present application.

[0031] FIGS. 8 and 9 are diagrams for explaining a real hole structure of an FMM manufactured according to an embodiment of the present application.

[0032] Reference numerals 300: FMM 310: silicon substrate 320: protective film 330: conductive layer 340: invar plating layer 350: alignment hole 360: virtual hole 370: pattern hole

[0033] 380: light pattern layer DETAILED DESCRIPTION

[0034] The present application can be variously changed and can have various embodiments, and a specific embodiment is exemplified in the drawings and described in detail in the specific description. However, it should be understood that the present application is not limited to the specific embodiments, but includes all changes, equivalent technical solutions, and even alternative technical solutions contained in the idea and technical scope of the present application. In the process of explaining each drawing, similar reference numerals are used for similar structural elements.

[0035] The terms of first, second, A, B, etc. can be used to explain various structural elements, but the above structural elements are not limited to the above terms. The above terms are used only for the purpose of distinguishing one structural element from another structural element. For example, the first structural element can be named as the second structural element without departing from the scope of the present application, and similarly, the second structural element can be named as the first structural element. And / or this term includes a combination of a plurality of related items or any one of a plurality of related items.

[0036] When referring to one structural element being "connected" or "connected" to another structural element, it should be understood that it can be directly connected or connected to the other structural element, but other structural elements can be present in the middle. In contrast, when referring to one structural element being "directly connected" or "directly connected" to another structural element, it should be understood that no other structural element is present in the middle.

[0037] The terms used in the present application are used only to describe particular embodiments and do not limit the present application. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, it should be understood that the terms "include" or "have" or the like are used to designate the presence of features, numbers, steps, actions, structural elements, components or combinations thereof described in the specification, and do not preclude the presence or possibility of additional one or more other features, numbers, steps, actions, structural elements, components or combinations thereof.

[0038] Unless differently defined, all terms used herein including technical terms or scientific terms have the same meaning as that generally understood by those having ordinary knowledge in the art to which the present application pertains. The terms as generally used in dictionaries should be interpreted as having the meanings consistent with the context of the relevant technology, and should not be interpreted as ideal or overly formal meanings unless clearly defined in the present application.

[0039] Hereinafter, preferred embodiments according to the present application will be described in detail with reference to the accompanying drawings.

[0040] FIG. 1 is a diagram for explaining a manufacturing method of an OLED using an FMM according to the prior art.

[0041] Hereinafter, in each of the drawings related to the prior art and the embodiments of the present application, the size or thickness of a structural element is exaggerated (or thickened) or reduced (or thinned) for convenience of understanding or the like, or is simply represented, but should not be construed as limiting the scope of protection of the present application thereto.

[0042] Referring to FIG. 1, an OLED manufacturing apparatus implementing a manufacturing method of an OLED using an FMM according to the prior art includes a magnet plate 10 housing a magnet 11 and a cooling water line 12, and a deposition source supply part 40 supplying an organic material source 41 from a lower portion of the magnet plate 10.

[0043] An object substrate 20 of glass or the like on which the organic material source 41 is deposited can be interposed between the magnet plate 10 and the deposition source supply part 40. An FMM 30 on which the organic material source 41 is deposited by different pixels can be disposed in close contact or in close proximity to the object substrate 20. The magnet 11 generates a magnetic field, and the FMM 30 can be brought into close contact with the object substrate 20 by an attractive force caused by the magnetic field.

[0044] The FMM 30 needs to be aligned before being brought into close contact with the object substrate 20. One or more masks can be combined with a frame 35. The frame 35 is fixedly provided in the OLED manufacturing apparatus, and the mask can be combined with the frame 35 through an additional attachment or welding process.

[0045] The deposition source supply part 40 supplies the organic material source 41 to the left and right paths in a reciprocating manner, and the organic material source 41 supplied in the deposition source supply part 40 can be deposited on one side of the object substrate 20 through the pattern hole 32 formed in the FMM 30. The organic material source 41 deposited through the pattern of the FMM 30 can function as the pixel 21 of the OLED.

[0046] In order to prevent non-uniform deposition of the pixel 21 due to a shadow effect, the pattern hole 32 of the FMM 30 can be formed in a slanting manner (S) [or in a tapered manner (S)]. The organic material source 41 passing through the pattern hole 32 in a diagonal direction along the slanting surface can also form the pixel 21, and thus the overall thickness of the pixel 21 can be uniformly deposited.

[0047] The FMM 30 in FIG. 1 can perform a pixel deposition process on a large area of the object substrate 20.

[0048] A manufacturing method of such an FMM 30 will be described below.

[0049] FIGS. 2 and 3 are diagrams for explaining a manufacturing method of an FMM according to the related art.

[0050] First, as shown in (a) of FIG. 2, a relatively thin INVAR substrate 30a prepared in a calendering manner is prepared.

[0051] The INVAR substrate 30a is formed of an alloy having a small coefficient of thermal expansion by adding nickel (Ni) to iron (Fe) at a predetermined ratio.

[0052] The thickness of the initially calendered INVAR substrate 30a can be about 25 μm. In order to manufacture an FMM for AR / VR OLED manufacturing, an INVAR substrate 30a having a thickness of about 5 μm is required, but there is a limitation in using the calendering method.

[0053] Therefore, as shown in (b) of FIG. 2, the surface of the INVAR substrate 30a is processed into a thinner sheet shape through half etching. At this time, the thickness of the INVAR substrate 30a subjected to the half etching can be about 5 μm.

[0054] At this time, the target thickness of the INVAR substrate can be achieved through the half etching, but according to the characteristics of the etching process, a serious thickness deviation occurs, and the thickness has a spread of 5 μm ± 3 μm in total.

[0055] Also, as shown in (c) of FIG. 2, the INVAR substrate 30a in the sheet shape is processed by punching a small pattern hole 32.

[0056] In order to manufacture the FMM of 3000 PPI, the pattern hole 32 of 3 μm in diameter is processed with a pitch of 8 μm by laser or etching. In this process, the thickness deviation of the inconel substrate 30a needs to be ±3 μm or less, but as described above, the thickness deviation of the inconel substrate 30a is large by the calendering and the semi-etching adjustment of the thickness, and it is difficult to uniformly manufacture the pattern hole 32.

[0057] After that, as shown in (d) of FIG. 2, the inconel substrate 30a in the form of a thin plate in which the pattern hole 32 is formed is stretched, and is welded to the frame 35 to manufacture the FMM 30.

[0058] The above-described stretching process is used to adjust the distance (PPA) between the accurate pattern holes 32, and after the inconel substrate 30a in which the pattern hole 32 is formed as shown in (a) of FIG. 3 is combined with the frame 35 as shown in (b) of FIG. 3, the inconel substrate 30a is welded to the frame 35 in a state in which the inconel substrate 30a is pulled in four directions using laser. At this time, the welding is performed while the pitch is measured in real time in such a manner that the deviation of the distance between the pattern holes 32 becomes ±3 μm or less. After that, as shown in (c) of FIG. 3, the side portions of the inconel substrate 30a are cut to complete the FMM 30 product.

[0059] As shown in (e) of FIG. 2, the thus-manufactured FMM 30 is brought into close contact with the object substrate 20, and the organic material source 41 is supplied in the deposition source supply portion 40, and the organic material source 41 can be deposited on one side of the object substrate 20 through the pattern hole 32 formed in the FMM 30. The organic material source 41 deposited through the pattern of the FMM 30 can function as the pixel 21 of the OLED.

[0060] The manufacturing method of the FMM according to the related art has the following problems.

[0061] 1) The inconel substrate 30a is difficult to be thinned to a level that can be used for the manufacture of the AR / VR OLED in the calendering and semi-etching manner, and even if it is thinned, the thickness deviation is generated overall, thereby reducing the product reliability.

[0062] 2) In order to combine the inconel substrate 30a and the frame 35, a precise physical stretching process is required, and thus the productization process is very difficult, and the inconel substrate 30a for the manufacture of the AR / VR OLED is very thin, and thus it is difficult to precisely distribute the stretching force, a great PPA error is generated, and the yield is reduced.

[0063] 3) Since the inconel substrate 30a and the frame 35 of different kinds are combined by laser welding, the bonding force of the combined portion is reduced, and the durability is reduced when the FMM is repeatedly used.

[0064] 4) Since the thickness of the inconel substrate 30a is very thin, sagging or deformation occurs on the frame 35, thereby causing a decrease in the positional accuracy of the pattern hole 32, and finally, there is a problem of a decrease in the deposition accuracy.

[0065] The manufacturing method of the FMM according to the embodiment of the present application explained below is characterized in that an inconel mask is formed on a silicon wafer by electroplating, and the silicon wafer is used as a frame of the mask, thereby enabling the mask to be manufactured with a thin thickness while reducing thickness deviation, omitting a process of welding the mask and an additional frame or a stretching process of the mask, simplifying the manufacturing process, and reducing manufacturing costs, compared to a calendering method of inconel sheets.

[0066] FIG. 4 is a diagram for explaining the manufacturing method of the FMM according to the first embodiment of the present application.

[0067] First, as shown in (a) of FIG. 4, a silicon substrate 310 is prepared.

[0068] The silicon substrate 310 can use a silicon wafer (Si) or a quartz wafer (SiO2), and can be used without being limited to the above examples as long as it is a material having a coefficient of thermal expansion (CTE) of 3 PPM / °C or less.

[0069] The silicon substrate 310 can be formed to have a thickness of 50 to 700 μm.

[0070] Also, as shown in (b) of FIG. 4, a protective film 320 is deposited on both upper and lower surfaces of the silicon substrate 310.

[0071] The protective film 320 can be a SiNx inorganic film having high blocking properties and excellent adhesion. The SiNx inorganic film coats the outer surface of the silicon substrate 310 to prevent the silicon substrate 310 from reacting with an electroplating solution in a later-described electroplating process.

[0072] The SiNx inorganic film can be deposited using a vacuum sputter, and can be deposited to have a thickness of about 10 to 50 nm, and preferably, about 30 nm.

[0073] After that, as shown in (c) of FIG. 4, a conductive layer 330 is deposited on the upper surface of the silicon substrate 310 on which the protective film 320 is deposited on both upper and lower surfaces.

[0074] Basically, since the silicon substrate 310 is an insulator, it is necessary to perform a conductive treatment for electroplating. Also, for electroplating of inconel (Ni-Fe) or super inconel (Ni-Fe-Co) described later, it has a feature that the resistance is high during the electroplating process, and the conductivity of the conductor needs to be low.

[0075] In the embodiment of the present application, in order to perform plating on the silicon substrate 310, an electrically conductive layer 330 is deposited to impart electrical conductivity. The electrically conductive layer 330 can be formed of TiN or Ti-Cu, and can be used without being limited to the above examples as long as it is a material that can impart electrical conductivity to the silicon substrate 310.

[0076] When the electrically conductive layer 330 is formed of TiN, the TiN layer can be deposited using a vacuum sputter, and can be deposited to a thickness of about 100 to 400 nm, and preferably, about 200 nm.

[0077] When the electrically conductive layer 330 is formed of Ti-Cu, a Ti layer is first deposited (to ensure adhesion of silicon-Cu), and a Cu layer is secondarily deposited (to ensure low electrical conductivity). The Ti layer and the Cu layer can be deposited using a vacuum sputter. The Ti layer can be deposited to a thickness of about 10 to 50 nm, and preferably, about 30 nm. The Cu layer can be deposited to a thickness of about 100 to 300 nm, and preferably, about 200 nm.

[0078] In this case, when the Cu layer is deposited on the surface, the adhesion between the Cu-Invar alloy layer or the Cu-super Invar alloy layer becomes very high, and thus, stable adhesion between the silicon substrate 310 and the Invar plated layer 340 can be ensured.

[0079] Subsequently, as shown in (d) of FIG. 4, the Invar plated layer 340 is deposited on the electrically conductive layer 330 deposited thereon.

[0080] According to the related art, a representative production method for manufacturing Invar (Ni-Fe) or super Invar (Ni-Fe-Co) used for FMMs uses a cold rolling method, but in order to obtain a thin plate having a thickness of 50 μm or less in the cold rolling method, a multi-stage calendering process is required, and thus, the process is long and complicated, and has a disadvantage of high manufacturing cost.

[0081] Recently, a manufacturing method for manufacturing Invar for FMMs in an electroplating method has been developed. A general electroplating manufacturing method for Invar for FMMs using the electroplating method is configured in such a manner that an anode electrode plate and a mother material serving as a cathode are arranged to face each other in a state of being parallel to each other in an internal space of an electroplating bath, an electroplating solution (electrolyte) is supplied to the internal space of the electroplating bath, and then, an anode power source and a cathode power source are connected to the anode electrode plate and the mother material, respectively, and current is applied thereto, thereby forming a plated layer (Invar) on one surface of the mother material.

[0082] The Invar thin plate or super Invar thin plate manufactured in the electroplating method as described above has a very low coefficient of thermal expansion (CTE), and thus, there is little concern that heat energy causes deformation of the pattern shape of a mask, and is mainly used for manufacturing high-resolution OLEDs. Among them, the primary qualification of the Invar raw material for FMMs is a low coefficient of thermal expansion (CTE).

[0083] According to another prior art, an example of using single crystal silicon as a mother material for electroplating exists as a document (Korean Patent Application No. 2017-0067396, etc.). The mother material is used as an electrically conductive substrate by performing a high concentration doping process on the entire or surface of the single crystal silicon, has a process of separating the plated layer and the mother material after electroplating is completed, and rejoining the separated plated layer to an additional frame. However, since the adhesion between the plated layer and the single crystal silicon as the mother material is very high, the process of separating the two is difficult, and an additional physical and chemical treatment process for separation is required, so there is a problem that the process becomes complicated and the plated layer is damaged.

[0084] In an embodiment of the present application, the invar alloy plated layer 340 is directly deposited on the electrically conductive layer 330 deposited on the silicon substrate 310, and is directly used as a frame without separating the silicon substrate 310 (with reference to the open part 311 and the support part 312), thereby having the advantage that the separation process of the silicon substrate 310 and the electrically conductive layer 330 can be omitted and the electrically conductive layer 330 can be maintained in an electroplated state without change.

[0085] The above invar alloy plated layer 340 can be formed by electroplating a binary or ternary alloy having a coefficient of thermal expansion (CTE) of 3 PPM / °C or less, and can be electroplated to a thickness of 2 to 5 μm. Also, since the electroplating method is used, the thickness deviation can be ± 0.3 μm.

[0086] At this time, the deposited invar alloy plated layer 340 can be subjected to heat treatment.

[0087] Since the invar alloy plated layer 340 by electroplating has a dense structure, in order to adjust the crystal structure to be softened, heat treatment can be performed at a high temperature, and the elongation rate can be improved by such annealing.

[0088] Also, a body-centered cubic (bcc) structure and a face-centered cubic (fcc) structure are mixed in the crystal structure, and in order to reduce the coefficient of thermal expansion (CTE), the BCC structure is changed to the FCC structure by heating above the critical temperature (about 450°C) for about 1 hour or more.

[0089] Especially, a compressed tension is generated between the silicon substrate 310 and the invar alloy plated layer 340 during the heat treatment, and the phenomenon of sagging or wrinkling of the invar alloy plated layer 340 exposed after the back etching process described later can be prevented.

[0090] And, the Invar alloy plating layer 340 is subjected to a volume change during the heat treatment, and is subjected to a compressive stress, which is released by the dummy hole 360 formed in the dry etching process described later.

[0091] After that, as shown in (e) of FIG. 4, the silicon substrate 310 is removed from the lower protective film 320, and the protective film 320 is removed from the center region of the surface shape of the opening portion 311 and the peripheral region of the alignment hole 350 by hole formation, and a portion of the lower surface of the silicon substrate 310 is opened.

[0092] After that, as shown in (f) of FIG. 4, back etching is performed on the lower surface of the silicon substrate 310, and the center region of the silicon substrate 310 is removed by surface formation, and the peripheral region is removed by hole formation, and the alignment hole 350 is formed while the opening portion 311 is formed.

[0093] The center region removed from the silicon substrate 310 by the back etching forms the opening of the opening portion 311, and the silicon substrate 310 of the portion not removed from the peripheral region forms the support portion 312, and the alignment hole 350 is formed in the hole shape in the peripheral support portion 312.

[0094] The support portion 312 manufactured by the back etching directly functions as a frame supporting the Invar alloy plating layer 340. Also, the opening portion 311 formed on the inner side of the support portion 312 functions to directly expose the Invar alloy plating layer 340 to the downward direction.

[0095] Further, by the back etching process, since the edge (support portion 312) of the silicon substrate 310 replaces the existing bonding type frame, the process of stretching the Invar alloy plating layer on the additional bonding type frame and the process of bonding the Invar alloy plating layer to the frame by welding the frame, which must be performed in the existing process, can be omitted.

[0096] At this time, the inner side of the support portion 312 of the silicon substrate 310 can be formed in an inclined shape, and more accurately, can be formed in a tapered shape.

[0097] After that, as shown in (g) of FIG. 4, the opening portion 311 of the silicon substrate 310 is removed to form the dummy hole 360 and the pattern hole 370 while passing through the position of the alignment hole 350 by performing dry etching on the Invar alloy plating layer 340, the conductive layer 330, and the protective film 320.

[0098] The dry etching process can be implemented by forming a hole using a pico laser or etching a hole using plasma.

[0099] The alignment hole 350 is a hole for alignment with a substrate to be manufactured when manufacturing an OLED.

[0100] In order to achieve a high resolution of 3000 PPI or more, the pattern hole 370 can have a diameter of about 3 μm or less and can be formed with a pitch of 8 μm or less. The pattern hole 370 can have a substantially conical shape and can provide a path through which the organic material source 410 of the deposition source supply part 400 can pass. The pattern hole 370 can be formed in a cluster at a center portion of the invar plating layer 340.

[0101] The dummy hole 360 can be formed in a cluster in a manner of surrounding the cluster of the pattern hole 370. The dummy hole 360 can be formed in a region from an outermost portion of the cluster of the pattern hole 370 to the support part 312.

[0102] Referring to (a) of FIG. 6, the dummy hole 360 can be formed in a substantially elliptical shape having a long axis and a short axis. The dummy hole 360 can be arranged in a direction of the long axis to be spaced apart from an adjacent dummy hole 360 and a plurality of dummy hole 360 rows can be arranged in a radial direction of the silicon substrate 310. The spaced apart dummy hole 360 rows can be arranged in the radial direction with the long axis of the adjacent dummy hole 360 being staggered.

[0103] The dummy hole 360 can be formed at a position where the invar plating layer 340 is in contact with the open portion 311 of the silicon substrate 310, and the compressive stress applied to the invar plating layer 340 at the position can be released. More specifically, as the dummy hole 360 shown in (a) of FIG. 6 is deformed in a length of the short axis due to a tensile stress (see arrows) applied in a horizontal radial direction of the invar plating layer 340 as shown in (b) of FIG. 6, the dummy hole 360 can function to release the compressive stress.

[0104] Accordingly, the dummy hole 360 and the pattern hole 370 can be simultaneously formed through a dry etching process, but preferably, the dummy hole 360 can be formed first to release the compressive stress and then the pattern hole 370 can be formed as shown in (c) of FIG. 6, so that a deformation of the pattern hole 370 due to the compressive stress when the pattern hole 370 is formed can be reduced.

[0105] Here, the dry etching process of the invar plating layer 340, the conductive layer 330, and the protective film 320 (see (g) of FIG. 4) and the back etching process of the lower back surface of the silicon substrate 310 (see (f) of FIG. 4) are shown in the order of the back etching process followed by the dry etching process, but the order can be reversed.

[0106] The FMM 300 can be manufactured through the process of the first embodiment.

[0107] Fig. 7(a) is an upper side view of the FMM 300, and Fig. 7(b) is a lower side view of the FMM 300. As such, by plating the invar plating layer 340 on the silicon substrate 310 and etching the lower portion of the silicon substrate 310 from the back, the silicon substrate 310 directly functions as a frame, and an additional stretching process or a soldering process can be omitted as described above.

[0108] Further, Figs. 8 and 9 are diagrams for explaining the actual structure of the FMM manufactured according to the embodiment of the present application.

[0109] As shown in Fig. 8, the invar plating layer 340 is formed on the silicon substrate 310, and as shown in Fig. 9, the silicon substrate 310 supporting the invar plating layer 340 becomes a structure in which the plating layer 340 is exposed to the invar lower side by etching from the back while supporting the invar plating layer 340 from the lower side.

[0110] On the other hand, Fig. 5 is a diagram for explaining a manufacturing method of the FMM according to the second embodiment of the present application.

[0111] Referring to Fig. 5, the resulting product of the manufacturing method of the FMM according to the second embodiment of the present application is the same as that of the first embodiment, but the manufacturing process is different. In the following description of the second embodiment, the description repeated in the first embodiment is abbreviated or omitted, and only the different parts are described.

[0112] First, the silicon substrate 310 is prepared (see Fig. 5(a)), and the protective film 320 is deposited on both upper and lower surfaces of the silicon substrate 310 (see Fig. 5(b)), and the conductive layer 330 is deposited on the upper surface of the silicon substrate 310 on which the protective film 320 is deposited on both upper and lower surfaces (see Fig. 5(c)).

[0113] The silicon substrate 310 can use a silicon wafer (Si) or a quartz wafer (SiO2), and can use materials having a coefficient of thermal expansion (CTE) of 3 PPM / °C or less, without being limited to the above examples. The silicon substrate 310 can be formed to have a thickness of 50 to 700 μm.

[0114] Further, the protective film 320 can be a SiNx inorganic film having high blocking properties and excellent adhesion. The SiNx inorganic film can be deposited using a vacuum sputter, and can be deposited to have a thickness of about 10 to 50 nm, and preferably, about 30 nm.

[0115] Also, the conductive layer 330 can be formed of TiN or Ti-Cu, and can be used without being limited to the above-described examples as long as it is a material that can impart conductivity to the silicon substrate 310. Among them, when the conductive layer 330 is formed of TiN, the TiN layer can be deposited using a vacuum sputter, and can be deposited at a thickness of about 100 to 400 nm, preferably about 200 nm. Also, when the conductive layer 330 is formed of Ti-Cu, a Ti layer is first deposited (in order to secure silicon-Cu adhesion), and a Cu layer is secondly deposited (in order to secure low electrical conductivity). The Ti layer and the Cu layer can be deposited using a vacuum sputter. The Ti layer can be deposited at a thickness of about 10 to 50 nm, preferably about 30 nm. The Cu layer can be deposited at a thickness of about 100 to 300 nm, preferably about 200 nm.

[0116] After that, as shown in (d) of FIG. 5, a photo (Photo) pattern layer 380 is formed on the conductive layer 330 deposited thereon.

[0117] The photo pattern layer 380 is made by thickly applying a photo resist, and forms the Invar plating layer 340 described later at a portion where a pattern is opened. That is, such a photo pattern layer 380 is formed at positions of the pattern hole 370 and the dummy hole 360.

[0118] After that, as shown in (e) of FIG. 5, the Invar plating layer 340 is deposited on the conductive layer 330 on which the photo pattern layer 380 is formed.

[0119] Among them, the Invar plating layer 340 is formed at a portion where a pattern is opened in the photo pattern layer 380, and the photo pattern layer 380 is removed.

[0120] Through this process, the Invar plating layer 340 naturally includes the pattern hole 370 and the dummy hole 360.

[0121] In order to achieve high resolution of 3000 PPI or more, the diameter of the pattern hole 370 can be about 3 μm or less, and can be processed at a pitch of 8 μm or less. Such a pattern hole 370 can be formed in a substantially conical shape, and can provide a path through which the organic material source 410 of the deposition source supply part 400 can pass. The pattern hole 370 can be clustered to be formed at a central portion of the Invar plating layer 340.

[0122] The dummy hole 360 is formed in a state of surrounding the clustered pattern hole 370. The dummy hole 360 is formed at a region from an outermost portion of the clustered pattern hole 370 to the support portion 312 of the silicon substrate 310 described later.

[0123] Also, the individual virtual holes 360 are formed in a substantially elliptical shape having a long axis and a short axis. Also, the individual virtual holes 360 are arranged so as to be spaced apart from adjacent virtual holes 360 in the long axis direction, and a plurality of virtual hole rows 360 are arranged in the radial direction of the silicon substrate 310. Also, the spaced apart virtual hole rows 360 are arranged so that the long axes of adjacent individual virtual holes 360 are offset in the radial direction.

[0124] The above-described Invar alloy plating layer 340 can be formed by electroplating a binary or ternary alloy having a coefficient of thermal expansion (CTE) of 3 PPM / °C or less, and can be electroplated to a thickness of 2 to 5 μm. Also, since electroplating is used, the thickness deviation can be ±0.3 μm.

[0125] At this time, the deposited Invar alloy plating layer 340 can be subjected to heat treatment. The above-described method and effects of the heat treatment have been described, and thus will be omitted here.

[0126] After that, as shown in (f) of FIG. 5, the silicon substrate 310 is removed from the lower protective film 320, and the protective film 320 is removed from the center region of the surface shape in which the opening portion 311 is to be formed and the peripheral region in which the alignment hole 350 is to be formed by hole formation, and a portion of the lower surface of the silicon substrate 310 is exposed.

[0127] After that, as shown in (g) of FIG. 5, back etching is performed on the lower surface of the silicon substrate 310, and the center region of the silicon substrate 310 is removed by surface formation, and the peripheral region is removed by hole formation, thereby forming the opening portion 311 and the alignment hole 350.

[0128] The center region removed from the silicon substrate 310 by the back etching forms the opening portion 311, and the silicon substrate 310 of the region not removed from the peripheral region forms the support portion 312, and the alignment hole 350 is formed in the hole shape in the peripheral support portion 312.

[0129] The support portion 312 formed by the back etching directly functions as a frame supporting the Invar alloy plating layer 340. Also, the opening portion 311 formed on the inner side of the support portion 312 functions to directly expose the Invar alloy plating layer 340 in the downward direction.

[0130] Further, by the back etching process, since the edge (support portion 312) of the silicon substrate 310 replaces the conventional bonding type frame, the process of stretching the Invar alloy plating layer on the additional bonding type frame and the process of bonding the Invar alloy plating layer to the frame by welding can be omitted.

[0131] At this time, the inner side of the support portion 312 of the silicon substrate 310 can be formed in an inclined shape, and more accurately, can be formed in a tapered shape.

[0132] After that, as shown in (h) of FIG. 5, dry etching is performed on the conductive layer 330 and the protective film 320 in the open portion 311, whereby the silicon substrate 310 is removed at the positions of the virtual holes 360 and the pattern holes 370 in the open portion 311, and dry etching is performed on the invar plated layer 340, the conductive layer 330 and the protective film 320 in the support portion 312 to pass through the positions of the alignment holes 350.

[0133] The above dry etching process can be implemented by processing holes using a Pico Laser or etching holes using a Plazma.

[0134] In the etching process for the lower back surface of the silicon substrate 310 (see (g) of FIG. 5) and the dry etching process for the conductive layer 330 and the protective film 320 (see (h) of FIG. 5), the order is shown in the drawing in which the dry etching process is performed after the back surface etching process, but conversely, the dry etching process can be performed first and then the back surface etching process.

[0135] The FMM 300 can be manufactured by the process of the second embodiment.

[0136] First, the FMM 300 manufactured according to the embodiment of the present application has a structure in which the invar plated layer 340 is formed directly on the upper surface of the silicon substrate 310, and the silicon substrate 310 replaces the frame.

[0137] Looking at the structure in more detail, the protective film can be deposited on the upper and lower surfaces of the silicon substrate 310.

[0138] Further, the conductive layer 330 can be deposited on the upper surface of the silicon substrate 310 on which the protective film 320 is deposited on both the upper and lower surfaces.

[0139] Further, the invar plated layer 340 can be deposited on the conductive layer 330 deposited on the upper surface.

[0140] In this case, the invar plated layer 340 deposited can be subjected to heat treatment.

[0141] Further, the lower surface of the silicon substrate 310 is subjected to back surface etching, the central region of the silicon substrate 310 is removed from the surface shape, the silicon substrate 310 of the portion which is not removed from the peripheral region forms the support portion 312, and the alignment holes 350 in the form of holes are formed in the support portion 312 of the periphery.

[0142] The support portion 312 manufactured by the back surface etching directly functions as a frame which supports the invar plated layer 340. Further, the open portion 311 formed on the inner side of the support portion 312 functions to directly expose the invar plated layer 340 in the downward direction.

[0143] At this time, the inner side of the support portion 312 of the silicon substrate 310 can be formed in an inclined shape, more precisely, in a tapered shape.

[0144] The invar plating layer 340, the conductive layer 330, and the protective film 320 disposed at the center of the open portion 311 of the silicon substrate 310 can be formed in a plurality of pattern holes 370 by the penetration shape clustering.

[0145] Also, from the outermost portion of the pattern holes 370 clustered in the pattern holes 370 surrounding the cluster to the area of the support portion 312, a plurality of virtual holes 360 can be formed by the penetration shape clustering.

[0146] As described above, the best mode is disclosed in the drawings and the specification. In this case, specific terms are used, but they are only for the purpose of explaining the present application, and are not used to limit the meaning or to limit the scope of the present application described in the claims. Therefore, as long as it is a person skilled in the art to which the present application belongs, it should be understood that various modifications and equivalent embodiments can be made therefrom. Therefore, the true technical protection scope of the present application should depend on the technical idea of the appended claims.

Claims

1. A method for manufacturing an FMM, characterized in that: include: Step (a), depositing a protective film on the upper and lower surfaces of the silicon substrate; Step (b), depositing a conductive layer on the silicon substrate with protective films deposited on the upper and lower surfaces; Step (c), depositing an Invar alloy coating on the conductive layer deposited thereon; Step (d) of removing a portion of the underlying protective film and performing back etching on the lower surface of the silicon substrate to remove a central region of the silicon substrate in a surface shape to form an opening, using the unremoved peripheral region of the silicon substrate to form a support portion while removing the peripheral region of the silicon substrate in a hole shape to form an alignment hole; as well as Step (e) is to dry-etch the Invar alloy coating, the conductive layer and the protective film exposed in the opening to form pattern holes clustered in the center of the opening and clustered virtual holes surrounding the clustered pattern holes, while penetrating the position of the alignment holes.

2. A method for manufacturing an FMM, characterized in that: include: Step (A), depositing a protective film on the upper and lower surfaces of the silicon substrate; Step (B), depositing a conductive layer on the silicon substrate with protective films deposited on the upper and lower surfaces; Step (C), forming a light pattern layer on the conductive layer deposited thereon at positions of the pattern holes clustered at the center and the virtual holes of the cluster surrounding the clustered pattern holes; Step (D), depositing an Invar alloy coating on the conductive layer having the optical pattern layer formed thereon; Step (E) of removing a portion of the underlying protective film and performing back etching on the lower surface of the silicon substrate to remove a central region of the silicon substrate in a surface shape to form an opening, using the unremoved peripheral region of the silicon substrate to form a support portion while removing the peripheral region of the silicon substrate in a hole shape to form an alignment hole; as well as Step (F) is to perform dry etching on the conductive layer and the protective film exposed in the opening portion, penetrate the pattern hole and the virtual hole position in the opening portion, and simultaneously penetrate the Invar alloy plating layer, the conductive layer and the protective film in the supporting portion to penetrate the position of the alignment hole.

3. The method for manufacturing an FMM according to claim 1 or 2, wherein: The silicon substrate is a silicon wafer or a quartz wafer and is formed with a thickness of 50 to 700 μm.

4. The method for manufacturing an FMM according to claim 1 or 2, wherein: The protective film is a SiNx inorganic film, which is deposited with a thickness of 10 to 50 μm.

5. The method for manufacturing an FMM according to claim 1 or 2, wherein: The conductive layer is formed of TiN or Ti—Cu and is deposited with a thickness of 100 to 400 μm.

6. The method for manufacturing an FMM according to claim 1 or 2, wherein: The invar alloy coating is formed of an invar alloy (Ni-Fe) or a super invar alloy (Ni-Fe-Co) having a thermal expansion coefficient (CTE) of 3 PPM / °C or less, and is electroplated to a thickness of 2 to 5 μm.

7. The method for manufacturing an FMM according to claim 1 or 2, wherein: The inner side of the support portion that defines the open portion is formed in a tapered shape.

8. The method for manufacturing an FMM according to claim 1 or 2, wherein: The pattern holes have a diameter of 3 μm or less and are processed with a pitch of 8 μm or less.

9. The method for manufacturing an FMM according to claim 1 or 2, wherein: The virtual hole is formed in the form of an elliptical through-hole with a longer major axis and a shorter minor axis. Individual virtual holes are arranged along the major axis direction and separated from adjacent virtual holes. Multiple virtual hole columns are arranged along the radial direction of the silicon substrate. The separated virtual hole columns are arranged along the radial direction so that the major axes of adjacent individual virtual holes are staggered.

10. The method for manufacturing an FMM according to claim 1 or 2, wherein: The virtual holes and the pattern holes are formed simultaneously, or the virtual holes are formed first and then the pattern holes.

11. The method for manufacturing an FMM according to claim 1 or 2, wherein: The Invar alloy plating layer formed on the conductive layer is heat-treated before the backside etching process.

12. An FMM manufactured by the method for manufacturing an FMM according to claim 1 or 2, characterized in that: include: Silicon substrate; A protective film is deposited on the upper and lower surfaces of the silicon substrate; A conductive layer is deposited on the silicon substrate with protective films deposited on the upper and lower surfaces; Invar alloy coating, deposited on the conductive layer deposited above, The central area of ​​the lower surface of the silicon substrate is removed from the surface to form an open portion, and the silicon substrate in the peripheral area that is not removed forms a supporting portion. A plurality of pattern holes are formed by clustering through shapes at the center of the opening portion, and a plurality of virtual holes are formed by clustering through shapes from the outermost portion of the pattern holes clustered in the form of surrounding the clustered pattern holes to the area of ​​the support portion.

13. The FMM according to claim 12, wherein: The inner side of the support portion in the silicon substrate is formed in a tapered shape.

14. The FMM according to claim 12, wherein: An alignment hole is formed in the support portion of the silicon substrate, and the alignment hole passes through the protective film, the conductive layer, and the Invar alloy plating layer including the support portion in the vertical direction.

Images