Wiring board and electronic module

Abstract

A wiring board according to one embodiment of the present invention has a first resin board. The first resin board has a first resin layer and an electrode layer positioned on the first resin layer. The electrode layer has a first conductor pad, a second conductor pad, a third conductor pad, and a first line conductor. The third conductor pad is positioned apart from the second conductor pad by a first section. The first line conductor passes through the first section and is connected to the first conductor pad. The first line conductor has a first portion passing through at least the first section and a second portion connected to the first portion. The width of the first portion is smaller than the width of the second portion.

Description

Wiring board and electronic module

[0001] The present disclosure relates to a wiring board and an electronic module.

[0002] 2. Description of the Related Art Conventionally, there is known a technique for mounting electronic components on a motherboard via a wiring substrate such as a relay substrate or base substrate called an interposer (see, for example, Patent Document 1).

[0003] JP 2023-083003 A

[0004] A wiring board according to the present disclosure has a first resin substrate, the first resin substrate having a first resin layer and an electrode layer located on the first resin layer, the electrode layer having a first conductor pad, a second conductor pad, a third conductor pad located a first section away from the second conductor pad, and a first line conductor passing through the first section and connected to the first conductor pad, the first line conductor having a first portion passing through at least the first section and a second portion connected to the first portion, and the width of the first portion being smaller than the width of the second portion.

[0005] Furthermore, a wiring board according to the present disclosure includes a first resin substrate and a first region for bonding an electronic component, the first resin substrate including a first resin layer and an electrode layer located on the first resin layer, the electrode layer including a first conductor pad located within the first region in a planar view and a first line conductor connected to the first conductor pad, the first line conductor including a first portion located within the first region in a planar view and a second portion connected to the first portion and located outside the first region in a planar view, and the width of the first portion is smaller than the width of the second portion.

[0006] Furthermore, an electronic module according to the present disclosure includes a wiring board and an electronic component bonded to the wiring board.

[0007] 1 is a cross-sectional view of an electronic module according to an embodiment of the present disclosure; FIG. 2 is a perspective view of a wiring board according to the present disclosure; FIG. 3 is an enlarged plan view of an electrode layer and a ground conductor layer inside a main part B shown in FIG. 2; FIG. 4 is an enlarged perspective view of a main part A shown in FIG. 1;

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, for the sake of convenience, the figures referred to below are simplified views of the main components necessary for explaining the embodiments. Therefore, embodiments of the present disclosure may include optional components not shown in the figures referred to. Furthermore, the figures do not necessarily faithfully represent the dimensional ratios of the actual components. For convenience, directions are defined using the Cartesian coordinate system XYZ. The positive side of the X direction is the right side, the positive side of the Y direction is the front side, and the positive side of the Z direction is the top side. In this disclosure, "planar view" refers to a view from the top side of the wiring board (the positive side of the Z direction) and includes planar perspective views.

[0009] In the following description, expressions such as "constant," "orthogonal," "vertical," or "parallel" may be used. These expressions do not necessarily mean "constant," "orthogonal," "vertical," or "parallel" in their strict sense. In other words, these expressions allow for deviations due to, for example, manufacturing precision, installation precision, etc. Numerical ranges expressed using "to" include the numerical values ​​before and after the range as the lower and upper limits, respectively.

[0010] In recent years, with the increasing integration and density of electronic components, the spacing between electrodes on wiring boards has become shorter, while there is a demand for forming more electrodes on the wiring boards.

[0011] The wiring board and electronic module of the present disclosure can realize high-density wiring with reduced degradation of transmission characteristics. The wiring board and electronic module of the present disclosure will be described in detail below.

[0012] 1 and other figures, a wiring board 1 according to the present disclosure includes a first resin substrate 11. The first resin substrate 11 includes a first resin layer 71 and an electrode layer 5 located on the first resin layer 71.

[0013] As shown in FIG. 3 , the electrode layer 5 has a first conductor pad 51 and a first line conductor 54 connected to the first conductor pad 51. The first line conductor 54 has a first portion 541 and a second portion 542 connected to the first portion 541. The width of the first portion 541 is smaller than the width of the second portion 542. The width of the first portion 541 is, for example, 1 to 6 μm. The width of the second portion 542 is, for example, 8 to 30 μm. The first portion 541 may be connected to the first conductor pad 51. The width here refers to the dimension of the first line conductor 54 in a direction perpendicular to the direction in which the first line conductor 54 extends, and in FIG. 3 , for example, refers to the dimension in the Y direction. The width here may also be rephrased as the dimension of the first line conductor 54 in the direction in which the second conductor pad 52 and the third conductor pad 53 are aligned.

[0014] The electrode layer 5 may have a second conductor pad 52 and a third conductor pad 53 spaced apart from the second conductor pad 52 by a first section s1. The dimensions of the first section s1 can be set arbitrarily, for example, to 40 to 80 μm. In this case, the first portion 541 may pass through at least the first section s1. In this way, the first portion 541 of the first line conductor 54, which has a relatively small width, passes through the first section s1 between the conductor pads, thereby narrowing the distance between the conductor pads and facilitating the formation of more electrodes. Furthermore, the first line conductor 54 also has a second portion 542, which has a relatively large width, which facilitates the attainment of good transmission characteristics. Examples of transmission characteristics include reflection characteristics, transmission characteristics, and impedance. Therefore, by having the first line conductor 54 have the first portion 541 and the second portion 542 and having the first portion 541 pass through the first section s1, high-density wiring with reduced degradation of transmission characteristics can be achieved. More specifically, impedance deviation can be reduced.

[0015] As shown in FIG. 2 , the wiring board 1 may have a first region 14 for bonding the electronic component 4. The first region 14 is a region that overlaps the electronic component 4 in a planar view when the electronic component 4 is bonded. Here, "bonding" also includes bonding via solder or the like. As shown in FIG. 3 , when the wiring board 1 has the first region 14, the first conductor pad 51 may be located within the first region 14 a in a planar view. Furthermore, at least a portion of the first portion 541 may be located within the first region 14 a in a planar view, and at least a portion of the second portion 542 may be located outside the first region 14 b in a planar view. In this way, by having at least a portion of the first portion 541, which has a relatively small width, located within the first region 14 a in a planar view, it becomes easier to form many electrodes for bonding the electronic component 4 in the first region 14. Furthermore, by having the first line conductor 54 also have the second portion 542, which has a relatively large width, it becomes easier to obtain good transmission characteristics. Therefore, the first line conductor 54 has a first portion 541 and a second portion 542, and at least a portion of the first portion 541 is located within the first region 14a in a plan view, thereby realizing high-density wiring with reduced degradation of transmission characteristics. More specifically, impedance deviation can be reduced, particularly in areas where conductor pads are densely packed. Note that "within the first region 14a in a plan view" refers to an area that overlaps with the first region 14 in a plan view. "Outside the first region 14b in a plan view" refers to an area that does not overlap with the first region 14 in a plan view.

[0016] Furthermore, compared to a configuration in which the width of the first line conductor 54 is uniformly small, a configuration in which the first line conductor 54 has a first portion 541 and a second portion 542 makes it easier to adjust the impedance while ensuring insulation between the electrode layer 5 and the ground conductor layer 66 when a ground conductor layer 66 (described later) is disposed above and / or below the electrode layer 5. Specifically, for a line conductor with a small width, it is easier to set the impedance appropriately by placing the ground conductor closer to the electrode layer 5, but placing the ground conductor too close makes it difficult to ensure insulation between the line conductor and the ground conductor. Here, in a configuration in which the first line conductor 54 has the first portion 541 and the second portion 542, by adjusting the distance between the electrode layer 5 and the ground conductor layer 66 to adjust the impedance of the second portion 542, it is possible to adjust the impedance of the entire first line conductor 54 to a certain extent while maintaining the distance enough to ensure insulation.

[0017] The conductor pads such as the first conductor pad 51, the second conductor pad 52, and the third conductor pad 53 may be lands to which vias are connected, or may be electrodes for connecting to electronic components 4 if they are located on the surface layer of the wiring substrate 1.

[0018] 3 , the connection portion between the first portion 541 and the second portion 542 may be located within the first region 14a in a plan view. That is, the entire first portion 541, which has a relatively small width, may be located within the first region 14a in a plan view, and the second portion 542, which has a relatively large width, may overlap the boundary portion between the inside and outside of the first region 14 in a plan view. Stress caused by, for example, underfill is likely to concentrate at the boundary portion between the inside and outside of the first region 14 when the electronic component 4 is mounted, but the overlap of the boundary portion with the second portion 542 reduces the possibility of disconnection of the first line conductor 54.

[0019] The length of the first portion 541 may be smaller than the length of the second portion 542. Because the width of the second portion 542 is larger than the width of the first portion 541, the impedance deviation is small in the second portion 542. Therefore, by making the length of the first portion 541 smaller than the length of the second portion 542, it becomes easier to reduce the impedance deviation in the entire wiring of the first line conductor 54.

[0020] When the wavelength of a signal transmitted through the first line conductor 54 is λ, the length of the first portion 541 may be λ / 4 or less, which makes it easier to reduce the deviation in impedance.

[0021] The thickness of the first portion 541 may be within -80% of the thickness of the second portion 542, that is, the thickness of the first portion 541 may be within a range of 20 to 100% of the thickness of the second portion 542. Here, the thickness refers to the dimension in the Z direction. With this configuration, the possibility of disconnection of the first line conductor 54 in the first portion 541 is reduced compared to when the thickness of the first portion 541 is less than 20% of the thickness of the second portion 542. The thicknesses of the first portion 541 and the second portion 542 are, for example, 2 to 10 μm.

[0022] As shown in FIG. 4 , the first conductor 54 may have a diffusion-reducing layer 54a on a surface that contacts the first resin layer 71. Specifically, when the side and bottom surfaces of the first conductor 54 contact the first resin layer 71, the side and bottom surfaces of the first conductor 54 may have the diffusion-reducing layer 54a. The diffusion-reducing layer 54a can reduce diffusion of metal components contained in the first conductor 54 into the first resin layer 71. Therefore, by providing the diffusion-reducing layer 54a on the surface of the first conductor 54 that contacts the first resin layer 71, the possibility of electrical conduction between the first conductor 54 and other surrounding conductors via metal components diffused from the first conductor 54 can be reduced. The diffusion-reducing layer 54a may contain any of Cr, Ti, Ni, and compounds containing two or more of these elements. This further reduces diffusion of metal components contained in the first conductor 54. The diffusion-reducing layer 54a may also be referred to as a seed layer.

[0023] The first resin substrate 11 may have a second resin layer 72 in contact with the first resin layer 71. This configuration may improve the strength of the wiring substrate 1. The second resin layer 72 may be located above the first resin layer 71 (positive side in the Z direction) and in contact with the electrode layer 5 as shown in FIG. 1 etc., or may be located below the first resin layer 71 (negative side in the Z direction).

[0024] The first resin substrate 11 may have a third resin layer 73. In the present disclosure, the third resin layer 73 refers to a resin layer other than the first resin layer 71 or the second resin layer 72, and is not limited to a resin layer included in the first resin substrate 11. Having the third resin layer 73 in the first resin substrate 11 makes it easier to design the wiring substrate 1 with a multilayer wiring structure, thereby improving the degree of freedom in wiring design and enabling higher wiring density. In the first resin substrate 11, the third resin layer 73 may be located on the opposite side of the first resin layer 71 from the second resin layer 72, as shown in FIG. 1 and other figures. The first resin substrate 11 may have one or more third resin layers 73.

[0025] When the first resin substrate 11 has the second resin layer 72 in contact with the electrode layer 5, the surface roughness of the surface of the electrode layer 5 in contact with the first resin layer 71 may be greater than the surface roughness of the surface of the electrode layer 5 in contact with the second resin layer 72. This configuration improves the bonding strength between the electrode layer 5 and the first resin layer 71.

[0026] When the first resin substrate 11 has the second resin layer 72, the surface roughness of the first resin layer 71 in contact with the electrode layer 5 may be greater than the surface roughness of the first resin layer 71 in contact with the second resin layer 72. This configuration improves the bonding strength between the electrode layer 5 and the first resin layer 71.

[0027] The surface roughness of each member can be measured, for example, by a surface roughness measuring instrument SURFCOM 1400D (manufactured by Tokyo Seimitsu Co., Ltd.).

[0028] Resin layers such as the first resin layer 71, the second resin layer 72, and the third resin layer 73 are primarily composed of resin. In the present disclosure, "primary component" refers to a component that accounts for 30% or more by volume. Examples of resins include epoxy resin, acrylic resin, polycarbonate resin, polyimide resin, olefin resin, polyphenylene resin, polyphenylene ether resin, polytetrafluoroethylene resin, and other fluororesins. Because fine wiring patterns can be easily formed in resin layers, having a wiring board with a resin layer such as the first resin layer improves the freedom of wiring design and enables higher wiring density.

[0029] The electrode layer 5 may be located closer to the electronic component bonding side (positive side in the Z direction) than the center in the thickness direction (Z direction) of the wiring board 1. This configuration makes it possible to achieve high-density wiring with reduced deterioration in transmission characteristics on the electronic component bonding side where a finer wiring pattern is required.

[0030] 3, the electrode layer 5 may have one or more fourth conductor pads 56. The fourth conductor pads 56 are conductor pads other than the first conductor pad 51, the second conductor pad 52, and the third conductor pad 53. The fourth conductor pad 56 may be located within the first region 14a in plan view.

[0031] As shown in FIG. 3 , the electrode layer 5 may have one or more second line conductors 57. The second line conductor 57 is a line conductor other than the first line conductor 54. The second line conductor 57 may be connected to a fourth conductor pad 56. The second line conductor 57 may have a third portion and a fourth portion connected to the third portion. The width of the third portion may be smaller than the width of the fourth portion. The third portion may pass through the first section s1 alongside the first portion. This may enable further density increase while reducing deterioration of transmission characteristics. The third portion may be connected to the fourth conductor pad 56. Furthermore, at least a portion of the third portion may be located within the first region 14 a in a plan view, and at least a portion of the fourth portion may be located outside the first region 14 b in a plan view. This may further reduce impedance deviation, particularly in areas where conductor pads are densely packed. The connection portion between the third portion and the fourth portion may be located within the first region 14 a in a plan view. This reduces the possibility of the second line conductor 57 being broken.

[0032] The first resin layer 71 may contain first silica particles. Silica particles usually have a lower thermal expansion coefficient than resin. Therefore, by including the first silica particles in the first resin layer 71, the thermal expansion coefficient of the first resin layer 71 can be reduced. This allows the thermal expansion coefficient of the first resin layer 71 to be closer to the thermal expansion coefficient of the conductor that constitutes the electrode layer, etc.

[0033] The maximum particle size of the first silica particles may be equal to or less than half the width of the first portion 541. This makes it less likely that the first silica particles will interfere with the formation of the first line conductor 54, making it easier to stably form the first line conductor 54 in the first resin layer 71. Note that the "maximum particle size" in this disclosure refers to the maximum dimension in any direction, and corresponds to the diameter when the particles are spherical.

[0034] When the first resin substrate 11 has a second resin layer 72, the second resin layer 72 may contain second silica particles. In this case, the maximum particle size of the second silica particles may be larger than the maximum particle size of the first silica particles. As the particle size of the silica particles increases, the volume ratio of the silica particles in the resin layer increases. In other words, as the particle size of the silica particles increases, the bulk density of the silica particles in the resin layer decreases. This reduces the dielectric tangent of the resin layer containing the silica particles, thereby reducing signal transmission loss in the line conductor near the resin layer. Therefore, by increasing the particle size of the second silica particles contained in the second resin layer 72, signal transmission loss in the electrode layer 5 can be reduced while reducing the particle size of the first silica particles contained in the first resin layer 71.

[0035] The first resin substrate 11 may have one or more ground conductor layers 66 located around the electrode layer 5. This strengthens the ground potential. The periphery of the electrode layer 5 refers to positions that are not in contact with the electrode layer 5, such as above, below, or to the sides of the electrode layer 5.

[0036] 1 and 4, the ground conductor layer 66 may be located above and / or below the electrode layer 5. "Above the electrode layer 5" refers to, for example, above the second resin layer 72 located above the electrode layer 5, at a position overlapping the electrode layer 5 in a plan view. "Below the electrode layer 5" refers to, for example, below the first resin layer 71 located below the electrode layer 5, at a position overlapping the electrode layer 5 in a plan view.

[0037] 3, the ground conductor layer 66 may be located to the side of the electrode layer 5. To the side of the electrode layer 5 means, for example, on the first resin layer 71, and in a position that does not overlap with the electrode layer 5 in a plan view.

[0038] The ground conductor layer 66 may be located around the first portion 541 and / or the second portion 542. That is, the ground conductor layer 66 may be located not only around the first portion 541 but also around the second portion 542.

[0039] The wiring board 1 may have a first support substrate 13 bonded to the first resin substrate 11. This configuration improves the strength of the wiring board 1. The first support substrate 13 is located, for example, on the opposite side of the first resin substrate 11 from the side where the electronic components are bonded (the lower side in the Z direction).

[0040] 5 and 6 , the first support substrate 13 may be directly bonded to the first resin substrate 11 without using a bonding material layer 74 or the like. In other words, the first support substrate 13 may be in contact with the first resin substrate 11. This configuration can reduce the thickness of the wiring board 1 when the wiring board 1 includes the first support substrate 13, and can simplify the manufacturing process.

[0041] 1 , the first support substrate 13 may be bonded to the first resin substrate 11 via a bonding material layer 74. In this case, the electrode 61 located on the first resin substrate 11 may be electrically bonded to the electrode 61 located on the first support substrate 13 via a bonding conductor 64. The bonding conductor 64 is, for example, solder.

[0042] The first support substrate 13 may have one or more core layers 76 containing glass or ceramic as a main component. This configuration further improves the strength of the wiring substrate 1. The glass may be amorphous glass or crystallized glass. Examples of crystallized glass include SiO ２ -CaO system, MgO-B ２ O ３ System, La ２ O ３ -B ２ O ３ -MgO system, La ２ O ３ -B ２ O ３ -ZnO-based, SiO ２-CaO-ZnO system, etc. The core layer 76 may contain glass cloth. Examples of ceramics include aluminum oxide sintered body, aluminum nitride sintered body, silicon carbide sintered body, and mullite sintered body. The ceramic may be LTCC (Low Temperature Co-fired Ceramics). LTCC has a relatively low dielectric constant and excellent high frequency characteristics.

[0043] The first support substrate 13 may have one or more third resin layers 73 .

[0044] 5 and 6 , the wiring board 1 may have a second resin substrate 12 located on the opposite side of the first resin substrate 11 with the first support substrate 13 in between. The second resin substrate 12 may have one or more third resin layers 73.

[0045] Even when the wiring board 1 includes the second resin substrate 12, the electrode layer 5 including the first line conductor 54 and the like may be included only in the first resin substrate 12. In other words, the second resin substrate 12 does not need to include the first line conductor 54 including the first portion 541 and the second portion 542.

[0046] The wiring board 1 may have electrodes 61 on its surface or inside. The electrodes 61 may be lands, pads, surface wiring, inner layer wiring, etc. The wiring board 1 may have resin layer vias 62 that penetrate a resin layer such as the first resin layer 71, or core layer vias 63 that penetrate a core layer 76. The electrodes 61, resin layer vias 62, and core layer vias 63 may be electrically connected to the electrode layer 5, the ground conductor layer 66, or other conductor layers. The numbers of the electrodes 61, resin layer vias 62, and core layer vias 63 are not limited, and there may be more than one of each.

[0047] When there are multiple core layers 76, the core layer vias 63 may be so-called through-hole vias that penetrate the multiple core layers 76 together, or may be vias that connect to inner layer wiring midway through the multiple core layers 76. When there are multiple core layers 76, internal ground conductors 8 may be located between the core layers 76 as shown in Figures 1 and 6. This makes it easier to adjust the impedance in the vias, and improves high-frequency characteristics.

[0048] Examples of materials for the conductors such as the electrode layer 5, the electrode 61, the resin layer via 62, the core layer via 63, the bonding conductor 64, the ground conductor layer 66, and the internal ground conductor 8 include copper, silver, tungsten, molybdenum, manganese, palladium, gold, platinum, nickel, cobalt, chromium, bismuth, antimony, tin, indium, and alloys thereof. The materials for each conductor may be the same or different from each other.

[0049] There are no particular limitations on the manufacturing method of the wiring board 1. For example, the electrode layer 5 having the first portion 541 of the conductor, which has a relatively small width, may be formed by a damascene method, which is easy to form a fine conductor, and the ground conductor layer 66 and other layers other than the electrode layer 5 may be formed by a semi-additive method, which is advantageous in terms of cost. Even in this case, the ground conductor layer 66 located next to the electrode layer 5 may be formed by the damascene method simultaneously with the electrode layer 5.

[0050] The wiring board 1 of the present disclosure may be used as a base substrate in an electronic module 100, or may be used as an interposer as shown in FIG. 1 . When the wiring board 1 is used as an interposer as shown in FIG. 1 , the wiring board 1 may be bonded to a base substrate 2. The base substrate 2 may have a fourth resin substrate 21, a fifth resin substrate 22, and a third support substrate 23. The fourth resin substrate 21 and the fifth resin substrate 22 may have one or more third resin layers 73. The third support substrate 23 may have one or more core layers 76. The base substrate 2 may have an electrode 61, a resin layer via 62, a core layer via 63, and an internal ground conductor 8. The wiring board 1 may be bonded directly to the base substrate 2 without using a bonding material layer 74 or the like, or may be bonded via a bonding material layer 74 as shown in FIG. 1 . When the wiring board 1 is connected to the base substrate 2 via a bonding material layer 74, the electrode 61 located on the base substrate 2 may be electrically connected to the electrode 61 located on the wiring board 1 via a bonding conductor 64.

[0051] Furthermore, as shown in FIG. 5 , the wiring board 1 of the present disclosure may have an interposer 3 bonded to the first resin substrate 11, and the base substrate and the interposer may be integrated into one component. In this case, the interposer 3 may have a third resin substrate 31 similar to the first resin substrate 11 and a second support substrate 33 similar to the first support substrate 13. The third resin substrate 31 may or may not have an electrode layer 5. The second support substrate 33 may be bonded directly to the third resin substrate 31 without a bonding material layer 74 or the like, or may be bonded via a bonding material layer 74 as shown in FIG. 5 . The interposer 3 may be bonded directly to the first resin substrate 11 without a bonding material layer 74 or the like, or may be bonded via a bonding material layer 74 as shown in FIG. 5 . When the interposer 3 is connected to the first resin substrate 11 via the bonding material layer 74, the electrodes 61 located on the first resin substrate 11 may be electrically bonded to the electrodes 61 located on the interposer 3 via bonding conductors 64.

[0052] Furthermore, since the wiring board 1 of the present disclosure has the above-described configuration, it may be used as a substrate in an electronic module 100 that does not require an interposer, as shown in FIG.

[0053] 1, 5, and 6, an electronic module 100 may include a wiring board 1 and an electronic component 4 bonded to the wiring board 1. The electronic component 4 may be bonded to a first resin substrate 11 included in the wiring board 1 as shown in FIGS. 1 and 6, or may be bonded to an interposer 3 included in the wiring board 1 as shown in FIG.

[0054] The electronic component 4 is not particularly limited and may be, for example, an IC chip, a chiplet, or the like. The electronic module 100 may have one or more electronic components 4. The electronic component 4 is joined to the wiring substrate 1 by flip-chip bonding, for example, via solder. The electronic component 4 may be sealed with underfill. The electronic module 100 is used by being mounted on, for example, a motherboard.

[0055] Further embodiments of the wiring board and electronic module according to the present disclosure are described below. (1) One embodiment of the wiring board according to the present disclosure includes a first resin substrate, wherein the first resin substrate includes a first resin layer and an electrode layer located on the first resin layer, wherein the electrode layer includes a first conductor pad, a second conductor pad, a third conductor pad located a first section away from the second conductor pad, and a first line conductor passing through the first section and connected to the first conductor pad, wherein the first line conductor has a first portion passing through at least the first section and a second portion connected to the first portion, and wherein the width of the first portion is smaller than the width of the second portion.

[0056] (2) One embodiment of a wiring board according to the present disclosure includes a first resin substrate and a first region for bonding an electronic component, the first resin substrate including a first resin layer and an electrode layer located on the first resin layer, the electrode layer including a first conductor pad located within the first region in a planar view and a first line conductor connected to the first conductor pad, the first line conductor including a first portion located within the first region in a planar view and a second portion connected to the first portion and located outside the first region in a planar view, and the width of the first portion is smaller than the width of the second portion.

[0057] (3) One embodiment of the wiring board according to the present disclosure is the wiring board according to (2) above, wherein a connection portion between the first portion and the second portion is located within the first region in a plan view.

[0058] (4) One embodiment of the wiring board according to the present disclosure is the wiring board according to any one of (1) to (3) above, further comprising a first support substrate directly bonded to the first resin substrate.

[0059] (5) One embodiment of the wiring board according to the present disclosure is the wiring board of any one of (1) to (3) above, further comprising a first support substrate bonded to the first resin substrate via a bonding material layer.

[0060] (6) One embodiment of the wiring board according to the present disclosure is the wiring board of any one of (1) to (5) above, further comprising a first support substrate bonded to the first resin substrate, and the first support substrate has a core layer containing glass or ceramic as a main component.

[0061] (7) One embodiment of the wiring board according to the present disclosure is the wiring board according to any one of (1) to (6) above, wherein the first resin layer contains first silica particles.

[0062] (8) One embodiment of the wiring board according to the present disclosure is the wiring board according to (7) above, in which the maximum particle size of the first silica particles is equal to or less than half the width of the first portion.

[0063] (9) One embodiment of the wiring board according to the present disclosure is the wiring board of any one of (1) to (8) above, wherein the first resin substrate further has a second resin layer in contact with the first resin layer.

[0064] (10) One embodiment of the wiring board according to the present disclosure is the wiring board according to any one of (1) to (9) above, wherein the length of the first portion is shorter than the length of the second portion.

[0065] (11) One embodiment of the wiring board according to the present disclosure is the wiring board of any one of (1) to (10) above, wherein the first resin substrate further has a ground conductor layer located around the electrode layer.

[0066] (12) One embodiment of the wiring board according to the present disclosure is the wiring board according to (11) above, wherein the ground conductor layer is located above and / or below the electrode layer.

[0067] (13) One embodiment of the wiring board according to the present disclosure is the wiring board of any one of (1) to (12) above, wherein the first line conductor has a diffusion-reducing layer on a surface that contacts the first resin layer, and the diffusion-reducing layer contains any of Cr, Ti, Ni, and a compound that combines two or more of these.

[0068] (14) One embodiment of the wiring board according to the present disclosure is the wiring board according to any one of (1) to (13) above, wherein the thickness of the first portion is within −80% of the thickness of the second portion.

[0069] (15) One embodiment of the wiring board according to the present disclosure is the wiring board of (9) above, wherein the surface roughness of the surface of the electrode layer that contacts the first resin layer is greater than the surface roughness of the surface of the electrode layer that contacts the second resin layer.

[0070] (16) One embodiment of the wiring board according to the present disclosure is the wiring board of (9) or (15) above, wherein the surface roughness of the surface of the first resin layer that contacts the electrode layer is greater than the surface roughness of the surface of the first resin layer that contacts the second resin layer.

[0071] (17) One embodiment of the wiring board according to the present disclosure is the wiring board according to any one of (1) to (16) above, further comprising an interposer bonded to the first resin substrate.

[0072] (18) One embodiment of the wiring board according to the present disclosure is the wiring board of any one of (9), (15), and (16) above, wherein the first resin layer contains first silica particles, the second resin layer contains second silica particles, and the maximum particle size of the second silica particles is larger than the maximum particle size of the first silica particles.

[0073] (19) An embodiment of an electronic module according to the present disclosure includes the wiring board according to any one of (1) to (18) above, and an electronic component joined to the wiring board.

[0074] (20) An embodiment of an electronic module according to the present disclosure includes the wiring board according to (17) above, and an electronic component joined to the interposer.

[0075] In addition, the details shown in the above embodiments can be modified as appropriate without departing from the spirit of the present disclosure. The scope of the present invention includes the scope of the invention described in the claims and its equivalents. Various combinations of the embodiments are not limited to the examples of the above embodiments. Furthermore, combinations of the embodiments with each other are also possible.

[0076] REFERENCE SIGNS LIST 1 wiring substrate 11 first resin substrate 12 second resin substrate 13 first support substrate 14 first region 14a inside first region 14b outside first region 2 base substrate 21 fourth resin substrate 22 fifth resin substrate 23 third support substrate 3 interposer 31 third resin substrate 33 second support substrate 4 electronic component 5 electrode layer 51 first conductor pad 52 second conductor pad 53 third conductor pad 54 first line conductor 541 first portion 542 second portion 54a diffusion reduction layer 56 fourth conductor pad 57 second line conductor s1 first section 61 electrode 62 resin layer via 63 core layer via 64 joining conductor 66 ground conductor layer 71 first resin layer 72 second resin layer 73 third resin layer 74 joining material layer 76 core layer 8 Internal ground conductor 100 Electronic module

Claims

1. A wiring board comprising a first resin substrate, the first resin substrate comprising a first resin layer and an electrode layer located on the first resin layer, the electrode layer comprising: a first conductor pad, a second conductor pad, a third conductor pad located a first section away from the second conductor pad, and a first line conductor passing through the first section and connected to the first conductor pad, the first line conductor having a first portion passing through at least the first section and a second portion connected to the first portion, and the width of the first portion being smaller than the width of the second portion.

2. A wiring board having a first resin substrate and a first region for bonding an electronic component, wherein the first resin substrate has a first resin layer and an electrode layer located on the first resin layer, wherein the electrode layer has a first conductor pad located within the first region in a planar view and a first line conductor connected to the first conductor pad, wherein the first line conductor has a first portion located within the first region in a planar view and a second portion connected to the first portion and located outside the first region in a planar view, and wherein the width of the first portion is smaller than the width of the second portion.

3. The wiring board according to claim 2, wherein a connection portion between the first portion and the second portion is located within the first region in a plan view.

4. The wiring board according to any one of claims 1 to 3, further comprising a first support substrate directly bonded to the first resin substrate.

5. The wiring board according to any one of claims 1 to 3, further comprising a first support substrate bonded to the first resin substrate via a bonding material layer.

6. The wiring board according to any one of claims 1 to 5, further comprising a first support substrate bonded to said first resin substrate, said first support substrate having a core layer containing glass or ceramic as a main component.

7. The wiring board according to any one of claims 1 to 6, wherein the first resin layer contains first silica particles.

8. The wiring board according to claim 7, wherein the maximum particle size of the first silica particles is equal to or less than half the width of the first portion.

9. The wiring board according to any one of claims 1 to 8, wherein the first resin substrate further comprises a second resin layer in contact with the first resin layer.

10. The wiring board according to any one of claims 1 to 9, wherein the length of the first portion is shorter than the length of the second portion.

11. The wiring board according to any one of claims 1 to 10, wherein the first resin substrate further comprises a ground conductor layer positioned around the electrode layer.

12. The wiring board according to claim 11, wherein the ground conductor layer is located above and / or below the electrode layer.

13. A wiring board according to any one of claims 1 to 12, wherein the first line conductor has a diffusion-reducing layer on a surface in contact with the first resin layer, and the diffusion-reducing layer contains any of Cr, Ti, Ni, and compounds combining two or more of these.

14. The wiring board according to any one of claims 1 to 13, wherein the thickness of the first portion is within -80% of the thickness of the second portion.

15. The wiring board according to claim 9, wherein the surface roughness of the surface of the electrode layer that contacts the first resin layer is greater than the surface roughness of the surface of the electrode layer that contacts the second resin layer.

16. A wiring board according to claim 9 or 15, wherein the surface roughness of the surface of the first resin layer that contacts the electrode layer is greater than the surface roughness of the surface of the first resin layer that contacts the second resin layer.

17. The wiring board according to any one of claims 1 to 16, further comprising an interposer bonded to the first resin substrate.

18. A wiring board as described in any one of claims 9, 15 and 16, wherein the first resin layer contains first silica particles, the second resin layer contains second silica particles, and the maximum particle size of the second silica particles is larger than the maximum particle size of the first silica particles.

19. An electronic module comprising the wiring board according to any one of claims 1 to 18 and an electronic component joined to the wiring board.

20. An electronic module comprising the wiring board according to claim 17 and an electronic component bonded to the interposer.

Images