Kernel based modeling of edge interactions in three-dimensional photomask transmission

Abstract

Methods for use in integrated circuit design and corresponding systems and computer- readable mediums. A method includes receiving (902) a mask pattern for a semiconductor layer. The method includes creating (904) edge grids (322, 324, 326, 328, 330) corresponding to the mask pattern and creating (906) proximity grids (1002) corresponding to the mask pattern. The method includes convolving (908) each edge grid (322, 324, 326, 328, 330) and each proximity grid (1002) with a corresponding kernel (700) and summing (910) the convolutions and a rastered mask grid to produce a final mask pattern. The method includes performing (912) a simulation of a manufacturing process using the final mask pattern.

Description

KERNEL BASED MODELING OF EDGE INTERACTIONS IN THREE-DIMENSIONAL PHOTOMASK TRANSMISSIONTECHNICAL FIELD

[0001] The present disclosure is directed, in general, to integrated circuit (IC) design and in particular to photomask modeling in IC design.BACKGROUND OF THE DISCLOSURE

[0002] Optical proximity correction (OPC) requires fast but accurate modeling of the three-dimensional photomask topography. The edge-to-edge interaction within and between smaller mask features is more challenging to accurately model than the relatively isolated edges of larger features. Existing methods work well for “Manhattan” mask designs with small features that are all substantially vertically or horizontally oriented, and for curvlinear designs with larger features, but they do not work as well for curvilinear masks with small features. Improved systems are desirable.SUMMARY OF THE DISCLOSURE

[0003] Various disclosed embodiments include methods for use in integrated circuit manufacturing and corresponding systems and computer-readable mediums. A method includes receiving a mask pattern for a semiconductor layer. The method includes creating edge grids corresponding to the mask pattern and creating proximity grids corresponding to the mask pattern. The method includes convolving each edge grid and each proximity grid with a corresponding kernel, summing the results of the convolutions, and combining the summed convolutions with a rastered mask grid to produce a final mask pattern. The method includes performing a simulation of a manufacturing process for the final mask pattern.

[0004] In various embodiments, creating the edge grids by simulating each of a plurality of training mask patterns in three dimensions, creating target grids by subtracting a thin mask approximation of each mask pattern from the corresponding simulated mask pattern to produce a first array, extracting edge grids corresponding to geometry of each training mask pattern, creating a first matrix based on the geometry of each training mask pattern, a through-the-lens (TTL) target order for the geometry of each training mask pattern, and a Zernike polynomial value, and solving a linear equation based on the first array and the first matrix to produce the kernel. This can include producing the coefficients for each Zernike polynomial which define the kernels for each edge.

[0005] In various embodiments, extracting the edge grids includes calculating TTL orders for each edge grid. In various embodiments, creating the target grid includes calculating the TTL target orders for each geometry in the target grid.

[0006] In various embodiments, creating proximity grids includes blurring the edge grids directionally using a one-sided, one-dimensional function, and multiplying the blurred edge grids to create the proximity grids. In various embodiments, blurring the edge grids includes blurring vertical edges in a horizontal direction and blurring horizontal edges in a vertical direction. Various embodiments also include producing a signal corresponding to the convolution of each kernel and each grid. In various embodiments, the rastered mask grid is created by rastering the original mask pattern to a grid.

[0007] Disclosed embodiments include a computer system comprising a processor and an accessible memory, the computer system particularly configured to perform processes as disclosed herein. Disclosed embodiments include a non-transitory computer-readable medium encoded with executable instructions that, when executed, cause one or more computer systems to perform processes as disclosed herein.

[0008] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure will be described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0009] Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and / or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety ofembodiments, the appended claims may expressly limit these terms to specific embodiments.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:

[0011] FIGS. 1 and 2 illustrate aspects of a computer system that can be used to implement various embodiments disclosed herein;

[0012] FIG. 3A illustrates examples of kernels of different edge orientations in accordance with disclosed embodiments;

[0013] FIG. 3B illustrates extracted edge grids, in accordance with disclosed embodiments, corresponding to the examples of FIG. 3 A;

[0014] FIGS. 4, 5, and 6 illustrate processes in accordance with disclosed embodiments;

[0015] FIG. 7 illustrates an example of a “blurring kernel” in accordance with disclosed embodiments;

[0016] FIG. 8 illustrates an example of the calculation of left / right proximity grids in accordance with disclosed embodiments;

[0017] FIG. 9 illustrates a process in accordance with disclosed embodiments; and

[0018] FIG. 10 illustrates the calculation of signals for left / right proximity kernels in accordance with disclosed embodiments.DETAILED DESCRIPTION

[0019] FIGS. 1 through 10, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged device. The numerous innovative teachings of the present application will be described with reference to exemplary non-limiting embodiments.

[0020] IC design is typically performed using electronic design automation (EDA) tools such as the Calibre software product by Siemens. EDA products must model various aspects of the design process, including modeling the photolithographic masks used in manufacture of the IC. Some tools use the domain decomposition method with additional “crosstalk” signals to accurately model manhattan patterns with small features. ID signals can added perpendicularly to all edges to model electromagnetic mask effects for isolated edges. Then, crosstalk signals can be added based on the width of the gaps.

[0021] For curvilinear masks, an edge-only kernel domain decomposition method (DDM) can be used, as disclosed below, but this method does not account for the interaction of edges in small features. When edges are far apart, then the edge-only kernel DDM is sufficient to accurately model mask transmission because the edges are too far apart to have additional edge to edge interaction. But, for mask geometries with edges which are closer together, additional signals are needed. Further, the masking interactions become more significant as the edges move closer together.

[0022] For both manhattan and curvilinear masks, this process can be repeated for multiple sectors in the source as part of the Hybrid-Hopkins Abbe (HHA) method for optical-proximity correction (OPC), such as described in “Hybrid Hopkins-Abbe method for modeling oblique angle mask effects in OPC” by Adam, et al. (2008), incorporated herein by reference.

[0023] Disclosed embodiments improve on other techniques by providing a fast and accurate mask model for curvilinear mask designs with strong edge interactions due to small features and gaps between features.Illustrative Operating Environment

[0024] FIGS. 1 and 2 illustrate aspects of a computer system than can be used to implement various embodiments disclosed herein. The execution of various processes described herein may be implemented using computer-executable software instructions executed by one or more programmable computing devices. Because these processes may be implemented using software instructions, the components and operation of a generic programmable computer system on which various embodiments of these processes may be employed will first be described. Further, because of the complexity of some electronic design and testing processes and the large size of many circuit designs, various electronic design and testing tools are configured to operate on a computing system capable of simultaneously running multiple processing threads. The components and operation of a computer system having a host or master computer and one or more remote or slave computers therefore will be described with reference to FIG. 1. This operating environment is only one example of a suitable operating environment, however, and is not intended to suggest any limitation as to the scope of use or functionality of any implementations of the invention.

[0025] In FIG. 1, the computer system 101 includes a master computer 103. In the illustrated example, the master computer 103 is a multi-processor computer that includes a plurality of input and output devices 105 and a memory 107. The input and output devices 105 may include any device for receiving input data from or providing output data to a user. The input devices may include, for example, a keyboard, microphone, scanner or pointing device for receiving input from a user. The output devices may then include a display monitor, speaker, printer or tactile feedback device. These devices and their connections are well known in the art, and thus will not be discussed at length here.

[0026] The memory 107 may similarly be implemented using any combination of computer readable media that can be accessed by the master computer 103. The computerreadable media may include, for example, microcircuit memory devices such as readwrite memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD- ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable media may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storage devices, or any other non-transitory storage medium that can be used to store desired information. As used herein, the term "non-transitory" refers to the ability to store information for subsequent retrieval at a desired time, as opposed to propagating electromagnetic signals.

[0027] As will be discussed in detail below, the master computer 103 runs a software application for performing one or more operations according to various examples of the invention. Accordingly, the memory 107 stores software instructions 109A that, when executed, will implement a software application for performing one or more operations. The memory 107 also stores data 109B to be used with the software application. In the illustrated embodiment, the data 109B contains process data that the software application uses to perform the operations, at least some of which may be parallel.

[0028] The master computer 103 also includes a plurality of processor units 111 and an interface device 113. The processor units 111 may be any type of processor device that can be programmed to execute the software instructions 109A, but will conventionally be a microprocessor device. For example, one or more of the processor units 111 may be a commercially generic programmable microprocessor, such as Intel® Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors or Motorola 68K / Coldfire® microprocessors. Alternately or additionally, one or more of the processor units 111 may be a custom-manufactured processor, such as a microprocessor designed to optimally perform specific types of mathematical operations. The interface device 113, the processor units 111, the memory 107 and the input / output devices 105 are connected together by a bus 115.

[0029] With some implementations of the invention, the master computer 103 may employ one or more processing units 111 having more than one processor core.Accordingly, FIG. 2 illustrates an example of a multi-core processor unit 111 that may be employed with various embodiments of the invention. As seen in this figure, the processor unit 111 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those of ordinary skill in the art, a computing engine contains logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203 may then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0030] Each processor core 201 is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 201. With some processor cores 201, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, Calif, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 communicate through the interconnect 207 with an input / output interfaces 209 and a memory controller 211. The input / output interface 209 provides a communication interface between the processor unit 201 and the bus 115. Similarly, the memory controller 211 controls the exchange of information between the processor unit 201 and the system memory 107. With some implementations of the invention, the processor units 201 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201.

[0031] While FIG. 2 shows one illustration of a processor unit 201 that may be employed by some embodiments of the invention, it should be appreciated that this illustration is representative only and is not intended to be limiting. It also should be appreciated that, with some implementations, a multi-core processor unit 111 can be used in lieu ofmultiple, separate processor units 111. For example, rather than employing six separate processor units 111, an alternate implementation of the computing system 101 may employ a single processor unit 111 having six cores, two multi-core processor units each having three cores, a multi-core processor unit 111 with four cores together with two separate single-core processor units 111, etc.

[0032] Returning now to FIG. 1, the interface device 113 allows the master computer 103 to communicate with the slave computers 117A, 117B, 117C . . . 117x through a communication interface. The communication interface may be any suitable type of interface including, for example, a conventional wired network connection or an optically transmissive wired network connection. The communication interface may also be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. The interface device 113 translates data and control signals from the master computer 103 and each of the slave computers 117 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP), the user datagram protocol (UDP), and the Internet protocol (IP). These and other conventional communication protocols are well known in the art, and thus will not be discussed here in more detail.

[0033] Each slave computer 117 may include a memory 119, a processor unit 121, an interface device 123, and, optionally, one more input / output devices 125 connected together by a system bus 127. As with the master computer 103, the optional input / output devices 125 for the slave computers 117 may include any conventional input or output devices, such as keyboards, pointing devices, microphones, display monitors, speakers, and printers. Similarly, the processor units 121 may be any type of conventional or custom-manufactured programmable processor device. For example, one or more of the processor units 121 may be commercially generic programmable microprocessors, such as Intel®. Pentium®, or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors or Motorola 68K / Coldfire®. microprocessors. Alternately, one or more of the processor units 121 may be custom-manufactured processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Still further, one or more of the processor units 121 may have more than onecore, as described with reference to FIG. 2 above. The memory 119 then may be implemented using any combination of the computer readable media discussed above. Like the interface device 113, the interface devices 123 allow the slave computers 117 to communicate with the master computer 103 over the communication interface.

[0034] In the illustrated example, the master computer 103 is a multi-processor unit computer with multiple processor units 111, while each slave computer 117 has a single processor unit 121. It should be noted, however, that alternate implementations of the technology may employ a master computer having single processor unit 111. Further, one or more of the slave computers 117 may have multiple processor units 121, depending upon their intended use, as previously discussed. Also, while only a single interface device 113 or 123 is illustrated for both the master computer 103 and the slave computers, it should be noted that, with alternate embodiments of the invention, either the computer 103, one or more of the slave computers 117, or some combination of both may use two or more different interface devices 113 or 123 for communicating over multiple communication interfaces.

[0035] With various examples of the computer system 101, the master computer 103 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of non-transitory computer readable media that can be accessed by the master computer 103. The computer readable media may include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable media may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storage devices, or any other medium that can be used to store desired information. According to some implementations of the computer system 101, one or more of the slave computers 117 may alternately or additions be connected to one or more external non-transitory data storage devices. Typically, these external non-transitory data storage devices will include data storage devices that also areconnected to the master computer 103, but they also may be different from any data storage devices accessible by the master computer 103.

[0036] It also should be appreciated that the description of the computer system 101 illustrated in FIG. 1 and FIG. 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of various embodiments of the invention.

[0037] OPC processes require fast but accurate modeling of the three-dimensional photomask topography. Existing methods work well for manhattan mask designs, but they do not work as well for curvilinear masks. As described above, EDA systems may use DDM.

[0038] To perform accurate OPC modeling for curvilinear masks, disclosed embodiments can use a rastered mask grid as input to an optical simulator to produce an accurate representation of the wafer image in conjunction with coherent kernels, which act as low- pass filters. In various embodiments, for modelling purposes, each kernel is defined as a sum of complex Zernike polynomials. Using Zernike polynomials provides a number of advantages, including that it reduces the number of free parameters to be solved for, it simplifies resampling of kernels to the simulation frame size, it guarantees reasonable values for orders which may not be well represented in training geometries, and the kernel complexity can be selected by setting maximum “n” of Zernikes.

[0039] FIG. 3A illustrates examples of kernels of different edge orientations in accordance with disclosed embodiments - left, up, right, and down, shown with both the real results (left column 302, 304, 306, and 308) and the modeled image results (right column 310, 312, 314, and 316). Because these images are reproduced in grayscale, in FIG. 3A and other images, (1) generally designates areas associated with a left edge, and (r) generally designates areas associated with a right edge.

[0040] FIG. 3B illustrates extracted edge grids, in accordance with disclosed embodiments, corresponding to the examples of FIG. 3A, for the same edge orientations(324, 326, 328, and 330) and in full (322). Note that, in FIG. 3B, larger pixel sizes are used to make the edges visible.

[0041] Disclosed embodiments can create a rastered mask grid that can be used as input to an optical simulator to produce an accurate representation of the wafer image.

[0042] FIG. 4 illustrates a process 400 in accordance with disclosed embodiments to create such a rastered mask grid for use in edge-only DDM and corresponding spectrum model. This process can be performed by one or more computer systems 101, referred to herein generically as the “system.”

[0043] At 402, the system receives a mask pattern for a semiconductor wafer. The wafer can be for an integrated circuit to be manufactured. “Receiving,” as used herein, can include loading from storage, receiving from another device or process, receiving via an interaction with a user, or otherwise.

[0044] At 404, the system rasters the mask pattern to a grid to create a rastered mask grid.

[0045] At 406, the system extracts separate grids for a plurality of edge orientations. These can include left, right, up, and down orientations, such as illustrated in FIG. 3B.

[0046] At 408, the system calculates a mask spectrum for each edge orientation. The system can reduce the mask spectrum calculation to only the orders relevant to the image.

[0047] At 410, the system multiplies separate frequency domain kernels by each mask spectrum to produce a spectrum model of the three-dimensional (3D) electromagnetic mask effects of each edge orientation.

[0048] At 412, the system sums the spectrum models of each edge to produce a complete spectrum model.

[0049] At 414, the system performs an optical simulation using the complete spectrum model.

[0050] FIG. 5 illustrates a process 500 in accordance with disclosed embodiments to generate kernels, that can be performed by one or more computer systems 101. In this process, the system can solve an Ax=b linear system for use in edge-only DDM.

[0051] At 502, the system receives a plurality of two-dimensional (2D) training mask patterns of a semiconductor layer.

[0052] At 504, the system simulates each of the plurality of 2D training mask patterns in 3D. This can be a rigorous simulation.

[0053] At 506, the system creates target grids by subtracting a thin mask approximation of the each mask pattern from the corresponding 3D-simulated mask pattern to produce a first array. In doing so, the system can calculate the through-the-lens (TTL) target orders for each geometry. These TTL target orders are the “b” array in the Ax=b linear problem, which may be referred to as the “first” array.

[0054] At 508, the system extracts four edge grids for the geometry of each training mask pattern. In doing so, the system can calculate the TTL orders for each edge grid.

[0055] At 510, the system creates the “A” matrix in the Ax=b linear problem, where each row corresponds to a single order for a single geometry, each column represents a single Zernike coefficient for a single edge kernel, and each cell in the matrix is the product of a TTL edge grid order and Zernike polynomial value. The A matrix may be referred to as a “first” matrix.

[0056] At 512, the system solves the Ax=b linear problem for x, to produce a kernel corresponding to the 2D mask patterns of the semiconductor layer. The kernel can be stored, displayed, or transmitted for use in another device or process.

[0057] The processes described above can operate on the full 2D mask pattern and can handle any mask layout including curvilinear layouts. Other methods treat each edge and corner independently and therefore are not as accurate for curvilinear patterns where edges are very short and at arbitrary skew angles.

[0058] Further, in disclosed processes, since any pattern can be used for training data the model can be trained for specific types of mask designs.

[0059] In the processes above, an input mask is split into multiple sub-grids, and kernels are trained which, when convolved with these sub-grids and summed, accurately represent the relevant TTL orders diffracted from the mask. In such a representation, any errors, compared to the true values, are small enough to enable IC manufacturing with curvilinear masks.

[0060] Disclosed embodiments can create additional sub-grids to model edge to edge interaction. These new sub-grids are created based on the edge grids used in edge-only kernel DDM described above.

[0061] FIG. 6 illustrates a process 600 in accordance with disclosed embodiments to generate proximity grids, that can be performed by one or more computer systems 101.

[0062] At 602, the system receives a plurality of edge grids. These can be edge grids for a semiconductor layer as described above.

[0063] At 604, the system blurs the edge grids directionally with a one-sided onedimensional function. In this step, the extent of the blur function determines the size range which is affected by proximity kernels. Vertical edges are blurred left and right, and horizontal edges are blurred up and down, in various implementations.

[0064] FIG. 7 illustrates an example of a “blurring kernel” 700 for left edges in accordance with disclosed embodiments. The blurring kernel 700 is only non-zero on a single line on one side of the origin. For the left-edge blurring kernel depicted here, nonzero values occur to the right of the origin; this allows the left edge grids to be blurred so that they overlap with the blurred version of adjacent right edges. The blurring kernels for other edge types are supported with similar values along different directions. Note that the blurring kernels discussed here are distinct from the kernels used to calculate signals as discussed above.

[0065] Returning to the process of FIG. 6, at 606, the system multiplies the two opposite blurred edge grids in space to create the proximity grids. For example, a left edge blurred with a kernel facing right, and a right edge blurred with a kernel facing left can be multiplied to create non-zero values inside narrow polygons.

[0066] FIG. 8 illustrates an example of the calculation of left / right proximity grids in accordance with disclosed embodiments. In each diagram, the grey background depicts the original mask pattern.

[0067] The top panel indicates locations of edge grids 802, including where the left edge grids and the right edge grids are supported. As before, (1) generally designates areas associated with a left edge, and (r) generally designates areas associated with a right edge, so the (1) indicates left edge grids and the (r) indicates right edge grids. The center panel illustrates the blurred edge grids 804, with (1) and (r) respectively indicating locations where the blurred left and right grids are supported. The bottom panel shows locations where the final proximity grid 806, found by multiplying the blurred left and right grids, is supported.

[0068] Returning to the process of FIG. 5, at 608, the system outputs the proximity grids, which can correspond to the original mask pattern. Outputting can include storing, displaying, or transmitting to another device or process. The proximity grids can then be added as additional grids for which unique kernels are trained.

[0069] FIG. 9 illustrates a process 900 in accordance with disclosed embodiments to simulate a mask transmission, that can be performed by one or more computer systems 101.

[0070] At 902, the system receives a mask pattern for a semiconductor layer.

[0071] At 904, the system creates edge grids corresponding to the mask pattern for edge- only kernel DDM. This can be performed according to the process described above.

[0072] At 906, based on the edge grids, the system creates proximity grids corresponding to the mask pattern. This can be performed according to the process described above.

[0073] At 908, the system convolves each edge and proximity grid with a corresponding kernel.

[0074] At 910, the system sums the results of all convolutions to produce a final mask pattern based on the summed convolutions (which in turn were based on the mask pattern) combined with a rastered mask grid. The rastered mask grid can be produced by rastering the original mask pattern to a grid as in the process of FIG. 4. As part of this step, the system may produce one or more signals, such as a vertical (left / right) or horizontal (up / down) signal. A signal is the result of one convolution of a specific kernel and grid. At this point, the summed result of the convolutions with edge grids and kernels and the convolutions with proximity grids and kernels produces the full mask to be passed to optical simulation. In general, there can be four proximity kernels, which include those operating primarily on vertical narrow polygons, those operating primarily on vertical narrow spaces, those operating primarily on horizontal narrow polygons, and those operating primarily on horizontal narrow spaces.

[0075] At 912, the system performs a simulation of a manufacturing process for the mask pattern using the final mask pattern.

[0076] FIG. 10 illustrates the calculation of kernels and signals for a left / right proximity grid in accordance with disclosed embodiments. As noted above, a kernel is the input to the convolution with a specific edge or proximity grid. A signal is the result of the one convolution of a specific kernel and grid. The top panel shows the left / right proximity grid 1002 for a rounded cross pattern depicted by the dashed black contour. Again, (1) generally designates areas associated with a left edge / grid, and (r) generally designates areas associated with a right edge / grid.

[0077] This left / right proximity grid 1002 is then convolved with the left / right proximity kernel, shown in the center panels as the real part of left / right proximity kernel 1004 and the imaginary part of left / right proximity kernel 1006, to produce the signal corresponding to the left / right proximity grid. The bottom panels illustrate the real signal for left / right proximity grid 1008 and the imaginary signal for left / right proximity grid 1010. Areas indicated by (+) represent positive values and areas indicated by (-) representnegative values of the corresponding quantities. Note that this diagram only shows the signal contributions from the left / right proximity grids. Similar signals must be calculated for the other edge and proximity kernel types, and the total signal is the sum of these signals. In other words, the “total signal” is the sum of all convolutions combined with the rastered mask. Stated differerently, the total signal is the total grid added to the rastered mask to approximate the correct mask transmission.

[0078] Other techniques may exploit manhattan crosstalk. Crosstalk signals can be used to correct the same physical effects as the proximity kernel, but the exact signal is added based on measurement of the mask layout between two parallel edges. Parallel edges rarely exist in curvilinear layouts so this method will not work in many cases.

[0079] Some techniques use edge-only kernel DDM. Edge-only kernel DDM can accurately model the electromagnetic effects of an isolated edge transmission for any curvilinear shape, but the edge to edge interaction cannot be modeled.

[0080] Disclosed embodiments provide a distinct technical advantage over both these methods by creating proximity grids, which highlight nearby edges but vary smoothly for any curvilinear shapes. When kernels are trained to these grids, they are able to model the edge-to-edge interaction, similar to manhattan crosstalk, but are accurate and consistent for any curvilinear mask pattern, maintaining the value of kernel DDM.

[0081] Of course, those of skill in the art will recognize that, unless specifically indicated or required by the sequence of operations, certain steps in the processes described above may be omitted, performed concurrently or sequentially, or performed in a different order.

[0082] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all computer systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a computer system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction andoperation of computer system 101 may conform to any of the various current implementations and practices known in the art.

[0083] It is important to note that while the disclosure includes a description in the context of a fully functional system, those skilled in the art will appreciate that at least portions of the mechanism of the present disclosure are capable of being distributed in the form of instructions contained within a machine-usable, computer-usable, or computer- readable medium in any of a variety of forms, and that the present disclosure applies equally regardless of the particular type of instruction or signal bearing medium or storage medium utilized to actually carry out the distribution. Examples of machine usable / readable or computer usable / readable mediums include: nonvolatile, hard-coded type mediums such as read only memories (ROMs) or erasable, electrically programmable read only memories (EEPROMs), and user-recordable type mediums such as floppy disks, hard disk drives and compact disk read only memories (CD-ROMs) or digital versatile disks (DVDs).

[0084] Although an exemplary embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0085] None of the description in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims. Moreover, none of these claims are intended to invoke 35 USC §112(f) unless the exact words "means for" are followed by a participle. The use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “member,” “apparatus,” “machine,” “system,” “processor,” or “controller,” within a claim is understood and intended to refer to structures known to those skilled in the relevant art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 U.S.C. §112(f).

Claims

WHAT IS CLAIMED IS:

1. A method for use in integrated circuit manufacturing, the method performed by a computer system (101) and comprising: receiving (902) a mask pattern for a semiconductor layer; creating (904) edge grids (322, 324, 326, 328, 330) corresponding to the mask pattern; creating (906) proximity grids (1002) corresponding to the mask pattern; and convolving (908) each edge grid (322, 324, 326, 328, 330) and each proximity grid (1002) with a corresponding kernel (700); summing (910) the convolutions and a rastered mask grid to produce a final mask pattern; and performing (912) a simulation of a manufacturing process using the final mask pattern.

2. The method of claim 1, wherein each corresponding kernel (700) is created by: simulating (504) each of a plurality of training mask patterns in three dimensions; creating (506) target grids by subtracting a thin mask approximation of each mask pattern from the corresponding simulated mask pattern to produce a first array; extracting (508) edge grids corresponding to geometry of each training mask pattern; creating (510) a first matrix based on the geometry of each training mask pattern, a through-the-lens (TTL) target order for the geometry of each training mask pattern, and a Zernike polynomial value; and solving (512) a linear equation based on the first array and the first matrix to produce the kernel (700).

3. The method of claim 2, wherein extracting the edge grids includes calculating TTL orders for each edge grid (322, 324, 326, 328, 330).

4. The method of claim 2, wherein creating the target grid includes calculating the TTL target order for the geometry of each training mask pattern in the target grid.

5. The method of claim 1, wherein creating proximity grids (1002) includes: blurring the edge grids (322, 324, 326, 328, 330) directionally using a one-sided, one-dimensional function; and multiplying the blurred edge grids (804) to create the proximity grids (1002).

6. The method of claim 5, wherein blurring the edge grids (322, 324, 326, 328, 330) includes blurring vertical edges in a horizontal direction and blurring vertical edges in a vertical direction.

7. The method of claim 1, further comprising producing a signal (1008, 1010) corresponding to the convolution of each kernel and each grid.

8. The method of claim 1, wherein the rastered mask grid is created by rastering the mask pattern to a grid.

9. A computer system (101) comprising a processor (111) and an accessible memory (107), the computer system (101) particularly configured to perform processes as in any of claims 1 -7.

10. A non-transitory computer-readable medium (107) encoded with executable instructions that, when executed, cause one or more computer systems (101) to perform processes as in any of claims 1-7.

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