Converter and method for controlling a converter

Abstract

A converter comprises a first and second power converter each comprising one or more controllable semiconductor switches; and a series connection of a first, second and one or more third capacitor units. The converter comprises for each two neighboring capacitor units of the series connection of capacitor units a circuit comprising a series connection of two semiconductor switch units and a resonant circuit connected with the two semiconductor switch units. The first power converter is connected with the first capacitor unit. The second power converter is connected with the second capacitor unit. The one or more third capacitor units are connected in series between the first and second capacitor unit. The circuit is connected with each two neighboring capacitor units of the series connection of capacitor units such that the series connection of two semiconductor switch units of the circuit is connected in parallel with the two neighboring capacitor units.

Description

[0001] CONVERTER AND METHOD FOR CONTROLLING A CONVERTER

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to a converter and a method for controlling a converter.

[0004] BACKGROUND

[0005] Solar energy may be translated into electrical energy by solar photovoltaic (PV) panels, e.g. PV arrays. The electrical energy translated from solar energy is in the form of direct current (DC) energy. Eventually, the DC electric energy is delivered to alternating current (AC) power systems by means of power electronic conversion systems. Consumption and loads may use the electrical energy in the form of AC energy. Examples of loads may comprise home appliances, industry motors, etc.

[0006] SUMMARY

[0007] A power converter system for converting DC power to AC power may comprise two stages. A first stage may comprise or be a DC-to-DC power converter stage. That is, one level of DC voltage or current may be converted to a lower or greater level of DC voltage or current. For example, a DC voltage or current may be converted to a lower or greater DC voltage or current (i.e. voltage or current of lower or higher level), respectively. The second stage may comprise or be a DC-to-AC power converter stage, which may be referred to as inverter stage. That is, DC power may be converted to AC power. For example, a DC voltage or current may be converted to an AC voltage or current, respectively. Optionally, the power converter system may be bidirectional. In this case, the second stage may be configured to be an AC-to-DC power converter stage. That is, AC power may be converted to DC power.

[0008] In case a PV system, such as a PV array or PV panel, are electrically connected to a DC-to-DC power converter stage, the DC- to-DC converter stage may be configured to boost an input DC voltage provided by the PV array or panel to a value higher at the output of the DC-to-DC converter stage. The terms “solar PV” and, thus, “solar PV system” may be used as synonyms for the terms “PV” and “PV system”, respectively.

[0009] In view of the above, this disclosure aims to provide a converter for a DC-to-DC conversion that is improved with regard to at least one of losses of semiconductor switches used in the converter for controlling the converter, costs and size. An objective of this disclosure is to provide such a converter that allows guaranteeing a maximum energy being harvested from a PV system, when the converter is directly connected with the PV system for converting the DC voltage provided by the PV system.

[0010] These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0011] Herein, the terms “electrically connect” and “connect” are used as synonyms. The term “controlled semiconductor switch” may be used as a synonym for the term “controllable semiconductor switch”. The term “controllable semiconductor switch” means a semiconductor switch comprising a control terminal, such as a transistor, a thyristor, triac etc. The controllable semiconductor switch may be controlled via the control terminal to switch between the conducting state (i.e. on-state) and the non-conducting state (i.e. off-state). Herein, controllable semiconductor switches may be power semiconductor transistors, such as insulated- gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). Using MOSFET instead of IGBTS for the controllable semiconductor switches has the following advantages: The operation speed of a MOSFET is faster than the operation speed of a similar rated IGBT. Power losses of a MOSFET are lower than power losses of a similar rated IGBT. IGBTs and MOSFETs allow to switch high current and voltages.

[0012] Herein, controllable semiconductor switches may be transistors. A controllable semiconductor switch being a transistor may be an insulated-gate bipolar transistor (IGBT), a field-effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistors (BJT) or a junction gate field-effect transistor (JFET). Optionally, a controllable semiconductor switch may be a semiconductor switch with a diode associated to it. For example, a controllable semiconductor switch may be a transistor, such as a IGBT, with a diode connected in anti-parallel to the transistor. That is, in case a controllable semiconductor switch is a transistor, optionally a diode is connected in anti-parallel to the transistor. For example, a controllable semiconductor switch may be a transistor, such as a MOSFET, comprising an intrinsic body diode. The diode and intrinsic body diode are examples of an “uncontrollable semiconductor switch”, which may be referred to as “uncontrolled semiconductor switch”. The term “bidirectional semiconductor switch” means a semiconductor switch that allows a bidirectional current flow, that is a current flow in two directions. The term “unidirectional semiconductor switch” means a semiconductor switch that allows a unidirectional current flow, that is a current flow in one direction.

[0013] The term “uncontrollable semiconductor switch” means a semiconductor switch without a control terminal that allows a unidirectional current flow, that is a current flow in one direction. Examples of an “uncontrollable semiconductor switch” are a diode (may be referred to as “p-n semiconductor diode”), a pin diode, a Schottky diode, an intrinsic body diode of a respective device / transistor etc.

[0014] A first aspect of this disclosure provides a converter. The converter comprises a first, second, third and fourth terminal for receiving DC voltages. The converter comprises a first and second power converter each comprising a first, second and third terminal and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal to a further voltage of lower or higher level at the second and third terminal. The converter comprises a series connection of a first capacitor unit, second capacitor unit and one or more third capacitor units. The converter comprises for each two neighboring capacitor units of the series connection of the first capacitor unit, second capacitor unit and one or more third capacitor units a circuit comprising a series connection of two semiconductor switch units and a resonant circuit electrically connected with the two semiconductor switch units. The first terminal of the first power converter is electrically connected with the second terminal of the converter. The second and third terminal of the first power converter are electrically connected with a first and second terminal of the first capacitor unit, respectively. The first terminal of the converter is electrically connected with the first terminal of the first capacitor unit. The first terminal of the second power converter is electrically connected with the third terminal of the converter. The second and third terminal of the second power converter are electrically connected with a first and second terminal of the second capacitor unit, respectively. The fourth terminal of the converter is electrically connected with the second terminal of the second capacitor unit. The one or more third capacitor units are electrically connected in series between the second terminal of the first capacitor unit and the first terminal of the second capacitor unit. The circuit is electrically connected with each two neighboring capacitor units of the series connection of the first capacitor unit, second capacitor unit and one or more third capacitor units such that the series connection of two semiconductor switch units of the circuit is electrically connected in parallel with the two neighboring capacitor units.

[0015] The circuits for respective two neighboring capacitor units of the series connection of the first capacitor unit, second capacitor unit and one or more third capacitor units allow maintaining an electrical energy balance between the first capacitor unit, second capacitor unit and one or more third capacitor units. In other words, these circuits are configured to counter any imbalance from input sources connected to the converter. Any imbalance in voltage sources connected to the converter may result in imbalance in the energy stored in the capacitor units. In case of an imbalanced source scenario, the first, second and one or more third capacitor units may be unequally charged creating an unequal voltage distribution among the series connected capacitor units. The aforementioned circuits of the converter allow balancing the electrical energies between the capacitor units by exchanging unequal energy between the series connected capacitor units. Thus, these circuits may be referred to as “balancer circuits” or “resonant balancer circuits”. These circuits may be resonant power converters. For example, these circuits may be or may be based on resonant switch capacitor converter (RSCC) structures. That is, the structure of these circuits may be the structure of a resonant power converter. The circuit (i.e. balancer circuit) being connected in parallel to two neighboring capacitor units being connected in series allows maintaining a balance of electrical energy between the two neighboring capacitor units.

[0016] The circuit for each two neighboring capacitor units of the series connection of the first capacitor unit, second capacitor unit and one or more third capacitor units may be operated without a close loop control. This enables an uncontrolled balancing operation simplifying the converter.

[0017] The one or more third capacitor units allow the first and second capacitor unit to be rated for lower voltage and / or lower current, because the series connection of the first capacitor unit, second capacitor unit and one or more third capacitor unit splits a voltage (e.g. DC load voltage) into several lower voltage levels. This allows reducing costs and size of the converter. Multiple third capacitor units, i.e. more than three series connected capacitor units, enables the use of further low voltage and / or low current devices to be used in the converter. This allows to reduce further the costs and increase system efficiency.

[0018] The converter allows, due to its structure, a partial power processing for power conversion. In a partial power processing, a majority of the power from the source (feeding the converter) is directed to the load side (which provides power to a load when the load is connected to the converter) without any switching, while a small portion of the power is processed by means of the first power converter and second power converter of the converter. In this case, the first and second power converter may be partial power converters. The term “partially rated power converter” may be used as a synonym for the term “partial power converter. The converter can maintain the voltage at the first capacitor unit, second capacitor unit and one or more third capacitor unit at a predefined level as well as maintain the MPPT point of an input to the first, second, third and fourth terminals of the converter. At all input variations of voltage sources connectable to the first, second, third and fourth terminal of the converter, the first and second power converter operate a smaller portion of the total power, and therefore, may be implemented using low voltage and / or low current semiconductor devices, such as low voltage and / or low current controllable semiconductor switches. Such low voltage and / or low current semiconductor devices are lower in costs compared to semiconductor devices rated for higher voltage and / or higher current. Low voltage and / or low current semiconductor devices can be switched faster and at high frequencies compared to semiconductor devices rated for higher voltage and / or higher current. Therefore, size of passive elements (such as inductors and capacitors) used in the power converters can be reduced considerably. These devices dissipate lower losses resulting lower cooling and heatsink requirements. As a result, the converter of the first aspect is improved with regard to costs and size. In addition, the converter is improved with regard to losses of semiconductor switches used in the converter for controlling the converter. Thus, the converter allows a scalability for higher voltage applications without compromising efficiency and cost.

[0019] The terms “converter circuit”, “converter device” or “converter module” may be used as a synonym for the term “converter”. The components of the converter may be arranged in a housing of the converter.

[0020] The converter may be a DC-to-DC converter. Optionally, the converter may be a DC-to-DC converter stage that feeds an DC- to-AC converter stage (i.e. an inverter stage). The converter may be configured to boost DC voltage(s) received at the first, second, third and fourth terminals of the converter, i.e. convert a received DC voltage to a voltage of higher level. The converter of the first aspect being a DC-to-DC converter stage and a DC-to-AC converter stage being fed by the converter may interface a PV system and a grid. That is, they may be used to convert the DC voltage / direct current provided by the PV system to an AC voltage / altemating current for the grid. The term “DC link capacitor unit” may be used for referring to a capacitor unit. The first capacitor unit, second capacitor unit and one or more third capacitor units electrically connected in series may form a DC link.

[0021] The first and third terminal may be configured to be electrically connected with a first voltage source and the second and fourth terminal may be configured to be electrically connected with a second voltage source. The first and second voltage source may be a first and second PV system, the PV system comprising or being one or more PV panels and / or PV arrays. The first and second voltage sources may be a first and second battery, optional rechargeable batteries. The term “battery energy storage (BES)” may be used as a synonym for the term “battery”. The converter of the first aspect allows providing a low loss MPPT operation. This allows an increase of an extraction of energy from energy sources, e.g. solar PV energy from PV systems, that may be connected to the first, second, third and fourth terminals of the converter.

[0022] Herein, a voltage at the first terminal of a power converter (e.g. first or second power converter) means a voltage between the first terminal of the power converter and a further terminal, e.g. a terminal of the converter. That is, the voltage at the first terminal of the first power converter means the voltage between the second and fourth terminal of the converter (the first terminal of the first power converter is electrically connected with the second terminal of the converter). Accordingly, the voltage at the first terminal of the second power converter means the voltage between the third and first terminal of the converter (the first terminal of the second power converter is electrically connected with the third terminal of the converter).

[0023] Herein, a voltage at the second and third terminal of a power converter (e.g. first or second power converter) means a voltage between the second and third terminal of the power converter.

[0024] In an implementation form of the first aspect, the converter comprises one or more additional first power converters with the first terminal being electrically connected to a respective further terminal of the converter and the second and third terminal being electrically connected to the first and second terminal of the first capacitor unit, respectively. In addition or alternatively, the converter may comprise one or more additional second power converters with the first terminal being electrically connected to a respective further terminal of the converter and the second and third terminal being electrically connected to the first and second terminal of the second capacitor unit, respectively.

[0025] This allows, connecting additional voltage sources to the converter. Therefore, the converter may be used for more than two voltage sources in order to provide a voltage and / or current conversion for the multiple voltage sources. Each of the one or more additional first power converters may be implemented like the first power converter. Thus, the description of the first power converter is correspondingly valid for the one or more additional first power converters. Each of the one or more additional second power converters may be implemented like the second power converter. Thus, the description of the second power converter is correspondingly valid for the one or more additional second power converters.

[0026] In an implementation form of the first aspect, each of the first and second power converter is a partial power converter.

[0027] This allows using low voltage and / or low current semiconductor switches as the controllable semiconductor switches of the first and second power convert.

[0028] In an implementation form of the first aspect, the converter is unidirectional and each of the first, second, third and fourth terminal of the converter is an input terminal. Alternatively, the converter may be bidirectional.

[0029] In case the converter is bidirectional, rechargeable batteries may be connected to the converter. For example, a first rechargeable battery may be connected to the first and third terminal of the converter and a second rechargeable battery may be connected to the second and fourth terminal of the converter. This allows converting by the converter a DC voltage provided by the first and second battery to a voltage of lower or higher level and charging by the converter the first and second rechargeable battery.

[0030] In an implementation form of the first aspect, the converter comprises a fifth and sixth terminal that are configured to be electrically connected with an electrical load. The fifth terminal is electrically connected with the first terminal of the first capacitor unit, and the sixth terminal is electrically connected with the second terminal of the second capacitor unit.

[0031] The electrical load may be for example a converter stage, such as a DC-to-AC converter stage. The electrical load may be an electrical equipment that is configured to be electrically supplied with DC power, e.g. DC voltage or DC current.

[0032] In an implementation form of the first aspect, each semiconductor switch unit of the series connection of two semiconductor switch units of the circuit comprises two controllable semiconductor switches electrically connected in series.

[0033] This allows the converter to be bidirectional, i.e. allow a bidirectional power flow.

[0034] In an implementation form of the first aspect, a semiconductor switch unit of the series connection of two semiconductor switch units of the circuit comprises two controllable semiconductor switches electrically connected in series, and another semiconductor switch unit of the series connection of two semiconductor switch units of the circuit comprises two uncontrollable semiconductor switches electrically connected in series.

[0035] This allows the converter to be unidirectional, i.e. allow a unidirectional power flow.

[0036] In an implementation form of the first aspect, the resonant circuit of the circuit comprises a series connection of a capacitor and an inductor. A first end of the series connection of the capacitor and the inductor may be electrically connected with a first semiconductor switch unit of the series connection of two semiconductor switch units. A second end of the series connection of the capacitor and the inductor may be electrically connected with a second semiconductor switch unit of the series connection of two semiconductor switch units.

[0037] In an implementation form of the first aspect, the first end of the series connection of the capacitor and the inductor is electrically connected with a node between the two semiconductor switches of the first semiconductor switch unit of the series connection of two semiconductor switch units. The second end of the series connection of the capacitor and the inductor may be electrically connected with a node between the two semiconductor switches of the second semiconductor switch unit of the series connection of two semiconductor switch units.

[0038] In an implementation form of the first aspect, the resonant circuit of the circuit comprises a capacitor and an inductor. A first terminal and second terminal of the capacitor may be electrically connected with a first semiconductor switch unit and a second semiconductor switch unit, respectively, of the series connection of two semiconductor switch units. A first terminal of the inductor may be electrically connected with a node between the two semiconductor switch units of the series connection of two semiconductor switch units. A second terminal of the inductor may be electrically connected with a node between the two neighboring capacitor units of the series connection of the first capacitor unit, second capacitor unit and one or more third capacitor units.

[0039] In an implementation form of the first aspect, the first terminal of the capacitor is electrically connected with a node between the two semiconductor switches of the first semiconductor switch unit of the series connection of two semiconductor switch units. The second terminal of the capacitor may be electrically connected with a node between the two semiconductor switches of the second semiconductor switch unit of the series connection of two semiconductor switch units.

[0040] In an implementation form of the first aspect, the converter is configured to control the semiconductor switches (i.e. controllable semiconductor switches) of the power converters of the converter by performing a maximum power point tracking (MPPT) algorithm.

[0041] Herein, controlling the controllable semiconductor switches means controlling switching of the controllable semiconductor switches.

[0042] Performing the MPPT algorithm for controlling the controllable semiconductor switches of the first and second power converter allows harvesting a maximum energy from electrical sources, e.g. voltage sources, that may be connected to the first, second, third and fourth terminal of the converter. Such electrical sources may be PV systems, such as PV panels or PV arrays. For example, the first, second, third and fourth terminal of the converter may be connected to PV systems, such as PV panels or PV arrays. In this case, performing the MPPT algorithm for controlling the switches of the first and second power converter allows ensuring that the PV systems produce the maximum available energy.

[0043] The present disclosure is not limited to a specific type of MPPT algorithm. Thus, any known MPPT algorithm may be used.

[0044] The converter may be a MPPT-DC-to-DC converter. The converter may be configured to employ the MPPT algorithm to draw the most power possible from a photovoltaic (PV) system. The maximum power point (MPP) is the voltage at which a PV system may generate its maximum power.

[0045] In an implementation form of the first aspect, the converter is configured to control the two semiconductor switch units of the circuit for each two neighboring capacitor units such that at any time only one of the two semiconductor switch units is in the conducting state.

[0046] The converter is configured to control the two semiconductor switch units of the circuit for each two neighboring capacitor units using a duty cycle of 50%. Especially, the converter is configured to control the two semiconductor switch units of the circuit such that they are operated in complimentary with 50% duty cycle. That is, the two semiconductor switch units of the circuit may be operated in complimentary with 50% duty cycle in order to excite the resonant circuit of the circuit.

[0047] In an implementation form of the first aspect, the converter is configured to control the two semiconductor switch units of the circuit for each two neighboring capacitor units with a frequency that is smaller than or equal to a resonant frequency of the resonant circuit of the circuit for each two neighboring capacitor units. This allows a high-efficiency switching operation. The frequency (i.e. switching frequency) being equal or similar to the resonant frequency allows soft switching of the semiconductor switch units. The frequency (switching frequency) being slightly lower than the resonant frequency allows maintaining soft switching for wider operating conditions.

[0048] In an implementation form of the first aspect, a capacitor unit of the first capacitor unit, second capacitor unit and one or more third capacitor units comprises or is a capacitor or a series connection of multiple capacitors. In case of multiple capacitors, capacitors rated for lower voltage and / or lower current may be used. This allows reducing costs and size of the converter. The multiple capacitors may be for example two capacitors electrically connected in series. In order to achieve the converter according to the first aspect of the disclosure, some or all of the implementation forms and optional features of the first aspect, as described above, may be combined with each other.

[0049] A second aspect of this disclosure provides a method for controlling a converter according to the first aspect of this disclosure. The method comprises controlling the semiconductor switches of the power converters of the converter by performing a maximum power point tracking (MPPT) algorithm.

[0050] In an implementation form of the second aspect, the method comprises controlling the two semiconductor switch units of the circuit for each two neighboring capacitor units such that at any time only one of the two semiconductor switch units is in the conducting state.

[0051] The method comprises controlling the two semiconductor switch units of the circuit for each two neighboring capacitor units using a duty cycle of 50%. Especially, the method comprises controlling the two semiconductor switch units of the circuit such that they are operated in complimentary with 50% duty cycle. That is, the two semiconductor switch units of the circuit may be operated in complimentary with 50% duty cycle in order to excite the resonant circuit of the circuit.

[0052] In an implementation form of the second aspect, the method comprises controlling the two semiconductor switch units of the circuit for each two neighboring capacitor units with a frequency that is smaller than or equal to a resonant frequency of the resonant circuit of the circuit for each two neighboring capacitor units. The frequency (i.e. switching frequency) being equal or similar to the resonant frequency allows soft switching of the semiconductor switch units. The frequency (switching frequency) being slightly lower than the resonant frequency allows maintaining soft switching for wider operating conditions.

[0053] The above description of the converter according to the first aspect is correspondingly valid for the method of the second aspect. The converter of the first aspect may be configured to perform the method of the second aspect.

[0054] The method of the second aspect and its implementation forms and optional features achieve the same advantages as the converter of the first aspect and its respective implementation forms and respective optional features.

[0055] In order to achieve the method according to the second aspect of the disclosure, some or all of the implementation forms and optional features of the second aspect, as described above, may be combined with each other.

[0056] The converter of the first aspect and method of the second aspect allow a low cost MPPT DC-to-DC conversion. With regard to string inverters for interfacing a PV system (e.g. a PV array) to a grid, each string inverter comprising the converter of the first aspect as a DC-to-DC converter stage and an DC-to-AC converter stage, the converter of the first aspect and method of the second aspect enable having a string level optimization, rather than multiple strings to be maintained at one MPPT. The converter of the first aspect and method of the second aspect allows extension of PV strings, BES integration or any combination of both.

[0057] With the converter of the first aspect and method of the second aspect, it is possible to improve the efficiency, power density and the cost of a MPPT DC / DC converter, e.g. when used for PV systems. Moreover, a high electrical efficiency can be achieved as lower voltage semiconductor devices can be used and by means of the integration of control and driving circuits in close proximity to switching power cells thereby minimizing delays and latencies in the control loop.

[0058] All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

[0059] BRIEF DESCRIPTION OF DRAWINGS

[0060] The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

[0061] FIG. 1 shows an example of a converter of this disclosure.

[0062] FIG. 2 shows an example of an implementation form of the converter of FIG. 1.

[0063] FIG. 3 shows an example of an implementation form of the converter of FIG. 1.

[0064] FIG. 4 shows an example of an implementation form of the converter of FIG. 1.

[0065] FIG. 5 a) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1,

[0066] 2, 3 and 4.

[0067] FIG. 5 b) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1,

[0068] 2, 3 and 4.

[0069] FIG. 6 a) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1,

[0070] 2, 3 and 4.

[0071] FIG. 6 b) shows an example of an implementation form of a power converter of the converter of any one of FIGs 1,

[0072] 2, 3 and 4.

[0073] FIG. 7 a) shows an example of an implementation form of the converter of FIG. 1.

[0074] FIG. 7 b) shows an example of an implementation form of the converter of FIG. 1.

[0075] FIG. 8 shows an example of an implementation form of the converter of FIG. 1.

[0076] FIG. 9 shows an example of an implementation form of the converter of FIG. 1.

[0077] FIG. 10 shows an example of an implementation form of the converter of FIG. 1.

[0078] Same elements shown in the Figures (FIGs) are labeled with the same reference sign, and may be implemented likewise. DETAILED DESCRIPTION OF EMBODIMENTS

[0079] FIG. 1 shows an example of a converter of this disclosure. The converter of FIG. 1 is an example of the converter of the first aspect. Thus, the description of the converter of the first aspect is correspondingly valid for the converter of FIG. 1.

[0080] The converter 1 of FIG. 1 comprises a first terminal Tl, second terminal T2, third terminal T3 and fourth terminal T4 for receiving DC voltages. As shown in FIG. 1, the first and third terminal Tl, T3 may be configured to be electrically connected with a first voltage source 100 and the second and fourth terminal T2, T4 may be configured to be electrically connected with a second voltage source 200. The converter 1 comprises a first power converter 21 and second power converter 22. Each power converter of the first and second power converter 21, 22 comprises a first terminal X, second terminal Yl and third terminal Y2 and one or more controllable semiconductor switches (not shown in FIG. 1 ) for controlling a conversion of a voltage at the first terminal X to a further voltage of lower or higher level at the second and third terminal Yl, Y2. FIGs 5 a), 5 b), 6 a), 6 b), 8, 9 and 10 show examples of implementation forms of the first and second power converter 21, 22. The converter 1 comprises a series connection of a first capacitor unit Cl, second capacitor unit C2 and one or more third capacitor units C3. According to FIG. 1, the converter comprises one third capacitor unit C3. This is only by way of example and, thus, the converter may comprise two or more third capacitor units C3. For example, FIGs 7 a), 7 b) and 10 show optional implementation forms of the converter 1 with two third capacitor units C3.

[0081] As shown in FIG. 1 , the converter 1 comprises for each two neighboring capacitor units (i.e. for the pair of capacitor units C 1 and C3 and the pair of capacitor units C3 and C2) of the series connection of the first capacitor unit Cl, second capacitor unit C2 and one or more third capacitor units C3 a circuit 50. Thus, according to the example of FIG. 1, the converter comprises two circuits 50. The number of the circuits 50 is one less than the number of the series connected first capacitor unit C 1 , second capacitor unit C2 and one or more third capacitor units C3. The circuit 50 (i.e. each circuit 50) comprises a series connection of two semiconductor switch units 31, 32 and a resonant circuit 40 electrically connected with the two semiconductor switch units 31, 32.

[0082] The circuit 50 (top circuit 50 in FIG. 1) being connected in parallel to the two neighboring capacitor units Cl, C3 allows maintaining a balance of electrical energy between the two neighboring capacitor units Cl, C3. The circuit 50 (bottom circuit 50 in FIG. 1) being connected in parallel to the two neighboring capacitor units C3, C2 allows maintaining a balance of electrical energy between the two neighboring capacitor units C3, C2.

[0083] As shown in FIG. 1, the first terminal X of the first power converter 21 is electrically connected with the second terminal T2 of the converter 1. The second terminal Yl and third terminal Y2 of the first power converter 21 are electrically connected with a first and second terminal of the first capacitor unit Cl, respectively. The first terminal Tl of the converter 1 is electrically connected with the first terminal of the first capacitor unit C 1. The first terminal X of the second power converter is 22 electrically connected with the third terminal T3 of the converter 1. The second terminal Yl and third terminal Y2 of the second power converter 22 are electrically connected with a first and second terminal of the second capacitor unit C2, respectively. The fourth terminal T4 of the converter 1 is electrically connected with the second terminal of the second capacitor unit C2. The one or more third capacitor units C3 are electrically connected in series between the second terminal of the first capacitor unit C 1 and the first terminal of the second capacitor unit C2. The circuit 50 is electrically connected with each two neighboring capacitor units Cl, C3 and C3, C2 of the series connection of the first capacitor unit Cl, second capacitor unit C2 and one or more third capacitor units C3 such that the series connection of two semiconductor switch units 31, 32 of the circuit 50 is electrically connected in parallel with the two neighboring capacitor units Cl, C3 and C3, C2. That is, each circuit 50 is connected with the respective pair of neighboring capacitor units Cl, C3 or C3, C2 such that the series connection of two switch units 31, 32 of the circuit 50 is connected in parallel with the respective pair of neighboring capacitor units Cl, C3 or C3, C2, respectively.

[0084] Each of the first power converter 21 and second power converter 22 of the converter 1 may be a partial power converter. The converter 1 may be unidirectional and each of the first, second, third and fourth terminal Tl, T2, T3, T4 of the converter 1 may be an input terminal. As shown in FIG. 1, the converter 1 may comprise a fifth terminal T5 and sixth terminal T6 that are configured to be electrically connected with an electrical load 300. The fifth terminal T5 is electrically connected with the first terminal of the first capacitor unit C 1 and, thus, with the first terminal Tl of the converter 1. The sixth terminal T6 is electrically connected with the second terminal of the second capacitor unit C2 and, thus, with the fourth terminal T4 of the converter 1.

[0085] For example, the converter may be a DC-to-DC converter and the load 300 may be an DC-to-AC converter. In this case, the first and second voltage sources 100, 200 may be PV systems, such as PV panel(s) and / or PV array(s). Optionally, the sources 100, 200 may be two close strings in a PV park that are designed to generate similar DC power. The converter 1 being a DC- to-DC converter and the load 300 being a DC-to-AC converter may be used for converting DC power, e.g. DC voltage and / or direct current, provided by the first and second voltage sources 100, 200, e.g. PV systems, to AC power, e.g. AC voltage and / or alternating current, and provide the AC power to the grid. Optionally, the load 300 may be a DC load.

[0086] Alternatively, the converter 1 may be bidirectional. An example of an implementation form of the converter being bidirectional is shown in FIGs. 9 and 10. In this case, the first and second voltage sources 100, 200 may be rechargeable battery energy storages (BES) and the load 300 may be configured to use electrical energy from the BES 100, 200 (power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 1) and charge the BES 100, 200 with electrical energy (power flow from the terminals T5, T6 to the terminals Tl , T2, T3, T4 of the converter 1 ). Thus, the converter 1 being bidirectional supports discharging and charging of BES 100, 200.

[0087] The converter 1 may be configured to control the semiconductor switches (i.e. controllable semiconductor switches) of the power converters 21 , 22 of the converter by performing a maximum power point tracking (MPPT) algorithm. The converter 1 may be configured to control the two semiconductor switch units 31, 32 of the circuit 50 for each two neighboring capacitor units Cl, C3 and C3, C2 (i.e. of each circuit 50) such that at any time only one of the two semiconductor switch units 31, 32 is in the conducting state. For example, the converter 1 is configured to control the two semiconductor switch units 31 , 32 of the circuit 50 for each two neighboring capacitor units Cl, C3 and C3, C2 (i.e. of each circuit 50) using a duty cycle of 50%.

[0088] The converter 1 may be configured to control the two semiconductor switch units 31, 32 of the circuit 50 for each two neighboring capacitor units Cl, C3 and C3, C2 (i.e. of each circuit 50) with a frequency that is smaller than or equal to a resonant frequency of the resonant circuit 40 of the circuit 50 for each two neighboring capacitor units Cl, C3 and C3, C2 (i.e. of each circuit 50).

[0089] For the aforementioned control function(s), the converter 1 may comprise a control unit (not shown in FIG. 1). The control unit may comprise or correspond to a processor, microprocessor, controller, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC) or any combination of the aforementioned components. The control unit is configured to provide control signals, such as pulse width modulated (PWM) signals, to controllable semiconductor switches of the first and second power converter 21, 22, especially to the control terminal of the controllable semiconductor switches. The control unit is configured to provide control signals, such as pulse width modulated (PWM) signals, to the two semiconductor switch units 31, 32 of each circuit 50. For example, the control unit is configured to provide control signals, such as pulse width modulated (PWM) signals, to controllable semiconductor switches of the two semiconductor switch units 31 , 32 of each circuit 50, especially to the control terminal of the controllable semiconductor switches. As shown in FIG. 1, a capacitor unit of the first capacitor unit Cl, second capacitor unit C2 and one or more third capacitor units C3 may comprise or be a capacitor. For example, as shown in FIG. 1, each of the first, second and third capacitor unit Cl, C2, C3 may comprise or be a capacitor. Alternatively, a capacitor unit of the first capacitor unit Cl, second capacitor unit C2 and one or more third capacitor units C3 may comprise or be multiple capacitors (e.g. two capacitors) electrically connected in series. Optionally, each of the first capacitor unit C 1 , second capacitor unit C2 and one or more third capacitor units C3 may comprise or be multiple capacitors (e.g. two capacitors) electrically connected in series. The number of capacitors of the first capacitor unit Cl and the second capacitor unit C2 may depend on the implementation form of the first power converter 21 and second power converter 22, respectively. Optionally, the first and second power converter 21, 22 may be implemented by the same power converter type. The power converters of the converter 1 may be implemented the same way. Optionally, at least one power converter of the converter 1 may be implemented differently. As outlined already above, examples of implementation forms of the power converter 21, 22 of the converter 1 are shown in FIGs 5 a), 5 b), 6 a), 6 b), 8, 9 and 10.

[0090] For further information on the converter 1 reference is made to FIGs 2, 3, 4, 5 a), 5 b), 6 a), 6 b), 7, 8, 9 and 10.

[0091] FIG. 2 shows an example of an implementation form of the converter of FIG. 1. The converter 1 of FIG. 2 corresponds to the converter 1 of FIG. 1. Thus, the description of the converter 1 of FIG. 1 is correspondingly valid for the converter 1 of FIG. 2 and in the following mainly a difference, especially an optional feature, of the converter 1 of FIG. 2 with regard to the converter 1 of FIG. 1 is described.

[0092] As shown in FIG. 2, the resonant circuit 40 of the circuit 50 (i.e. each circuit 50) comprises a series connection of a capacitor Cr and an inductor Lr. A first end of the series connection of the capacitor Cr and the inductor Lr is electrically connected with a first semiconductor switch unit 31 of the series connection of two semiconductor switch units 31, 32 of the circuit 50. A second end of the series connection of the capacitor Cr and the inductor Lr is electrically connected with a second semiconductor switch unit 32 of the series connection of two semiconductor switch units 31, 32 of the circuit 50.

[0093] Each semiconductor switch unit of the series connection of two semiconductor switch units 31, 32 of the circuit 50 may comprise two semiconductor switches electrically connected in series, as shown in FIGs 8, 9 and 10. The two semiconductor switches may form a half bridge arrangement. Optionally more than two semiconductor switches connected in series may be provided for a semiconductor switch unit. FIG. 8 shows an example of the converter 1 , where the semiconductor switches of one switch unit of the series connection of two semiconductor switch units 31, 32 of the circuit 50 are controllable semiconductor switches and the semiconductor switches of the other semiconductor switch unit of the series connection of two semiconductor switch units 31, 32 of the circuit 50 are uncontrollable semiconductor switches. FIGs 9 and 10 show examples of the converter, where the semiconductor switches of each semiconductor switch unit of the series connection of two semiconductor switch units 31, 32 of the circuit 50 are controllable semiconductor switches. In the aforementioned case, with regard to each circuit 50, the first end of the series connection of the capacitor Cr and the inductor Lr of the resonant circuit 40 may be electrically connected with a node between the two semiconductor switches of the first semiconductor switch unit 31 of the series connection of two semiconductor switch units 31, 32. The second end of the series connection of the capacitor Cr and the inductor Lr of the resonant circuit 40 may be electrically connected with a node between the two semiconductor switches of the second semiconductor switch unit 32 of the series connection of two semiconductor switch units 31, 32.

[0094] The implementation of the resonant circuit 40 is only by way of example and may be differently implemented. A different implementation form is shown in FIG. 3.

[0095] FIG. 3 shows an example of an implementation form of the converter of FIG. 1. The converter 1 of FIG. 2 corresponds to the converter 1 of FIG. 1. Thus, the description of the converter 1 of FIG. 1 is correspondingly valid for the converter 1 of FIG. 3 and in the following mainly a difference, especially an optional feature, of the converter 1 of FIG. 3 with regard to the converter 1 of FIG. 1 is described.

[0096] As shown in FIG. 3, the resonant circuit 40 of the circuit 50 (i.e. each circuit 50) comprises a capacitor Cr and an inductor Lr. A first terminal and second terminal of the capacitor Cr may be electrically connected with a first semiconductor switch unit

[0097] 31 and a second semiconductor switch unit 32, respectively, of the series connection of two semiconductor switch units 31, 32. A first terminal of the inductor Lr may be electrically connected with a node between the two semiconductor switch units 31,

[0098] 32 of the series connection of two semiconductor switch units 31 , 32. As shown in FIG. 3 , a second terminal of the inductor Lr may be electrically connected with a node between the two neighboring capacitor units Cl, C3 or C3, C2 to which the circuit 50 is connected in parallel.

[0099] Each semiconductor switch unit of the series connection of two semiconductor switch units 31, 32 of the circuit 50 may comprise two semiconductor switches electrically connected in series, as shown in FIGs 8, 9 and 10. FIG. 8 shows an example of the converter 1 , where the semiconductor switches of one switch unit of the series connection of two semiconductor switch units 31 , 32 of the circuit 50 are controllable semiconductor switches and the semiconductor switches of the other switch unit of the series connection of two semiconductor switch units 31 , 32 of the circuit 50 are uncontrollable semiconductor switches. FIGs 9 and 10 show examples of the converter, where the semiconductor switches of each of the series connection of two semiconductor switch units 31, 32 of the circuit 50 are controllable semiconductor switches. In the aforementioned case, with regard to each circuit 50, the first terminal of the capacitor Cr of the resonant circuit 40 may be electrically connected with a node between the two semiconductor switches of the first semiconductor switch unit 31 of the series connection of two semiconductor switch units 31, 32. The second terminal of the capacitor Cr may be electrically connected with a node between the two semiconductor switches of the second semiconductor switch unit 32 of the series connection of two semiconductor switch units 31, 32.

[0100] The resonant converter 40 of FIG. 3 differs from the resonant converter 40 of FIG. 2 in that according to FIG. 2 both the capacitor Cr and the inductor Lr (being connected in series to each other) of the resonant converter 40 of the circuit 50 are connected between the first semiconductor switch unit 31 and the second semiconductor switch unit 32 of the circuit 50, whereas according to FIG. 3 merely the capacitor Cr of the resonant converter 40 of the circuit 50 is connected between the first semiconductor switch unit 31 and the second semiconductor switch unit 32 of the circuit 50. According to FIG. 3, the inductor Lr of the resonant converter 40 of the circuit 50 is connected between a node between the two semiconductor switch units 31, 32 of the circuit 50 and a node between the two neighboring capacitor (of the series connection of the first capacitor unit Cl, second capacitor unit C2 and one or more third capacitor units C3) for which the circuit 50 is provided. The capacitor Cr of the resonant converter 40 of the circuit 50 of FIG. 3 may be connected to the two semiconductor switch units 31, 32 of the circuit 50 in the same way as the series connection of the capacitor Cr and inductor Lr of the resonant converter 40 of the circuit 50 of FIG. 2 is connected to the two semiconductor switch units 31, 32 of the circuit 50.

[0101] FIG. 4 shows an example of an implementation form of the converter of FIG. 1. The converter 1 of FIG. 4 corresponds to the converter 1 of FIG. 1. Thus, the description of the converter 1 of FIG. 1 is correspondingly valid for the converter 1 of FIG. 4 and in the following mainly a difference, especially an optional feature, of the converter 1 of FIG. 4 with regard to the converter 1 of FIG. 1 is described.

[0102] As shown in FIG. 4, the converter 1 comprises one or more additional first power converters 21a with the first terminal X of the additional first power converter 21a being electrically connected to a respective further terminal Ta of the converter 1 and the second and third terminal Y1 , Y2 being electrically connected to the first and second terminal of the first capacitor unit C 1 , respectively. According to FIG. 3 one additional first power converter 21a is shown. This is only by way of example and, thus, more than one additional first power converter 21a may be provided. The converter 1 comprises one or more additional second power converters 22a with the first terminal X of the additional second power converter being electrically connected to a respective further terminal Tb of the converter 1 and the second and third terminal Yl, Y2 being electrically connected to the first and second terminal of the second capacitor unit C2, respectively. According to FIG. 3 one additional second power converter 22a is shown. This is only by way of example and, thus, more than one additional second power converter 22a may be provided. Providing additional first and second power converters 21a, 22a allows connecting additional voltage sources 101, 201 to the converter 1. For example, a voltage source 201 may be connected with the further terminal Ta and the fourth terminal T4 of the converter 1, and a voltage source 101 may be connected with the further terminal Tb and the first terminal T1 of the converter 1.

[0103] The one or more additional first power converters 21a are implemented in line with the first power converter 21. Thus, a description of the first power converter 21 , such as a description of the structure and control of the first power converter 21 , is correspondingly valid for the one or more additional first power converters 21a. The one or more additional second power converters 22a are implemented in line with the second power converter 22. Thus, a description of the second power converter 22, such as a description of the structure and control of the second power converter 22, is correspondingly valid for the one or more additional second power converters 22a. The description with regard to the sources 100, 200 is correspondingly valid for the sources 101, 201.

[0104] The implementation form of FIG. 4 allows connecting multiple 2n voltage sources, such as PV systems and / or BES to the converter 1, wherein n is an integer that is greater than one (n > 1). The number of power converters 21, 22, 21a, 22a equals to the number of voltage sources that may be connected to the converter 1. In case n equals 1 (n = 1 ), the converter corresponds to the implementation form of FIG. 1 for two voltage sources.

[0105] According to the example of FIG. 4, the resonant circuit 40 of each circuit 50 is implemented in line with the implementation of the resonant circuit 40 of each circuit 50 shown in FIG. 2. Thus, the description of FIG. 2 is correspondingly valid. The implementation form of the converter 1 is not limited to the implementation form of the resonant circuit 40 shown in FIG. 2 and, thus, the resonant circuit may be implemented differently, with above description of FIG. 4 being still valid. For example, the resonant circuit 40 of each circuit 50 may be implemented in line with the implementation of the resonant circuit 40 of each circuit 50 shown in FIG. 3. In this case, the description of FIG. 3 is correspondingly valid.

[0106] FIGs 5 a), 5 b), 6 a) and 6 b) each show an example of an implementation form of a power converter of the converter of any one of FIGs 1, 2, 3 and 4. The implementation of the controllable semiconductor switches of the power converters of FIGs 5 a), 5 b), 6 a) and 6 b) is only by way of example and, thus, may be implemented by a different controllable semiconductor switch type, such as a different transistor type, compared to the type shown in the respective Figure. The number of capacitors of the respective capacitor unit Cl, C2 may be different compared to the shown number.

[0107] As shown in FIG. 5 a), the power converter 21, 22 may comprise an inductor LI and two controllable semiconductor switches SI, S2. In the example of FIG. 5 a) the two switches SI, S2 are two IGBTs, wherein a diode is connected in anti-parallel to each IGBT. As shown in FIG. 5 a), a first terminal of the inductor LI is connected with the first terminal X of the power converter 21, 22. A first terminal of the switch SI (e.g. the emitter terminal of the IGBT SI) is connected with the second terminal of the inductor LI and a second terminal of the switch SI (e.g. the collector terminal of the IGBT SI) is connected with the second terminal Yl of the power converter 21, 22. A first terminal of the switch S2 (e.g. the emitter terminal of the IGBT S2) is connected with the third terminal Y2 of the power converter 21, 22. A second terminal of the switch S2 (e.g. the collector terminal of the IGBT S2) is connected with the second terminal of the inductor LI . The third terminal of the controllable semiconductor switches SI, S2 are the control terminals (e.g. gate terminal of the IGBT) via which the controllable semiconductor switches SI, S2 may be controlled with control signals, such as PWM signals.

[0108] As shown in FIG. 5 b), the power converter 21, 22 may have the structure of the power converter 21, 22 of FIG. 5 a) and additionally may comprise a bidirectional semiconductor switch that is formed by two controllable semiconductor switches S3 and S4 (e.g. two IGBTs, wherein a diode is connected in anti-parallel to each IGBT). The bidirectional switch may be connected between the second terminal of the inductor LI and a fourth terminal Y3 of the power converter 21, 22. The fourth terminal Y3 may be connected with a node between two capacitors of a respective capacitor unit Cl, C2.

[0109] As shown in FIG. 6 a) the power converter 21 , 22 may comprise an inductor L 1 , four controllable semiconductor switches S 1 , S2, S3, S4 (e.g. four IGBTs) and a capacitor C4. A first terminal of the inductor LI is connected with the first terminal X of the power converter 21, 22. A second terminal of the inductor LI is connected with a first terminal of a first switch SI (e.g. emitter terminal of IGBT SI) and a second terminal of a second switch S2 (e.g. collector terminal of IGBT S2). The second terminal of the first switch SI (e.g. collector terminal of IGBT SI) is connected with a first terminal of the capacitor C4 and the first terminal of the second switch S2 (e.g. emitter terminal of IGBT S2) is connected with a second terminal of the capacitor C4. The third switch S3 (e.g. IGBT S3) is connected between the first terminal of the capacitor C4 and the second terminal Y1 of the power converter 21, 22, as shown in FIG. 6 a). The fourth switch S4 (e.g. IGBT S4) is connected between the second terminal of the capacitor C4 and the third terminal Y2 of the power converter 21 , 22, as shown in FIG. 6 a).

[0110] As shown in FIG. 6 b), the power converter 21, 22 may have the structure of the power converter 21, 22 of FIG. 6 a), wherein the capacitor C4 may be replaced by a fifth and sixth controllable semiconductor switch S5, S6 (e.g. IGBTs S5, S6). The fifth switch S5 (e.g. IGBT S5) is connected between the second terminal of the first switch SI and a fourth terminal Y3 of the power converter 21, 22, as shown in FIG. 5 b). The sixth switch S6 (e.g. IGBT S6) is connected between the first terminal of the second switch S2 and the fourth terminal Y3 of the power converter 21, 22, as shown in FIG. 6 b). The fourth terminal Y3 may be connected with a node between two capacitors of a respective capacitor unit Cl, C2.

[0111] FIGs 7 a) and 7b) each show an example of an implementation form of the converter of FIG. 1. Especially, FIGs 7 a) and 7 b) show an example of the series connected capacitor units and the respective circuits 50 of an implementation form of the converter, in case the converter comprises multiple, e.g. two, third capacitor units. As shown in FIGs 7 a) and 7 b), in this case a circuit 50 is provided for each pair of neighboring capacitor units Cl, C3 or C3, C3, or C3, C2 of the series connection of the first capacitor unit Cl, second capacitor unit C2 and the two third capacitor units C3. According to FIGs 7 a) and 7 b), two third capacitor units C3 are provided. This is only by way of example and, thus, the converter 1 may comprise more than two capacitor units C3.

[0112] In the implementation form of the converter 1 of FIG. 7 a) the resonant circuit of each circuit 50 comprising the series connection of the capacitor Cr and inductor Lr is implemented in line with the implementation form of the resonant circuit 40 of the circuit 50 shown in FIG. 2. Thus, the description of FIG. 2 is correspondingly valid for the converter 1 of FIG. 7 a). In the implementation form of the converter 1 of FIG. 7 b) the resonant circuit of each circuit 50 comprising the capacitor Cr and inductor Lr is implemented in line with the implementation form of the resonant circuit 40 of the circuit 50 shown in FIG. 3. Thus, the description of FIG. 3 is correspondingly valid for the converter 1 of FIG. 7 b).

[0113] Each of FIGs 8, 9 and 10 shows an example of an implementation form of the converter of FIG. 1. In the implementation forms of FIGs 8, 9 and 10 the resonant circuit 40 of each circuit 50 is implemented in line with the implementation form of the resonant circuit 40 of the circuit 50 shown in FIG. 2. The description of FIG. 2 is correspondingly valid for the converter 1 of FIGs 8, 9 and 10. This is only by way of example and, thus, the resonant circuit 40 may be differently implemented. For example, with regard to the implementation forms of FIGs 8, 9 and 10, the resonant circuit 40 of the circuit 50 may be implemented in line with the implementation form of the resonant circuit 40 of the circuit 50 shown in FIG. 3. In this case, the description of FIG. 3 is correspondingly valid for the converter 1 of FIGs 8, 9 and 10. The following description of FIGs 8, 9 and 10 is valid irrespective of the implementation form of the resonant circuit 40 of the circuit 50. Moreover, the optional feature described with regard to FIG. 4 may be implemented in any one of the converters of FIGs 8, 9 and 10.

[0114] The converter of FIG. 8 corresponds to the converter of FIG. 1. Thus, the description of the converter of FIG. 1 is correspondingly valid for the converter of FIG. 8 and in the following mainly the implementation of the power converters 21 and 22 and the semiconductor switch units 31, 32 of the circuit 50 are described.

[0115] As shown in FIG. 8, each of the first and second power converter 21 , 22 may comprise an inductor L 1 , a controllable semiconductor switch S 1 and an uncontrollable semiconductor switch D 1. The inductor L 1 is connected between the first terminal X of the power converter and a node, the uncontrollable semiconductor switch DI is connected between the node and the second terminal Y1 of the power converter, and the controllable semiconductor switch SI is connected between the node and the third terminal Y2 of the power converter, as shown in FIG. 8. The power converter 21, 22 of FIG. 8 have a 2-level boost topology. Due to the structure of the converter 1 of FIG. 8, semiconductor switches with 1 / 3 of semiconductor blocking voltage ratings to voltage across the series connection of the first capacitor unit Cl, second capacitor unit C2 and third capacitor unit C3 (e.g. to the full DC link) may be used. According to the example of FIG. 8, the controllable semiconductor switch SI is an IGBT with a diode connected in antiparallel to the IGBT, and the uncontrollable semiconductor switch DI is a diode. This is only by way of example. Thus, the controllable semiconductor switch SI may be implemented by a different controllable semiconductor switch type, e.g. different transistor type, and / or the uncontrollable semiconductor switch DI may be implemented by a different uncontrollable semiconductor switch type. The power converters 21, 22 are not limited to the implementation form shown in FIG. 8. That is, the power converters 21, 22 may be differently implemented, e.g. according to an implementation form of FIGs 5 a), 5 b), 6 a) and 6 b).

[0116] As shown in FIG. 8, the two semiconductor switch units 31, 32 of each circuit 50 may be implemented as follows: a semiconductor switch unit of the two semiconductor switch units 31, 32 comprises two controllable semiconductor switches S2, S3 electrically connected in series, and another semiconductor switch unit of the two semiconductor switch units 31, 32 of the circuit comprises two uncontrollable semiconductor switches D2, D3 electrically connected in series. For example, as shown in FIG. 8, a first semiconductor switch unit 31 of the circuit 50 connected in parallel to the third capacitor unit C3 and second capacitor unit C2 comprises two controllable semiconductor switches S2, S3 and a second semiconductor switch unit 32 of the aforementioned circuit 50 comprises two uncontrollable semiconductor switches D2, D3. The first semiconductor switch unit 31 of the circuit 50 connected in parallel to the first capacitor unit C 1 and third capacitor unit C3 comprises two uncontrollable semiconductor switches D2, D3 and the second semiconductor switch unit 32 of the aforementioned circuit 50 comprises two controllable semiconductor switches S2, S3. According to the example of FIG. 8, the controllable semiconductor switches S2, S3 of each circuit 50 are IGBTs with a diode connected in antiparallel to each IGBT, and the uncontrollable semiconductor switches D2, D3 of each circuit 50 are diodes. This is only by way of example. Thus, the controllable semiconductor switches may be implemented by a different controllable semiconductor switch type, e.g. different transistor type, and / or the uncontrollable semiconductor switches may be implemented by a different uncontrollable semiconductor switch type.

[0117] On the top left of FIG. 8, an example of a control unit 400 of the converter 1 is shown, which may be part of the converter 1. The control unit 400 may be configured to control the controllable semiconductor switches of the converter 1 , especially the switch SI of the power converters 21, 22 and the switches S2 and S3 of the circuits 50. As shown in FIG. 8, for this, the control unit 400 may obtain for example a current II at the first terminal X of the first power converter 21, a current 12 at the first terminal X of the second power converter 22, a voltage VI of the first capacitor unit Cl, a voltage V2 of the second capacitor unit C2 and a voltage V3 of the third capacitor unit C3. The control unit 400 may provide control signals, e.g. PWM control signals, “21 - S 1”, “22 - S 1”, “31” and “32” for controlling the switch SI of the first power converter 21 , the switch SI of the second power converter 22, the first semiconductor switch unit 31 of the circuit 50 being parallel to the third and second capacitor unit C3, C2 and the second semiconductor switch unit 32 of the circuit 50 being parallel to the first and third capacitor unit Cl, C3, respectively.

[0118] Controlling a semiconductor switch unit comprising two controllable semiconductor switches connected in series to switch to the conducting state (on-state) or non-conducting state (off-state) comprises controlling the two controllable semiconductor switches to switch to the conducting state (on-state) or non-conducting state (off-state), respectively.

[0119] The implementation form of FIG. 8 is an example of the converter 1 being unidirectional. That is, there may be a power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter and, thus, from the voltage sources 100, 200 to the load 300.

[0120] The power converters 21, 22 and the two semiconductor switch units 31, 32 of each circuit 50 may be differently implemented, as exemplarily shown in FIG. 9.

[0121] The converter of FIG. 9 corresponds to the converter of FIG. 8. Thus, the description of the converter of FIG. 8 is correspondingly valid for the converter of FIG. 9 and in the following mainly difference(s) of the converter of FIG. 9 with regard to the converter of FIG. 8 is described.

[0122] As shown in FIG. 9, the converter 1 of FIG. 9 differs from the converter 1 of FIG. 8 in that in each power converter of the first and second power converter 21, 22 the uncontrollable semiconductor DI is replaced by a controllable semiconductor switch S2. According to the example of FIG. 9, the controllable semiconductor switches SI, S2 of the power converters 21, 22 are IGBTs with a diode connected in antiparallel to each IGBT. This is only by way of example. Thus, the controllable semiconductor switches may be implemented by a different controllable semiconductor switch type, e.g. different transistor type.

[0123] As shown in FIG. 9, the converter 1 of FIG. 9 differs from the converter 1 of FIG. 8, in that each semiconductor switch unit of the series connection of two semiconductor switch units 31 , 32 of each circuit 50 of the converter 1 comprises two controllable semiconductor switches S3, S4 electrically connected in series. According to the example of FIG. 9, the controllable semiconductor switches S3, S4 of the semiconductor switch units 31, 32 of each circuit 50 are IGBTs with a diode connected in antiparallel to each IGBT. This is only by way of example. Thus, the controllable semiconductor switches may be implemented by a different controllable semiconductor switch type, e.g. different transistor type.

[0124] The implementation form of FIG. 9 allows a bidirectional power flow over the converter 1. Thus, the converter 1 of FIG. 9 is an example of a bidirectional converter. As a result, the first and second voltage sources 100, 200 may be rechargeable battery energy storages (BES) and the load 300 may be configured to use electrical energy from the BES 100, 200 (power flow from the terminals Tl, T2, T3, T4 to the terminals T5, T6 of the converter 1) and charge the BES 100, 200 with electrical energy (power flow from the terminals T5, T6 to the terminals Tl , T2, T3, T4 of the converter 1 ).

[0125] The converter of FIG. 10 corresponds to the converter of FIG. 9. Thus, the description of the converter of FIG. 9 is correspondingly valid for the converter of FIG. 10 and in the following mainly a difference, especially an optional feature, of the converter of FIG. 10 with regard to the converter of FIG. 9 is described. In line with FIG. 7 a), FIG. 10 shows an implementation form, in which the converter 1 comprises multiple, e.g. two, third capacitor units C3. As shown in FIG. 10, in this case a circuit 50 is provided for each pair of neighboring capacitor units Cl, C3 or C3, C3, or C3, C2 of the series connection of the first capacitor unit Cl, second capacitor unit C2 and the two third capacitor units C3. According to FIG. 10, two third capacitor units C3 are provided. This is only by way of example and, thus, the converter 1 may comprise more than two capacitor units C3. According to another example (not shown in FIG. 10), the converter 1 of FIG. 10 may be differently implemented in that the power converters 21 , 22 and the semiconductor switch units 31, 32 of each circuit 50 of the converter 1 are implemented in line with the power converters 21, 22 and the semiconductor switch units 31, 32 of each circuit 50 of the converter 1 of FIG. 8. The converter of FIG. 10 allows achieving a further reduction of semiconductor voltage rating compared to the converter of FIGs 8 and 9, in the expense of reduced controllable voltage range. This allows reducing costs for producing the converter 1.

[0126] The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A converter ( 1 ) comprising : a first, second, third and fourth terminal (T1 , T2, T3, T4) for receiving DC voltages, a first and second power converter (21 , 22) each comprising a first, second and third terminal (X, Y1 , Y2) and one or more controllable semiconductor switches for controlling a conversion of a voltage at the first terminal (X) to a further voltage of lower or higher level at the second and third terminal (Y1 , Y2), a series connection of a first capacitor unit (Cl), second capacitor unit (C2) and one or more third capacitor units (C3), and for each two neighboring capacitor units of the series connection of the first capacitor unit (Cl), second capacitor unit (C2) and one or more third capacitor units (C3) a circuit (50) comprising a series connection of two semiconductor switch units (31, 32) and a resonant circuit (40) electrically connected with the two semiconductor switch units (31, 32); wherein the first terminal (X) of the first power converter (21) is electrically connected with the second terminal (T2) of the converter (1 ), the second and third terminal (Yl, Y2) of the first power converter (21) are electrically connected with a first and second terminal of the first capacitor unit (C 1 ), respectively, the first terminal of the converter (Tl) is electrically connected with the first terminal of the first capacitor unit (Cl), the first terminal (X) of the second power converter (22) is electrically connected with the third terminal (T3) of the converter (1 ), the second and third terminal (Yl, Y2) of the second power converter (22) are electrically connected with a first and second terminal of the second capacitor unit (C2), respectively, the fourth terminal (T4) of the converter (1) is electrically connected with the second terminal of the second capacitor unit (C2), the one or more third capacitor units (C3) are electrically connected in series between the second terminal of the first capacitor unit (Cl) and the first terminal of the second capacitor unit (C2), and the circuit (50) is electrically connected with each two neighboring capacitor units of the series connection of the first capacitor unit (Cl), second capacitor unit (C2) and one or more third capacitor units (C3) such that the series connection of two semiconductor switch units (31, 32) of the circuit (50) is electrically connected in parallel with the two neighboring capacitor units.

2. The converter (1) according to claim 1, comprising: one or more additional first power converters (21, 21a) with the first terminal (X) being electrically connected to a respective further terminal (Ta) of the converter (1) and the second and third terminal (Yl, Y2) being electrically connected to the first and second terminal of the first capacitor unit (C 1 ), respectively, and / or one or more additional second power converters (22, 22a) with the first terminal (X) being electrically connected to a respective further terminal (Tb) of the converter (1) and the second and third terminal (Yl, Y2) being electrically connected to the first and second terminal of the second capacitor unit (C2), respectively.

3. The converter (1) according to any one of the previous claims, wherein each of the first and second power converter (21 , 22) is a partial power converter.

4. The converter (1 ) according to any one of the previous claims, wherein the converter (1) is unidirectional and each of the first, second, third and fourth terminal (Tl, T2, T3, T4) of the converter (1 ) is an input terminal, or the converter (1 ) is bidirectional.

5. The converter (1) according to any one of the previous claims, wherein the converter (1 ) comprises a fifth and sixth terminal (T5, T6) that are configured to be electrically connected with an electrical load (300), the fifth terminal (T5 ) is electrically connected with the first terminal of the first capacitor unit (Cl), and the sixth terminal (T6) is electrically connected with the second terminal of the second capacitor unit (C2).

6. The converter (1 ) according to any one of the previous claims, wherein each semiconductor switch unit of the series connection of two semiconductor switch units (31 , 32) of the circuit (50) comprises two controllable semiconductor switches (S2, S3) electrically connected in series.

7. The converter (1) according to any one of claims 1 to 5, wherein a semiconductor switch unit of the series connection of two semiconductor switch units (31, 32) of the circuit (50) comprises two controllable semiconductor switches (S2, S3) electrically connected in series, and another semiconductor switch unit of the series connection of two semiconductor switch units (31 , 32) of the circuit comprises two uncontrollable semiconductor switches (D2, D3) electrically connected in series.

8. The converter (1) according to any one of the previous claims, wherein the resonant circuit (40) of the circuit (50) comprises a series connection of a capacitor (Cr) and an inductor (Lr), a first end of the series connection of the capacitor (Cr) and the inductor (Lr) is electrically connected with a first semiconductor switch unit (31 ) of the series connection of two semiconductor switch units (31 , 32), and a second end of the series connection of the capacitor (Cr) and the inductor (Lr) is electrically connected with a second semiconductor switch unit (32) of the series connection of two semiconductor switch units (31 , 32).

9. The converter (1 ) according to claim 8 when depending on claim 6 or 7, wherein the first end of the series connection of the capacitor (Cr) and the inductor (Lr) is electrically connected with a node between the two semiconductor switches of the first semiconductor switch unit (31 ) of the series connection of two semiconductor switch units (31, 32), and the second end of the series connection of the capacitor (Cr) and the inductor (Lr) is electrically connected with a node between the two semiconductor switches of the second semiconductor switch unit (32) of the series connection of two semiconductor switch units (31, 32).

10. The converter (1) according to any one of claims 1 to 7, wherein the resonant circuit (40) of the circuit comprises a capacitor (Cr) and an inductor (Lr), a first terminal and second terminal of the capacitor (Cr) is electrically connected with a first semiconductor switch unit (31) and a second semiconductor switch unit (32), respectively, of the series connection of two semiconductor switch units (31, 32), a first terminal of the inductor (Lr) is electrically connected with a node between the two semiconductor switch units (31, 32) of the series connection of two semiconductor switch units (31, 32), anda second terminal of the inductor is electrically connected with a node between the two neighboring capacitor units of the series connection of the first capacitor unit (C 1 ), second capacitor unit (C2) and one or more third capacitor units (C3).

11. The converter (1) according to claim 10 when depending on claim 6 or 7, wherein the first terminal of the capacitor (Cr) is electrically connected with a node between the two semiconductor switches of the first semiconductor switch unit (31 ) of the series connection of two semiconductor switch units (31, 32), and the second terminal of the capacitor (Cr) is electrically connected with a node between the two semiconductor switches of the second semiconductor switch unit (32) of the series connection of two semiconductor switch units (31, 32).

12. The converter (1 ) according to any one of the previous claims, wherein the converter (1) is configured to control the semiconductor switches of the power converters (21, 22) of the converter (1) by performing a maximum power point tracking, MPPT, algorithm.

13. The converter ( 1 ) according to any one of the previous claims, wherein the converter (1) is configured to control the two semiconductor switch units (31, 32) of the circuit (5) for each two neighboring capacitor units such that at any time only one of the two semiconductor switch units (31, 32) is in the conducting state.

14. The converter (1) according to any one of the previous claims, wherein the converter (1) is configured to control the two semiconductor switch units (31, 32) of the circuit (50) for each two neighboring capacitor units with a frequency that is smaller than or equal to a resonant frequency of the resonant circuit (40) of the circuit (50) for each two neighboring capacitor units.

15. The converter according to any one of the previous claims, wherein a capacitor unit of the first capacitor unit (C 1 ), second capacitor unit (C2) and one or more third capacitor units (3) comprises or is a capacitor (Cl 1) or a series connection of multiple capacitors (Cl 1, C12).

16. A method for controlling a converter (1) according to any one of claims 1 to 15, wherein the method comprises: controlling the semiconductor switches of the power converters (21, 22) of the converter (1) by performing a maximum power point tracking, MPPT, algorithm.

17. The method according to claim 16, wherein the method comprises: controlling the two semiconductor switch units (31, 32) of the circuit (5) for each two neighboring capacitor units such that at any time only one of the two semiconductor switch units (31, 32) is in the conducting state.

18. The method according to claim 16 or 17, wherein the method comprises: controlling the two semiconductor switch units (31 , 32) of the circuit (50) for each two neighboring capacitor units with a frequency that is smaller than or equal to a resonant frequency of the resonant circuit (40) of the circuit (50) for each two neighboring capacitor units.

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