DC / DC converter and method for operating a DC / DC converter and inverter having a DC / DC converter

Abstract

The invention relates to a DC / DC converter (10, 20) for the transfer of electrical power between a first DC connection (12) and a second DC connection (14), wherein the first DC connection (12) has a first positive pole (P1+) and a first negative pole (P1-) and is designed for two-pole connection to a unipolar DC source, in particular to a photovoltaic generator, wherein the second DC connection (14) has a second positive pole (P2+) and a second negative pole (P2-) and a center pole (PM) and is designed for three-pole connection to a bipolar load, in particular to a three-level DC / AC converter (16), wherein the DC / DC converter (10, 20) has a bridge circuit which has a first series circuit of a first semiconductor element (T1) and a second semiconductor element (T2) between the second positive pole (P2+) and the center pole (PM) as well as a second series circuit of a third semiconductor element (T3) and a fourth semiconductor element (T4) between the center pole (PM) and the second negative pole (P2-), wherein the first positive pole (P1+) is connected via a first connection to a first center tap between the first and the second semiconductor element (T1, T2), wherein the first negative pole (P1-) is connected via a second connection to a second center tap between the third and the fourth semiconductor element (T3, T4), wherein a first choke (L1) is arranged in the first connection and a second choke (L2) is arranged in the second connection, wherein the first choke and the second choke (L1, L2) are symmetrical to one another. The invention also relates to a method for operating a DC / DC converter (10, 20), and to an inverter (30) having a DC / DC converter (10, 20) and a method for operating an inverter (30) having a DC / DC converter (10, 20).

Description

[0001] DC / DC CONVERTER AND METHOD FOR OPERATING A DC / DC CONVERTER AND INVERTER WITH A DC / DC CONVERTER

[0002] TECHNICAL FIELD

[0003] The application relates to a DC / DC converter (DC: Direct Current) and a method for operating a DC / DC converter, as well as to an inverter with a DC / DC converter. A DC / DC converter, also referred to as a DC-DC converter, is an electronic circuit that converts an input direct voltage (DC) into an output direct voltage (DC), which can be either higher, lower, or inverse to the input voltage. This conversion can be achieved using a bridge circuit of semiconductor elements, e.g., clocked semiconductor switches. An inverter converts an input direct voltage (DC) into an output alternating voltage (AC) and for this purpose comprises a DC / DC converter and a DC / AC converter that converts the output direct voltage of the DC / DC converter into the output alternating voltage.

[0004] STATE OF THE ART

[0005] From DE 20 2022 100 172 U1 a power converter is known in which, in order to protect a DC intermediate circuit in the event of a semiconductor defect, an electrical connection between a center point of a DC-side divided intermediate circuit capacitance and a center point of the DC / AC inverter bridge can be switched and (if necessary) separated, whereby this connection is always conductive in normal operation, ie without the presence of a semiconductor defect.

[0006] From DE 10 2021 200 628 A1 a DC-DC converter is known which is designed to transfer electrical power between a unipolar first DC connection and a unipolar second DC connection and comprises a series circuit of four semiconductor switches, wherein a unipolar DC voltage is applied via a respective choke to center taps between the first and second and between the third and fourth semiconductor switches of the series circuit and is converted into a unipolar DC output voltage by means of the semiconductor switches, wherein the DC output voltage is passed through a series circuit of filter capacitors whose center point is connected to a center pole of the series circuit of the semiconductor switches.

[0007] TASK

[0008] The application is based on the object of providing an improved DC / DC converter and an improved method for operating a DC / DC converter as well as an improved inverter with a DC / DC converter and an improved method for operating an inverter with a DC / DC converter.

[0009] SOLUTION

[0010] The object is achieved by a DC / DC converter having the features of independent claim 1 and a method having the features of independent claim 6, as well as an inverter having the features of claim 11 and a method having the features of claim 12. Embodiments of the application are recited in the dependent claims.

[0011] DESCRIPTION

[0012] A DC / DC converter is configured for the transfer of electrical power between a first DC terminal of the DC / DC converter and a second DC terminal of the DC / DC converter. The first DC terminal has a first positive pole and a first negative pole and is configured for a two-pole connection to a unipolar DC source, in particular to a photovoltaic generator or a battery. The second DC terminal has a second positive pole, a second negative pole, and a center pole. The center pole is arranged between the second positive pole and the second negative pole. The potential of the center pole lies between the second positive pole and the second negative pole. The second DC terminal is configured for a three-pole connection to a bipolar load, in particular to a three-level DC / AC converter, and is therefore suitable, for example, for use on the DC side of an inverter with a split intermediate circuit.

[0013] The DC / DC converter comprises a bridge circuit comprising a first series circuit of a first semiconductor element and a second semiconductor element between the second positive pole and the center pole, and a second series circuit of a third semiconductor element and a fourth semiconductor element between the center pole and the second negative pole. The semiconductor elements of the bridge circuit can, for example, comprise tactile semiconductor switches that can be switched back and forth between conducting and non-conducting. The semiconductor elements of the bridge circuit can also comprise unidirectionally conductive elements, such as diodes.

[0014] The first positive pole is connected via a first connection to a first center tap between the first and second semiconductor elements. The first negative pole is connected via a second connection to a second center tap between the third and fourth semiconductor elements. A first choke is arranged in the first connection and a second choke is arranged in the second connection. The first choke and the second choke are designed symmetrically to one another. Electrical chokes are also referred to as coils or inductors. Symmetrical chokes have respective inductances, each of which has approximately the same properties. Symmetrical chokes are particularly advantageous for use in circuits with symmetrical signals. The symmetry of this DC / DC converter results from the second DC connection, which has the center pole.For the second DC connection, for example, the aim can be to keep the center pole at a potential midway between the second positive pole and the second negative pole. This results in a symmetrical design in which the symmetrical choke can suppress or reduce parasitic currents, particularly common mode currents, by clocking the semiconductor elements of the bridge circuit, leading to more efficient power transmission. Common-mode currents are parasitic currents that flow in the same direction on the positive lines assigned to the respective positive poles and on the negative lines assigned to the respective negative poles, particularly via ground. The described reduction in common-mode voltages by the symmetrical chokes can also contribute to improving the electromagnetic compatibility (EMC) of the DC / DC converter.This can lead to less interference with other electronic devices and increase overall system reliability.

[0015] The symmetrical design of the first and second chokes can be configured such that the first and second chokes have the same inductance values. In some embodiments, the first and second chokes can have the same number of turns. In some embodiments, the first and second chokes can be wound identically, each with the same number of turns.

[0016] In embodiments of the DC / DC converter, the first and second chokes are magnetically coupled. Magnetically coupled chokes are wound on a common magnetic core. This allows for a reduction of common-mode currents as well as differential-mode noise.

[0017] In embodiments of the DC / DC converter, the first connection and the second connection are connected via a further coupled choke. The coupled choke has two coils, one in the first connection and one in the second connection, which are wound on a common magnetic core. This allows for even better filtering of parasitic currents, especially higher-frequency interference, and prevents excessive currents, especially excessive common-mode currents.

[0018] In embodiments of the DC / DC converter, a further series circuit comprising a first and a second capacitor is arranged between the first positive pole and the first negative pole, with a further center tap between the first and second capacitors, wherein the further center tap and the center pole of the second DC connection are connected via a third capacitor. Such a capacitive center connection can further improve the filtering of parasitic currents, particularly low-frequency interference. In particular, excessively high common-mode voltages can also be avoided.

[0019] The DC / DC converter is designed to transfer electrical power between the first DC terminal and the second DC terminal. The first DC terminal has the first positive pole and the first negative pole and, during operation, is connected in two poles to a unipolar DC source, in particular to a photovoltaic generator or a battery. The second DC terminal has the second positive pole, a second negative pole, and the center pole and, during operation, is connected in three poles to a bipolar load, in particular to a three-level DC / AC converter. The bridge circuit of the DC / DC converter has the first series connection of the first semiconductor switch and the second semiconductor switch between the second positive pole and the center pole, and the second series connection of the third semiconductor switch and the fourth semiconductor switch between the center pole and the second negative pole.

[0020] A method for operating such a DC / DC converter for transferring electrical power between the first and the second DC terminal and thus during operation between a connected DC source and a connected load has symmetrical switching states and at least one asymmetrical switching state.

[0021] In the symmetrical switching states, the first and fourth semiconductor switches are switched on or off at the same time, and in the opposite direction, the second and third semiconductor switches are switched on or off at the same time. In the asymmetrical switching states, the first and third semiconductor switches are switched on or off at the same time, and in the opposite direction, the second and fourth semiconductor switches are switched on or off at the same time. Simultaneously here means the periods in which the semiconductor switches connected together predominantly have the same switching state, i.e. are switched on or off, whereby the actual switch-on or switch-off times can differ from one another by fractions of the duration of the respective switching state, for example to take dead times into account.

[0022] To transfer electrical power via the DC / DC converter, the symmetrical switching states are alternately adopted, and one of the asymmetrical switching states is only adopted when needed. In this context, "only when needed" means that the duration of the asymmetrical switching state over the operating life of the DC / DC converter is significantly shorter than that of the symmetrical switching states. Due to the predominantly symmetrical switching, potential jumps at the DC terminals and thus common-mode voltages can be reduced or even avoided. The symmetrical switching states produce no or only low common-mode voltages, and the asymmetrical switching states, which can generate more common-mode voltages, can be reduced to a minimum.At the same time, power transmission can be further optimized by transferring asymmetric power to or from the second DC connection via asymmetric clocking only when it is needed.

[0023] In embodiments of the method, the need for asymmetric switching states is detected when the power drawn from the two parts of the second DC connection by the bipolar load is unequal, for example when a three-level DC / AC converter of an inverter draws electrical power asymmetrically from a split intermediate circuit connected to the second DC connection. The two parts of the second DC connection refer to a first part between the second positive pole and the center pole on the one hand, and to a second part between the center pole and the second negative pole on the other. If it is desired that the potential of the center pole lies symmetrically between the potentials of the second positive pole and the second negative pole, a need for asymmetric switching states can also be detected if the potential of the center pole is not symmetrical between the potentials of the second positive pole and the second negative pole (P2-).Furthermore, a need for asymmetric switching states can be recognized if the position of the potential of the center pole relative to the potentials of the second positive pole and the second negative pole changes and this change is to be counteracted in order to stabilize the position of the potential of the center pole relative to the potentials of the second positive pole and the second negative pole.

[0024] One embodiment of the method has a first symmetrical switching state in which the first and fourth semiconductor switches are simultaneously switched to conduction and the second and third semiconductor switches are simultaneously switched to non-conduction. In a second symmetrical switching state, the first and fourth semiconductor switches are simultaneously switched to non-conduction and the second and third semiconductor switches are simultaneously switched to conduction. In a first asymmetrical switching state, the first and third semiconductor switches are simultaneously switched to conduction and the second and fourth semiconductor switches are simultaneously switched to non-conduction. In a second asymmetrical switching state, the first and third semiconductor switches are simultaneously switched to non-conduction and the second and fourth semiconductor switches are simultaneously switched to conduction.

[0025] In embodiments of the method, the first and second symmetrical switching states are alternately adopted for the transfer of electrical power, and the first asymmetrical switching state is adopted only when required instead of the first symmetrical switching state.

[0026] In embodiments of the method, the first and second symmetrical switching states are alternately adopted for the transfer of electrical power, and the second asymmetrical switching state is adopted only when required instead of the second symmetrical switching state.

[0027] Optionally, the described method can be selected for operating the described embodiments of the DC / DC converter.

[0028] This allows any common-mode voltages that may occur to be further reduced both in terms of time and amplitude. This means that common-mode voltages can occur less frequently, and the amplitudes of any common-mode voltages that do occur can be reduced, thus reducing the common-mode currents generated by the DC / DC converter.

[0029] The power conversion by the DC / DC converter with positive and negative poles symmetrically coupled by chokes already exhibits a reduced common-mode voltage due to the symmetrical chokes, which occurs even less frequently due to the described asymmetrical switching states. The common-mode voltage can be further reduced by the capacitive center connection via the third capacitor, especially if the coupling inductance and the third capacitor form a resonant circuit with a suitable resonant frequency. The common-mode voltages reduced by the symmetrical and / or coupled chokes and, if applicable, by the capacitive center connection are generated only as often as absolutely necessary due to the asymmetrical switching states.

[0030] The method and the described DC / DC converter can therefore be advantageously combined to further improve the overall reduction of common-mode voltages and the associated common-mode currents.

[0031] This is particularly advantageous if, for example, a three-level DC / AC converter is connected to the second DC connection, which is part of an inverter with a split intermediate circuit forming an island grid. If this inverter is loaded asymmetrically on the output side, e.g. by a zero-sequence system or negative-sequence system on the AC side (AC: alternating current), then the intermediate circuit of the inverter is also loaded asymmetrically and, as a result, power is drawn asymmetrically via the second DC connection. This asymmetric power draw can be compensated for by temporarily asymmetrical clocking. The risk of common-mode voltages and common-mode currents can be reduced by the described DC / DC converter or the described method, or a combination of the two.

[0032] An inverter with a three-level DC / AC converter can therefore be particularly advantageously constructed with a DC / DC converter as described above, with a unipolar first DC connection and a bipolar second DC connection. The method for operating the DC / DC converter described above can be advantageously used to operate the inverter. In a particularly advantageous embodiment, the three-level DC / AC converter draws unequal electrical power from the two parts of the bipolar second DC connection, which fundamentally negatively influences the position of the potential of the center pole relative to the potentials of the second positive pole and the second negative pole.According to the application, the position of the potential of the center pole relative to the potentials of the second positive pole and the second negative pole is at least stabilized by assuming the asymmetric switching state of the DC / DC converter as needed, and ideally the position of the potential of the center pole is symmetrical relative to the potentials of the second positive pole and the second negative pole.

[0033] Overall, more efficient power transfer and on-demand asymmetric switching can help reduce heat generation in the system, leading to improved thermal performance. Furthermore, the overall performance and reliability of the DC / DC converter and the resulting inverter can be improved, which can expand its applicability in various applications.

[0034] BRIEF DESCRIPTION OF THE CHARACTERS

[0035] In the following, the application is further explained and described using exemplary embodiments shown in the figures.

[0036] Fig. 1 shows a first embodiment of a DC / DC converter.

[0037] Fig. 2 shows a second embodiment of a DC / DC converter.

[0038] Fig. 3 shows the first embodiment of the DC / DC converter in an inverter.

[0039] Fig. 4 shows time courses of successive switching states of the DC / DC converter.

[0040] The same reference numerals are used throughout the figures for identical or similar elements. The illustrations in the figures may not be to scale. DESCRIPTION OF THE FIGURES

[0041] Figure 1 shows a first embodiment of a DC / DC converter 10. The DC / DC converter 10 is configured to transfer electrical DC power between a first DC terminal 12 and a second DC terminal 14. The DC / DC converter 10, also called a DC-DC converter, is an electronic circuit design that can convert a DC voltage from one level to another.

[0042] The first DC connection 12 is unipolar and has a first positive pole P1+ and a first negative pole P1-. The second DC connection 14 is bipolar and has a second positive pole P2+, a center pole PM, and a second negative pole P2-. The first positive pole P1+ has a first positive potential. The second positive pole P2+ has a second positive potential. The first negative pole P1- has a first negative potential. The second negative pole P2- has a second negative potential. The potential of the center pole PM lies between the second positive potential and the second negative potential.

[0043] The conversion of the DC power from a first DC voltage at the first DC terminal 12 to a second DC voltage at the second DC terminal 14 occurs via a bridge circuit. The bridge circuit has a first series circuit of a first semiconductor element T1 and a second semiconductor element T2 between the second positive pole P2+ and the center pole PM. The bridge circuit also has a second series circuit of a third semiconductor element T3 and a fourth semiconductor element T4 between the center pole PM and the second negative pole P2-. The first series circuit and the second series circuit are connected in series with each other.

[0044] The first positive pole P1+ is connected via a first connection to a first center tap between the first semiconductor element T1 and the second semiconductor element T2. The first negative pole P1- is connected via a second connection to a second center tap between the third semiconductor element T3 and the fourth semiconductor element T4. A first choke L1 is arranged in the first connection from the first positive pole P1+ and a second choke L2 is arranged in the second connection from the first negative pole P1-. The first choke L1 and the second choke L2 are designed symmetrically to one another. The first choke L1 and the second choke L2 have, in particular, the same inductance values ​​and optionally the same number of windings. Such symmetrical chokes can effectively attenuate a common-mode voltage.Figure 1 shows, as an example, a first inductor current IL1, which flows on the DC line with the first positive potential from the first positive pole P1+ via the first inductor L1 toward the bridge circuit. It is also optionally possible for the first and second inductors L1, L2 to be magnetically coupled to each other, e.g., by being wound on the same core. Such coupled symmetrical inductors can then further improve common-mode rejection.

[0045] In the illustrated first embodiment of the DC / DC converter 10, the four semiconductor elements T1-T4 are designed as semiconductor switches which can be controlled and are conductive or non-conductive depending on the control. For such an embodiment, power can flow in both directions, from the first DC connection 12 to the second DC connection 14 and vice versa. Optionally, it is also possible for the first and fourth semiconductor elements T1, T4, for example, to be designed as diodes which block in the direction from positive potential to negative potential and conduct in the other direction. Optionally, it is also possible for the second and third semiconductor elements T2, T3, for example, to be designed as diodes which block in the direction from positive potential to negative potential and conduct in the other direction. For such examples, the direction of power transfer is then unidirectional.

[0046] Figure 2 shows a second embodiment of the DC / DC converter 20. Compared to the first embodiment of the DC / DC converter 10 in Figure 1, the illustrated second embodiment additionally features a coupled choke L3. The coupled choke L3 comprises a coil in each of the first and second connections. The two coils are magnetically coupled, e.g., by both coils being wound on the same magnetic core.

[0047] Figure 2 shows, as an example, a first inductor current IL1, which flows on the DC line with the first positive potential from the first positive pole P1+ via the coupled inductor L3 and first inductor L1 toward the bridge circuit. Figure 2 also shows, as an example, a common-mode current ICM, which, due to periodically varying potential differences between the first negative pole P1- and the second negative pole P2-, can flow via respective leakage capacitances and the ground potential PE. This common-mode current is reduced or even suppressed in the illustrated DC / DC converter according to the application.

[0048] In the second embodiment of the DC / DC converter 20 shown in Figure 2, a further series circuit comprising a first capacitor C1 and a second capacitor C2 is arranged between the first positive pole P1+ and the first negative pole P1-. The further series circuit has a further center tap between the first capacitor C1 and the second capacitor C2. A third capacitor C3 is arranged between the further center tap and the center pole PM of the second DC connection 14. The described arrangement of the capacitors C1, C2, C3 and the coupled choke L3 allows for improved filtering of parasitic currents and noise suppression. In particular, high-frequency noise and voltage spikes can be filtered. The short-term storage of energy in the third capacitor C3 and / or the coupled choke L3 allows for the common-mode current ICM to be reduced, e.g.by the capacitor C3 and the coupled choke L3 forming a resonant circuit designed for relevant interference frequencies, in particular the switching frequency of the semiconductor elements T1-T4. Furthermore, the resonant energy storage can improve the energy transfer efficiency of the second embodiment of the DC / DC converter 20.

[0049] In the illustrated second embodiment of the DC / DC converter 20, the four semiconductor elements T1-T4 are designed as semiconductor switches which can be controlled and are conductive or non-conductive depending on the control. For such an embodiment, power can flow in both directions, from the first DC connection 12 to the second DC connection 14 and vice versa. Optionally, it is also possible for the first and fourth semiconductor elements T1, T4, for example, to be designed as diodes which block in the direction from positive potential to negative potential and conduct in the other direction. Optionally, it is also possible for the second and third semiconductor elements T2, T3, for example, to be designed as diodes which block in the direction from positive potential to negative potential and conduct in the other direction. For such examples, the direction of power transfer is then unidirectional.

[0050] Figure 3 shows an inverter 30 with the DC / DC converter 10 according to Figure 1 and a DC / AC converter 16. Alternatively, the DC / DC converter 20 according to Figure 2 can be used in the inverter 30 (not shown), whereby the following statements apply analogously to both variants of the DC / DC converter 10, 20.

[0051] The second DC terminal 14 of the DC / DC converter 10 is connected to the DC / AC converter 16 via three poles, with the second positive pole P2+ being connected to a DC positive pole DC+, the second negative pole P2- being connected to a DC negative pole DC-, and the center pole PM being connected to a DC center potential DCM of the DC / AC converter 16. The DC / AC converter 16 is designed in particular as a three-level DC / AC converter and usually comprises a split DC intermediate circuit, the center point of which corresponds to the DC center potential DCM, as well as a DC / AC bridge circuit, which is designed, for example, in a known NPC topology.

[0052] The DC / AC converter 16 converts the bipolar DC output voltage of the DC / DC converter 10 (or the DC / DC converter 20 according to Figure 2) into an AC output voltage at the AC terminal AC, which is connected to an AC load, in particular to an AC grid 18. The connection between the inverter 30 and the AC grid 18 is preferably three-pole, whereby the AC grid can be designed, in particular, as a split-phase AC grid or as a three-phase system. Optionally, the center pole PM or the center potential DOM can be connected to any neutral conductor N of the AC grid 18.

[0053] Depending on the specific load on the inverter 30 by the AC grid 18 (or vice versa), asymmetric power flows may occur during operation, which may lead to an asymmetric load on the second DC connection 14; such an asymmetric load may be counteracted by the design of the DC / DC converter 10, 20 as registered and, in particular, by its operation as registered.

[0054] Figure 4 shows exemplary switching states of semiconductor elements T1-T4 with the associated curve of the first inductor current IL1. Semiconductor elements T1-T4 each have semiconductor switches that are controlled in a clocked manner. The switching states shown are assumed by the first embodiment of DC / DC converter 10 or the second embodiment of DC / DC converter 20 when operated accordingly.

[0055] In a first symmetrical switching state S1, the first and fourth semiconductor switches T1, T4 are simultaneously switched to conducting. In the first symmetrical switching state S1, the second and third semiconductor switches T2, T3 are also simultaneously switched to non-conducting. In the first symmetrical switching state S1, electrical power is exchanged symmetrically with the two parts of the second DC connection 14, i.e., essentially the same power is input or output with the upper part between the second positive pole P2+ and the center pole PM and with the lower part between the center pole PM and the second negative pole P2-.

[0056] In a second symmetrical switching state S2, the first and fourth semiconductor switches T1, T4 are simultaneously switched non-conductive. In the second symmetrical switching state S2, the second and third semiconductor switches T2, T3 are simultaneously switched conductive. The second switching state S2 represents a freewheeling phase in which a current flows in a circuit from the first positive pole P1+ via the first inductor L1, the second and third semiconductor switches T2, T3 and second inductor L2 to the first negative pole P1-, wherein no electrical power is exchanged with the second DC terminal 14.

[0057] In a first asymmetrical switching state A1, the first and third semiconductor switches T1, T3 are simultaneously switched on. In the first asymmetrical switching state A1, the second and fourth semiconductor switches T2, T4 are simultaneously switched off. In the first asymmetrical switching state A1, electrical power is exchanged between the first DC terminal 12 and the upper part of the second DC terminal 14, while no electrical power is exchanged between the first DC terminal 12 and the lower part of the second DC terminal 14. If the first semiconductor switch T1 is designed as an IGBT and has a parallel freewheeling diode, the first asymmetrical switching state A1 can also be realized without explicitly switching on the first semiconductor switch T1, by the corresponding electrical current flowing via the freewheeling diode of the first semiconductor switch T1.

[0058] In a second asymmetrical switching state A2 (not shown), the first and third semiconductor switches T1, T3 are simultaneously switched non-conductive. In the second asymmetrical switching state, the second and fourth semiconductor switches T2, T4 are simultaneously switched conductive. In the second asymmetrical switching state A2, electrical power is exchanged between the first DC terminal 12 and the lower part of the second DC terminal 14, while no electrical power is exchanged between the first DC terminal 12 and the upper part of the second DC terminal 14. If the fourth semiconductor switch T4 is designed as an IGBT and has a parallel freewheeling diode, the second asymmetrical switching state A2 can also be realized without explicitly switching on the first semiconductor switch T4, by the corresponding electrical current flowing via the freewheeling diode of the first semiconductor switch T1.

[0059] For the transfer of electrical power between the first DC terminal 12 and the second DC terminal 14, as shown in Figure 4, the first and the second symmetrical switching states S1, S2 are alternately adopted, so that the electrical power is exchanged symmetrically with both parts of the second DC terminal.

[0060] The first asymmetric switching state A1 is adopted instead of the first symmetric switching state S1 in order to transfer electrical power between the first DC connection 12 and the upper part of the second DC connection 14. The second asymmetric switching state A2 (not shown) can be adopted in order to transfer electrical power between the first DC connection 12 and the lower part of the second DC connection 14. The use of the asymmetric switching states A1, A2 is particularly advantageous when an asymmetric power transfer to or from the second DC connection 14 is necessary, for example to compensate for an asymmetric power outflow to an asymmetric external load at the second DC connection 14. The appropriate asymmetric switching state A1 or A2 can, for example,can also be adopted instead of the first symmetrical switching state S1 if the potential of the center terminal PM is not in the middle between the second positive potential and the second negative potential and if this asymmetry is to be compensated, or if a shift of the potential of the center terminal PM relative to the second positive potential and the second negative potential due to an asymmetrical withdrawal of electrical power via the second DC terminal 14 is to be prevented.

[0061] In the embodiment according to Fig. 4, the symmetrical switching states S1, S2 are initially set alternately in the first four cycles, so that the transferred electrical power, which is represented by the illustrated inductor current IL1, is exchanged symmetrically with the two parts of the second DC connection 14. In the fifth to ninth cycles according to Fig. 3, the symmetrical switching state S2 and the asymmetrical switching state A1 are used alternately to transfer electrical power preferentially to the upper part of the second DC connection 14, for example to compensate for an asymmetrical load on the second DC connection 14. The illustrated inductor current IL1 increases on average, whereby this behavior is independent of the asymmetrical power transfer and represents an interim increase in the total power transferred from the first DC connection 12 to the second DC connection 14. From the tenth cycle in Fig.3 the symmetrical switching states S1, S2 are set alternately.

[0062] In an alternative embodiment not shown, individual clock pulses may have the second asymmetric switching state A2 and, in particular, replace the first symmetric switching state in order to transfer electrical power preferentially to the lower part of the second DC connection, for example, to compensate for a corresponding asymmetric load on the second DC connection 14.

[0063] In a further embodiment not shown, the clocking can comprise switching cycles consisting of a sequence of symmetrical switching states S1, S2 and an inserted asymmetrical switching state A1 or A2, wherein the temporal component, i.e., the pulse duration of the inserted asymmetrical switching state A1, A2, can be varied as required. As a result, electrical power can be transferred with each individual switching cycle either symmetrically between the first DC terminal 12 and the second DC terminal 14 by setting the pulse length of the asymmetrical switching state A1, A2 to zero in a switching cycle, or asymmetrically by setting the pulse length of the asymmetrical switching state A1, A2 to a suitable finite value in a switching cycle. Such clocking is particularly easy to implement and generates particularly few potential jumps and thus particularly low common-mode currents. LIST OF REFERENCE SYMBOLS

[0064] T1, T2, T3, T4 semiconductor switches

[0065] 10 DC / DC converters

[0066] 12 first DC connection

[0067] 14 second DC connection

[0068] 16 DC / AC converters

[0069] 18 AC load

[0070] 20 DC / DC converters

[0071] 30 inverters

[0072] L1 , L2 first and second throttle

[0073] P1 + first positive pole

[0074] P1- first negative pole

[0075] P2+ second positive pole

[0076] PM Mittenpol

[0077] P2- second negative pole

[0078] DC+ DC pulse pole

[0079] DC-DC negative pole

[0080] DCM DC center potential

[0081] AC AC connection

[0082] N neutral conductor

[0083] L3 coupled choke

[0084] IL1 first choke current

[0085] C1, C2 first and second capacity

[0086] C3 third capacity

[0087] PE earth potential

[0088] ICM common mode current

[0089] T1, T2, T3, T4 semiconductor elements

[0090] S1 first symmetrical switching state

[0091] S2 second symmetrical switching state

[0092] A1 first asymmetric switching state

Claims

PATENT CLAIMS 1. DC / DC converter (10, 20) for the transfer of electrical power between a first DC terminal (12) and a second DC terminal (14), wherein the first DC terminal (12) has a first positive pole (P1+) and a first negative pole (P1-) and is designed for a two-pole connection to a unipolar DC source, in particular to a photovoltaic generator, wherein the second DC terminal (14) has a second positive pole (P2+), a second negative pole (P2-) and a center pole (PM) and is designed for a three-pole connection to a bipolar load, in particular to a three-level DC / AC converter (16), wherein the DC / DC converter (10, 20) has a bridge circuit,which comprises a first series circuit of a first semiconductor element (T1) and a second semiconductor element (T2) between the second positive pole (P2+) and the center pole (PM), and a second series circuit of a third semiconductor element (T3) and a fourth semiconductor element (T4) between the center pole (PM) and the second negative pole (P2-), wherein the first positive pole (P1+) is connected via a first connection to a first center tap between the first and second semiconductor elements (T1, T2), wherein the first negative pole (P1-) is connected via a second connection to a second center tap between the third and fourth semiconductor elements (T3, T4), wherein a first choke (L1) is arranged in the first connection and a second choke (L2) is arranged in the second connection, wherein the first choke (L1) and the second choke (L1) are designed symmetrically to one another.

2. DC / DC converter (10, 20) according to claim 1, wherein the first choke (L1) and the second choke (L2) have the same inductance values ​​and in particular comprise the same number of turns.

3. DC / DC converter (10, 20) according to claim 1 or 2, wherein the first choke (L1) and the second choke (L2) are magnetically coupled to each other.

4. DC / DC converter (10, 20) according to one of the preceding claims, wherein the first connection and the second connection are connected via a coupled choke (L3).

5. DC / DC converter (10, 20) according to one of the preceding claims, wherein between the first positive pole (P1+) and the first negative pole (P1-) a further series circuit comprising a first and a second capacitor (C1, C2) with a further center tap between the first and the second capacitor (C1, C2) is arranged, wherein between a third capacitor (C3) is arranged between the further center tap and the center pole (PM) of the second DC connection (14).

6. A method for operating a DC / DC converter (10, 20) which is designed for the transfer of electrical power between a first DC terminal (12) and a second DC terminal (14), wherein the first DC terminal (12) has a first positive pole (P1+) and a first negative pole (P1-) and is connected via two poles to a unipolar DC source, in particular to a photovoltaic generator, wherein the second DC terminal (14) has a second positive pole (P2+), a second negative pole (P2-) and a center pole (PM) and is connected via three poles to a bipolar load, in particular to a three-level DC / AC converter (16), wherein the DC / DC converter (10, 20) has a bridge circuit,which has a first series circuit of a first semiconductor switch (T1) and a second semiconductor switch (T2) between the second positive pole (P2+) and the center pole (PM), and a second series circuit of a third semiconductor switch (T3) and a fourth semiconductor switch (T4) between the center pole (PM) and the second negative pole (P2-), wherein in symmetrical switching states (S1, S2), the first and fourth semiconductor switches (T1, T4) are simultaneously switched to conducting or non-conducting, and in opposite directions, the second and third semiconductor switches (T2, T3) are simultaneously switched to conducting or non-conducting, respectively, wherein in asymmetrical switching states (A1), the first and third semiconductor switches (T1, T3) are simultaneously switched to conducting or non-conducting, and in opposite directions, the second and fourth semiconductor switches (T2, T4) are simultaneously switched to conducting or non-conducting, respectively, respectively,whereby for the transfer of electrical power the symmetrical switching states (S1, S2) are alternately adopted and one of the asymmetrical switching states (A1) is adopted only when required., 7. The method according to claim 6, wherein the need is detected when a power draw from the two parts of the second DC terminal (14) by the bipolar load is unequal and / or when the potential of the center pole (PM) is not symmetrical between the potentials of the second positive pole (P2+) and the second negative pole (P2-) and / or when a position of the potential of the center pole (PM) relative to the potentials of the second positive pole (P2+) and the second negative pole (P2-) is to be stabilized.

8. The method according to claim 6 or 7, wherein in a first symmetrical switching state (S1) the first and the fourth semiconductor switch (T1, T4) are simultaneously switched to conducting and the second and the third semiconductor switch (T2, T3) are simultaneously switched to non-conducting are switched, wherein in a second symmetrical switching state (S2) the first and the fourth semiconductor switch (T 1 , T4) are simultaneously switched non-conductive and the second and the third semiconductor switch (T2, T3) are simultaneously switched conductive, wherein in a first asymmetrical switching state (A1) the first and the third semiconductor switch (T 1 , T3) are simultaneously switched conductive and the second and the fourth semiconductor switch (T2, T4) are simultaneously switched non-conductive, wherein in a second asymmetrical switching state the first and the third semiconductor switch (T 1 , T3) are simultaneously switched non-conductive and the second and the fourth semiconductor switch (T2, T4) are simultaneously switched conductive.

9. Method according to one of claims 6 to 8, wherein for the transfer of electrical power the first and the second symmetrical switching state (S1, S2) are alternately adopted and the first asymmetrical switching state (A1) is adopted only when required instead of the first symmetrical switching state (S1).

10. Method according to one of claims 6 to 9, wherein for the transfer of electrical power the first and the second symmetrical switching state (S1, S2) are alternately adopted and the second asymmetrical switching state is adopted only when required instead of the second symmetrical switching state (S2).

11. Inverter (30) with a three-level DC / AC converter (16) and a DC / DC converter (10, 20) according to one of claims 1 to 5.

12. A method for operating an inverter (30) according to claim 11, wherein the DC / DC converter (10, 20) is operated using a method according to one of claims 6 to 10.

13. The method according to claim 11, wherein the three-level DC / AC converter (16) draws unequal electrical power from the two parts of the second DC terminal (14) and the position of the potential of the center pole (PM) relative to the potentials of the second positive pole (P2+) and the second negative pole (P2-) is stabilized by assuming the asymmetric switching state (A1) as needed.

Images