Capacitor and method for manufacturing capacitor

Abstract

A capacitor according to the present invention includes a substrate, two or more grooves, a dielectric layer, a conductive layer, a first contact hole, a second contact hole, a first electrode, and a second electrode. Two or more grooves are formed in a first main surface of the substrate. At least two or more dielectric layers and conductive layers are alternately stacked on the first main surface and in the grooves. The first contact hole and the second contact hole are formed above the first main surface. The first electrode is partially embedded in the first contact hole and is electrically connected to one or two or more first conductive layers of the two or more conductive layers. The second electrode is partially embedded in the second contact hole and is electrically connected to one or two or more second conductive layers of the two or more conductive layers. As viewed from the normal direction of the first main surface, two or more grooves are arranged in the transverse direction of the grooves, and the first contact hole and the second contact hole are disposed so as to sandwich a region including the plurality of grooves from the longitudinal direction of the grooves.

Description

Capacitor and method of manufacturing the capacitor

[0001] The present disclosure relates to capacitors and methods for manufacturing capacitors.

[0002] Patent Document 1 describes a trench capacitor in which conductive polysilicon layers and dielectric layers are alternately formed within a pore in a substrate, and the polysilicon layers are electrically connected to electrodes via contacts on the surface of the substrate.

[0003] Special Publication No. 2009-515353

[0004] Patent Document 1 does not consider a structure in which a plurality of pores are densely packed on the surface of a substrate, and therefore does not disclose anything about how to arrange the contact between the electrode and the polysilicon layer on the surface of the substrate in such a structure, and does not address the need to shorten the current path between the high-potential contact and the low-potential contact.

[0005] An object of the present disclosure is to provide a capacitor in which the equivalent series resistance (ESR) is reduced by shortening the current path between the contact of the high potential side electrode and the contact of the low potential side electrode, and a method for manufacturing the same.

[0006] A capacitor according to one or more embodiments of the present disclosure includes two or more grooves formed on a first main surface of a substrate, a dielectric layer, a conductive layer, a first contact hole, a second contact hole, a first electrode, and a second electrode. The dielectric layer and the conductive layer are alternately stacked in at least two layers on the first main surface and within the grooves. The first contact hole and the second contact hole are formed above the first main surface. The first electrode is partially embedded in the first contact hole and electrically connected to one or more first conductive layers of the two or more conductive layers. The second electrode is partially embedded in the second contact hole and electrically connected to one or more second conductive layers of the two or more conductive layers. When viewed from the normal direction of the first main surface, the two or more grooves are arranged in the short direction of the grooves, and the first contact hole and the second contact hole are arranged to sandwich a region including the multiple grooves from the long direction of the grooves.

[0007] According to one or more embodiments of the present disclosure, it is possible to provide a capacitor in which the equivalent series resistance (ESR) is reduced by shortening the current path between the contact of the high potential side electrode and the contact of the low potential side electrode, and a method for manufacturing the same.

[0008] FIG. 1 is a plan view showing the configuration of a capacitor 100 according to the first embodiment. FIG. 2A is a cross-sectional view showing the structure of the capacitor 100 along the IIA-IIA cross section of FIG. 1 . FIG. 2B is a cross-sectional view showing the structure of the capacitor 100 along the IIB-IIB cross section of FIG. 1 . FIG. 2C is a cross-sectional view showing the structure of the capacitor 100 along the IIC-IIC cross section of FIG. 1 . FIG. 3A is a plan view showing a manufacturing process of the capacitor 100 (part 1). FIG. 3B is a cross-sectional view showing the structure of the capacitor 100 along the IIIB-IIIB cross section of FIG. 3A . FIG. 3C is a cross-sectional view showing the structure of the capacitor 100 along the IIIC-IIIC cross section of FIG. 3A . FIG. 4A is a cross-sectional view showing a manufacturing process of the capacitor 100 (part 2), showing a structure corresponding to the IIA-IIA cross section of FIG. 1 . FIG. 4B is a cross-sectional view showing a manufacturing process of the capacitor 100 (part 2), showing a structure corresponding to the IIB-IIB cross section of FIG. 1 . FIG. 5A is a plan view showing a manufacturing process of the capacitor 100 (part 3). FIG. 5B is a cross-sectional view showing the structure of capacitor 100 taken along the VB-VB cross section of FIG. 5A. FIG. 5C is a cross-sectional view showing the structure of capacitor 100 taken along the VC-VC cross section of FIG. 5A. FIG. 5D is a cross-sectional view showing the structure of capacitor 100 taken along the VD-VD cross section of FIG. 5A. FIG. 6A is a plan view (part 4) showing a manufacturing process for capacitor 100. FIG. 6B is a cross-sectional view showing the structure of capacitor 100 taken along the VIB-VIB cross section of FIG. 6A. FIG. 6C is a cross-sectional view showing the structure of capacitor 100 taken along the VIC-VIC cross section of FIG. 6A. FIG. 6D is a cross-sectional view showing the structure of capacitor 100 taken along the VID-VID cross section of FIG. 6A. FIG. 7A is a plan view (part 5) showing a manufacturing process for capacitor 100. FIG. 7B is a cross-sectional view showing the structure of capacitor 100 taken along the VIIB-VIIB cross section of FIG. 7A. FIG. 7C is a cross-sectional view showing the structure of capacitor 100 taken along the VIIC-VIIC cross section of FIG. 7A. Fig. 7D is a cross-sectional view showing the structure of capacitor 100 taken along the line VIID-VIID in Fig. 7A. Fig. 8A is a plan view (part 6) showing a manufacturing process of capacitor 100. Fig. 8B is a cross-sectional view showing the structure of capacitor 100 taken along the line VIIIB-VIIIB in Fig. 8A.FIG. 8C is a cross-sectional view showing the structure of capacitor 100 taken along the VIIIC-VIIIC cross section of FIG. 8A . FIG. 8D is a cross-sectional view showing the structure of capacitor 100 taken along the VIIID-VIIID cross section of FIG. 8A . FIG. 9 is an enlarged plan view of the trenches and contact holes extracted from the first main surface of capacitor 100. FIG. 10A is a plan view schematically showing the layout of trenches and contact holes in the first embodiment. FIG. 10B is a plan view schematically showing the layout of trenches and contact holes in a comparative example. FIG. 11 is a graph showing the relationship between the frequency of an AC voltage applied to capacitor 100 and the impedance of capacitor 100. FIG. 12A is a cross-sectional view showing a state in which a laminated structure is formed on the first main surface of a substrate. FIG. 12B is a cross-sectional view showing a state in which a contact hole exposing the first main surface is formed in the laminated structure of FIG. 12A . FIG. 12C is a cross-sectional view showing a state in which a contact hole exposing the conductive layer closest to the first main surface is formed in the laminated structure of FIG. 12A . FIG. 13 is a plan view showing the configuration of a capacitor 101 according to a second embodiment. FIG. 14A is a cross-sectional view showing the structure of the capacitor 101 taken along the XIVA-XIVA cross section of FIG. 13 . FIG. 14B is a cross-sectional view showing the structure of the capacitor 101 taken along the XIVB-XIVB cross section of FIG. 13 . FIG. 14C is a cross-sectional view showing the structure of the capacitor 101 taken along the XIVC-XIVC cross section of FIG. 13 . FIG. 15A is a plan view showing a manufacturing process of the capacitor 101 (part 1). FIG. 15B is a cross-sectional view showing the structure of the capacitor 101 taken along the XVB-XVB cross section of FIG. 15A . FIG. 15C is a cross-sectional view showing the structure of the capacitor 101 taken along the XVC-XVC cross section of FIG. 15A . FIG. 15D is a cross-sectional view showing the structure of the capacitor 101 taken along the XVD-XVD cross section of FIG. 15A . FIG. 16A is a plan view showing a manufacturing process of the capacitor 101 (part 2). Fig. 16B is a cross-sectional view showing the structure of capacitor 101 taken along the XVIB-XVIB cross section of Fig. 16A. Fig. 16C is a cross-sectional view showing the structure of capacitor 101 taken along the XVIC-XVIC cross section of Fig. 16A. Fig. 16D is a cross-sectional view showing the structure of capacitor 101 taken along the XVID-XVID cross section of Fig. 16A.FIG. 17A is a cross-sectional view (part 3) showing the manufacturing process of capacitor 101, illustrating a structure corresponding to the XIVA-XIVA cross section of FIG. 13 . FIG. 17B is a cross-sectional view (part 3) showing the manufacturing process of capacitor 101, illustrating a structure corresponding to the XIVB-XIVB cross section of FIG. 13 . FIG. 17C is a cross-sectional view (part 3) showing the manufacturing process of capacitor 101, illustrating a structure corresponding to the XIVC-XIVC cross section of FIG. 13 . FIG. 18A is a plan view (part 4) showing the manufacturing process of capacitor 101. FIG. 18B is a cross-sectional view showing the structure of capacitor 101 in the XVIIIB-XVIIIB cross section of FIG. 18A . FIG. 18C is a cross-sectional view showing the structure of capacitor 101 in the XVIIIC-XVIIIC cross section of FIG. 18A . FIG. 18D is a cross-sectional view showing the structure of capacitor 101 in the XVIIIID-XVIIID cross section of FIG. 18A . FIG. 19A is a plan view (part 5) showing a manufacturing process of the capacitor 101. FIG. 19B is a cross-sectional view showing the structure of the capacitor 101 taken along the XIXB-XIXB cross section of FIG. 19A. FIG. 19C is a cross-sectional view showing the structure of the capacitor 101 taken along the XIXC-XIXC cross section of FIG. 19A. FIG. 19D is a cross-sectional view showing the structure of the capacitor 101 taken along the XIXD-XIXD cross section of FIG. 19A. FIG. 20A is a cross-sectional view showing the structure of a capacitor 102 according to a third embodiment, corresponding to the IIA-IIA cross section of FIG. 1. FIG. 20B is a cross-sectional view showing the structure of a capacitor 102 according to the third embodiment, corresponding to the IIB-IIB cross section of FIG. 1. FIG. 20C is a cross-sectional view showing the structure of a capacitor 102 according to the third embodiment, corresponding to the IIC-IIC cross section of FIG. 1.

[0009] Capacitors 100 to 102 according to the embodiments will be described in detail below with reference to the drawings. The embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, component placement locations, and connection configurations shown in the following embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts are described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. The following embodiments and their variations may include similar components, and the same reference numerals will be used to denote similar components, and redundant explanations will be omitted.

[0010] First Embodiment [Capacitor 100] FIG. 10A is a plan view schematically illustrating the layout of trenches 2 and contact holes 6 and 7 in a capacitor 100 according to the first embodiment. The capacitor 100 has a dielectric layer and a conductive layer (not shown) embedded inside trenches 2 formed on a first main surface 1A of a substrate 1. The high-potential side conductive layer is connected to a high-potential side electrode (not shown) via a first contact hole 6, and the low-potential side conductive layer is connected to a low-potential side electrode (not shown) via a second contact hole 7. As shown in FIG. 10A , two or more trenches 2 are arranged in a short-side direction S of the trenches 2 when viewed from the normal direction of the first main surface 1A. The high-potential side first contact hole 6 and the low-potential side second contact hole 7 are arranged to sandwich a region 17 including multiple trenches 2 in a longitudinal direction L of the trenches 2.

[0011] Fig. 1 is a plan view showing the configuration of a capacitor 100 according to the first embodiment. Fig. 2A is a cross-sectional view showing the structure of the capacitor 100 taken along the IIA-IIA cross section of Fig. 1. Fig. 2B is a cross-sectional view showing the structure of the capacitor 100 taken along the IIB-IIB cross section of Fig. 1. Fig. 2C is a cross-sectional view showing the structure of the capacitor 100 taken along the IIC-IIC cross section of Fig. 1.

[0012] The capacitor 100 includes a substrate 1, two or more grooves 2, a dielectric layer 3, conductive layers 4 and 5, first contact holes 6 a and 6 b, second contact holes 7 a and 7 b, a first electrode 11 (an example of an electrode on the high potential side), and a second electrode 12 (an example of an electrode on the low potential side). The two or more grooves 2 are formed on a first main surface 1A of the substrate 1.

[0013] At least two or more dielectric layers 3 and conductive layers 4, 5 are alternately stacked on the first main surface 1A and in the groove 2. First contact holes 6a, 6b and second contact holes 7a, 7b are formed in at least one of the dielectric layer 3 and conductive layers 4, 5 above the first main surface 1A. A first electrode 11 is partially embedded in the first contact holes 6a, 6b and electrically connected to one or more first conductive layers 4 of the two or more conductive layers 4, 5. A second electrode 12 is partially embedded in the second contact holes 7a, 7b and electrically connected to one or more second conductive layers 5 of the two or more conductive layers 4, 5.

[0014] The capacitor 100 has a layered structure consisting of dielectric layers and conductive layers alternately stacked in a groove 2 formed in a first main surface 1A of a substrate 1. The substrate 1 has a first main surface 1A and a groove 2 formed in the first main surface 1A. The substrate 1 is a single crystal substrate made of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). In this embodiment, the substrate 1 is doped with a high concentration of N-type or P-type impurities, and is conductive like a conductive layer described later. For example, a substrate 1 having a resistivity of 1×10 −４ ~1×10 −５ Ω cm ２ A silicon substrate having a high impurity concentration of about 10 ...

[0015] 1, the grooves 2 are arranged in the short direction of the grooves 2 when viewed from the normal direction of the first main surface 1A. In the first embodiment, the grooves 2 do not penetrate the substrate 1, but have a bottom surface and a side surface (collectively referred to as "inner surfaces"). In the third embodiment, a capacitor 102 in which the grooves 2 penetrate will be described.

[0016] 1, 13 grooves 2 are arranged in the short direction of the grooves 2. The region in which the 13 grooves 2 are arranged is sandwiched between high-potential side contact holes 6a and 6b and low-potential side contact holes 7a and 7b in the longitudinal direction L of the grooves 2.

[0017] The dielectric layer 3 is, for example, a silicon oxide film (SiO ２ ) or silicon nitride film (Si ３ N ４ ) can be used. By using a silicon oxide film with low film stress, operation at high voltage becomes possible. Furthermore, by using a silicon nitride film with a high dielectric constant, the capacitance density can be improved. By using a material with a high breakdown field and a high relative dielectric constant, the dielectric layer 3 with high withstand voltage and dielectric constant can be formed. Therefore, a semiconductor capacitor with high withstand voltage and high capacitance density can be manufactured.

[0018] The dielectric layer 3 may have a multilayer structure formed by laminating a plurality of dielectric layers made of different materials. For example, the dielectric layer 3 may be formed by laminating a silicon nitride film having a relatively high dielectric constant but high film stress and a silicon oxide film having a relatively low dielectric constant but low film stress. This allows the dielectric layer 3 to have a desired thickness and a high dielectric constant with a good balance between the dielectric constant and stress.

[0019] The conductive layers 4 and 5 may be, for example, polycrystalline silicon films. Polycrystalline silicon films can be formed, for example, by low-pressure CVD, resulting in conductive layers 4 and 5 with good coverage. This allows the conductive layers 4 and 5 to be formed with good coverage inside the trenches 2 even when the aspect ratio of the trenches 2 is large, thereby enabling the production of a capacitor 100 with high capacitance density. Alternatively, metal may be used for the conductive layers 4 and 5. Because metals have low resistivity, the equivalent series resistance (ESR) of the conductive layers 4 and 5 can be reduced. The conductive layers 4 and 5 may also be metal films or silicide films made of conductive materials such as polysilicon carbide (SiC), silicon germanium (SiGe), or aluminum (Al).

[0020] The conductive layers 4, 5 include a first conductive layer 4 on the high potential side and a second conductive layer 5 on the low potential side. A dielectric layer 3 is first laminated on the first main surface 1A of the substrate 1 and on the inner surface of the groove 2. The first conductive layer 4 is laminated on the dielectric layer 3. A second conductive layer 5 is laminated on the first conductive layer 4 with another dielectric layer 3 interposed therebetween. The first conductive layer 4 and the second conductive layer 5 are alternately laminated with the dielectric layer 3 interposed therebetween. A structure in which the dielectric layer 3 and the conductive layers 4, 5 are laminated is called a "laminate structure."

[0021] As shown in Figure 2A, the first contact holes 6a and 6b are formed on the IIA-IIA cross section of Figure 1. The first contact hole 6a is a hole formed in the dielectric layer 3 and the conductive layers 4 and 5. A first interlayer film 8 is formed on the inner surface of the first contact hole 6a and on the stacked structure. The first interlayer film 8 may be, for example, a silicon oxide film.

[0022] The first contact hole 6b is a hole formed in the first interlayer film 8. Specifically, the first contact hole 6b is a hole formed in the first interlayer film 8 laminated on the laminated structure or on the bottom surface of the first contact hole 6a. The first conductive layer 4 is exposed at the bottom surface of the first contact hole 6b.

[0023] The first electrode 11 is disposed on the first interlayer film 8, and a portion of it is embedded inside the first contact holes 6a and 6b. The first electrode 11 is ohmically connected to the first conductive layer 4 exposed at the bottom of the first contact hole 6b. In this manner, the first electrode 11 is electrically connected to the first conductive layer 4 via the first contact holes 6a and 6b. The first electrode 11 is electrically insulated from the second conductive layer 5 by the first interlayer film 8 disposed on the side surface of the first contact hole 6a.

[0024] As shown in Fig. 2C, the second contact holes 7a and 7b are formed on the IIC-IIC cross section of Fig. 1. The second contact hole 7a is a hole formed in the dielectric layer 3 and the conductive layers 4 and 5. A first interlayer film 8 is formed on the inner surface of the second contact hole 7a and on the laminated structure.

[0025] The second contact hole 7b is a hole formed in the first interlayer film 8. Specifically, the second contact hole 7b is a hole formed in the first interlayer film 8 laminated on the laminated structure or on the bottom surface of the second contact hole 7a. The second conductive layer 5 or the first main surface 1A of the substrate 1 is exposed at the bottom surface of the second contact hole 7b.

[0026] The second electrode 12 is disposed on the first interlayer film 8, and a portion of it is embedded inside the second contact holes 7a and 7b. The second electrode 12 is ohmically connected to the second conductive layer 5 exposed at the bottom of the second contact hole 7b. In this manner, the second electrode 12 is electrically connected to the second conductive layer 5 via the second contact holes 7a and 7b. The second electrode 12 is electrically insulated from the first conductive layer 4 by the first interlayer film 8 disposed on the side surface of the second contact hole 7a.

[0027] 1, the first contact holes 6a, 6b and the first electrode 11, the second contact holes 7a, 7b and the second electrode 12 are arranged on the first main surface 1A of the substrate 1 excluding the grooves 2. The first contact holes 6a, 6b and the second contact holes 7a, 7b are arranged in the same direction as the arrangement direction of the grooves 2 (the short side direction of the grooves). The first electrode 11 and the second electrode 12 similarly have a planar shape whose longitudinal direction is the same as the arrangement direction of the grooves 2. The high potential side and the low potential side of the conductive layers 4, 5 and the electrodes 11, 12 may be interchanged.

[0028] Metal is generally used as the material for the first electrode 11 and the second electrode 12. For example, a laminated film of titanium (Ti) and aluminum (Al) can be used for the first electrode 11 and the second electrode 12. Alternatively, a single layer film or a laminated film of two or more elements selected from the group consisting of aluminum (Al), titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), silver (Ag), and copper (Cu) can be used.

[0029] The capacitor 100 further includes a second interlayer film 10 disposed on the first electrode 11 and the second electrode 12, and a first pad electrode 15 and a second pad electrode 16 disposed on the second interlayer film 10. The first pad electrode 15 is electrically connected to two or more first electrodes 11 through a third contact hole 13. The second pad electrode 16 is electrically connected to two or more second electrodes 12 through a fourth contact hole 14. A portion of the first pad electrode 15 is embedded in the third contact hole 13 and electrically connected to the first electrode 11. A portion of the second pad electrode 16 is embedded in the fourth contact hole 14 and electrically connected to the second electrode 12. The second interlayer film 10 may be, for example, a silicon oxide film.

[0030] For example, a laminated film of titanium (Ti) and aluminum (Al) can be used for the first pad electrode 15 and the second pad electrode 16. In addition, a single layer film or a laminated film of two or more elements selected from the group consisting of aluminum (Al), titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), silver (Ag), and copper (Cu) can also be used.

[0031] The basic operation of the capacitor 100 will be described. A positive voltage is applied to the first electrode 11 with respect to the second electrode 12. Alternatively, a negative voltage is applied to the second electrode 12 with respect to the first electrode 11. A potential difference is generated between the first conductive layer 4 and the second conductive layer 5, and positive charges are attracted to the first conductive layer 4 and negative charges are attracted to the second conductive layer 5 by electrostatic induction. At this time, polarization occurs within the dielectric layer 3, generating capacitance. In this way, the capacitor 100 can charge between the first conductive layer 4 and the second conductive layer 5 by applying a voltage between the first electrode 11 and the second electrode 12.

[0032] 3A to 8D, an example of a method for manufacturing the capacitor 100 will be described. Note that the method for manufacturing the capacitor 100 described below is just an example, and various other manufacturing methods can be used.

[0033] A semiconductor substrate doped with a high concentration of N-type or P-type impurities is prepared as the substrate 1. When a Si substrate is used, an N-type semiconductor substrate can be manufactured by adding an impurity of a pentavalent element such as phosphorus (P) or arsenic (As), and a P-type semiconductor substrate can be manufactured by adding an impurity of a trivalent element such as boron (B) or gallium (Ga).

[0034] Next, a portion of the substrate 1 is etched from the first main surface 1A of the substrate 1 to form the groove 2. Specifically, first, a mask material is deposited on the first main surface 1A of the substrate 1. A silicon oxide film can be used as the mask material, and thermal CVD or plasma CVD can be used as the deposition method. Next, a resist is patterned on the mask material. A typical photolithography method can be used as the patterning method. The mask material is etched using the patterned resist as a mask. The mask material has openings in the areas where the grooves 2 are to be formed. Etching methods that can be used include wet etching using a potassium hydroxide aqueous solution, hydrofluoric acid, or hot phosphoric acid, or dry etching such as reactive ion etching. Next, the resist is removed using oxygen plasma, sulfuric acid, or the like. Using the mask material thus formed, the substrate 1 exposed through the openings in the mask material is etched by dry etching to form the grooves 2.

[0035] When forming the grooves 2 in the Si substrate, the etching method can be wet etching using HF (hydrofluoric acid) or KOH (potassium hydroxide), or dry etching using plasma. In dry etching of the substrate 1, plasma can be generated using fluorine gas (SF6, CF4, etc.). Wet etching is less expensive than dry etching and is suitable for mass production. Dry etching allows for higher accuracy and better pattern formation than wet etching, but requires more advanced technology for equipment and operation.

[0036] Next, a dielectric layer 3 is deposited on the inner surfaces of the trenches 2 and on the surface of the substrate 1, including the first main surface 1A. A silicon oxide film can be used as the dielectric layer 3, and a thermal oxidation method or a thermal CVD method can be used as the deposition method. When using the thermal CVD method, a reduced pressure condition can be used to deposit the silicon oxide film with good coverage even when the trenches 2 are deep.

[0037] Next, a first conductive layer 4 is deposited on the inner surface of the trench 2 and the surface of the substrate 1, including the first principal surface 1A, so as to cover the dielectric layer 3. Here, a polysilicon film is used as an example of the first conductive layer 4. After the polysilicon film is deposited, an annealing treatment is performed in POCl3 at 950°C to form an N-type polysilicon film, which makes the first conductive layer 4 conductive. Here, an N-type polysilicon film is used as an example of the first conductive layer 4, but a P-type polysilicon film, silicon germanium, a semiconductor film such as a conductive polysilicon carbide film, or a metal film such as titanium (Ti) or aluminum (Al) can also be used. A low-pressure CVD method can be used to deposit the polysilicon film. The state after the above steps are completed is shown in Figures 3A to 3C.

[0038] Next, a dielectric layer 3 is again deposited on the inner surface of the groove 2 and the surface of the substrate 1, including the first main surface 1A, so as to cover the first conductive layer 4. Next, a second conductive layer 5 is deposited on the inner surface of the groove 2 and the surface of the substrate 1, including the first main surface 1A, so as to cover the dielectric layer 3. The material and deposition method of the second conductive layer 5 are the same as those of the first conductive layer 4. By alternately stacking the first conductive layers 4 and the second conductive layers 5 with the dielectric layer 3 sandwiched therebetween, a laminated structure consisting of the dielectric layer 3, the first conductive layer 4, and the second conductive layer 5 can be formed on the inner surface of the groove 2 and the surface of the substrate 1, including the first main surface 1A. In the first embodiment, two first conductive layers 4, one second conductive layer 5, and three dielectric layers 3 are formed on the inner surface of the groove 2 and the first main surface 1A. The groove 2 is backfilled with a second second conductive layer 5. The state after the above steps are completed is shown in FIGS. 4A and 4B .

[0039] Next, a photoresist is applied to the first main surface 1A of the substrate 1 and exposed to light to form a patterned mask material 21. The patterned mask material 21 has openings in the areas where the first contact holes 6a and second contact holes 7a are to be formed. The mask material 21 is used to selectively etch the dielectric layer 3, the first conductive layer 4, and the second conductive layer 5 exposed through the openings in the mask material 21. An anisotropic etching method may be used as the etching method. The dielectric layer 3, the first conductive layer 4, and the second conductive layer 5 exposed through the openings in the mask material 21 are removed, exposing the first conductive layer 4, the second conductive layer 5, or the first main surface 1A of the substrate 1. The state after the above steps are completed is shown in Figures 5A to 5D.

[0040] 5B and 5D illustrate the mask material 21 having openings in the regions where the first contact holes 6a and second contact holes 7a of different depths will be formed for convenience. However, in reality, different mask materials and etching processes are used depending on the depths of the contact holes to be formed. Specifically, a mask material 21 forming process and etching process are performed to form the first contact holes 6a deep enough to reach the first conductive layer 4 of the first layer, a mask material 21 forming process and etching process to form the second contact holes 7a deep enough to reach the second conductive layer 5, and a mask material 21 forming process and etching process to form the second contact holes 7a deep enough to reach the first main surface 1A of the substrate 1. The order of these processes is not important. Here, the term "first layer" refers to the order in which the multiple first conductive layers 4 are counted from the substrate 1 side.

[0041] Next, a first interlayer film 8 is deposited on the inner surfaces of the first contact holes 6a and 7a and on the second-layer first conductive layer 4. The thickness of the first interlayer film 8 is preferably such that it does not backfill the first contact holes 6a and 7a. A silicon oxide film can be used for the first interlayer film 8. Next, a mask material 22 made of patterned photoresist is formed on the first main surface 1A of the substrate 1. The patterned mask material 22 has openings in areas where the first contact holes 6b and second contact holes 7b will be formed. The mask material 22 is used to selectively etch the first interlayer film 8 exposed through the openings in the mask material 22. For example, an anisotropic etching method may be used as the etching method. This results in the formation of the first contact holes 6b and second contact holes 7b. The state after the above steps is shown in Figures 6A to 6D. Here, the "second layer" refers to the order in which the multiple first conductive layers 4 are counted from the substrate 1 side.

[0042] Next, after removing the mask material 22, an electrode film is deposited to cover the first main surface 1A. The metal film can be deposited by sputtering, electron beam (EB) evaporation, or atomic layer deposition (ALD). Next, a mask material (not shown) made of a silicon oxide film is formed on the electrode film, and the mask material is patterned using lithography and etching techniques. The patterned mask material is used to selectively etch the electrode film by dry etching or wet etching. Alternatively, the metal film may be patterned using a lift-off method. This forms the first electrode 11 and the second electrode 12. The state after the above steps are completed is shown in FIGS. 7A to 7D.

[0043] Next, a second interlayer film 10 is deposited on the first electrode 11, the second electrode 12, and the first interlayer film 8. A silicon oxide film can be used as the second interlayer film 10. Next, a mask material 23 made of patterned photoresist is formed so as to cover the second interlayer film 10. The patterned mask material 23 has openings in the regions where the third contact hole 13 and the fourth contact hole 14 will be formed. The second interlayer film 10 is selectively etched by dry etching using the mask material 23. The state after the above steps are completed is shown in FIGS. 8A to 8D.

[0044] Next, after removing the mask material 23, a pad electrode film is deposited to cover the first main surface 1A. The pad electrode film can be deposited by sputtering, EB evaporation, or ALD. Next, a mask material (not shown) made of a silicon oxide film is formed on the pad electrode film, and the mask material is patterned using lithography and etching techniques. The patterned mask material is used to selectively etch the pad electrode film by dry etching. Alternatively, the pad electrode film may be patterned using a lift-off method. This forms the first pad electrode 15 and the second pad electrode 16. Through the above steps, the capacitor 100 shown in FIGS. 1 and 2A-2C is completed.

[0045] According to the first embodiment, the following advantageous effects can be obtained.

[0046] In the capacitor 52 of the comparative example ( FIG. 10B ), the high-potential side contact hole 56 and the low-potential side contact hole 57 are arranged to sandwich the groove 2 in the lateral direction S. This results in a long current path between the contact holes 56 and 57 because the current flows through the groove 2. In contrast, in the capacitor 100 of the first embodiment ( FIG. 10A ), when viewed from the normal direction to the first main surface 1A of the substrate 1, two or more grooves 2 are arranged in the lateral direction S of the groove 2, and the first contact hole 6 and the second contact hole 7 are arranged to sandwich the region 17 including the plurality of grooves 2 in the longitudinal direction L of the groove 2. The current does not pass through the groove 2 but flows on the first main surface 1A of the substrate 1 between the grooves 2. This shortens the current path between the first contact hole 6 and the second contact hole 7, thereby reducing the equivalent series resistance (ESR) of the capacitor 100.

[0047] FIG. 11 shows the results of calculating the magnitude of impedance at each frequency for the capacitor 52 of the comparative example ( FIG. 10B ) and the capacitor 100 of the first embodiment. As shown in FIG. 11 , in the capacitive region of the capacitor, where the impedance decreases with increasing frequency, the impedance of the capacitor 100 is lower than that of the capacitor 52. Even near the self-resonant frequency of the capacitor 100, where the impedance shows a minimum value, the impedance of the capacitor 100 is lower than that of the capacitor 52. Therefore, it was confirmed that the equivalent series resistance (ESR) of the capacitor 100 can be reduced. This is believed to be due to the shortest current path between the first contact holes 6 a, 6 b and the second contact holes 7 a, 7 b, which reduces the ESR between the electrodes. The inventors of the present application also calculated the current distribution on the surface of the conductive layer for the capacitor 52 of the comparative example ( FIG. 10B ) and the capacitor 100 of the first embodiment. As a result, it was confirmed that the current value at the surface of the conductive layer sandwiching the dielectric layer was larger in capacitor 100 than in capacitor 52 .

[0048] As shown in FIG. 12A , in capacitor 100, a dielectric layer 3 and conductive layers 4 and 5 are stacked on a first main surface 1A of a substrate 1. Due to differences in thermal expansion coefficients, stress occurs in the substrate 1, the dielectric layer 3, and the conductive layers 4 and 5. In particular, significant stress occurs between the substrate 1 and the dielectric layer 3 in contact with the first main surface 1A. As shown in FIG. 2C , second electrode 12 is electrically connected to the first main surface 1A via second contact holes 7 a and 7 b. As shown in FIG. 12B , second contact hole 7 a is formed deep enough to contact the first main surface 1A of the substrate 1. Therefore, the stress applied to the dielectric layer 3 in contact with the first main surface 1A of the substrate 1 can be separated by second contact hole 7 a, thereby reducing the stress at the location where the greatest stress concentration occurs. The inventors calculated the stress applied to substrate 1 and confirmed that the stress applied to substrate 1 in the state shown in FIG. 12B is significantly reduced compared to the stress in the state shown in FIG. 12A .

[0049] As shown in FIG. 2A , the first electrode 11 is electrically connected to the conductive layer (first conductive layer 4) closest to the first major surface 1A via the first contact holes 6 a and 6 b. As shown in FIG. 12C , the first contact hole 6 a is formed deep enough to expose the first conductive layer 4 closest to the first major surface 1A. Because the first contact hole 6 a is formed at a position that leaves the bottommost dielectric layer 3 and conductive layer (first conductive layer 4) closest to the first major surface 1A of the substrate 1, stress is applied to the dielectric layer 3 and conductive layer (first conductive layer 4), but the stress applied to the substrate 1 can be significantly reduced. The inventors calculated the stress applied to the substrate 1 and confirmed that the stress applied to the substrate 1 in the state shown in FIG. 12C is significantly reduced compared to the stress in the state shown in FIG. 12A and is even further reduced compared to the stress in the state shown in FIG. 12B .

[0050] One destruction mode that should be avoided is one in which stress concentrates on the substrate 1, causing the substrate 1 to crack and destroy the capacitor 100. Therefore, it is desirable to avoid stress concentration on the substrate 1 by leaving one dielectric layer. Furthermore, by arranging contact holes (6a, 6b, 7a, 7b) of different depths on the main surface 1A of the substrate 1, stress concentration on the substrate 1 and the laminated structure can be avoided.

[0051] 9, when viewed from the normal direction of first main surface 1A, first contact holes 6a, 6b and second contact holes 7a, 7b are arranged to sandwich portion 26 between adjacent grooves 2 in region 17 in FIG. 10A. In other words, line segments connecting grooves 2 pass through portion 26 between grooves 2. Since the current paths between first contact holes 6a, 6b and second contact holes 7a, 7b can be further shortened, the equivalent series resistance of capacitor 100 can be further reduced.

[0052] The substrate 1 is made of single crystal silicon, and by forming the sidewalls of the grooves 2 along the (111) plane, which is the cleavage plane of the single crystal Si substrate, it is possible to make it less likely that cracks will occur in the substrate 1 across the grooves 2.

[0053] Since the substrate 1 is conductive, the substrate 1 itself can be used as an electrode of the capacitor 100 .

[0054] The substrate 1 may have insulating properties, which makes it easier to separate the capacitor 100 from other elements when they are formed on the same substrate 1.

[0055] The etching method for the grooves 2 is dry etching, which makes it possible to form grooves with a high aspect ratio.

[0056] The etching method for the grooves 2 may be wet etching, which allows the grooves 2 to be formed at low cost.

[0057] Second Embodiment [Capacitor 101] Fig. 13 is a plan view showing the configuration of a capacitor 101 according to a second embodiment. Fig. 14A is a cross-sectional view showing the structure of capacitor 101 in the XIVA-XIVA cross section of Fig. 13. Fig. 14B is a cross-sectional view showing the structure of capacitor 101 in the XIVB-XIVB cross section of Fig. 13. Fig. 14C is a cross-sectional view showing the structure of capacitor 101 in the XIVC-XIVC cross section of Fig. 13.

[0058] 13 , when viewed from the normal direction of the first main surface 1A, two or more trenches 2 are arranged in the short direction of the trenches 2. The first contact hole 6 and the second contact hole 7 are arranged to sandwich the region including the plurality of trenches 2 from the longitudinal direction of the trench 2.

[0059] 1, a plurality of first contact holes 6a, 6b and a plurality of second contact holes 7a, 7b are arranged in the short direction of the groove 2. In contrast, in the capacitor 101, as shown in FIG. 13, one first contact hole 6 and one second contact hole 7 are arranged extending in the short direction of the groove 2. Therefore, a plurality of grooves 2 (here, 11 grooves 2) are arranged between the first contact hole 6 and the second contact hole 7. In this way, by densely packing the plurality of grooves 2 between the contact holes 6, 7, the capacitance density can be improved.

[0060] The configuration of the capacitor 101 according to the second embodiment will be described below, focusing on the differences from the capacitor 100 according to the first embodiment.

[0061] As shown in FIG. 14A , a first contact hole 6 is formed in the XIVA-XIVA cross section of FIG. 13 . The first contact hole 6 is a hole that penetrates the first interlayer film 8, the second-layer first conductive layer 4, and the dielectric layer 3 to reach the first-layer first conductive layer 4. A first electrode 11 (an example of an electrode on the high-potential side) is buried in the first contact hole 6. The first electrode 11 is in ohmic contact with the first-layer first conductive layer 4 at the bottom surface of the first contact hole 6 and in ohmic contact with the second-layer first conductive layer 4 at the side surface of the first contact hole 6. Note that the second conductive layer 5 is not stacked on the XIVA-XIVA cross section of FIG. 13 . The "region where the second conductive layer 5 is not stacked" will be described later with reference to FIG. 16A .

[0062] As shown in Figure 14C, a second contact hole 7 is formed in the XIVC-XIVC cross section of Figure 13. The second contact hole 7 is a hole that penetrates the first interlayer film 8, the second conductive layer 5, and the dielectric layer 3 to reach the first main surface 1A of the substrate 1. A second electrode 12 (an example of an electrode on the low potential side) is buried in the second contact hole 7. The second electrode 12 is in ohmic contact with the first main surface 1A of the substrate 1 at the bottom surface of the second contact hole 7 and is in ohmic contact with the second conductive layer 5 at the side surface of the second contact hole 7. Note that the first conductive layer 4 is not stacked on the XIVC-XIVC cross section of Figure 13. The "region where the first conductive layer 4 is not stacked" will be described later with reference to Figure 15A.

[0063] The other configuration of the capacitor 101 is the same as that of the capacitor 100, and the same components are denoted by the same reference numerals and will not be described again.

[0064] 15A to 19D, an example of a method for manufacturing the capacitor 101 will be described. Note that the method for manufacturing the capacitor 101 described below is just an example, and various other manufacturing methods can be used.

[0065] A semiconductor substrate heavily doped with N-type or P-type impurities is prepared as the substrate 1. Next, a portion of the substrate 1 is etched from the first main surface 1A of the substrate 1 to form the groove 2. When forming the groove 2 in a Si substrate, wet etching using HF (hydrofluoric acid) or KOH (potassium hydroxide) or dry etching using plasma can be used as the etching method.

[0066] Next, a silicon oxide film is deposited as a dielectric layer 3 on the inner surfaces of the trenches 2 and on the surface of the substrate 1, including the first main surface 1A. Next, a polysilicon film is deposited as a first conductive layer 4 on the inner surfaces of the trenches 2 and on the surface of the substrate 1, including the first main surface 1A, so as to cover the dielectric layer 3. After the deposition of the polysilicon film, an annealing treatment is performed in POCl3 at 950°C to form an N-type polysilicon film.

[0067] Next, a mask material 18 made of patterned photoresist is formed above the first main surface 1A of the substrate 1. The patterned mask material 18 has openings 19 on the first main surface 1A, as shown in FIG. 15A. The openings 19 correspond to "areas where the first conductive layer 4 is not stacked." Etching is performed using the mask material 18, and as shown in FIG. 15D, the first conductive layer 4 exposed through the openings 19 in the mask material 21 is selectively etched. The state after the above steps are completed is shown in FIGS. 15A to 15D.

[0068] Next, after removing the mask material 18, a silicon oxide film is deposited as the dielectric layer 3 on the inner surfaces of the trenches 2 and on the surface of the substrate 1, including the first main surface 1A. Next, a polysilicon film is deposited as the first conductive layer 4 on the inner surfaces of the trenches 2 and on the surface of the substrate 1, including the first main surface 1A, so as to cover the dielectric layer 3. After the deposition of the polysilicon film, an annealing treatment is performed in POCl3 at 950°C to form an N-type polysilicon film.

[0069] Next, a mask material 24 made of patterned photoresist is formed above the first main surface 1A of the substrate 1. The patterned mask material 24 has openings 25 on the first main surface 1A, as shown in FIG. 16A. The openings 25 correspond to "areas where the second conductive layer 5 is not stacked." Etching is performed using the mask material 24, and as shown in FIG. 16B, the second conductive layer 5 exposed through the openings 25 in the mask material 24 is selectively etched. The state after the above steps are completed is shown in FIGS. 16A to 16D.

[0070] Next, after removing the mask material 24, the steps described with reference to FIGS. 15A to 15D and 16A to 16D are performed again. The state after the mask material is removed is shown in FIGS. 17A to 17C. As shown in FIG. 17A, in the "region where the second conductive layer 5 is not stacked" of the first main surface 1A, a dielectric layer 3, a first conductive layer 4, a dielectric layer 3, and a second conductive layer 4 are stacked in this order. As shown in FIG. 17C, in the "region where the first conductive layer 4 is not stacked" of the first main surface 1A, a dielectric layer 3, a second conductive layer 5, and a dielectric layer 3 are stacked in this order. Meanwhile, as shown in FIG. 17B, in the interior of the groove 2 and on the rest of the first main surface 1A, a first conductive layer 4, a second conductive layer 5, and a second conductive layer 4 are stacked with a dielectric layer 3 interposed therebetween. The interior of the groove 2 is backfilled with a second conductive layer 4.

[0071] Next, a photoresist is applied to the first main surface 1A of the substrate 1 and exposed to light to form a patterned mask material 27. The patterned mask material 27 has openings in the areas where the first contact holes 6 and second contact holes 7 will be formed. The mask material 27 is used to selectively etch the dielectric layer 3, the first conductive layer 4, and the second conductive layer 5 exposed through the openings in the mask material 27. An anisotropic etching method may be used as the etching method. The dielectric layer 3, the first conductive layer 4, and the second conductive layer 5 exposed through the openings in the mask material 21 are removed, exposing the first conductive layer 4 of the first layer or the first main surface 1A of the substrate 1. The state after the above steps are completed is shown in Figures 18A to 18D. The second conductive layer 4 and second conductive layer 5 are exposed on the side surfaces of the first contact holes 6 and second contact holes 7, respectively.

[0072] 18B and 18D show, for convenience, a mask material 27 having openings in regions where first contact holes 6 and second contact holes 7 of different depths will be formed, but in reality, different mask materials and etching processes are used depending on the depths of the contact holes to be formed. Specifically, a mask material 27 forming process and etching process are performed to form first contact holes 6 with a depth reaching the first conductive layer 4 of the first layer, and a mask material 27 forming process and etching process are performed to form second contact holes 7 with a depth reaching the first main surface 1A of the substrate 1. The order of these processes does not matter.

[0073] Next, after removing the mask material 27, an electrode film is deposited inside the first contact hole 6, inside the second contact hole 7, and on the first main surface 1A. The metal film can be deposited by sputtering, EB evaporation, or ALD.

[0074] Next, a mask material (not shown) made of a silicon oxide film is formed on the electrode film, and the mask material is patterned using lithography and etching techniques. The patterned mask material is used to selectively etch the electrode film by dry etching or wet etching. Alternatively, the metal film may be patterned using a lift-off method. This forms the first electrode 11 and the second electrode 12. The state after the above steps are completed is shown in Figures 19A to 19D.

[0075] Next, after removing the mask material, a pad electrode film is deposited to cover the first main surface 1A. Next, a mask material (not shown) made of a silicon oxide film is formed on the pad electrode film. The pad electrode film is selectively etched by dry etching using the patterned mask material. Alternatively, the pad electrode film may be patterned using a lift-off method. This forms the first pad electrode 15 and the second pad electrode 16. Through the above steps, the capacitor 101 shown in FIG. 13 and FIGS. 14A to 14C is completed.

[0076] 20B , a capacitor 102 will be described in which the grooves 2 extend all the way to the rear surface (second main surface 1B) of the substrate 1. In the capacitor 102, the grooves 2 can be formed deeper than in the capacitors 100 and 101, which increases the surface area of ​​the grooves 2 and increases the capacitance density per unit area of ​​the substrate 1. The capacitor 102 according to the third embodiment will be described, focusing on the differences from the capacitor 100 according to the first embodiment.

[0077] The dielectric layer 3 and the conductive layers (4, 5) are stacked not only on the first main surface 1A and in the groove 2 of the substrate 1, but also on the second main surface 1B. The first contact holes 6a, 6b and the second contact holes 7a, 7b are formed on both the first main surface 1A and the second main surface 1B of the substrate 1. The first electrode 11, the second electrode 12, the first pad electrode 15, and the second pad electrode 16 are also formed on the second main surface 1B of the substrate 1. Therefore, by stacking a plurality of chip-like capacitors 102 in the thickness direction of the substrate 1 and joining the pad electrodes together, a module with improved capacitance or withstand voltage can be easily produced.

[0078] The planar layout of the front surface (first main surface 1A) and back surface (second main surface 1B) of capacitor 102 is the same as that of the front surface (first main surface 1A) of capacitor 100, and therefore will not be illustrated or described here. The other configurations, basic operations, and manufacturing methods of capacitor 102 are the same as those of capacitor 100, and therefore will not be illustrated or described here.

[0079] The above-described embodiment is merely an example of the present invention, and therefore the present invention is not limited to the above-described embodiment, and various modifications can be made to the design and other aspects of the present invention without departing from the technical concept of the present invention.

[0080] REFERENCE SIGNS LIST 1 substrate 1A first main surface 1B second main surface 2 groove 3 dielectric layer 4 first conductive layer 5 second conductive layer 6, 6a, 6b first contact hole 7, 7a, 7b second contact hole 8 first interlayer film 10 second interlayer film 11 first electrode 12 second electrode 13 third contact hole 14 fourth contact hole 15 first pad electrode 16 second pad electrode 17 region including two or more grooves 100 to 102 capacitor L longitudinal direction S lateral direction

Claims

A substrate; two or more grooves formed in a first main surface of the substrate; At least two or more dielectric layers and conductive layers are alternately stacked on the first main surface and in the groove; a first contact hole and a second contact hole formed above the first main surface; a first electrode partially embedded in the first contact hole and electrically connected to one or more first conductive layers of the two or more conductive layers; a second electrode that is partially embedded in the second contact hole and electrically connected to one or more second conductive layers of the two or more conductive layers; the two or more grooves are arranged in a short-side direction of the grooves when viewed from a normal direction of the first main surface, A capacitor, wherein the first contact hole and the second contact hole are arranged to sandwich a region including the two or more grooves in the longitudinal direction of the grooves when viewed from the normal direction of the first main surface. 　 The capacitor according to claim 1 , wherein the second electrode is electrically connected to the first main surface through the second contact hole.

3. The capacitor according to claim 1, wherein the first electrode is electrically connected to the conductive layer closest to the first main surface through the first contact hole.

4. A capacitor according to claim 1, wherein, when viewed from the normal direction of the first main surface, the first contact hole and the second contact hole are arranged so as to sandwich a portion of the region between adjacent grooves.

5. The capacitor according to claim 1, wherein a plurality of the grooves are provided between the first contact hole and the second contact hole when viewed from a normal direction of the first main surface. 　 The substrate is made of single crystal silicon, The capacitor according to claim 1 , wherein the sidewalls of the groove are formed along a (111) plane of the substrate. 　 the substrate has a second main surface facing in a direction opposite to the first main surface; The capacitor according to claim 1 , wherein the groove extends from the first main surface to the second main surface. 　 the dielectric layer and the conductive layer are also deposited on the second major surface; 8. The capacitor according to claim 7, wherein the first contact hole and the second contact hole are formed on both the first main surface and the second main surface of the substrate. 　 The capacitor according to claim 1 , wherein the substrate is electrically conductive. 　 The capacitor according to claim 1 , wherein the substrate has insulating properties. 　 The method for manufacturing a capacitor according to claim 1 , wherein the etching method for forming the groove is dry etching. 　 The method for manufacturing a capacitor according to claim 1 , wherein the etching method for forming the groove is wet etching.

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