Power semiconductor device and method for manufacturing same

Abstract

A power semiconductor device (1) has, formed in a semiconductor element (13) mounted to an insulating substrate (3), a wire wiring pad (15) and an upper surface electrode (17). The wire wiring pad (15) has formed thereon a plate material (25) provided with a first surface (25a) and a second surface (25b). The first surface (25a) has high wettability with respect to melted bonding materials (21b, 19). The second surface (25b) has low wettability with respect to melted bonding materials (21a, 19). One end of a wire wiring (33) is bonded to the second surface (25b). A lead electrode (35) is bonded to the upper surface electrode (17) by means of the bonding material (21a).

Description

Power semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to power semiconductor devices and methods for manufacturing the same.

[0002] Patent Document 1 discloses a power semiconductor device in which a semiconductor element mounted on a wiring board and one end of a metal lead electrode are joined by high-temperature solder, and an electrode formed on the wiring board and the other end of the metal lead electrode are joined by low-temperature solder.

[0003] In general power semiconductor devices, a method of electrically connecting a semiconductor element to the outside or between semiconductor elements is often performed by using wire wiring. In addition to wire wiring, a method of electrically connecting a semiconductor element to the outside or between semiconductor elements is also known (Patent Document 2).

[0004] JP 2001-110957 A JP 2008-182074 A

[0005] In a power semiconductor device that electrically connects to a semiconductor element or the like through both wire wiring and metal lead electrodes, the semiconductor element is formed with one electrode to which the wire wiring is joined and another electrode to which the metal lead electrode is joined. A plating layer is formed on each of the surfaces of the one electrode and the other electrode by plating. The metal lead electrode is joined to the other electrode on which the plating layer is formed by a joining material. In the process of joining the metal lead electrode to the other electrode, the joining material is melted.

[0006] At this time, it is expected that a part of the molten bonding material will scatter and adhere to the surface of the first electrode. Furthermore, if a part of the scattered bonding material adheres to the surface of the first electrode on which the plating layer is formed, there is a risk that a part of the adhered bonding material will be bonded to the surface of the first electrode.

[0007] After the metal lead electrode is bonded to the other electrode, the wire wiring is bonded to the first electrode. At this time, the wire wiring is bonded to the surface of the first electrode to which a portion of the bonding material is attached or bonded. This may reduce the bonding strength of the wire wiring to the first electrode, which is thought to be one of the factors that impair the reliability of the power semiconductor device.

[0008] The present disclosure has been made to solve such anticipated problems, and one object of the present disclosure is to provide a power semiconductor device that prevents a decrease in bonding strength of wire wiring, and another object of the present disclosure is to provide a method for manufacturing such a power semiconductor device.

[0009] The power semiconductor device according to the present disclosure comprises a substrate, a semiconductor element, wire wiring, a lead electrode, and a bonding material. A circuit pattern is formed on the substrate. The semiconductor element is bonded to the circuit pattern, and a first electrode and a second electrode spaced apart are arranged on the side opposite to the side on which the circuit pattern is located. The wire wiring is electrically connected to the first electrode. The lead electrode is electrically connected to the second electrode. The bonding material includes a first bonding material that bonds the second electrode and the lead electrode. The first electrode is formed with a bonding material adhesion bonding prevention portion that prevents the first bonding material that bonds the lead electrode to the second electrode from adhering to and bonding the first electrode. The wire wiring is bonded to the bonding material adhesion bonding prevention portion.

[0010] A method for manufacturing a power semiconductor device according to the present disclosure includes the following steps: forming a semiconductor element arranged such that a first electrode and a second electrode spaced apart are exposed; preparing a substrate on which a circuit pattern is formed; placing the semiconductor element on a circuit pattern such that the side of the semiconductor element opposite the side on which the first electrode and the second electrode are arranged faces the circuit pattern; forming a bonding material, including a step of forming a first bonding material on the second electrode; forming a bonding material adhesion bonding prevention portion on the first electrode that prevents the first bonding material from adhering to and bonding the first electrode; placing a lead electrode on the first bonding material; performing a heat treatment, including a step of melting the first bonding material to bond the lead electrode to the second electrode; and bonding a wire wiring to the bonding material adhesion bonding prevention portion.

[0011] In the power semiconductor device according to the present disclosure, the first electrode is formed with a bonding material adhesion and bonding prevention portion that prevents a first bonding material that bonds a lead electrode to a second electrode from adhering to the first electrode, and the wire wiring is bonded to the bonding material adhesion and bonding prevention portion, thereby preventing a decrease in the bonding strength of the wire wiring to the first electrode.

[0012] According to the method for manufacturing a power semiconductor device of the present disclosure, the first bonding material is melted on the first electrode to which the wire wiring is electrically connected, while forming a bonding material adhesion bonding-blocking portion that prevents the first bonding material bonding the lead electrode to the second electrode from adhering to the first electrode and bonding the lead electrode to the second electrode. This prevents the molten first bonding material from adhering to the first electrode and bonding the lead electrode to the second electrode. The wire wiring is bonded to the bonding material adhesion bonding-blocking portion. As a result, a decrease in the bonding strength of the wire wiring to the bonding material adhesion bonding-blocking portion can be prevented.

[0013] 1 is a cross-sectional view of a power semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view showing one step of a manufacturing method of a power semiconductor device according to a second embodiment; FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the second embodiment; FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the second embodiment; FIG. 6 is a cross-sectional view for explaining a problem of a power semiconductor device according to a comparative example; FIG. 7 is a cross-sectional view for explaining an action and effect of the power semiconductor device in the second embodiment; FIG. 8 is a cross-sectional view for explaining an action and effect of the power semiconductor device in the second embodiment; FIG. 9 is a cross-sectional view for explaining an action and effect of the power semiconductor device in the third embodiment; FIG. 10 is a cross-sectional view for explaining an action and effect of the power semiconductor device in the second embodiment; FIG. 11 is a cross-sectional view for explaining an action and effect of the power semiconductor device in the second embodiment;

[0014] First Embodiment An example of a power semiconductor device according to a first embodiment will be described. As shown in Fig. 1, in the power semiconductor device 1, a semiconductor element 13 is mounted on an insulating substrate 3. Wire wiring pads 15 formed on the semiconductor element 13 are electrically connected to external electrodes 37 by wire wiring 33. Top electrodes 17 formed on the semiconductor element 13 are electrically connected to lead electrodes 35. The semiconductor element 13 and other components are sealed in a sealing resin 39 in such a manner that the external electrodes 37 and lead electrodes 35 protrude.

[0015] The structure of the power semiconductor device 1 will be described in more detail. The insulating substrate 3 as a substrate includes an insulating layer 5, a circuit pattern 7, and a circuit pattern 9. For example, a ceramic with excellent thermal conductivity, such as aluminum nitride or silicon nitride, is used as the insulating layer 5. The insulating layer 5 may also be made of a resin. However, the insulating layer 5 is not limited to these materials.

[0016] Each of the circuit pattern 7 and the circuit pattern 9 is formed from, for example, copper or an aluminum alloy. The circuit pattern 7 is formed on one main surface of the insulating layer 5. The circuit pattern 9 is formed on the other main surface of the insulating layer 5. The circuit pattern 9 may be joined to another heat dissipating base plate (not shown) by solder or the like, or may be mounted on a cooling fin or the like by heat dissipating grease or the like.

[0017] The semiconductor element 13 is bonded to the circuit pattern 7 by a bonding material 11. For example, a solder alloy material containing tin (Sn) as a main component and various metal elements added thereto is used as the bonding material 11. Alternatively, a sintered bonding material made of a paste of highly conductive silver or copper may be used as the bonding material 11.

[0018] The semiconductor element 13 is a power semiconductor element, such as an IGBT (Insulated Gate Bipolar Transistor), a diode, or a reverse conducting IGBT formed on a silicon substrate. The semiconductor element 13 may also be a silicon carbide (SiC)-based power semiconductor element or a gallium nitride (GaN)-based power semiconductor element. Furthermore, the semiconductor element 13 may also be a metal oxide semiconductor field effect transistor (MOSFET) or a Schottky diode.

[0019] A wire wiring pad 15 serving as a first electrode and an upper surface electrode 17 serving as a second electrode are formed on the semiconductor element 13. The wire wiring pad 15 and the upper surface electrode 17 are formed on the side of the semiconductor element 13 opposite to the side facing the bonding material 11. The wire wiring pad 15 and the upper surface electrode 17 are formed so as to be spaced apart from each other.

[0020] A signal circuit that controls the semiconductor element 13 is electrically connected to the wire wiring pad 15 via a wire wiring 33. A lead electrode 35 is joined to the upper surface electrode 17 by a bonding material 21a (bonding material 19) that serves as a first bonding material having a high melting point. The lead electrode 35 is made of a copper material or the like that has excellent conductivity.

[0021] A wire wiring connection portion 23 is formed on the wire wiring pad 15 as a bonding material adhesion bonding prevention portion. Here, a plate material 25 is formed as the wire wiring connection portion 23. The plate material 25 is bonded to the wire wiring pad 15 by a bonding material 21b (bonding material 19) as a second bonding material. A solder alloy material containing Sn (tin) as a main component and various metal elements added thereto is used as the bonding material 19 (bonding material 21a, bonding material 21b). Note that the bonding material 19 is not limited to a solder alloy material as long as it is a material that can be bonded by melting.

[0022] The plate material 25 has a first surface 25a and a second surface 25b. The first surface 25a is disposed to face the bonding material 21b (bonding material 19) and bonded thereto. The first surface 25a has high wettability with respect to the molten bonding material 21b (bonding material 19). That is, the first surface 25a has a small contact angle (for example, less than 90°) with the molten bonding material 21b (bonding material 19). The first surface 25a also has high wettability with respect to the molten bonding material 21a (bonding material 19).

[0023] On the other hand, the second surface 25b has low wettability with respect to the molten bonding material 21a (bonding material 19). That is, the second surface 25b has a large contact angle (for example, 90° or more) with the molten bonding material 21a (bonding material 19). The second surface 25b also has low wettability with respect to the molten bonding material 21b (bonding material 19).

[0024] The plate material 25 may be, for example, an aluminum plate with one surface plated with Sn. In this case, the Sn-plated surface serves as the first surface 25a, and the aluminum surface serves as the second surface 25b. Alternatively, an aluminum-copper clad material may be used. Furthermore, a multilayer substrate such as a printed circuit board (PCB) may be used.

[0025] One end of the wire wiring 33 is joined to the second surface 25b. The other end of the wire wiring 33 is joined to the external electrode 37. The wire wiring 33 is made of a wiring material that can be joined by ultrasonic bonding, such as aluminum, copper, silver, or gold, which has excellent thermal conductivity and electrical conductivity.

[0026] The sealing resin 39 that seals the semiconductor element 13 and the like seals the circuit pattern 9 mounted on a cooling fin (not shown) or the like in a manner that exposes it. Epoxy resin or silicone gel can be used as the sealing resin 39, but the resin is not limited to these. For example, a material that satisfies desired physical properties such as elastic modulus, heat resistance, adhesiveness, or linear expansion coefficient can be used.

[0027] Although the sealing resin 39 is formed by pressure-molding molten resin injected into a mold, it may also be formed by, for example, placing the insulating substrate 3 on which the semiconductor element 13 is mounted in a pre-molded resin case, and then pouring molten resin into the resin case. The power semiconductor device 1 according to the first embodiment is configured as described above.

[0028] In the power semiconductor device 1 according to the first embodiment described above, the wire wiring 33 is bonded to the second surface 25b of the plate material 25, which has low wettability with respect to the bonding material 21a (bonding material 19), thereby preventing a decrease in the bonding strength of the wire wiring 33 to the plate material 25. This will be described in the manufacturing method according to the following embodiment.

[0029] Second Embodiment An example of a method for manufacturing a power semiconductor device 1 according to a second embodiment will be described. First, an insulating substrate 3 including an insulating layer 5, a circuit pattern 7, and a circuit pattern 9 is prepared (see FIG. 2). A semiconductor element 13 is also prepared (see FIG. 3).

[0030] 2, the bonding material 11 is formed on the circuit pattern 7 on the insulating substrate 3 by, for example, screen printing using a metal mask. Other methods for forming the bonding material 11 include, for example, dispensing a paste-like bonding material, and, for example, placing a solid bonding material such as a solder plate.

[0031] Next, as shown in Fig. 3, the semiconductor element 13 is placed on the bonding material 11. Next, as shown in Fig. 4, a bonding material 21b (bonding material 19) is formed on the wire wiring pad 15. A bonding material 21a (bonding material 19) is formed on the upper electrode 17. The thickness of the bonding material 21a (bonding material 19) is greater than the thickness of the bonding material 21b (bonding material 19). A solder alloy material is used as the bonding material 19 (bonding materials 21a, 21b).

[0032] When a solid bonding material such as a solder plate is used as the bonding material 19, the thickness can be changed by adjusting the number of solder plates supplied. When a paste-like bonding material is used, the thickness can be changed by adjusting the amount applied.

[0033] 5, the lead electrode 35 is placed on the bonding material 21a. The plate material 25 is placed on the bonding material 21b. At this time, the plate material 25 is placed on the bonding material 21b so that the first surface 25a of the plate material 25, on which a Sn plating layer having high wettability with respect to the bonding material 19 is formed, comes into contact with the bonding material 21b. By placing the first surface 25a having high wettability in contact with the bonding material 21b, the second surface 25b having low wettability with respect to the bonding material 19 is exposed on the upper surface of the plate material 25.

[0034] Next, a heat treatment is performed to melt the bonding material 19 (bonding materials 21a and 21b), thereby bonding the lead electrode 35 to the upper electrode 17. The plate material 25 is also bonded to the wire wiring pad 15. When solder is used as the bonding material 19, reflow heating is performed at a temperature equal to or higher than the melting point of the solder. For example, when a solder having a general composition (such as SAC305 solder) is used, heating is performed to 240°C or higher. The heat treatment is performed in a nitrogen atmosphere to prevent the solder from reoxidizing during heating.

[0035] At this time, the heat treatment is performed with the second surface 25b of the plate material 25 exposed as the upper surface. The second surface 25b has low wettability with respect to the bonding material 21a (bonding material 19). As a result, even if a portion of the molten bonding material 21a (bonding material 19) is scattered toward the plate material 25, the scattered bonding material 21a can be prevented from adhering to the second surface 25b and bonding. This will be described later. Note that this heat treatment also melts the bonding material 11, thereby bonding the semiconductor element 13 to the circuit pattern 7.

[0036] Next, as shown in Fig. 6, one end of the wire wiring 33 is joined (bonded) to the second surface 25b of the plate material 25, and the other end of the wire wiring 33 is joined to the external electrode 37. Next, as shown in Fig. 7, the insulating substrate 3 on which the semiconductor element 13 and the like are mounted is placed, for example, in a mold 41. The mold 41 includes an upper mold 41a and a lower mold 41b. The insulating substrate 3 on which the semiconductor element 13 and the like are mounted is accommodated in a cavity 43 with the lead electrode 35 and the external electrode 37 sandwiched between the upper mold 41a and the lower mold 41b.

[0037] Thereafter, a sealing resin is injected into the cavity 43 to seal the semiconductor element 3 and the like. After the sealing resin 39 has hardened, the power semiconductor device 1 is removed from the mold 41, thereby completing the power semiconductor device 1 sealed with the sealing resin 39 as shown in FIG.

[0038] In the manufacturing method of the power semiconductor device 1 described above, when the lead electrode 35 is bonded to the upper surface electrode 17, the wire wiring pad 15 is subjected to heat treatment with the second surface 25b of the plate material 25 exposed, thereby preventing the scattered bonding material 21a from adhering to and bonding to the second surface 25b. This will be explained in comparison with a power semiconductor device 101 according to a comparative example (see FIG. 8).

[0039] In the power semiconductor device 101 according to the comparative example, a bonding material 111 is formed on the circuit pattern 107 of the insulating substrate 103 having the insulating layer 105, the circuit pattern 107, and the circuit pattern 109, and then a semiconductor element 113 is placed on the bonding material 111 (see FIG. 8).

[0040] Next, a bonding material 121a is formed on the upper surface electrode 117 of the semiconductor element 113 (see FIG. 8). Next, as shown in FIG. 8, a lead electrode 135 is placed on the bonding material 121a. Next, a heat treatment is performed to melt the bonding material 121a, thereby bonding the lead electrode 135 to the upper surface electrode 117.

[0041] At this time, as shown by the arrow YY, it is assumed that part of the molten bonding material 121a will scatter, and further that part of the scattered bonding material 121a will adhere to and bond to the surface of the wire wiring pad 115 of the semiconductor element 113. Therefore, if the wire wiring 133 is bonded in a state where the scattered bonding material 121a is still adhering to the surface of the wire wiring pad 115, the bonding strength of the wire wiring 133 to the wire wiring pad 115 may be reduced.

[0042] 9 , in the power semiconductor device 1 described above, a bonding material 21b is formed on the wire wiring pad 15, and a plate material 25 is placed on the bonding material 21b. At this time, the plate material 25 is placed on the bonding material 21b so that a first surface 25a of the plate material 25, on which a Sn plating layer having high wettability with respect to the bonding material 19 is formed, contacts the bonding material 21b. By placing the first surface 25a having high wettability in contact with the bonding material 21b, a second surface 25b having low wettability with respect to the bonding material 21a (bonding material 19) is exposed on the upper surface of the plate material 25.

[0043] Therefore, the heat treatment is performed in a state where the second surface 25b, which has low wettability with respect to the bonding material 21a (bonding material 19), is exposed. As a result, even if a part of the molten bonding material 21a (bonding material 19) is scattered toward the plate material 25 as shown by the arrow Y, the scattered part of the bonding material 21a can be prevented from adhering to the second surface 25b and bonding. As a result, it is possible to prevent a decrease in the bonding strength of the wire wiring 33 to the plate material 25 (second surface 25b).

[0044] Third Embodiment An example of a power semiconductor device according to a third embodiment will be described. As shown in FIG. 10 , in the power semiconductor device 1, a wire wiring connection portion 23 is formed on the wire wiring pad 15 as a bonding material adhesion bonding prevention portion. Here, a plate material block 27 is formed as the wire wiring connection portion 23, which serves as a first plate material block. The plate material block 27 is formed from a material that can be bonded with a bonding material 21c, which serves as a third bonding material. The plate material block 27 is formed from a single material, such as copper. The plate material block 27 is bonded to the wire wiring pad 15 by a bonding material 21c (bonding material 19).

[0045] The height of the top of plate block 27 from semiconductor element 13 is higher than the height (dotted line position) of the upper ends of lead electrodes 35 from semiconductor element 13. Wire wiring 33 is joined to the top of plate block 27. Note that the rest of the configuration is similar to that of power semiconductor device 1 shown in Figure 1, so the same members are given the same reference numerals and their description will not be repeated unless necessary.

[0046] In the above-described power semiconductor device 1, the top of the plate block 27 to which the wire wiring 33 is joined is located higher than the upper end of the lead electrode 35, thereby preventing a decrease in the joining strength of the wire wiring 33 to the plate block 27. This will be described below.

[0047] 2 to 4, the lead electrode 35 is placed on the bonding material 21a as shown in Fig. 11. The plate block 27 is placed on the bonding material 21c. Next, a heat treatment is performed to melt the bonding material 19 (bonding material 21a, bonding material 21c), thereby bonding the lead electrode 35 to the upper electrode 17. The plate block 27 is also bonded to the wiring pad 15.

[0048] At this time, the heat treatment is performed in a state where the top of the plate block 27 to which the wire wiring 33 is bonded is positioned higher than the upper end (see dotted line) of the lead electrode 35. As a result, even if part of the molten bonding material 21a (bonding material 19) splashes toward the plate block 27 as shown by arrow Y, the splashed bonding material 21a can be prevented from adhering to the top of the plate block 27 and bonding it to the lead electrode 35. As a result, it is possible to prevent a decrease in the bonding strength of the wire wiring 33 bonded to the wire wiring pad 15.

[0049] Furthermore, by using the plate block 27 formed from a single material such as copper, it is not necessary to perform additional processing such as Sn (tin) plating so that the plate block 27 is bonded by the bonding material 21c, which can contribute to improving the productivity of the power semiconductor device 1.

[0050] Fourth Embodiment An example of a power semiconductor device according to a fourth embodiment will be described. As shown in Fig. 12, a wire wiring pad 15 is formed with a wire wiring connection portion 23 as a bonding material adhesion bonding prevention portion. Here, an L-shaped plate material block 29 is formed as a second plate material block as the wire wiring connection portion 23. The L-shaped plate material block 29 includes a first portion 29a and a second portion 29b.

[0051] The second portion 29b is connected to the first portion 29a. The first portion 29a is bonded to the wire wiring pad 15 by a bonding material 21d serving as a fourth bonding material. The second portion 29b is located between the first portion 29a and the bonding material 21a that bonds the lead electrode 35 to the upper surface electrode 17. The height of the upper end of the second portion 29b from the semiconductor element 13 is higher than the height of the upper end of the lead electrode 35 (see dotted line) from the semiconductor element 13. The upper end of the second portion 29b is located higher than the upper end of the lead electrode 35.

[0052] On the other hand, first portion 29a (upper surface) is located at a position lower than the upper end of lead electrode 35. Wire interconnection 33 is joined to first portion 29a. Note that other configurations are similar to those of power semiconductor device 1 shown in Figure 1, and therefore the same members are denoted by the same reference numerals, and description thereof will not be repeated unless necessary.

[0053] In the above-described power semiconductor device 1, the second portion 29b is located between the first portion 29a and the bonding material 21a of the L-shaped plate block 29 to which the wire wiring 33 is bonded, and the upper end of the second portion 29b is located higher than the upper end of the lead electrode 35, thereby preventing a decrease in the bonding strength of the wire wiring 33 to the L-shaped plate block 29. This will be explained.

[0054] 2 to 4, the lead electrode 35 is placed on the bonding material 21a as shown in Fig. 13. An L-shaped plate block 29 is placed on the bonding material 21d. Next, a heat treatment is performed to melt the bonding material 19 (bonding material 21a, bonding material 21d), thereby bonding the lead electrode 35 to the upper electrode 17. The L-shaped plate block 29 is also bonded to the wiring pad 15.

[0055] At this time, the heat treatment is performed in a state in which the upper end of the second portion 29b, which is located between the first portion 29a and the bonding material 21a of the L-shaped plate material block 29, is located higher than the upper end of the lead electrode 35. As a result, even if part of the molten bonding material 21a (bonding material 19) splashes toward the L-shaped plate material block 29 as shown by arrow Y, the second portion 29b of the L-shaped plate material block 29 can prevent the splashed bonding material 21a from splashing to the first portion 29a and adhering thereto.

[0056] That is, the second portion 29 b functions as a shielding material that prevents the bonding material 21 a from scattering toward the first portion 29 a, thereby preventing a decrease in the bonding strength of the wire 33 bonded to the wire pad 15.

[0057] Furthermore, the first portion 29a (top surface) of the L-shaped plate material block 29 is located at a position lower than the upper end of the lead electrode 35. This lowers the position (first portion 29a) where the wire wiring 33 is joined, which contributes to preventing the power semiconductor device 1 from becoming larger in size.

[0058] Furthermore, by using the plate block 27 formed from a single material such as copper as the L-shaped plate block 29, it is not necessary to perform additional processing such as Sn (tin) plating so that the L-shaped plate block 29 is joined by the joining material 21d, which can also contribute to improving the productivity of the power semiconductor device 1.

[0059] Fifth Embodiment An example of a power semiconductor device according to a fifth embodiment will now be described. As shown in Fig. 14, a wire wiring pad 15 is formed with a wire wiring connection portion 23 as a bonding material adhesion blocking portion. Here, a non-plated surface 31a on which no plating layer is formed is formed on the surface of the wire wiring pad 15 as the wire wiring connection portion 23.

[0060] If the semiconductor element 13 is, for example, a type in which an IGBT or the like is formed on a silicon substrate, silicon (Si) will be exposed on the surface of the wire wiring pad 15. The wire wiring 33 is bonded to the non-plated surface 31 a on which no plating layer is formed.

[0061] On the other hand, a plated surface 31b on which a plating layer is formed is located on the surface of the top electrode 17 of the semiconductor element 13. The lead electrode 35 is joined to the top electrode 17 by a joining material 21a. Since the other configurations are the same as those of the power semiconductor device 1 shown in Fig. 1, the same members are designated by the same reference numerals, and the description thereof will not be repeated unless necessary.

[0062] In the above-described power semiconductor device 1, the non-plated surface 31 a on which no plating layer is formed is located on the surface of the wire wiring pad 15, thereby preventing a decrease in the bonding strength of the wire wiring 33 to the wire wiring pad 15. This will be described.

[0063] 15, semiconductor element 13 is manufactured in the form of a wafer (silicon substrate 51). A plating process is performed when forming top surface electrodes 17 and wire wiring pads 15. At this time, a mask material (not shown) is formed in a manner that covers wire wiring pads 15 but does not cover top surface electrodes 17.

[0064] Next, a plating process is performed. After the plating process, the mask material is removed. This plating process forms a plating layer on the surface of the upper electrode 17 that is not covered by the mask material, exposing the plated surface 31b. On the other hand, no plating layer is formed on the surface of the wiring pad 15 that is covered by the mask material, exposing the non-plated surface 31a. Thereafter, the silicon substrate 51 or the like is diced or the like to form the semiconductor element 13 as a chip.

[0065] 2 to 4, the lead electrode 35 is placed on the bonding material 21a as shown in Fig. 16. Next, a heat treatment is performed to melt the bonding material 19 (bonding material 21a), thereby bonding the lead electrode 35 to the upper electrode 17. At this time, the heat treatment is performed with the non-plated surface 31a of the wiring pad 15 exposed.

[0066] As a result, even if a portion of the molten bonding material 21a (bonding material 19) were to splash toward the wire wiring pad 15 as shown by the arrow Y, the non-plated surface 31a (silicon surface) exposed on the surface of the wire wiring pad 15 can prevent the splashed bonding material 21a from adhering to and bonding the wire wiring 33. As a result, it is possible to prevent a decrease in the bonding strength of the wire wiring 33 bonded to the wire wiring pad 15.

[0067] Furthermore, there is no need to form an appropriate member for joining the wire wiring 33 on the wire wiring pad 15, which contributes to reducing production costs. Furthermore, the position (height) of the non-plated surface 31a exposed on the surface of the wire wiring pad 15 is lower than the upper end of the lead electrode 35. This allows the position (non-plated surface 31a) where the wire wiring 33 is joined to be the lowest, which contributes to preventing the power semiconductor device 1 from becoming larger.

[0068] The power semiconductor device 1 and the manufacturing method thereof described in each embodiment can be variously combined as needed.

[0069] The embodiments disclosed herein are examples and are not intended to be limiting. The scope of the present disclosure is defined by the scope of the claims, not the scope described above, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

[0070] The present disclosure is effectively applied to a power semiconductor device having a pad for wire wiring.

[0071] 1 Power semiconductor device, 3 Insulating substrate, 5 Insulating layer, 7 Circuit pattern, 9 Circuit pattern, 11 Bonding material, 13 Semiconductor element, 15 Wire wiring pad, 17 Upper surface electrode, 19, 21a, 21b, 21c, 21d Bonding material, 23 Wire wiring connection portion, 25 Plate material, 25a First surface, 25b Second surface, 27 Plate material block, 29 L-shaped plate material block, 29a First part, 29b Second part, 31a Non-plated surface, 31b Plated surface, 33 Wire wiring, 35 Lead electrode, 37 External electrode, 39 Sealing resin, 41 Mold, 41a Upper mold, 41b Lower mold, 43 Cavity, 51 Silicon substrate.

Claims

1. A power semiconductor device comprising: a substrate on which a circuit pattern is formed; a semiconductor element bonded to the circuit pattern, the semiconductor element having a first electrode and a second electrode spaced apart on the side opposite the side on which the circuit pattern is located; a wire wiring electrically connected to the first electrode; a lead electrode electrically connected to the second electrode; and a bonding material including a first bonding material that bonds the second electrode to the lead electrode, wherein the first electrode has a bonding material adhesion bonding prevention portion that prevents the first bonding material that bonds the lead electrode to the second electrode from adhering to and bonding the first electrode, and the wire wiring is bonded to the bonding material adhesion bonding prevention portion.

2. A power semiconductor device as described in claim 1, wherein the bonding material adhesion bonding prevention portion has opposing first and second main surfaces and includes a plate material bonded to the first electrode, the bonding material includes a second bonding material that bonds the first main surface of the plate material to the first electrode, the wettability of the second main surface of the plate material to the bonding material is lower than the wettability of the first main surface of the plate material to the bonding material, and the wire wiring is bonded to the second main surface.

3. A power semiconductor device as described in claim 1, wherein the bonding material adhesion bonding prevention portion includes a first plate material block bonded to the first electrode, the height of the first plate material block from the semiconductor element is greater than the height of the lead electrode from the semiconductor element, the bonding material includes a third bonding material that bonds the first plate material block to the first electrode, and the wire wiring is bonded to the top of the first plate material block.

4. A power semiconductor device as described in claim 1, wherein the bonding material adhesion bonding prevention portion includes a second plate material block bonded to the first electrode, the second plate material block including: a first portion; and a second portion located between the first portion and the first bonding material bonding the lead electrode to the second electrode and connected to the first portion; the height of the second portion from the semiconductor element is greater than the height of the lead electrode from the semiconductor element; the height of the first portion from the semiconductor element is less than the height of the lead electrode from the semiconductor element; the bonding material includes a fourth bonding material bonding the second plate material block to the first electrode; and the wire wiring is bonded to the first portion.

5. A power semiconductor device as claimed in claim 1, wherein the second electrode has a plated surface on which a plating layer is formed, the first electrode has a non-plated surface on which the plating layer is not formed, the bonding material adhesion preventing portion includes the non-plated surface located on the first electrode, and the wire wiring is bonded to the non-plated surface located on the first electrode.

6. The power semiconductor device according to any one of claims 1 to 5, wherein the bonding material includes a solder alloy material.

7. A method for manufacturing a power semiconductor device, comprising: a step of forming a semiconductor element arranged in a manner that exposes first and second electrodes that are spaced apart from each other; a step of preparing a substrate on which a circuit pattern is formed; a step of bonding the semiconductor element to the circuit pattern in a manner that the side of the semiconductor element opposite the side on which the first and second electrodes are arranged faces the circuit pattern; a step of forming a bonding material, including a step of forming a first bonding material on the second electrode; a step of forming a bonding material adhesion bonding prevention portion on the first electrode that prevents the first bonding material from adhering to and bonding to the first electrode; a step of placing a lead electrode on the first bonding material; a step of performing a heat treatment, including a step of melting the first bonding material to bond the lead electrode to the second electrode; and a step of bonding a wire wiring to the bonding material adhesion bonding prevention portion.

8. The method for manufacturing a power semiconductor device according to claim 7, wherein the step of forming the bonding material adhesion preventing portion includes the step of preparing a plate material having opposing first and second main surfaces, the second main surface having lower wettability to the bonding material than the first main surface, the step of forming the bonding material includes the step of forming a second bonding material that bonds the plate material to the first electrode, the step of applying heat treatment includes the step of placing the plate material on the second bonding material in a state where the first main surface of the plate material is in contact with the second bonding material, and melting the second bonding material while leaving the second main surface of the plate material exposed, the step of applying heat treatment simultaneously bonds the plate material to the first electrode and the step of bonding the lead electrode to the second electrode, and the step of bonding the wire wiring to the second main surface of the plate material.

9. A method for manufacturing a power semiconductor device as claimed in claim 7, wherein the step of forming the bonding material adhesion bonding prevention portion includes the step of preparing a first plate material block that, when placed on the first electrode, has a height from the semiconductor element that is higher than the height of the lead electrode from the semiconductor element; the step of forming the bonding material includes the step of forming a third bonding material that bonds the first plate material block to the first electrode; the step of applying heat treatment includes the step of melting the third bonding material while the first plate material block is placed on the third bonding material, thereby bonding the first plate material block to the first electrode; in the step of applying heat treatment, the step of bonding the first plate material block to the first electrode and the step of bonding the lead electrode to the second electrode are carried out simultaneously; and in the step of bonding the wire wiring, the wire wiring is bonded to the top of the first plate material block.

10. The step of forming the bonding material adhesion bonding prevention portion includes a step of preparing a second plate material block having, in a state where it is placed on the first electrode, a first portion whose height from the semiconductor element is lower than the height of the lead terminal from the semiconductor element and a second portion whose height from the semiconductor element is higher than the height of the lead terminal from the semiconductor element, the first portion and the second portion being connected; the step of forming the bonding material includes a step of forming a fourth bonding material that bonds the second plate material block to the first electrode; the step of applying heat treatment includes a step of bonding the second plate material block to the first electrode by melting the fourth bonding material in a state where the second portion is located between the first portion and the first bonding material; and in the step of applying heat treatment, the step of bonding the second plate material block to the first electrode and the step of bonding the lead terminal to the second electrode are performed simultaneously; 8. The method for manufacturing a power semiconductor device according to claim 7, wherein in the step of joining the wire wiring, the wire wiring is joined to the first portion of the second plate material block.

11. The method for manufacturing a power semiconductor device according to claim 7, wherein the step of forming the semiconductor element comprises the steps of: forming the first electrode and the second electrode; plating the second electrode to form a plated surface, and not plating the first electrode, leaving the surface of the first electrode as an unplated surface; the step of forming the bonding material adhesion preventing portion comprises the step of leaving the first electrode as the unplated surface; in the step of forming the bonding material, the first bonding material is formed on the plated surface; in the step of applying heat treatment, the unplated surface is exposed; and in the step of bonding the wire wiring, the wire wiring is bonded to the unplated surface.

12. The method for manufacturing a power semiconductor device according to any one of claims 7 to 11, wherein in the step of forming the bonding material, a solder alloy material is formed as the bonding material.

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