Array substrate, display panel and display apparatus

Abstract

An array substrate (001), a display panel and a display apparatus. The array substrate comprises a base substrate (101); a first common electrode line (102), which extends in a first direction (X) on the base substrate (101), and comprises a winding portion (1021); and a spacer base (103), which comprises a first portion (1031) and second portions (1032) that are integrally arranged, wherein the orthographic projection of the first portion (1031) on the base substrate (101) and the orthographic projection of the winding portion (1021) on the base substrate (101) are arranged side by side, the first dimension (h1) of the first portion (1031) in a second direction (Y) is greater than the second dimension (h2) of the second portions (1032) in the second direction (Y), and the second direction (Y) intersects with the first direction (X).

Description

Array substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0005] On one hand, embodiments of this disclosure provide an array substrate, including:

[0006] Substrate;

[0007] A first common electrode line extends along a first direction on the substrate, and the first common electrode line includes a winding portion;

[0008] The spacer base includes an integrally formed first part and a second part. The orthographic projection of the first part on the substrate and the orthographic projection of the winding part on the substrate are arranged side by side. The first dimension of the first part in a second direction is larger than the second dimension of the second part in the second direction. The second direction intersects the first direction.

[0009] In some embodiments, in the array substrate provided in the present disclosure, the linewidth of the first common electrode line is substantially uniform.

[0010] In some embodiments, in the array substrate provided in the present disclosure, there is a first distance between the orthographic projection of the winding portion on the substrate and the orthographic projection of the first portion on the substrate, and there is a second distance between the orthographic projection of the first common electrode line on the substrate and the orthographic projection of the second portion on the substrate, wherein the first distance is approximately equal to the second distance.

[0011] In some embodiments, in the array substrate provided in the present disclosure, the first center of the first part in the second direction and the second center of the second part in the second direction are substantially collinear.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the second portion is recessed by 1 μm to 3 μm on one side relative to the first portion in the second direction.

[0013] In some embodiments, in the array substrate provided in the present disclosure, the second portion is located on both sides of the first portion in the first direction.

[0014] In some embodiments, the array substrate provided in the present disclosure further includes: a transistor, a pixel electrode, and an insulating layer located between the pixel electrode layer and the first electrode layer of the transistor, the insulating layer including vias;

[0015] The first electrode of the transistor is electrically connected to the pixel electrode through the via, and at least a portion of the via's orthogonal projection on the substrate lies within the orthogonal projection of the second portion on the substrate.

[0016] In some embodiments, the array substrate provided in this disclosure further includes a data line extending along the second direction and integrally disposed with the second electrode of the transistor, and a second common electrode line extending along the second direction and integrally formed with the first common electrode line to form a mesh structure, wherein the orthographic projection of the second common electrode line on the substrate overlaps with the orthographic projection of the data line on the substrate.

[0017] In some embodiments, the array substrate provided in the present disclosure further includes a third common electrode line extending along the second direction and integrally disposed with the first common electrode line. The third common electrode line is located between adjacent second common electrode lines, and the orthographic projection of the third common electrode line on the substrate overlaps with the orthographic projection of the second electrode of the transistor on the substrate.

[0018] In some embodiments, in the array substrate provided in the present disclosure, there are multiple third common electrode lines, some of which are integrally disposed with the first common electrode line at the winding portion, and the remaining third common electrode lines are integrally disposed with the first common electrode line between the spacer bases.

[0019] In some embodiments, in the array substrate provided in the present disclosure, the substrate includes an array of red sub-pixel areas, green sub-pixel areas and blue sub-pixel areas, wherein the orthographic projection of the second electrode of the transistor corresponding to the red sub-pixel area and the green sub-pixel area on the substrate overlaps with the orthographic projection of the third common electrode line on the substrate, and the orthographic projection of the data line corresponding to the blue sub-pixel area on the substrate overlaps with the orthographic projection of the second common electrode line on the substrate.

[0020] In some embodiments, the array substrate provided in this disclosure further includes a common electrode disposed in contact with the first common electrode line on the side of the first common electrode line near the substrate, and the common electrode has a hollow structure at the via.

[0021] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other. The array substrate is the array substrate provided in this disclosure, and the counter substrate includes a spacer. The orthographic projection of the end face of the spacer facing the array substrate on the substrate is located within the orthographic projection of the spacer base on the substrate.

[0022] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate includes a black matrix, the orthographic projection of the black matrix on the substrate covers the orthographic projection of the spacer base on the substrate, and the orthographic projection of the black matrix on the substrate covers the orthographic projection of the first common electrode line on the substrate.

[0023] On the other hand, this disclosure provides a display device, which includes the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0024] Figure 1 is a schematic diagram of the orthographic projection of the spacer base, the common electrode line, and the black matrix in the related technology;

[0025] Figure 2 is another schematic diagram of the orthographic projection of the spacer base, the common electrode line, and the black matrix in the related technology;

[0026] Figure 3 is a schematic diagram of the orthographic projection of the septum base, the common electrode line, and the black matrix provided in the embodiments of this disclosure;

[0027] Figure 4(a) is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0028] Figure 4(b) is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0029] Figure 5 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0030] Figure 6 is a schematic diagram of the cross-sectional structure along line I-II in Figure 5;

[0031] Figure 7 is a schematic diagram of the structure of the layer containing the grid lines in Figure 5;

[0032] Figure 8 is a schematic diagram of the active layer in Figure 5;

[0033] Figure 9 is a schematic diagram of the structure of the layer where the data line is located in Figure 5;

[0034] Figure 10 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 5;

[0035] Figure 11 is a schematic diagram of the structure of the layer where the first common electrode line is located in Figure 5;

[0036] Figure 12 is a schematic diagram of the structure of the layer where the vias are located in Figure 5;

[0037] Figure 13 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 5;

[0038] Figure 14 is a structural schematic diagram of the layer where the diaphragm base is located in Figure 5;

[0039] Figure 15(a) is a schematic diagram of the structure of the array substrate provided in the present disclosure during the manufacturing process;

[0040] Figure 15(b) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0041] Figure 15(c) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0042] Figure 15(d) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0043] Figure 15(e) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0044] Figure 15(f) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0045] Figure 15(g) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0046] Figure 15(h) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0047] Figure 15(i) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0048] Figure 15(j) is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0049] Figure 16 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0050] Figure 17 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0052] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0053] In the display area (AA) design of a TFT-LCD panel, to ensure a flat surface beneath the spacer base on the array substrate side, the common electrode line needs to bypass the spacer base. As shown in Figure 1, because the common electrode line CL needs to bypass the spacer base PS', if the linewidth of the common electrode line CL remains unchanged, the black matrix BM on the substrate side needs to wrap around the common electrode line CL more, which will lead to a decrease in pixel aperture ratio and transmittance. As shown in Figure 2, if the aperture ratio is not reduced and the black matrix BM is not enlarged as much as possible, the linewidth of the common electrode line CL needs to be reduced, but the uniformity of the common voltage (com) will deteriorate, affecting display quality.

[0054] To at least improve the aforementioned technical problems, this disclosure provides an array substrate. Figure 3 is a schematic diagram of the orthographic projection of the spacer base, common electrode line, and black matrix provided in this disclosure embodiment. Figure 4(a) is a schematic diagram of one structure of the array substrate provided in this disclosure embodiment. Figure 4(b) is a schematic diagram of another structure of the array substrate provided in this disclosure embodiment. Figure 5 is a schematic diagram of yet another structure of the array substrate provided in this disclosure embodiment. As shown in Figures 3 to 5, the array substrate provided in this disclosure embodiment includes:

[0055] The substrate 101 may include a display area (AA) and a non-display area located on at least one side of the display area (AA), for example, the non-display area surrounds the display area (AA) around its perimeter. Optionally, the display area (AA) includes an array of red sub-pixel areas R, green sub-pixel areas G, blue sub-pixel areas B, etc., and the substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or other materials.

[0056] The first common electrode line 102 extends along the first direction X on the substrate 101. The first common electrode line 102 includes a winding portion 1021. In some embodiments, the material of the first common electrode line 102 includes at least one metal material such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), gold (Au), and silver (Ag), and / or at least one alloy material such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb). The first common electrode line 102 can be a single-layer structure or a multi-layer composite structure. For example, the first common electrode line 103 is a single-layer structure composed of a copper metal layer.

[0057] The spacer base 103 supports the spacers PS on the opposing substrate. The spacer base 103 may include an integrally formed first part 1031 and a second part 1032. The orthographic projection of the first part 1031 on the substrate 101 is arranged side by side with the orthographic projection of the winding part 1021 on the substrate 101. In other words, the winding part 1021 is used to avoid the first part 1031. In some embodiments, the first dimension h1 of the first part 1031 in the second direction Y is larger than the second dimension h2 of the second part 1032 in the second direction Y. The second direction Y intersects (e.g., is perpendicular to) the first direction X. In some embodiments, the material of the spacer base 103 may be at least one organic insulating material such as polyacrylic resin, polyepoxyacrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., without limitation.

[0058] Comparing FIG3 of the present disclosure embodiment with FIG1 and FIG2 of the related art, it can be seen that the present disclosure sets the first dimension h1 of the first part 1031 in the second direction Y of the spacer base 103 to be larger than the second dimension h2 of the second part 1032 in the second direction Y. This is equivalent to narrowing at least one of the left and right ends of the spacer base 103. This setting can, on the one hand, leave more space for designing the first common electrode line 102, so that the line width of the first common electrode line 102 is reduced less or even not reduced at all, thereby improving the uniformity of the common voltage, improving or even avoiding the greenish problem of the screen, and ensuring display quality. On the other hand, the black matrix BM used to block the spacer base 103 can be reduced, which is conducive to increasing the aperture ratio and thus improving the transmittance. Therefore, the present disclosure can improve the uniformity of the common voltage while improving the pixel aperture ratio.

[0059] In some instances, in the array substrate provided in the embodiments of this disclosure, in order to better ensure the uniformity of the common voltage, the linewidth of the first common electrode line 102 may be set to be approximately uniform. It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "approximately uniform" may be completely equivalent or may have some deviation. Therefore, as long as the relationship of "approximately uniform" between the above features meets the allowable error (e.g., fluctuation of up to 10%), it is within the protection scope of this disclosure.

[0060] In some embodiments, as shown in FIG3, in the array substrate provided in the present disclosure, the orthographic projection of the winding portion 1021 on the substrate 101 and the orthographic projection of the first portion 1031 on the substrate 101 have a first distance d1, and the orthographic projection of the first common electrode line 102 on the substrate 101 and the orthographic projection of the second portion 1032 on the substrate 101 have a second distance d2. The first distance d1 is approximately equal to the second distance d2, so that the first common electrode line 102 can be wired along the edge of the spacer base 103, ensuring that the first distance d1 and the second distance d2 between the first common electrode line 102 and the spacer base 103 are small, thereby reducing the black matrix BM used to block the first common electrode line 102, the spacer base 103, and the gap between them, thereby increasing the aperture ratio and improving the transmittance.

[0061] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately equal to" may be completely equal or may have some deviation (e.g., ±5% deviation). Therefore, as long as the relationship of "approximately equal to" between related features satisfies the allowable error, it is within the protection scope of this disclosure.

[0062] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG3, the first center O1 of the first part 1031 in the second direction Y can be arranged approximately collinearly with the second center O2 of the second part 1032 in the second direction Y. That is, the spacer base 103 has a symmetrical pattern in the first direction X, with a symmetry axis MN extending along the first direction X, and the first center O1 and the second center O2 are located on the symmetry axis MN. In this way, both sides of the second part 1032 extending in the first direction X are recessed relative to the first part 1031, ensuring that the spacer base 103 occupies a small space. Correspondingly, the black matrix BM that blocks the spacer base 103 is reduced, the aperture ratio is increased, and the transmittance is improved.

[0063] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately collinear" may be exactly collinear, or there may be some deviation (e.g., a deviation of ±1μm). Therefore, as long as the "approximately collinear" relationship between related features satisfies the allowable error, it falls within the protection scope of this disclosure.

[0064] In some embodiments, the larger first portion 1031 is used to support the spacer PS of the opposing substrate. If the spacer PS may slide under pressure, or if there is a slight misalignment between the spacer PS and the first portion 1031, the smaller second portion 1032 can provide auxiliary support for the spacer PS. To ensure support effectiveness, the second portion 1032 can be recessed by 1 μm to 3 μm on one side relative to the first portion 1031 in the second direction Y, which is equivalent to (h2-h1) / 2 being 1 μm to 3 μm, for example, 2 μm.

[0065] In some embodiments, in the array substrate provided in the present disclosure, the second part 1032 may be located on at least one side of the first part 1031 in the first direction X. When the second part 1032 is located on both sides of the first part 1031 in the first direction X, the spacer base 103 is narrowed at both ends, so that the spacer base 103 occupies less space overall. Correspondingly, the black matrix BM blocking the spacer base 103 is reduced, the aperture ratio is higher, and the transmittance is higher. Therefore, the present disclosure takes the example of the second part 1032 being located on both sides of the first part 1031 in the first direction X as an example for illustration, as shown in FIG3.

[0066] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG4(a), FIG5, FIG6 and FIG13, may further include: a transistor 104, a pixel electrode 105, and an insulating layer 106 located between the layer where the pixel electrode 105 is located and the layer where the first electrode D of the transistor 104 is located. The pixel electrode 105 may be a slit electrode or a block electrode, and the insulating layer 106 includes a via V. The first electrode D of the transistor 104 is electrically connected to the pixel electrode 105 through the via V. At least a portion of the orthogonal projection of the via V on the substrate 101 is located within the orthogonal projection of the second part 1032 on the substrate 101, so as to fill the via V with the second part 1032, thereby preventing the spacer PS of the opposing substrate from falling into the via V when the spacer base 103 is aligned with the spacer base 103.

[0067] In some embodiments, as shown in Figures 4(a), 5, and 6, the insulating layer 106 may include a first insulating layer 1061, a second insulating layer 1062, a third insulating layer 1063, and a fourth insulating layer 1064. The materials of the first insulating layer 1061, the third insulating layer 1063, and the fourth insulating layer 1064 may include at least one inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), and tantalum oxide (TaOx), and may be single-layer, multi-layer, or composite layers. The material of the second insulating layer 1062 may be at least one organic insulating material such as polyacrylic acid resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin. The via V can be divided into a first sub-via V1 that penetrates the first insulating layer 1061 and the second insulating layer 1062, and a second sub-via V2 that penetrates the third insulating layer 1063 and the fourth insulating layer 1064. The first sub-via V1 and the second sub-via V2 are vertically connected, and the first sub-via V1 is larger than the second sub-via V2.

[0068] In some embodiments, the pixel electrode 105 is made of at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO). The data line 107 is made of at least one metallic material such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), gold (Au), and silver (Ag), and / or at least one alloy material such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb). The data line 107 can be a single-layer structure or a multi-layer composite structure, for example, the data line 107 is a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0069] The active layer AC of transistor 104 (as shown in Figure 8) can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. This disclosure applies to transistors manufactured using oxide technology, silicon technology, and organic technology, but is not limited thereto. The first electrode D and the second electrode S of transistor 104 can be on the same layer and made of the same material as the data line 107. The gate G of transistor 104 can be made of at least one metal material such as molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), gold (Au), and silver (Ag), and / or at least one alloy material such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb). The gate G can be a single-layer structure or a multi-layer composite structure; for example, the gate G can be a single-layer structure composed of a copper metal layer.

[0070] In some embodiments, the array substrate provided in this disclosure, as shown in FIG5, 9, and 11, may further include a data line 107 extending along the second direction Y and integrally formed with the second electrode S of the transistor 104, and a second common electrode line 108 extending along the second direction Y and integrally formed with the first common electrode line 102 to form a mesh structure, so as to improve the uniformity of the common voltage through the mesh structure formed by the first common electrode line 102 and the second common electrode line 108. Optionally, the orthographic projection of the second common electrode line 108 on the substrate 101 overlaps with the orthographic projection of the data line 107 on the substrate 101. In some embodiments, the orthographic projection of the second common electrode line 108 on the substrate 101 and the orthographic projection of the data line 107 on the substrate 101 substantially coincide, so that the black matrix BM itself used to block the data line 107 can simultaneously block the second common electrode line 108, avoiding a reduction in aperture ratio and transmittance.

[0071] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±1μm). Therefore, as long as the relationship of "approximately coincident" between related features satisfies the allowable error, it falls within the protection scope of this disclosure.

[0072] In some embodiments, the array substrate provided in this disclosure, as shown in FIG4(a), 5, 9, and 11, may further include a third common electrode line 109 extending along the second direction Y and integrally disposed with the first common electrode line 102. The third common electrode line 109 is located between adjacent second common electrode lines 108. The orthographic projection of the third common electrode line 109 on the substrate 101 overlaps with the orthographic projection of the second electrode S of the transistor 104 on the substrate 101, so as to further improve the uniformity of the common voltage through the third common electrode line 109. Optionally, the orthographic projection of the third common electrode line 109 on the substrate 101 and the orthographic projection of the second electrode S of the transistor 104 on the substrate 101 substantially coincide, so as to utilize the black matrix BM itself used to block the second electrode S of the transistor 104 to simultaneously block the third common electrode line 109, avoiding a reduction in aperture ratio and transmittance.

[0073] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG4(a), FIG4(b), FIG5, FIG11 and FIG14, there are multiple third common electrode lines 109. Some of the third common electrode lines 109 are integrally formed with the first common electrode line 102 at the winding portion 1021, and the remaining third common electrode lines 109 are integrally formed with the first common electrode line 102 between the spacer bases 103. Since the spacer base 103 is relatively short in the second direction Y, the overlap area between the third common electrode line 109 integrally formed with the first common electrode line 102 at the winding portion 1021 and the spacer base 103 is small. Therefore, even if the third common electrode lines 109 and the spacer base 103 overlap, their impact on the flatness of the terrain below the spacer base 103 is small. The third common electrode line 109 located in the gap of the septum base 103 does not overlap with the septum base 103, so it will not affect the flatness of the terrain of the site below the septum base 103.

[0074] In some embodiments, as shown in FIG4(b), the orthographic projection of a portion of the second common electrode line 108 on the substrate 101 may overlap with the orthographic projection of the spacer base 103 on the substrate 101. The line width of the second common electrode line 108 at the point of overlap with the spacer base 103 is narrowed. Meanwhile, since the spacer base 103 is shorter in the second direction Y, the second common electrode line 108 has a smaller impact on the flatness of the terrain below the spacer base 103.

[0075] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG4(a), FIG5, FIG7, FIG9 and FIG11, the orthographic projection of the second electrode S of the transistor 104 corresponding to the red sub-pixel region R and the green sub-pixel region G on the substrate 101 overlaps with the orthographic projection of the third common electrode line 109 on the substrate 101, and the orthographic projection of the data line 107 corresponding to the blue sub-pixel region B on the substrate 101 overlaps with the orthographic projection of the second common electrode line 108 on the substrate 101. In this disclosure, the data line 107 is partially multiplexed as the second electrode S of the transistor 104. The length of the third common electrode line 109 is less than the length of the second common electrode line 108, such that the coupling capacitance between the third common electrode line 109 and the data line 107 is less than the coupling capacitance between the second common electrode line 108 and the data line 107. Thus, the common voltage has a certain impact on the data voltage of the blue sub-pixel area B. However, given that the pixel brightness of the blue sub-pixel area B is the lowest among the red sub-pixel area R, the green sub-pixel area G, and the blue sub-pixel area B, it will not affect the display effect overall.

[0076] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 5, 6, and 10 to 12, may further include a common electrode 110 disposed in contact with the first common electrode line 102 on the side near the substrate 101. The common electrode 110 has a hollow structure K at the via V to facilitate electrical connection between the pixel electrode 105 and the first electrode D of the transistor 104. In some embodiments, the material of the common electrode 110 includes, but is not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO). Since the layer containing the first common electrode line 102 can be made of metals such as copper (Cu), and Cu has a much lower resistance than ITO, the common electrode 110 is electrically connected to the first common electrode line 102, the second common electrode line 108, and the third common electrode line 109, which is beneficial for better uniformity of the common voltage within the display area AA.

[0077] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG5 and FIG7, may further include a gate line 111, which may be integrally disposed with the gate G. Other essential components of the array substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0078] This disclosure also provides a method for manufacturing the above-mentioned array substrate, which may include the following steps:

[0079] The first step, as shown in Figure 15(a), is to provide a substrate 101, and to form the gate G of the transistor 104 in the display area AA of the substrate 101 and to form the first trace 112 in the non-display area BB.

[0080] The second step, as shown in Figure 15(b), involves sequentially forming a fifth insulating layer 113 and a sixth insulating layer 114 on the layer containing the gate G, and then patterning the active layer AC of the transistor 104 on the sixth insulating layer 114.

[0081] The third step, as shown in Figure 15(c), is to form a first through hole Vth1 with its orthographic projection located within the first trace 112 for the fifth insulating layer 113 and the sixth insulating layer 114.

[0082] The fourth step, as shown in Figure 15(d), involves forming a first electrode D and a second electrode S that are in contact with the active layer AC on the active layer AC, and simultaneously forming a second trace 115 that is electrically connected to the first trace 112 at the first via V'.

[0083] Fifth step, as shown in Figure 15(e), a fourth insulating layer 1064, a third insulating layer 1063 and a second insulating layer 1062 are formed on the layer where the first electrode D is located, and a second through hole Vth2 and a third through hole Vth3 are formed through the second insulating layer 1062, wherein the second through hole Vth2 is located within the range of the first electrode D and the third through hole Vth3 is located within the range of the second trace 115.

[0084] The sixth step, as shown in Figure 15(f), is to form a conductive layer 110' on the second insulating layer 1062 for fabricating the common electrode 110, and to form a third common electrode line 109, a second common electrode line 108, and a first common electrode line 102 (not shown in Figure 15(f)) on the conductive layer 110'.

[0085] The seventh step, as shown in Figure 15(g), involves patterning multiple hollow structures K on the conductive layer 110'. The conductive layer 110' with the hollow structure K is the common electrode 110.

[0086] Step 8, as shown in Figure 15(h), forms a first insulating layer 1061 on the layer where the third common electrode line 109 is located, and patterns the first insulating layer 1061, the third insulating layer 1063, and the fourth insulating layer 1064 at the second through hole Vth2 and the third through hole Vth3 to form through holes V and connecting holes V', and simultaneously forms a fourth through hole Vth4 located within the range of the second common electrode line 108.

[0087] In the ninth step, as shown in Figure 15(i), a pixel electrode 105 and a transition electrode 116 are patterned on the first insulating layer 1061. The pixel electrode 105 is electrically connected to the first electrode D of the transistor 104 via a via V. The transition electrode 116 is electrically connected to the second common electrode line 108 via a fourth via Vth4 and to the second trace 115 via a connection hole V'. The first trace 112 can receive the common voltage of the external circuit and transmit the common voltage signal sequentially to the common electrode 110 via the second trace 115, the transition electrode 116, and the second common electrode line 108.

[0088] Step 10, as shown in Figure 15(j), forms a spacer base 103 on the layer where the pixel electrode 105 is located.

[0089] In some embodiments, after forming the spacer base 103, an alignment layer (PI) or other film layer known to those skilled in the art may also be formed, which will not be specifically described in this disclosure.

[0090] It should be noted that in the fabrication method provided in the embodiments of this disclosure, the patterning process involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and is not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0091] Based on the same inventive concept, this disclosure provides a display panel, as shown in Figures 3 and 16, including the array substrate 001 provided in this disclosure and a counter substrate 002 opposite to the array substrate 001; wherein, the counter substrate 002 includes spacers PS, and the orthographic projection of the end face of the spacers PS facing the array substrate 001 onto the substrate 101 lies within the orthographic projection of the spacer base 103 onto the substrate 101. Since the principle by which this display panel solves the problem is similar to that of the array substrate described above, the implementation of the display panel provided in this disclosure can refer to the implementation of the array substrate provided in this disclosure, and repeated details will not be described again.

[0092] In some embodiments, in the display panel provided in the present disclosure, as shown in FIG3 and FIG16, the opposing substrate 002 includes a black matrix BM, the orthographic projection of the black matrix BM on the substrate 101 covers the orthographic projection of the spacer base 103 on the substrate 101, and the orthographic projection of the black matrix BM on the substrate 101 covers the orthographic projection of the first common electrode line 102 on the substrate 101.

[0093] In some embodiments, as shown in FIG16, in the display panel provided in the embodiments of this disclosure, a liquid crystal layer 003 may be disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0094] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG17, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0095] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0096] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0097] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0098] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; A first common electrode line extends along a first direction on the substrate, and the first common electrode line includes a winding portion; The spacer base includes an integrally formed first part and a second part. The orthographic projection of the first part on the substrate and the orthographic projection of the winding part on the substrate are arranged side by side. The first dimension of the first part in a second direction is larger than the second dimension of the second part in the second direction. The second direction intersects with the first direction.

2. The array substrate as claimed in claim 1, wherein, The line width of the first common electrode line is approximately uniform.

3. The array substrate as described in claim 1 or 2, wherein, There is a first distance between the orthographic projection of the winding portion on the substrate and the orthographic projection of the first portion on the substrate, and there is a second distance between the orthographic projection of the first common electrode line on the substrate and the orthographic projection of the second portion on the substrate, wherein the first distance is approximately equal to the second distance.

4. The array substrate according to any one of claims 1 to 3, wherein, The first center of the first part in the second direction and the second center of the second part in the second direction are arranged approximately collinearly.

5. The array substrate according to any one of claims 1 to 4, wherein, In the second direction, the second part is recessed by 1 μm to 3 μm on one side relative to the first part.

6. The array substrate according to any one of claims 1 to 5, wherein, The second part is located on both sides of the first part in the first direction.

7. The array substrate according to any one of claims 1 to 6, wherein, Also includes: A transistor, a pixel electrode, and an insulating layer located between the layer containing the pixel electrode and the layer containing the first electrode of the transistor, the insulating layer including vias; The first electrode of the transistor is electrically connected to the pixel electrode through the via, at least partially. The orthogonal projection of the via on the substrate is located within the orthogonal projection of the second part on the substrate.

8. The array substrate as claimed in claim 7, wherein, It also includes a data line extending along the second direction and integrally disposed with the second electrode of the transistor, and a second common electrode line extending along the second direction and integrally formed with the first common electrode line to form a mesh structure, wherein the orthographic projection of the second common electrode line on the substrate overlaps with the orthographic projection of the data line on the substrate.

9. The array substrate as claimed in claim 8, wherein, It also includes a third common electrode line extending along the second direction and integrally disposed with the first common electrode line. The third common electrode line is located between adjacent second common electrode lines, and the orthographic projection of the third common electrode line on the substrate overlaps with the orthographic projection of the second electrode of the transistor on the substrate.

10. The array substrate as claimed in claim 9, wherein, There are multiple third common electrode lines. Some of the third common electrode lines are integrally formed with the first common electrode lines at the winding portion, while the remaining third common electrode lines are integrally formed with the first common electrode lines between the spacer bases.

11. The array substrate as claimed in claim 9 or 10, wherein, The substrate includes an array of red sub-pixel areas, green sub-pixel areas, and blue sub-pixel areas. The orthographic projections of the second electrodes of the transistors corresponding to the red and green sub-pixel areas on the substrate overlap with the orthographic projections of the third common electrode lines on the substrate. The orthographic projections of the data lines corresponding to the blue sub-pixel areas on the substrate overlap with the orthographic projections of the second common electrode lines on the substrate.

12. The array substrate according to any one of claims 7 to 11, wherein, It also includes a common electrode disposed on the side of the first common electrode line that is close to the substrate and in contact with the first common electrode line, wherein the common electrode has a hollow structure at the via.

13. A display panel, wherein, The array includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 12, and the counter substrate includes a spacer, wherein the orthographic projection of the end face of the spacer facing the array substrate on the substrate is located within the orthographic projection of the spacer base on the substrate.

14. The display panel as claimed in claim 13, wherein, The opposing substrate includes a black matrix, the orthographic projection of which on the substrate covers the orthographic projection of the spacer base on the substrate, and the orthographic projection of which on the substrate covers the orthographic projection of the first common electrode line on the substrate.

15. A display device, wherein, It includes the display panel as described in claim 13 or 14, and a backlight module located on the light-incident side of the display panel.

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