Display substrate, manufacturing method therefor and display apparatus

Abstract

Provided in the present disclosure are a display substrate, a manufacturing method therefor and a display apparatus. The display substrate comprises: gate lines and data lines, which define a plurality of pixel regions; pixel electrodes and thin-film transistors, the source of each thin-film transistor being connected to the pixel electrode in a same pixel region, the gate thereof being connected to a corresponding gate line and the drain thereof being connected to a corresponding data line; and a source compensation portion connected to the source, a gate compensation portion connected to the gate lines, and a semiconductor layer compensation portion spaced apart from a semiconductor layer. The sources partially overlap the gates and the semiconductor layer, so as to form a first gate-source parasitic capacitance. The source compensation portion partially overlaps the semiconductor layer compensation portion and the gate compensation portion, so as to form a gate-source compensation parasitic capacitance. The sum of the first gate-source parasitic capacitance and the gate-source compensation parasitic capacitance is an effective gate-source parasitic capacitance Cgs; and a difference between gate-source effective parasitic capacitances Cgs in different pixel regions is smaller than or equal to a threshold. The display substrate, the manufacturing method therefor and the display apparatus improve the Cgs stability.

Description

A display substrate, its manufacturing method, and a display device. Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] As display technology continues to advance, the requirements for display panel display effects are also gradually increasing. Existing display substrates can typically control the voltage of pixel electrodes through data signals, thereby changing the luminous brightness of the pixels corresponding to those electrodes.

[0003] In related technologies, the capacitance formed between the gate and source of a thin film transistor (TFT) is called the gate-source parasitic capacitance, or Cgs for short. It is the decisive factor in the pixel potential being pulled down by the gate potential.

[0004] In TFT manufacturing, the gate metal layer and source / drain metal layers are prone to overlap. TFT design cannot guarantee that the gate-source parasitic capacitance Cgs remains constant. The larger the gate-source parasitic capacitance Cgs, the larger the pixel's pull-down potential (ΔVp), resulting in greater grayscale differences between pixels with the same data signal voltage, leading to poor display quality. Therefore, a scheme is needed to compensate for the gate-source parasitic capacitance Cgs to ensure its stability.

[0005] Summary of the Invention

[0006] This disclosure provides a display substrate and its manufacturing method, as well as a display device, which can ensure the stability of the gate-source parasitic capacitance Cgs, improve the stability of the display image, and enhance the display effect of the display substrate.

[0007] The technical solutions provided in this disclosure are as follows:

[0008] In a first aspect, embodiments of this disclosure provide a display substrate, comprising:

[0009] Substrate;

[0010] Multiple gate lines and multiple data lines, wherein the data lines intersect with the gate lines to define multiple pixel regions;

[0011] A plurality of pixel electrodes and a plurality of thin-film transistors are provided. The pixel region includes the pixel electrodes and the thin-film transistors. Each thin-film transistor includes a gate, a source, a drain, and a semiconductor layer. The source is connected to the pixel electrode within the same pixel region, the gate is connected to a corresponding gate line, and the drain of the thin-film transistor is connected to a corresponding data line.

[0012] A source compensation section, a gate compensation section, and a semiconductor layer compensation section are provided in the pixel region. The source compensation section is connected to the source, the gate compensation section is connected to the gate line and is arranged at a distance from the gate, and the semiconductor layer compensation section is arranged at a distance from the semiconductor layer.

[0013] In the same pixel region, the source electrode, the gate electrode, and the orthographic projection portion of the semiconductor layer on the substrate overlap to form a first gate-source parasitic capacitance; the source electrode compensation portion, the semiconductor layer compensation portion, and the gate compensation portion on the substrate overlap to form a gate-source compensation parasitic capacitance; in the same pixel region, the sum of the first gate-source parasitic capacitance and the gate-source compensation parasitic capacitance is the effective gate-source parasitic capacitance Cgs; the difference between the effective gate-source parasitic capacitances Cgs of different pixel regions is less than or equal to a threshold.

[0014] For example, the gate line extends along a first direction, and the data line extends along a second direction; wherein each of the data lines is connected to at least two pixel regions located on opposite sides of the data line in the first direction via at least two thin-film transistors, to form a Z-pixel arrangement architecture.

[0015] For example, in each pixel region, the source electrode extends along the first direction, the source electrode compensation portion is formed by the source electrode extending along the first direction away from the corresponding data line, the gate electrode compensation portion is formed by the corresponding gate line protruding and extending towards the pixel electrode, and the gate electrode compensation portion and the gate electrode are spaced apart in the first direction, and the semiconductor layer compensation portion and the semiconductor layer are spaced apart in the first direction.

[0016] For example, the thin-film transistor is a U-shaped thin-film transistor, the drain is U-shaped, the U-shaped opening of the drain is arranged along the first direction, and the orthogonal projection of the source on the substrate is located in the U-shaped opening of the drain; wherein, between two pixel regions connected to the same data line and arranged adjacently in the second direction, the U-shaped opening of the drain is arranged in opposite directions.

[0017] For example, in each pixel region, the semiconductor layer compensation portion extends a first predetermined width in the first direction, such that the overlapping portion of the semiconductor layer compensation portion and the source compensation portion includes at least a first region and a second region in the first direction, wherein the first region is located on the side of the second region closer to the source, wherein the first region overlaps with the source compensation portion, and the second region does not overlap with the source compensation portion.

[0018] For example, the source compensation portion includes a first source compensation pattern in the shape of an elongated strip extending along the first direction, and the semiconductor layer compensation portion includes a first semiconductor compensation pattern in the shape of a block. The first source compensation pattern overlaps with the first semiconductor compensation pattern, and the first semiconductor compensation pattern includes a second region in the first direction that does not overlap with the first source compensation pattern.

[0019] For example, in each pixel region, the source compensation section includes a first source compensation pattern, a second source compensation pattern, and a third source compensation pattern. The first source compensation pattern is formed by the source extending away from the corresponding data line along the first direction. The second source compensation pattern and the third source compensation pattern are formed by the first source compensation pattern extending in opposite directions along the second direction.

[0020] The semiconductor layer compensation section includes a first semiconductor compensation pattern, a second semiconductor compensation pattern, and a third semiconductor compensation pattern. The second semiconductor compensation pattern and the third semiconductor compensation pattern are respectively located on opposite sides of the first semiconductor compensation pattern along the second direction, and are arranged at intervals from the first semiconductor compensation pattern.

[0021] The first source compensation pattern partially overlaps with the first semiconductor compensation pattern, the second source compensation pattern partially overlaps with the second semiconductor compensation pattern, and the third source compensation pattern partially overlaps with the third semiconductor compensation pattern.

[0022] For example, in each pixel region, the second semiconductor compensation pattern extends a second predetermined width in the second direction, such that the overlapping portion of the second semiconductor compensation pattern and the second source compensation pattern includes at least a third region and a fourth region in the second direction, wherein the third region is located on the side of the second region closer to the first source compensation pattern, wherein the third region overlaps with the second source compensation pattern, and the fourth region does not overlap with the second source compensation pattern.

[0023] For example, in each pixel region, the third semiconductor compensation pattern extends a third predetermined width in the second direction, such that the overlapping portion of the third semiconductor compensation pattern and the third source compensation pattern includes at least a fifth region and a sixth region in the second direction, wherein the fifth region is located on the side of the sixth region closer to the first source compensation pattern, wherein the fifth region overlaps with the third source compensation pattern, and the sixth region does not overlap with the third source compensation pattern.

[0024] For example, the first source compensation pattern has the same linewidth as the source.

[0025] For example, the source electrode and the source electrode compensation portion are arranged on the same layer and with the same material; the gate electrode and the gate electrode compensation portion are arranged on the same layer and with the same material; the semiconductor layer and the semiconductor layer compensation portion are arranged on the same layer and with the same material.

[0026] For example, two gate lines are provided between two adjacent rows of pixel regions arranged in the second direction, wherein the two gate lines are respectively connected to the gate and the gate compensation portion in the two rows of pixel regions.

[0027] Secondly, embodiments of this disclosure also provide a method for manufacturing a display substrate, used to manufacture the display substrate as described above, the method comprising:

[0028] Provide substrates;

[0029] Multiple gate lines, multiple data lines, multiple pixel electrodes, multiple thin-film transistors, source compensation portions, gate compensation portions, and semiconductor layer compensation portions are formed on the substrate. The data lines intersect with the gate lines to define multiple pixel regions. Each pixel region includes the pixel electrode and the thin-film transistor. The thin-film transistor includes a gate, a source, a drain, and a semiconductor layer. The source is connected to the pixel electrode in the same pixel region, the gate is connected to the corresponding gate line, and the drain of the thin-film transistor is connected to the corresponding data line. The source compensation portion is connected to the source, the gate compensation portion is connected to the gate line and spaced apart from the gate, and the semiconductor layer compensation portion is spaced apart from the semiconductor layer. In the same pixel region, the source, the gate, and the orthogonal projection portion of the semiconductor layer on the substrate overlap to form a first gate-source parasitic capacitance. The source compensation portion, the orthogonal projection portion of the semiconductor layer compensation portion, and the gate compensation portion on the substrate overlap to form a gate-source compensation parasitic capacitance. Within the same pixel region, the sum of the first gate-source parasitic capacitance and the gate-source compensated parasitic capacitance is the effective gate-source parasitic capacitance Cgs; the difference between the effective gate-source parasitic capacitance Cgs of different pixel regions is less than or equal to a threshold.

[0030] For example, in the method, the source electrode and the source electrode compensation portion are formed using the same patterning process; the gate electrode and the gate compensation portion are formed using the same patterning process; and the semiconductor layer and the semiconductor layer compensation portion are formed using the same patterning process.

[0031] Thirdly, embodiments of this disclosure also provide a display device, which includes the display substrate described above.

[0032] The beneficial effects of the embodiments disclosed herein are as follows:

[0033] The above solution compensates for the first gate-source parasitic capacitance formed by the gate and source of the thin-film transistor in each pixel region by forming a pattern of source compensation section, gate compensation section, and semiconductor layer compensation section within the pixel region. Thus, a semiconductor layer compensation section is also present at the overlapping position of the source compensation section and gate compensation section used for capacitance compensation, and a semiconductor layer is present at the overlapping position of the source and gate of the thin-film transistor. Therefore, the gate-source compensation parasitic capacitance formed between the source compensation section and the gate compensation section can be controlled by adjusting the distance between the source compensation section and the gate compensation section. The overlapping area between the source compensation section and the semiconductor layer compensation section is used to accurately and effectively compensate for the first gate-source parasitic capacitance in the pixel area, so that the difference in effective gate-source parasitic capacitance in different pixel areas is less than or equal to the threshold, that is, the effective gate-source parasitic capacitance in different pixel areas is approximately equal. This can reduce the phenomenon of excessive difference in effective gate-source parasitic capacitance Cgs between different pixel areas due to the overlap and offset of the gate and source of the thin film transistor, so as to ensure the stability of the effective gate-source parasitic capacitance Cgs and improve the stability of the display screen. Attached Figure Description

[0034] Figure 1 shows a schematic diagram of the pixel architecture of a display substrate provided in an embodiment of this disclosure;

[0035] Figure 2 shows one of the partial structural schematic diagrams at the dashed box Q in Figure 1;

[0036] Figure 3 shows a cross-sectional view of the dashed box E1 in Figure 2;

[0037] Figure 4 shows a cross-sectional view of the dashed box F1 in Figure 2;

[0038] Figure 5 shows a cross-sectional view of the dashed box E2 in Figure 2;

[0039] Figure 6 shows a schematic diagram of the cross section at point F2 (dashed box) in Figure 2;

[0040] Figure 7 shows the second partial structural schematic diagram of the area at the dashed box Q in Figure 1. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0043] Before providing a detailed description of the embodiments of this disclosure, the related technologies are described below:

[0044] As people's living standards improve and their understanding of display devices increases, they are placing higher and higher demands on the display performance of these devices. For example, they require display devices to have high resolution, high contrast, and high response speed. In addition, people are also demanding higher standards for the parameters that characterize the image quality of display devices (e.g., image retention, mullioning, light leakage).

[0045] The display substrate includes multiple pixel areas. Each pixel area can be driven by a thin film transistor (TFT, also known as a thin film field-effect transistor) to control the grayscale of each pixel area, thereby achieving high-speed, high-brightness, and high-contrast display of information on the display screen.

[0046] Normally, the pixel structure within a pixel area inevitably exhibits voltage transitions due to parasitic capacitance and the change in gate voltage from high to low. These voltage transitions directly affect the display quality of the display device. The theoretical formula for the voltage transition ΔVp is as follows: ΔVp=Cgs*(Vgh-Vgl) / (Cgs+Cst+Clc);

[0047] Where ΔVp is the switching voltage, Vgh is the gate high voltage, Vgl is the gate low voltage, Cst is the storage capacitance, and Clc is the liquid crystal capacitance. Typically, Cgs is the capacitance formed by the gate, source, and the gate insulating layer between them, i.e., the gate-source parasitic capacitance; Cst is the storage capacitance formed by the pixel electrode, common electrode, and the insulating layer between them.

[0048] Significant differences in the gate-source parasitic capacitance Cgs can lead to large jump voltages ΔVp. The gate and gate line are on the same layer, as are the source and drain. However, due to deposition and exposure variations, different fabrication processes can result in different positional offsets between the gate, gate line, source, and drain in displays fabricated on different motherboards or in different areas of the same motherboard. This means that process differences can cause variations in the relative positions of the gate and source in different displays, resulting in an overlap offset. Consequently, the overlap area of ​​the capacitor electrodes constituting the gate-source parasitic capacitance Cgs changes.

[0049] However, currently, because the debugging circuit is fixed, it can only provide a fixed common voltage Vcom. For the same debugging process, it is difficult to provide different appropriate Vcom for different displays. Therefore, when testing multiple displays simultaneously and setting the common voltage, the common voltage adjusted by the debugging circuit is the same for different displays. This results in mass-produced products with different gate-source parasitic capacitances Cgs, leading to different switching voltages ΔVp, which in turn causes grayscale differences. The larger the gate-source parasitic capacitance Cgs, the larger the switching voltage (ΔVp) that pulls down the pixel. Therefore, the grayscale difference between pixels with the same data signal voltage is also greater, resulting in screen flicker or uneven grayscale, affecting display quality. Therefore, it is necessary to design a scheme that can compensate for the gate-source parasitic capacitance Cgs to ensure its stability.

[0050] The applicant has discovered that the stability of the gate-source parasitic capacitance Cgs can be improved by compensating for it within the pixel region. However, if only source compensation patterns and gate compensation patterns are set within the pixel region, there is no semiconductor layer at the overlap of the source and gate compensation patterns. In contrast, a semiconductor layer exists at the overlap of the source and gate of the thin-film transistor. Therefore, if only source and gate compensation patterns are set, and capacitance compensation is achieved by controlling the overlap area of ​​the source and gate compensation patterns, the gate-source parasitic capacitance Cgs cannot be accurately and effectively compensated. The capacitance compensation effect is poor, and the stability problem of the gate-source parasitic capacitance Cgs still exists.

[0051] Therefore, in order to solve the above problems, the present disclosure provides a display substrate and its manufacturing method and display device, which can ensure the stability of the gate-source parasitic capacitance Cgs, improve the stability of the display screen, and enhance the display effect of the display substrate.

[0052] As shown in Figures 1 and 2, the display substrate provided in this embodiment includes:

[0053] Substrate 100;

[0054] Multiple gate lines 110 and multiple data lines 120 are disposed on the substrate 100, and the data lines 120 intersect with the gate lines 110 to define multiple pixel regions P;

[0055] A plurality of pixel electrodes 200 and a plurality of thin-film transistors 300 are disposed on the substrate 100. The pixel region P includes the pixel electrodes 200 and the thin-film transistors 300. The thin-film transistors 300 include a gate 301, a source 302, a drain 303 and a semiconductor layer 304. The source 302 is connected to the pixel electrode 200 in the same pixel region P. The gate 301 is connected to the corresponding gate line 110. The drain 303 of the thin-film transistors 300 is connected to the corresponding data line 120.

[0056] A source compensation part 500, a gate compensation part 600, and a semiconductor layer compensation part 700 are provided in the pixel region P. The source compensation part 500 is connected to the source 302, the gate compensation part 600 is connected to the gate line 110 and is arranged at a distance from the gate 301, and the semiconductor layer compensation part 700 is arranged at a distance from the semiconductor layer 304.

[0057] In the same pixel region P, the source electrode 302, the gate electrode 301, and the semiconductor layer 304 overlap on the orthogonal projection portion of the substrate 100 to form a first gate-source parasitic capacitance.

[0058] The source compensation portion 500 overlaps with the semiconductor layer compensation portion 700 and the gate compensation portion 600 on the orthogonal projection portion of the substrate 100 to form gate-source compensation parasitic capacitance.

[0059] In the same pixel region P, the sum of the first gate-source parasitic capacitance and the gate-source compensated parasitic capacitance is the effective gate-source parasitic capacitance Cgs.

[0060] The difference between the effective parasitic gate-source capacitance Cgs of different pixel regions P is less than or equal to a threshold.

[0061] The above scheme, by setting a pattern of source compensation part 500, gate compensation part 600 and semiconductor layer compensation part 700 in the pixel region P, and referring to the gate compensation part 600, the semiconductor layer compensation part 700 and the source compensation part 500 as the Cgs compensation pattern, compensates for the first gate-source parasitic capacitance formed by the gate 301 and source 302 of the thin film transistor 300 in each pixel region P. Thus, the overlapping position of the source compensation part 500 and the gate compensation part 600 for capacitance compensation also contains the semiconductor layer compensation part 700, and the overlapping position of the source 302 and the gate 301 of the thin film transistor 300 contains the semiconductor layer 304. Therefore, a semiconductor layer 304 is formed between the source compensation part 500 and the gate compensation part 600. The gate-source parasitic capacitance compensation can be achieved by controlling the overlap area between the source compensation section 500 and the gate compensation section 600, and between the source compensation section 500 and the semiconductor layer compensation section 700. This allows for accurate and effective compensation of the first gate-source parasitic capacitance within the pixel region P, ensuring that the difference in effective gate-source parasitic capacitance within different pixel regions P is less than or equal to a threshold. In other words, the effective gate-source parasitic capacitance within different pixel regions P is approximately equal. This reduces the phenomenon of excessive differences in effective gate-source parasitic capacitance Cgs between different pixel regions P caused by the overlap and offset of the gate 301 and source 302 of the thin-film transistor 300. This ensures the stability of the effective gate-source parasitic capacitance Cgs and improves the stability of the displayed image.

[0062] It should be noted that the threshold can be a value obtained from experimental testing, which can be the allowable difference in effective gate-source parasitic capacitance Cgs between pixels without affecting image stability. For example, the threshold can be equal to or close to 0.

[0063] It should also be noted that the pixel architecture of the display substrate can include single-gate pixel architecture and dual-gate pixel architecture. To achieve low power consumption, either single-gate or dual-gate pixel architecture can use a Z-pixel arrangement architecture.

[0064] For example, as shown in Figures 1 and 2, the gate line 110 extends along a first direction X, and the data line 120 extends along a second direction Y; wherein each of the data lines 120 is connected to at least two pixel regions P located on opposite sides of the data line 120 in the first direction X via at least two thin-film transistors 300, to form a Z-pixel arrangement architecture.

[0065] Using the above scheme, a data line 120 can be connected to at least two pixel areas P on the left and right sides of two adjacent rows through at least two thin-film transistors 300, and then the gate line 110 sequentially illuminates at least two pixel areas P on the left and right sides, thereby achieving a normal display screen with a constant refresh rate. In other words, the thin-film transistors 300 in odd-numbered rows and the thin-film transistors 300 in even-numbered rows are respectively connected to the left and right sides of the same data line 120.

[0066] In some exemplary embodiments, as shown in Figures 1 and 2, the thin-film transistor 300 is a U-shaped thin-film transistor, the drain 303 is U-shaped, the U-shaped opening of the drain 303 is arranged along the first direction X, and the orthographic projection of the source 302 on the substrate 100 is located in the U-shaped opening of the drain 303; wherein, between two pixel regions P connected to the same data line 120 and arranged adjacently in the second direction Y, the U-shaped opening of the drain 303 is arranged in opposite directions.

[0067] Taking the first direction X as an example, where the orientation shown in Figure 2 is left and right, among the two thin-film transistors 300 connected to the same data line 120 and located on the left and right sides of the data line 120, one thin-film transistor 300 has its U-shaped opening facing left, and the other thin-film transistor 300 has its U-shaped opening facing right. The source 302 of the thin-film transistor 300 can be located in the U-shaped opening of the drain 303. The source 302 can be a line extending along the first direction X. However, it is not limited to this; for example, the drain 303 of the thin-film transistor 300 can also be a line.

[0068] When the display substrate uses the aforementioned Z-pixel arrangement structure, the gate metal layer and the source / drain metal layer are prone to overlap during the TFT manufacturing process. Since one of the two thin-film transistors 300 connected to the same data line 120 has its U-shaped opening facing left and the other facing right, if the gate metal layer and the source / drain metal layer misalign along the left-right direction, the overlap area between the gate 301 and the source 302 in the two thin-film transistors 300 will be different. This results in different gate-source parasitic capacitances Cgs generated by the two thin-film transistors 300, leading to an additional difference in the switching voltage ΔVp between the corresponding two pixel regions P.

[0069] Specifically, as shown in Figure 2, the two thin-film transistors 300 connected to the left and right sides of the first data line 120A are the first thin-film transistor 300AA and the second thin-film transistor 300B, respectively.

[0070] Please refer to Figure 3. The gate-source parasitic capacitance Cgs1 formed by the first thin-film transistor 300A satisfies the following relationship:

[0071] Cgs1 = C1 + C2, where C1 is the gate-source parasitic capacitance generated by the overlapping region of the source 302, semiconductor layer 304 and gate 301, and C2 is the gate-source parasitic capacitance generated only by the overlapping region of the source 302 and gate 301.

[0072] Please refer to Figure 4. The gate-source parasitic capacitance Cgs2 formed by the second thin-film transistor 300B satisfies the following relationship:

[0073] Cgs2 = C1' + C2', where C1' is the gate-source parasitic capacitance generated by the overlapping region of the source 302, semiconductor layer 304 and gate 301, and C2' is the gate-source parasitic capacitance generated only by the overlapping region of the source 302 and gate 301.

[0074] If there is no misalignment between the gate metal layer and the source / drain metal layer, then obviously, Cgs1 = Cgs2.

[0075] If there is a misalignment between the gate metal layer and the source / drain metal layer, then obviously, Cgs1≠Cgs2.

[0076] An increased difference in the transition voltage ΔVp between pixels leads to changes in the optimal Vcom value for positive and negative polarity pixels, resulting in different optimal Vcom values ​​for pixels in odd and even rows. Ultimately, the difference in transition voltage ΔVp between odd and even rows, combined with the alternating positive and negative polarity of data line 120, will produce four types of pixel voltages and four types of pixel brightness. After periodic arrangement, this will form vertical dark and bright lines that change with the switching of positive and negative frames. In the temporal dimension, due to flicker, there are brightness changes when pixels switch between positive and negative frames; in the spatial dimension, when viewed from a fixed position, the brightness and darkness of adjacent frames overlap, and the difference in brightness is not visible; when viewed while moving, the visual superposition of the head-shaking lines in space is significantly enhanced.

[0077] In some exemplary embodiments of this disclosure, as shown in FIG2, in each pixel region P, the source electrode 302 extends along the first direction X, the source electrode compensation portion 500 is formed by the source electrode 302 extending along the first direction X in a direction away from the corresponding data line 120, the gate compensation portion 600 is formed by the corresponding gate line 110 protruding and extending in a direction close to the pixel electrode 200, and the gate compensation portion 600 and the gate electrode 301 are arranged at a distance from each other in the first direction X, and the semiconductor layer compensation portion 700 and the semiconductor layer 304 are arranged at a distance from each other in the first direction X.

[0078] Based on the previous analysis, when the source 302 is designed to extend along the first direction X (i.e., extending in the left-right direction in the figure), when the gate metal layer, source / drain layer 303, and semiconductor layer 304 are misaligned along the first direction X, the overlapping areas of the source 302, gate 301, and semiconductor layer 304 between two thin-film transistors 300 with opposite U-shaped opening directions in the left-right direction will be different. The gate compensation part 600, the semiconductor layer compensation part 700, and the source compensation part 500 are referred to as Cgs compensation patterns. The source compensation part 500 is designed to be formed directly by the source 302 extending in the first direction X. The gate compensation part 600 is formed by the corresponding gate line 110 protruding and extending in the direction close to the pixel electrode 200. The gate compensation part 600 and the gate 301 are arranged at intervals in the first direction X, and the semiconductor layer compensation part 700 and the semiconductor layer 304 are arranged at intervals in the first direction X.

[0079] In this way, the Cgs compensation pattern in each pixel region P can automatically compensate the gate-source parasitic capacitance in different pixel regions P to be approximately the same, so as to offset the Cgs difference between pixels caused by the alignment offset in the first direction X of the gate metal layer, source-drain layer 303 and semiconductor layer 304, thereby ensuring that the optimal Vcom of odd rows and even rows is at the same level, which can improve the head-shaking pattern defect.

[0080] Specifically, as shown in Figure 2, the two thin-film transistors 300 connected to the left and right sides of the first data line 120A are the first thin-film transistor 300A and the second thin-film transistor 300B, respectively.

[0081] Please refer to Figures 3 and 5. The effective gate-source parasitic capacitance Cgs3 formed by the first thin film transistor 300A satisfies the following relationship: Cgs3=C31+C32, where C31 is the first gate-source parasitic capacitance generated by the overlapping area of ​​the channel-side source 302, semiconductor layer 304 and gate 301 of the first thin film transistor 300A, and C32 is the gate-source compensation parasitic capacitance generated by the non-channel-side Cgs compensation pattern of the first thin film transistor 300A.

[0082] Please refer to Figures 4 and 6. The gate-source parasitic capacitance Cgs2 formed by the second thin-film transistor 300B satisfies the following relationship: Cgs4 = C41 + C42, where C41 is the first gate-source parasitic capacitance generated by the overlapping region of the channel-side source 302, semiconductor layer 304 and gate 301 of the second thin-film transistor 300B, i.e., C41 = C1 + C2; C42 is the gate-source compensation parasitic capacitance generated by the non-channel-side Cgs compensation pattern of the second thin-film transistor 300B, C42 = C3 + C4.

[0083] Regardless of whether there is a misalignment between the gate metal layer and the source / drain metal layer in the first direction X, Cgs3 is equal to Cgs4.

[0084] Furthermore, in some exemplary embodiments, as shown in FIG2, in each pixel region P, the semiconductor layer compensation portion 700 extends a first predetermined width L1 in the first direction X, such that the overlapping portion of the semiconductor layer compensation portion 700 and the source compensation portion 500 includes at least a first region S1 and a second region S2 in the first direction X. The first region S1 is located on the side of the second region S2 closer to the source 302, wherein the first region S1 overlaps with the source compensation portion 500, and the second region S2 does not overlap with the source compensation portion 500.

[0085] Using the above scheme, the semiconductor layer compensation portion 700 extends to a first predetermined width L1 in the first direction X, so as to ensure that the semiconductor layer compensation portion 700 does not overlap with the source compensation portion 500 at least partially on the side away from the source 302. In other words, on the side away from the source 302 along the first direction X, the boundary of the source compensation portion 500 will not exceed the boundary of the semiconductor layer compensation portion 700, so as to ensure that the Cgs compensation pattern can effectively compensate for the first gate-source parasitic capacitance Cgs between pixels.

[0086] It should be noted that the minimum value of the first predetermined width L1 can be determined in conjunction with the film layer patterning process in the display substrate manufacturing process. For example, the first predetermined width can be the maximum allowable offset of each film layer of the thin film transistor 300 in the first direction X.

[0087] Furthermore, in some exemplary embodiments, as shown in FIG2, the source compensation portion 500 includes a first source compensation pattern 510 extending in an elongated shape along the first direction X, and the semiconductor layer compensation portion 700 includes a first semiconductor compensation pattern 710 in a block shape. The first source compensation pattern 510 overlaps with the first semiconductor compensation pattern 710, and the first semiconductor compensation pattern 710 includes a second region S2 in the first direction X that does not overlap with the first source compensation pattern 510.

[0088] By adopting the above scheme, the source compensation unit 500 is designed to be elongated, which can realize Cgs compensation between pixels when the alignment shifts in the first direction X.

[0089] Furthermore, in some exemplary embodiments, as shown in FIG7, in each pixel region P, the source compensation portion 500 includes a first source compensation pattern 510, a second source compensation pattern, and a third source compensation pattern. The first source compensation pattern 510 is formed by the source 302 extending away from the corresponding data line 120 along the first direction X. The second source compensation pattern and the third source compensation pattern are respectively formed by the first source compensation pattern 510 extending in opposite directions along the second direction Y.

[0090] The semiconductor layer compensation section 700 includes a first semiconductor compensation pattern 710, a second semiconductor compensation pattern 720, and a third semiconductor compensation pattern 730. The second semiconductor compensation pattern 720 and the third semiconductor compensation pattern 730 are respectively located on opposite sides of the first semiconductor compensation pattern 710 along the second direction Y, and are both arranged at intervals from the first semiconductor compensation pattern 710.

[0091] The first source compensation pattern 510 partially overlaps with the first semiconductor compensation pattern 710, the second source compensation pattern partially overlaps with the second semiconductor compensation pattern 720, and the third source compensation pattern partially overlaps with the third semiconductor compensation pattern 730.

[0092] By adopting the above scheme, the first source compensation pattern 510 extending along the first direction X, in cooperation with the first semiconductor compensation pattern 710 and the gate compensation part 600, can realize Cgs compensation between pixels when the alignment shifts in the first direction X; at the same time, the second source compensation pattern, the third source compensation pattern, and the second semiconductor compensation pattern 720 and the third semiconductor compensation pattern 730 can also be used to realize Cgs compensation between pixels when the alignment shifts in the second direction Y.

[0093] In some exemplary embodiments, as shown in FIG7, in each pixel region P, the second semiconductor compensation pattern 720 extends a second predetermined width L2 in the second direction Y, such that the overlapping portion of the second semiconductor compensation pattern 720 and the second source compensation pattern includes at least a third region S3 and a fourth region S4 in the second direction Y. The third region S3 is located on the side of the second region S2 closer to the first source compensation pattern 510, wherein the third region S3 overlaps with the second source compensation pattern, and the fourth region S4 does not overlap with the second source compensation pattern.

[0094] For example, in each pixel region P, the third semiconductor compensation pattern 730 extends a third predetermined width L3 in the second direction Y, such that the overlapping portion of the third semiconductor compensation pattern 730 and the third source compensation pattern includes at least a fifth region and a sixth region in the second direction Y. The fifth region is located on the side of the sixth region closer to the first source compensation pattern 510, wherein the fifth region overlaps with the third source compensation pattern, and the sixth region does not overlap with the third source compensation pattern.

[0095] Using the above scheme, the extension width of the second semiconductor layer compensation pattern in the second direction Y is a second predetermined width L2, and the extension width of the third semiconductor layer compensation pattern is a third predetermined width L3, so as to ensure that the semiconductor layer compensation part 700 does not overlap with the source compensation part 500 at least partially in the second direction Y. In other words, along the second direction Y, the boundary of the source compensation part 500 will not exceed the boundary of the semiconductor layer compensation part 700, so as to ensure that the Cgs compensation pattern can effectively compensate for the first gate-source parasitic capacitance Cgs between pixels.

[0096] It should be noted that the minimum value of the second predetermined width L2 and the third predetermined width L3 can be determined in conjunction with the film layer patterning process in the display substrate manufacturing process. For example, the sum of the second predetermined width L2 and the third predetermined width L3 is greater than or equal to the maximum allowable offset of each film layer of the thin film transistor 300 in the second direction Y.

[0097] Furthermore, to make Cgs more stable, the length range of the first source compensation pattern 510 can be determined based on multiple experimental results. As for the linewidth of the first source compensation pattern 510, it can be selected within a certain range according to the actual compensation effect. However, to avoid increasing design and manufacturing complexity and to facilitate Cgs numerical calculation or adjustment, in some exemplary embodiments, as shown in the figure, the linewidth of the first source compensation pattern 510 is the same as that of the source 302. That is, in the actual design of the linewidth of the first source compensation pattern 510, its linewidth does not need to be designed separately; the width of the source 302 can be directly used, avoiding situations where excessive width affects the design space or excessive narrow width leads to poor Cgs compensation effect.

[0098] Furthermore, in some embodiments, the linewidths of the second and third source compensation patterns can be the same. For example, the linewidths of both the second and third source compensation patterns can be equal to the linewidth of the source 302. Thus, in the actual design of the linewidths of the second and third source compensation patterns, it is not necessary to design their linewidths separately; the width of the source 302 can be used directly, avoiding the impact of excessive width on design space or the poor Cgs compensation effect due to excessively narrow width.

[0099] It is understood that the specific size of the source compensation pattern is not limited to this.

[0100] Furthermore, in some exemplary embodiments, the source electrode 302 and the source compensation portion 500 are arranged on the same layer and with the same material; the gate electrode 301 and the gate compensation portion 600 are arranged on the same layer and with the same material; and the semiconductor layer 304 and the semiconductor layer compensation portion 700 are arranged on the same layer and with the same material. This simplifies the process and ensures that the Cgs compensation pattern and the film layer relationship of the thin-film transistor 300 are approximately the same, reducing the possibility of poor Cgs compensation due to differences in film layer relationships or materials.

[0101] Furthermore, in some exemplary embodiments, as shown in FIG2, two gate lines 110 are provided between two adjacent rows of pixel regions P arranged in the second direction Y, wherein the two gate lines 110 are respectively connected to the gate 301 and the gate compensation portion 600 in the two rows of pixel regions P. In other words, the display substrate adopts a dual-gate pixel architecture to reduce power consumption, etc. However, it is not limited to this, and the display substrate may also adopt a single-gate pixel architecture.

[0102] This disclosure also provides a method for manufacturing a display substrate, for manufacturing the display substrate as described above, the method comprising:

[0103] Step S01: Provide a substrate 100;

[0104] Step S02: Multiple gate lines 110, multiple data lines 120, multiple pixel electrodes 200, multiple thin-film transistors 300, a source compensation section 500, a gate compensation section 600, and a semiconductor layer compensation section 700 are formed on the substrate 100. The data lines 120 intersect with the gate lines 110 to define multiple pixel regions P. Each pixel region P includes the pixel electrode 200 and the thin-film transistor 300. The thin-film transistor 300 includes a gate 301, a source 302, a drain 303, and a semiconductor layer 304. The source 302 is connected to the pixel electrode 200 in the same pixel region P, the gate 301 is connected to the corresponding gate line 110, and the drain 303 of the thin-film transistor 300 is connected to the corresponding data line 120. The source compensation section 500 is connected to the source 302. The gate compensation portion 600 is connected to the gate line 110 and is spaced apart from the gate 301. The semiconductor layer compensation portion 700 is spaced apart from the semiconductor layer 304. In the same pixel region P, the source electrode 302 overlaps with the orthographic projection portions of the gate electrode 301 and the semiconductor layer 304 on the substrate 100 to form a first gate-source parasitic capacitance. The source compensation portion 500 overlaps with the orthographic projection portions of the semiconductor layer compensation portion 700 and the gate compensation portion 600 on the substrate 100 to form a gate-source compensation parasitic capacitance. In the same pixel region P, the sum of the first gate-source parasitic capacitance and the gate-source compensation parasitic capacitance is the effective gate-source parasitic capacitance Cgs. The difference between the effective gate-source parasitic capacitances Cgs of different pixel regions P is less than or equal to a threshold.

[0105] For example, in the method, in step S02, the source electrode 302 and the source electrode compensation part 500 are formed using the same patterning process; the gate electrode 301 and the gate compensation part 600 are formed using the same patterning process; and the semiconductor layer 304 and the semiconductor layer compensation part 700 are formed using the same patterning process.

[0106] Thirdly, embodiments of this disclosure also provide a display device, which includes the display substrate described above. The display device provided in embodiments of this disclosure can be applied to any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0107] Since the main improvement of the manufacturing method of the display substrate and the display device lies in the above-mentioned compensation scheme for Cgs of the display substrate, and the Cgs compensation scheme has been described in detail above, the manufacturing method of the display substrate and the structure of the display device will not be described again here with reference to the accompanying drawings.

[0108] The following points need to be explained:

[0109] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0110] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to actual scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0111] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0112] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A display substrate, characterized in that, include: Substrate; Multiple gate lines and multiple data lines, wherein the data lines intersect with the gate lines to define multiple pixel regions; The pixel region includes multiple pixel electrodes and multiple thin-film transistors. The pixel region includes the pixel electrodes and the thin-film transistors. The thin-film transistors include a gate, a source, a drain, and a semiconductor layer. The source is connected to the pixel electrode in the same pixel region. The gate is connected to the corresponding gate line. The drain of the thin-film transistor is connected to the corresponding data line. and A source compensation portion, a gate compensation portion, and a semiconductor layer compensation portion are provided in the pixel region. The source compensation portion is connected to the source, the gate compensation portion is connected to the gate line and is spaced apart from the gate, and the semiconductor layer compensation portion is spaced apart from the semiconductor layer. In the same pixel region, the source electrode, the gate electrode, and the orthogonal projection portion of the semiconductor layer on the substrate overlap to form a first gate-source parasitic capacitance; the source electrode compensation portion, the semiconductor layer compensation portion, and the gate compensation portion overlap to form a gate-source compensation parasitic capacitance. Within the same pixel region, the sum of the first gate-source parasitic capacitance and the gate-source compensated parasitic capacitance is the effective gate-source parasitic capacitance Cgs; the difference between the effective gate-source parasitic capacitance Cgs of different pixel regions is less than or equal to a threshold.

2. The display substrate according to claim 1, characterized in that, The gate line extends along a first direction, and the data line extends along a second direction; wherein each of the data lines is connected to at least two pixel regions located on opposite sides of the data line in the first direction via at least two thin-film transistors, to form a Z-pixel arrangement architecture.

3. The display substrate according to claim 2, characterized in that, In each pixel region, the source electrode extends along the first direction, the source electrode compensation portion is formed by the source electrode extending away from the corresponding data line along the first direction, the gate electrode compensation portion is formed by the corresponding gate line protruding and extending towards the pixel electrode, and the gate electrode compensation portion and the gate electrode are spaced apart in the first direction, and the semiconductor layer compensation portion and the semiconductor layer are spaced apart in the first direction.

4. The display substrate according to claim 2, characterized in that, The thin-film transistor is a U-shaped thin-film transistor, the drain is U-shaped, the U-shaped opening of the drain is arranged along the first direction, and the orthogonal projection of the source on the substrate is located in the U-shaped opening of the drain; wherein, between two pixel regions connected to the same data line and arranged adjacently in the second direction, the U-shaped opening of the drain is arranged in opposite directions.

5. The display substrate according to claim 2, characterized in that, In each pixel region, the semiconductor layer compensation portion extends a first predetermined width in the first direction, such that the overlapping portion of the semiconductor layer compensation portion and the source compensation portion includes at least a first region and a second region in the first direction, wherein the first region is located on the side of the second region closer to the source, wherein the first region overlaps with the source compensation portion, and the second region does not overlap with the source compensation portion.

6. The display substrate according to claim 5, characterized in that, The source compensation section includes a first source compensation pattern that is elongated and extends along the first direction, and the semiconductor layer compensation section includes a first semiconductor compensation pattern that is block-shaped. The first source compensation pattern overlaps with the first semiconductor compensation pattern, and the first semiconductor compensation pattern includes a second region in the first direction that does not overlap with the first source compensation pattern.

7. The display substrate according to claim 5, characterized in that, In each pixel region, the source compensation section includes a first source compensation pattern, a second source compensation pattern, and a third source compensation pattern. The first source compensation pattern is formed by the source extending away from the corresponding data line along the first direction. The second source compensation pattern and the third source compensation pattern are formed by the first source compensation pattern extending in opposite directions along the second direction. The semiconductor layer compensation section includes a first semiconductor compensation pattern, a second semiconductor compensation pattern, and a third semiconductor compensation pattern. The second semiconductor compensation pattern and the third semiconductor compensation pattern are located on opposite sides of the first semiconductor compensation pattern along the second direction, and are arranged at intervals from the first semiconductor compensation pattern. in The first source compensation pattern and the first semiconductor compensation pattern partially overlap, the second The source compensation pattern partially overlaps with the second semiconductor compensation pattern, and the third source compensation pattern partially overlaps with the third semiconductor compensation pattern.

8. The display substrate according to claim 7, characterized in that, In each pixel region, the second semiconductor compensation pattern extends a second predetermined width in the second direction, such that the overlapping portion of the second semiconductor compensation pattern and the second source compensation pattern includes at least a third region and a fourth region in the second direction. The third region is located on the side of the second region closer to the first source compensation pattern, wherein the third region overlaps with the second source compensation pattern, and the fourth region does not overlap with the second source compensation pattern.

9. The display substrate according to claim 7, characterized in that, In each pixel region, the third semiconductor compensation pattern extends a third predetermined width in the second direction, such that the overlapping portion of the third semiconductor compensation pattern and the third source compensation pattern includes at least a fifth region and a sixth region in the second direction, wherein the fifth region is located on the side of the sixth region closer to the first source compensation pattern, wherein the fifth region overlaps with the third source compensation pattern, and the sixth region does not overlap with the third source compensation pattern.

10. The display substrate according to claim 6 or 7, characterized in that, The first source compensation pattern has the same linewidth as the source.

11. The display substrate according to claim 1, characterized in that, The source electrode and the source electrode compensation part are arranged on the same layer and with the same material; the gate electrode and the gate electrode compensation part are arranged on the same layer and with the same material; the semiconductor layer and the semiconductor layer compensation part are arranged on the same layer and with the same material.

12. The display substrate according to claim 1, characterized in that, The gate line extends along a first direction, the data line extends along a second direction, and two gate lines are provided between two adjacent rows of pixel areas arranged in the second direction, wherein the two gate lines are respectively connected to the gate and the gate compensation part in the two rows of pixel areas.

13. A method for manufacturing a display substrate, characterized in that, The method for manufacturing a display substrate as described in any one of claims 1 to 12 includes: Provide substrates; Multiple gate lines, multiple data lines, multiple pixel electrodes, multiple thin-film transistors, source compensation sections, gate compensation sections, and semiconductor layer compensation sections are formed on the substrate, wherein the data lines and The gate lines intersect each other to define multiple pixel regions; each pixel region includes a pixel electrode and a thin-film transistor (TFT), the TFT including a gate, a source, a drain, and a semiconductor layer, the source being connected to the pixel electrode in the same pixel region, the gate being connected to the corresponding gate line, and the drain of the TFT being connected to the corresponding data line; a source compensation portion is connected to the source, a gate compensation portion is connected to the gate line and spaced apart from the gate, and a semiconductor layer compensation portion is spaced apart from the semiconductor layer; in the same pixel region, the source, the gate, and the orthogonal projection portion of the semiconductor layer on the substrate overlap to form a first gate-source parasitic capacitance; the source compensation portion, the semiconductor layer compensation portion, and the gate compensation portion on the substrate overlap to form a gate-source compensation parasitic capacitance; in the same pixel region, the sum of the first gate-source parasitic capacitance and the gate-source compensation parasitic capacitance is the effective gate-source parasitic capacitance Cgs; the difference between the effective gate-source parasitic capacitances Cgs of different pixel regions is less than or equal to a threshold.

14. The method for manufacturing a display substrate according to claim 13, characterized in that, In the method, the source electrode and the source electrode compensation part are formed using the same patterning process; the gate electrode and the gate electrode compensation part are formed using the same patterning process; and the semiconductor layer and the semiconductor layer compensation part are formed using the same patterning process.

15. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 12.

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