Power conversion device

Abstract

This power conversion device (100) comprises an inverter unit (1), which is a single-phase inverter multi-series circuit that is formed from three or more single-phase inverters (INV (n)) and that supplies power to a load (10). The power conversion device (100) has a reference breakdown voltage single-phase inverter (SV), which is a single-phase inverter formed from a semiconductor switch with a breakdown voltage equal to or less than a reference breakdown voltage, and a high breakdown voltage single-phase inverter (HV), which is a single-phase inverter formed from a semiconductor switch with a higher breakdown voltage than the reference breakdown voltage. At least two high breakdown voltage single-phase inverters (HV) are disposed with at least one reference breakdown voltage single-phase inverter (SV) therebetween, or are respectively disposed on the two sides of an L-shape with at least one reference breakdown voltage single-phase inverter (SV) at the corner.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] When heat is concentrated in a specific semiconductor switching element in an inverter or a multi-series inverter circuit, a larger heat sink is required, resulting in larger equipment and higher costs. For this reason, it is necessary to reduce the losses generated in the semiconductor switching elements. Furthermore, in a multi-series inverter circuit with single-phase inverters of different output voltages, the inverter on the higher voltage side must be a high-voltage product with poor switching characteristics, resulting in greater losses than the inverter on the lower voltage side. For this reason, it is necessary to reduce the losses generated in the semiconductor switching elements.

[0003] A power conversion device is disclosed that reduces losses and improves efficiency by connecting multiple single-phase inverters with different output voltages in series and combining the output voltages of each single-phase inverter to supply power to a load using gradation control.

[0004] Patent Publication No. 2010-094024

[0005] However, the power conversion device in Patent Document 1 does not include any description regarding the withstand voltage of the semiconductor switching elements or the placement of the single-phase inverters, which means that placing single-phase inverters with high losses close to each other may result in concentrated heat generation, which may lead to larger radiators, larger power conversion device, and higher costs.

[0006] The present disclosure discloses a technology for solving the above-mentioned problems, and aims to provide a power conversion device that can achieve heat dispersion through structural innovation in a single-phase inverter multi-series circuit consisting of three or more single-phase inverters.

[0007] In the power conversion device of the present disclosure, N is an integer of 3 or more, and n is an integer of 1 or more and N or less, In a power conversion device in which N single-phase inverters are connected in series, one end of a semiconductor switch Q1(n) and one end of a semiconductor switch Q3(n) are connected to a high-potential terminal of a DC power source V(n), one end of a semiconductor switch Q2(n) and one end of a semiconductor switch Q4(n) are connected to a low-voltage terminal of the DC power source V(n), the other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) are connected in series at a first midpoint P1(n), and the other end of the semiconductor switch Q3(n) and the other end of the semiconductor switch Q4(n) are connected in series at a second midpoint P2(n), a load connected to a first midpoint P1(1) of the single-phase inverter INV(1) and a second midpoint P2(N) of the single-phase inverter INV(N) and supplied with DC power or AC power, and a control unit that controls the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n), wherein, when the withstand voltage of the semiconductor switch in at least one of the single-phase inverters INV(n) is taken as a reference withstand voltage, in addition to a reference withstand voltage single-phase inverter that is a single-phase inverter having semiconductor switches with a withstand voltage equal to or lower than the reference withstand voltage, the withstand voltages of the semiconductor switches in at least two of the single-phase inverters are configured with high-voltage semiconductor switches that are semiconductor switches with a withstand voltage higher than the reference withstand voltage, and the at least two high-voltage single-phase inverters configured with the high-voltage semiconductor switches are arranged with at least one of the standard withstand voltage single-phase inverters sandwiched therebetween, or are arranged on each of two sides of an L shape having at least one of the standard withstand voltage single-phase inverters as a corner.

[0008] According to the power conversion device of the present disclosure, a power conversion device can be obtained that can achieve heat dispersion by devising a structure in a single-phase inverter multi-series circuit configured with three or more single-phase inverters.

[0009] FIG. 2A is an overall configuration diagram of a power conversion device according to embodiment 1. FIG. 2A is an explanatory diagram of an example of an arrangement of three single-phase inverters according to embodiment 1. FIG. 2B is an explanatory diagram of an example of an arrangement of three single-phase inverters according to embodiment 1. FIG. 2C is an explanatory diagram of an example of an arrangement of three single-phase inverters according to embodiment 1. FIG. 3A is an explanatory diagram of an example of an arrangement of five single-phase inverters according to embodiment 1. FIG. 3B is an explanatory diagram of an example of an arrangement of five single-phase inverters according to embodiment 1. FIG. 3C is an explanatory diagram of an example of an arrangement of five single-phase inverters according to embodiment 1. FIG. 4A is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 2. FIG. 4B is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 2. FIG. 4C is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 2. FIG. 4D is an explanatory diagram of an operating state of a single-phase inverter according to embodiment 2. An operating state transition diagram of a single-phase inverter according to embodiment 2. FIG. 6A is an explanatory diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 6B is an explanatory diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 6C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 7A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 7B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 7C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 7D is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 8A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 8B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 8C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 8D is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 8E is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 9A is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 9B is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 9C is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 9D is a diagram of a semiconductor switch arrangement of a single-phase inverter according to embodiment 3.FIG. 9E is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 9F is a diagram illustrating the semiconductor switch arrangement of a single-phase inverter according to embodiment 3. FIG. 10A is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 4. FIG. 10B is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 4. FIG. 11A is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 4. FIG. 11B is a diagram illustrating the operating states of a plurality of single-phase inverters according to embodiment 4. FIG. 12A is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 12B is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 13A is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 13B is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 14A is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 14B is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 15A is a diagram illustrating the semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. 15B is a diagram of a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 16A is a diagram of a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 16B is a diagram of a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 17A is a diagram of a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. FIG. 17B is a diagram of a semiconductor switch arrangement of a plurality of single-phase inverters according to embodiment 4. An example of a hardware configuration of a control unit. An operating state transition diagram of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2. An explanatory diagram of transition timing of a single-phase inverter according to embodiment 2.

[0010] Embodiment 1 In embodiment 1, a power conversion device including a single-phase inverter multi-series circuit configured with three or more single-phase inverters and supplying power to a load has a standard withstand voltage single-phase inverter that is a single-phase inverter configured with semiconductor switches having a withstand voltage equal to or lower than a standard withstand voltage, and a high withstand voltage single-phase inverter that is a single-phase inverter configured with semiconductor switches having a withstand voltage higher than the standard withstand voltage, and at least two high withstand voltage single-phase inverters are arranged at a distance from each other.

[0011] The configuration and operation of the power conversion device according to embodiment 1 will be described below with reference to FIG. 1, which is an overall configuration diagram of the power conversion device; FIGS. 2A, 2B, and 2C, which are explanatory diagrams of an example arrangement of three single-phase inverters; and FIGS. 3A, 3B, and 3C, which are explanatory diagrams of an example arrangement of five single-phase inverters.

[0012] The overall configuration of the power conversion device and the configuration of the single-phase inverter of the first embodiment will be described with reference to Fig. 1. The power conversion device 100 includes an inverter unit 1 and a control unit 20, and supplies AC power or DC power to a load 10.

[0013] First, the configuration and operation of the inverter unit 1 of the power conversion device 100 will be described. The inverter unit 1 is composed of single-phase inverters INV(1), INV(2), INV(3), ..., INV(N) (N is an integer of 3 or more). In the figure, for example, INV(1) is written as INV1 and INV(N) as INVN. Furthermore, for general explanations, n is an integer greater than or equal to 1 and less than or equal to N, and they are written as, for example, INV(n) and V(n).

[0014] Next, the configuration of each single-phase inverter will be described, taking the single-phase inverter INV(1) as a representative. The single-phase inverter INV(1) is configured as a full-bridge circuit consisting of self-extinguishing semiconductor switching elements Q1(1), Q2(1), Q3(1), and Q4(1), which are semiconductor switching elements such as insulated gate bipolar transistors (IGBTs) with multiple diodes connected in antiparallel, and a DC power supply V(1). For simplicity, in FIG. 1 , the diodes of the semiconductor switching elements are omitted and represented as switches. In the figure, for example, Q1(1) is referred to as Q11, Q2(1) as Q21, Q3(1) as Q31, Q4(1) as Q41, and V(1) as V1. The DC power supply is referred to as PS. The semiconductor switching elements are referred to as semiconductor switches. The semiconductor switching elements may be transistors, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc. Although the examples shown are each composed of a single component, each semiconductor switching element may be composed of a plurality of semiconductor switching elements connected in series, parallel, or series-parallel in order to ensure sufficient withstand voltage and current.

[0015] One end of semiconductor switch Q1(1) and one end of semiconductor switch Q3(1) are connected to the high-voltage terminal of DC power supply V(1), and one end of semiconductor switch Q2(1) and one end of semiconductor switch Q4(1) are connected to the low-voltage terminal of DC power supply V(1). The other end of semiconductor switch Q1(1) and the other end of semiconductor switch Q2(1) are connected in series at a first midpoint P1(1), and the other end of semiconductor switch Q3(1) and the other end of semiconductor switch Q4(1) are connected in series at a second midpoint P2(1). In the figure, for example, P1(1) is designated as P11.

[0016] Next, the internal configuration of the inverter unit 1 and the relationship between the inverter unit 1, the load 10, and the control unit 20 will be described. The outputs of the single-phase inverters INV(1), INV(2), INV(3), ..., INV(N) are connected in series. Specifically, for example, the second midpoint P2(1) of the single-phase inverter INV(1) is connected to the first midpoint P1(2) of the single-phase inverter INV(2). The second midpoint P2(2) of the single-phase inverter INV(2) is connected to the first midpoint P1(3) of the single-phase inverter INV(3). The load 10 is connected to the first midpoint P1(1) of the single-phase inverter INV(1) and the second midpoint P2(N) of the single-phase inverter INV(N). The control unit 20 controls the semiconductor switches of the single-phase inverters INV(1), INV(2), INV(3), ..., INV(N). Specifically, for example, the control unit 20 controls the semiconductor switches Q1(1), Q2(1), Q3(1), and Q4(1) of the INV(1). The load 10 may be a resistive load, an inductive load, or a capacitive load. Note that FIG. 1 illustrates a typical example of the circuit, and appropriate modifications can be made, such as adding a drive circuit for the semiconductor switches, a snubber circuit, an input capacitor, or an output filter.

[0017] Here, we will explain the reasons and methods for achieving heat dissipation by devising an appropriate layout of the single-phase inverters, a feature of the power conversion device 100 of the first embodiment. Furthermore, we will explain specific layout examples for effectively achieving heat dissipation with reference to the drawings. First, we will explain the relationship between the withstand voltage of semiconductor switches and the heat generated by the semiconductor switches. Note that the withstand voltage of a semiconductor switch here refers to the withstand voltage of the semiconductor switch. A semiconductor switch with a high withstand voltage has a higher on-resistance and poorer switching characteristics than a semiconductor switch with a low withstand voltage. As a result, semiconductor switches with a high withstand voltage have higher conduction losses and switching losses. Therefore, a single-phase inverter configured with semiconductor switches with a high withstand voltage generates more heat. Note that in the following explanation and drawings, when a standard withstand voltage is set, a single-phase inverter configured with semiconductor switches with a withstand voltage equal to or lower than this standard withstand voltage will be referred to as a standard withstand voltage single-phase inverter SV. A single-phase inverter configured with semiconductor switches with a withstand voltage higher than this standard withstand voltage will be referred to as a high-voltage single-phase inverter HV.

[0018] Next, we will explain a layout method for a single-phase inverter that can effectively achieve heat dissipation. A single-phase inverter, when considering layout, has four semiconductor switches (Q1 to Q4) as its components. The four semiconductor switches can be considered as a single-phase inverter, or the four semiconductor switches, snubber circuits, input capacitors, and other components can be considered as a single-phase inverter, or the single-phase inverter can be considered as a single-phase inverter including the semiconductor switch drive circuits. The basic concept of a layout that achieves heat dissipation is to place single-phase inverters (high-voltage single-phase inverters) that are composed of high-voltage semiconductor switches and have large switching losses apart. This can be achieved by utilizing single-phase inverters (standard-voltage single-phase inverters) that are composed of low-voltage semiconductor switches and have small conduction and switching losses.

[0019] The basic layout of the single-phase inverter in this disclosure is shown in Figures 2A to 2C. Figures 2A to 2C show an example including two high-voltage single-phase inverters (HV) and one standard-voltage single-phase inverter (SV), which are the minimum components of this disclosure. Note that, for simplicity, the single-phase inverter INV is depicted as a rectangle in Figures 2A to 2C, but the shape of the single-phase inverter INV is not limited. It can be changed to any shape as long as it includes the components of the single-phase inverter INV described above.

[0020] Basic single-phase inverter layouts include a line layout and an L-shaped layout. FIG. 2A shows an example of a line layout of single-phase inverters INV. By sandwiching a single-phase inverter INV(1), which is a standard voltage single-phase inverter (SV), between high-voltage single-phase inverters (HV), INV(2) and INV(3), the distance between the high-voltage single-phase inverters (HV) can be increased. FIG. 2C shows an example of an L-shaped layout. By placing the single-phase inverter INV(1), which is a standard voltage single-phase inverter (SV), at the corner of the L shape, and placing the single-phase inverter INV(2) and the single-phase inverter INV(3), which are high-voltage single-phase inverters (HV), at the two sides of the L shape, the distance between the high-voltage single-phase inverters (HV) can be increased. Note that the basic layout described above can be considered a line layout or an L-shaped layout even if it is not exactly a line or L-shaped layout. 2B shows an example in which the single-phase inverters INV are not neatly arranged in a single row, but are offset vertically. Even in this case, the effect of spacing the high-voltage single-phase inverters (HV) apart can be achieved, so the arrangement can be considered to be in a single row. In this way, even if the single-phase inverters in a single row or L-shaped arrangement are offset vertically or horizontally, they can still be considered to be in a single row or L-shaped arrangement. Furthermore, even if the spacing between the single-phase inverters INV is not uniform, they can still be considered to be in a single row or L-shaped arrangement.

[0021] Up to this point, the explanation has been given for the minimum configuration of the present disclosure, which is two high-voltage single-phase inverters (HV) and one standard-voltage single-phase inverter (SV). However, the power conversion device 100 of the present disclosure may include three or more single-phase inverters INV. When the number of standard-voltage single-phase inverters (SV) is A (A is a natural number) and the number of high-voltage single-phase inverters (HV) is B (B is a natural number equal to or greater than 2), the present disclosure can be applied as long as the relationship A≧B−1 is satisfied. Even when the number of single-phase inverters INV increases, the distance between the high-voltage single-phase inverters (HV) can be increased by selecting and combining the above-described linear arrangement and L-shaped arrangement.

[0022] As an example, an arrangement method for a power conversion device 100 composed of five single-phase inverters will be described using FIGS. 3A to 3C. FIGS. 3A to 3C show an example in which there are three high-voltage single-phase inverters (HV) and two standard-voltage single-phase inverters (SV). Since the above-mentioned relationship A≧B-1 is satisfied, the present disclosure can be applied. FIG. 3A shows an example in which all single-phase inverters INV are arranged in a row. By placing the standard-voltage single-phase inverters (SV) INV(1) and INV(2) between the high-voltage single-phase inverters (HV) INV(3), INV(4), and INV(5), the high-voltage single-phase inverters (HV) can be spaced apart. FIG. 3B shows an example in which an L-shaped arrangement is combined. The single-phase inverter INV(1), which is a standard voltage single-phase inverter (SV), is placed at the corner of an L-shape, and single-phase inverters INV(3) and INV(5), which are high voltage single-phase inverters (HV), are placed on both sides, thereby increasing the distance between the high voltage single-phase inverters (HV). The single-phase inverter INV(2), which is a standard voltage single-phase inverter (SV), is placed at the corner of an L-shape, and single-phase inverters INV(3) and INV(4), which are high voltage single-phase inverters (HV), are placed on both sides, thereby increasing the distance between the high voltage single-phase inverters (HV). Figure 3C shows another example of a combined L-shape arrangement. As in Figure 3B, the single-phase inverter INV(1), which is a standard voltage single-phase inverter (SV), is placed at the corner of an L-shape, and single-phase inverters INV(3) and INV(5), which are high voltage single-phase inverters (HV), are placed on both sides, thereby increasing the distance between the high voltage single-phase inverters (HV). The single-phase inverter INV(2), which is a standard voltage single-phase inverter (SV), is placed at the corner of the L-shape, and the single-phase inverters INV(3) and INV(4), which are high voltage single-phase inverters (HV), are placed on both sides, thereby increasing the distance between the high voltage single-phase inverters (HV). In this way, even when the number of single-phase inverters increases, as long as the relationship A≧B-1 is satisfied, the distance between the high voltage single-phase inverters (HV) can be increased by selecting and combining the above-mentioned linear arrangement and L-shaped arrangement. Heat can be dispersed by separating heat-generating areas.Although not shown, when single-phase inverters are arranged in two rows and two columns, this can also be considered to be configured with a plurality of L-shaped arrangements.

[0023] At least one of the high-voltage single-phase inverters (HV) is preferably a single-phase inverter with the highest DC power supply output voltage. Furthermore, the high-voltage single-phase inverters (HV) are preferably a single-phase inverter with the highest DC power supply output voltage and a single-phase inverter with the second highest output voltage. The high-voltage single-phase inverter (HV) is configured with semiconductor switches with a higher voltage resistance than other single-phase inverters INV, and is not limited to the above. For example, if there is a single-phase inverter INV that uses higher-voltage elements than other single-phase inverters INV due to wiring inductance, etc., as described below, this single-phase inverter INV can be considered a high-voltage single-phase inverter (HV).

[0024] Next, examples of circuit topologies that apply the above-described arrangement will be described. First, an example of a gradation-controlled inverter will be described. A gradation-controlled inverter is a circuit in which the output sides of multiple single-phase inverters, including single-phase inverters that output three or more different voltages, are connected in series. In gradation control, for example, the DC power supply V(n) of each of the multiple single-phase inverters is set to a power of two, such as 1:2:4:...:2^(n-1). Also, for example, the DC power supply V(n) of each of the multiple single-phase inverters is set to a power of three, such as 1:3:9:...:3^(n-1).

[0025] Here, as an example of a gradation-controlled single-phase inverter, assume that N=3, the voltage of the DC power supply V(1) of the smallest single-phase inverter INV(1) is set to 10 V, the DC power supply V(2) of the single-phase inverter INV(2) is set to 20 V, and the DC power supply V(3) of the single-phase inverter INV(3) is set to 40 V.

[0026] In the case of this gradation-controlled single-phase inverter, by combining the outputs of each single-phase inverter (gradation control), it is possible to supply a voltage of -70 to 70 in 10V increments to the load. Furthermore, by also using PWM control, it is possible to supply a voltage finer than 10V to the load equivalently. In this configuration, assuming that the surge voltage generated during the switching operation of each semiconductor switch is less than 10V, the withstand voltage of the semiconductor switch required for each single-phase inverter can be considered to be 20V or more for single-phase inverter INV(1), 30V or more for single-phase inverter INV(2), and 50V or more for single-phase inverter INV(3). Based on the above conditions, it is assumed that a 20V withstand voltage product is selected for INV(1), a 30V withstand voltage product for single-phase inverter INV(2), and a 50V withstand voltage product for single-phase inverter INV(3). Here, if the standard withstand voltage is 20 V, the single-phase inverters INV(2) and INV(3) configured with semiconductor switches with a withstand voltage of 30 V and 50 V are high-voltage single-phase inverters (HV), and the single-phase inverter INV(1) configured with a withstand voltage of 20 V is the standard withstand voltage inverter (SV). Therefore, for example, as shown in FIG. 2A , heat dissipation can be achieved by arranging the single-phase inverter INV(1), which is the standard withstand voltage single-phase inverter (SV), in a line arrangement sandwiched between the single-phase inverters INV(2) and INV(3), which are high-voltage single-phase inverters (HV). The above describes a gradation control inverter in which the power supply of the single-phase inverter is set to a power of 2 or a power of 3 as an example of application of the present disclosure.

[0027] The present disclosure can be applied as long as there are single-phase inverters in which the constituent semiconductor switches have different withstand voltages, and can be applied to inverters other than those in which the power supply of the single-phase inverter is set as a power of two or a power of three. For example, the DC power supply voltages of all single-phase inverters do not need to be set as a power of two or a power of three. For example, a configuration may include single-phase inverters in which the DC power supply voltage ratio of the single-phase inverters is set as a power of two or a power of three, such as 1:1:3:9 or 1:3:9:9:9. Furthermore, the voltage ratio does not need to be set as a power of two or a power of three, and as long as there are single-phase inverters in which the constituent semiconductor switches have different withstand voltages, the DC power supply voltage ratio of the single-phase inverters may be set as 1:5:5 or 1:10:10, for example. Furthermore, the features of the power conversion device of the first embodiment can be applied as long as there are single-phase inverters in which the DC power supply voltages of all single-phase inverters are the same but the constituent semiconductor switches have different withstand voltages.

[0028] An example of a single-phase inverter in which the power supply voltage of the single-phase inverter is the same but the constituent semiconductor switches have different withstand voltages will be described. Due to constraints on the shape of the board on which the semiconductor switches of the single-phase inverter of the power conversion device are mounted, it is possible that the surge voltage during switching operation will be large for some single-phase inverters. In this case, it is necessary to use high-voltage semiconductor switches for the single-phase inverter with high surge voltages. In this case, low-voltage semiconductor switches are used in areas where the surge voltage is small, and high-voltage semiconductor switches are used in areas where the surge voltage is large, resulting in single-phase inverters with semiconductor switches of different withstand voltages. As such, the present disclosure can be applied to any circuit that includes a single-phase inverter configured with semiconductor switches of different withstand voltages.

[0029] As described above, the power conversion device of the first embodiment includes a single-phase inverter multi-series circuit configured with three or more single-phase inverters and supplying power to a load. The power conversion device includes a standard-voltage single-phase inverter, which is a single-phase inverter configured with semiconductor switches having a withstand voltage equal to or lower than a standard withstand voltage, and a high-voltage single-phase inverter, which is a single-phase inverter configured with semiconductor switches having a withstand voltage higher than the standard withstand voltage. The at least two high-voltage single-phase inverters are arranged with at least one standard-voltage single-phase inverter sandwiched between them or diagonally arranged. Therefore, the power conversion device of the first embodiment can achieve heat dispersion through structural innovation in a single-phase inverter multi-series circuit configured with three or more single-phase inverters. Dispersing heat enables the use of a smaller heat sink, thereby enabling the device to be more compact. Furthermore, the mounting area of ​​the single-phase inverter can be reduced. A smaller mounting area reduces wiring inductance due to wiring length. This reduces surge voltages generated by the switching operations of the semiconductor switches, which, when low-voltage semiconductor switches with good characteristics can be used, can further reduce heat generation.

[0030] Second Embodiment A power conversion device according to a second embodiment aims to dissipate heat by appropriately controlling the semiconductor switches of each single-phase inverter.

[0031] The power conversion device of embodiment 2 will be described, focusing on the differences from embodiment 1, with reference to Figures 4A and 4B which are explanatory diagrams of the operating states of a single-phase inverter, Figure 5 which is an operating state transition diagram of a single-phase inverter, Figure 19 which is an operating state transition diagram of a single-phase inverter, and Figures 20 to 26 which are explanatory diagrams of transition timings of a single-phase inverter. In the configuration diagram of embodiment 2, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals.

[0032] The operating states of the single-phase inverter INV(n) will be described based on the operating state diagrams of the single-phase inverter shown in FIGS. 4A to 4D. Each single-phase inverter INV(n) has the following four operating states (first control state, second control state, first conduction state, and second conduction state). In the first control state (see FIG. 4A), the control unit 20 turns on the semiconductor switches Q1(n) and Q3(n) and turns off the semiconductor switches Q2(n) and Q4(n). The first control state is a state in which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n). In the second control state (see FIG. 4B), the control unit 20 turns on the semiconductor switches Q2(n) and Q4(n) and turns off the semiconductor switches Q1(n) and Q3(n). The second control state is a state in which zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n). In the first conduction state (see FIG. 4C), the control unit 20 turns on the semiconductor switches Q1(n) and Q4(n) and turns off the semiconductor switches Q2(n) and Q3(n). In the first conduction state, a voltage of Vn is output between the first midpoint P1(n) and the second midpoint P2(n). In the second conduction state (see FIG. 4D), the control unit 20 turns on the semiconductor switches Q2(n) and Q3(n) and turns off the semiconductor switches Q1(n) and Q4(n). In the second conduction state, a voltage of -Vn is output between the first midpoint P1(n) and the second midpoint P2(n). In each figure, the thick solid lines indicate the paths along which current flows.

[0033] Next, the transition of the operating state of the single-phase inverter INV(n), particularly the transition (switching of selection) between the first control state and the second control state, which is a feature of the power conversion device of the second embodiment, will be described based on the operating state transition diagram of the single-phase inverter shown in FIG. 5 . The control unit 20 can arbitrarily select between the first control state and the second control state. By arbitrarily selecting between the first control state and the second control state, conduction loss, which is loss generated in the semiconductor switches, can be dispersed. As shown in FIG. 5 , the transition between the first control state and the second control state is basically performed via the first conduction state or the second conduction state. That is, the control state transition is performed after transition (switching of selection) to the first conduction state or the second conduction state at least once. By not directly transitioning from the first control state to the second control state (or from the second control state to the first control state), an increase in switching loss due to an increase in the number of switching operations of the semiconductor switching can be suppressed, and waveform distortion due to the dead time required during the transition can also be suppressed.

[0034] Next, a case where a direct transition between the first control state and the second control state is performed will be described with reference to Fig. 19. As shown in Fig. 19, the transition between the first control state and the second control state is performed without passing through the first conduction state or the second conduction state. When the period of the first control state or the period of the second control state is long (i.e., when no transition to the first conduction state or the second conduction state occurs), it is effective to perform this direct transition between the first control state and the second control state (i.e., switching of selection) at least once, thereby enabling effective heat dissipation.

[0035] Next, we will explain the timing and effect of the transition (switching of selection) from the first control state to the second control state (from the second control state to the first control state). The transition timing will be explained using the examples shown in Figures 20 to 26. Figures 20 to 26 show an example of the operation of INV(m), which outputs a voltage of magnitude V. For simplicity, in Figures 20 to 26, the output states (INV states) of the four INV(m) are labeled A to D, i.e., A for the first control state, B for the second control state, C for the first conductive state, and D for the second conductive state. Method (1): Method (1) switches the selection between the first control state and the second control state every control period of the control unit 20 or every integer multiple of the control period. In the example shown in Figure 20, the INV state when outputting zero voltage is switched between the first control state (A) and the second control state (B) every control period. Method (1) is a method that enables heat dissipation with a simple configuration. Method (2): Method (2) switches between the first and second control states at the cycle of the AC power waveform output to the load 10 or an integer multiple thereof. In the example shown in FIG. 21 , the INV state at zero voltage output is set to the first control state (A) during the first output power cycle, and then the INV state at zero voltage output is switched to the second control state (B) during the next output power cycle. Like method (1), method (2) enables heat dissipation with a simple configuration. Furthermore, as shown in FIG. 21 , method (3) enables equal heat dissipation even under conditions where the off time changes periodically. Method (3): Method (3) switches between the first and second control states after a certain time has elapsed. In the example shown in FIG. 22 , time is measured, and when a certain time has elapsed (when a threshold value has been reached), the INV state at zero voltage output is switched from the first control state (A) to the second control state (B). Like method (1), method (3) enables heat dissipation with a simple configuration. This method also allows for equal heat distribution even under conditions where the off time varies. Note that Figure 22 shows an example of a method that does not directly switch between the first control state (A) and the second control state (B). Therefore, the first control state (A) and the second control state (B) are switched after passing through the first conduction state (C).In FIG. 22 , time measurement begins when the measurement time reaches a threshold value and the state switches to the first conduction state (C). However, the timing of measurement is not limited to this. For example, measurement may begin immediately upon reaching the threshold value, or upon switching to the second control state (B). Method (4): Method (4) measures the time during the first or second control state, and switches between the first and second control states when the total time reaches a certain value. In the example shown in FIG. 23 , the time during zero voltage output is measured, and once a certain time (threshold value) is reached, the INV state during zero voltage output is switched from the first control state (A) to the second control state (B). Compared to method (3), method (4) allows for more even distribution of off-time between the first and second control states, enabling more precise heat dissipation. Note that FIG. 23 illustrates an example of a method that does not directly switch between the first control state (A) and the second control state (B). Method (5): Method (5) switches between the first and second control states when the output voltage and current waveforms output to the load 10 reach zero current or zero voltage. In the example shown in FIG. 24 , the INV state during zero voltage output is switched from the first control state (A) to the second control state (B) when the output current reaches zero. Method (5) reduces losses in the semiconductor switch through zero-current switching or zero-voltage switching. Methods (1) to (5) can be freely combined. For example, method (3) may be used under certain output conditions, and method (2) may be used when the output conditions change. For example, method (1) may be normally used, and when a timing allowing switching to method (5) occurs, method (5) may be used.

[0036] Methods (1) to (5) can be applied both to cases where the transition between the first and second control states is performed directly and cases where it is not performed directly. Method (4) will be used as an example. Figure 25 illustrates a case where the transition between the first and second control states is not performed directly. The transition is performed after a predetermined time has elapsed and then after switching to another state. Figure 26 illustrates a case where the transition between the first and second control states is performed directly. The transition is performed immediately after a predetermined time has elapsed. When the zero voltage output time shown in Figures 23 and 24 is long, not performing direct switching would result in a longer time in the first or second control state, potentially resulting in concentrated heat generation. Therefore, direct switching is desirable when the zero voltage output time is long. Conversely, performing direct switching in the example of Figure 23 would increase the number of switching cycles and increase heat generation due to switching losses, so it is preferable not to perform switching. The decision on whether to perform direct switching should be made after taking into consideration the heat generation caused by an increased number of switching cycles and the heat concentration caused by maintaining the same control state.

[0037] The above-described switching of the control unit 20 is targeted for the operation during a period excluding the dead time period. Specifically, assuming that the semiconductor switch is a MOSFET, the switching operation of the control unit 20 is defined for the period during which the semiconductor switch is on and the gate voltage is applied between the gate and source of the MOSFET to turn the MOSFET on.

[0038] Although not specifically described in this embodiment, when transitioning from one control state or conduction state to another, a dead time period is inserted in which the upper and lower MOSFETs are simultaneously turned off to prevent short-circuiting of the semiconductor switches arranged above and below. The current path during this dead time period is determined by the direction of the current. It may form a current path different from the first and second control states and the first and second conduction states, or it may be the same path as the first and second control states or the first and second conduction states. For example, when a direct state transition is made from the first control state to the second control state, a period during the dead time period may occur in which the current path is the same as the first conduction state or the second conduction state.

[0039] In this embodiment, the switching operation of the control unit 20 covers a period excluding the dead time period. In the example of switching from the first control state to the second control state described above, even if the first conduction state or the second conduction state is entered during the dead time, it is treated as switching from the first control state to the second control state. The reason for excluding the dead time period is that the dead time period is generally sufficiently short compared to the on-time and off-time, and can be considered not to contribute to the heat dissipation that is the subject of this discussion. Note that if the proportion of the dead time period is large and operation during the dead time period affects heat dissipation, the switching operation of the control unit may be performed including the dead time state.

[0040] As described above, the power conversion device of the second embodiment achieves heat dissipation by appropriately controlling the semiconductor switches of each single-phase inverter. Therefore, the power conversion device of the second embodiment can achieve heat dissipation by ingeniously designing the structure in a single-phase inverter multi-series circuit consisting of three or more single-phase inverters. Furthermore, by appropriately controlling the semiconductor switches of each single-phase inverter, heat dissipation can be achieved.

[0041] Third Embodiment A power conversion device according to a third embodiment aims to dissipate heat from the semiconductor switches of a single-phase inverter by appropriately arranging the semiconductor switches.

[0042] The power conversion device of embodiment 3 will be described, focusing on the differences from embodiment 1, based on Figures 6A to 6C which are semiconductor switch layout diagrams (basic layout) of a single-phase inverter, Figures 7A to 7D which are semiconductor switch layout diagrams (single-row layout) of a single-phase inverter, Figures 8A to 8C which are semiconductor switch layout diagrams (L-shaped layout) of a single-phase inverter, Figures 8D and 8E which are semiconductor switch layout diagrams (two-row layout) of a single-phase inverter, and Figures 9A to 9F which are semiconductor switch layout diagrams (modified example) of a single-phase inverter. In the configuration diagrams of embodiment 3, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals.

[0043] In the power conversion device of the third embodiment, when semiconductor switches are arranged in one single-phase inverter INV(n), an appropriate arrangement method for achieving heat dispersion will be described.

[0044] The present disclosure is characterized by arranging the semiconductor switches Q1(n) and Q3(n), through which a current flows in the first control state of the single-phase inverter INV(n), and the semiconductor switches Q2(n) and Q4(n), through which a current flows in the second control state, at a distance from each other to disperse heat. The basic layout of the semiconductor switches in this disclosure is shown in FIGS. 6A to 6C. FIG. 6A shows an arrangement in which the semiconductor switches are arranged in a single row. By sandwiching the semiconductor switch Q2(n) or Q4(n), through which a current flows in the second control state, between the semiconductor switches Q1(n) and Q3(n), through which a current flows in the first control state, the distance between the semiconductor switches that generate heat in the same control state can be increased. FIG. 6B shows an arrangement in which the semiconductor switches are arranged in two rows. The semiconductor switches Q1(n) and Q3(n) or the semiconductor switches Q2(n) and Q4(n) are arranged at diagonal corners of a rectangle with the semiconductor switches as vertices. This allows the distance between semiconductor switches that generate heat under the same control state to be increased. Figure 6C shows an arrangement method in an L-shape. Semiconductor switch Q2(n) or semiconductor switch Q4(n) is arranged at the corner of the L-shape, and semiconductor switch Q1(n) and semiconductor switch Q3(n) are arranged at the remaining part of the L-shape. This allows the distance between semiconductor switches that generate heat under the same control state to be increased. In this second embodiment, by selecting and combining the three arrangement methods described above, the distance between semiconductor switches that generate heat under the same control state is increased, thereby achieving heat dispersion. Note that, due to the possibility of dielectric breakdown and short circuits, semiconductor switches are generally arranged with a space between them, rather than arranged so that one side of each semiconductor switch touches another side, as shown in Figures 7A to 7D (described later). For simplicity, the space between the switches is ignored in the description in this disclosure. Note that the shape of the semiconductor switches does not have to be square as shown in the figure, and can be modified depending on the package shape of the semiconductor switch.

[0045] Below, we will explain examples of combinations and variations of the above three arrangement methods. Figures 7A to 7D show arrangement examples when four semiconductor switches are arranged in a row. In all of Figures 7A to 7D, semiconductor switch Q2(n) or Q4(n) is arranged between semiconductor switch Q1(n) and semiconductor switch Q3(n), and semiconductor switch Q1(n) and semiconductor switch Q3(n) are arranged between semiconductor switch Q2(n) and semiconductor switch Q4(n). This makes it possible to increase the distance between semiconductor switches that generate heat under the same control state.

[0046] 8A to 8C are examples of arrangements in which four semiconductor switches are arranged in an L-shape. FIG. 8A is an example of a combination of a linear arrangement and an L-shape arrangement, in which semiconductor switch Q2(n) is arranged at the corner of the L-shape, thereby spacing semiconductor switch Q1(n) and semiconductor switch Q3(n). Furthermore, semiconductor switch Q3(n) is sandwiched between semiconductor switch Q2(n) and semiconductor switch Q4(n), spacing semiconductor switch Q2(n) and semiconductor switch Q4(n). FIG. 8B is also an example of a combination of a linear arrangement and an L-shape arrangement. This differs from FIG. 8A in that semiconductor switch Q3(n) is arranged at the corner of the L-shape, but like FIG. 8A, the distance between semiconductor switches that generate heat under the same control state can be increased. FIG. 8C is an example of a combination of an L-shape arrangement and an L-shape arrangement. By combining an L-shape arrangement in which semiconductor switch Q2(n) is arranged at the corner with an L-shape arrangement in which semiconductor switch Q3(n) is arranged at the corner, the distance between semiconductor switches that generate heat under the same control state can be increased.

[0047] 8D and 8E show examples of arrangements when four semiconductor switches are arranged in two rows. In both Figures 8D and 8E, semiconductor switch Q1(n) and semiconductor switch Q3(n) or semiconductor switch Q2(n) and semiconductor switch Q4(n) are arranged diagonally on the corners of a rectangle with the semiconductor switches as vertices. This allows the distance between semiconductor switches that generate heat under the same control state to be increased.

[0048] 9A to 9F are diagrams showing modified examples of FIGS. 7A to 7D and 8A to 8E. Even if the semiconductor switches are offset vertically or horizontally, or even if the spacing between the semiconductor switches is not constant, they can be considered to be arranged in a single row, a double row, or an L-shape. Although FIG. 5A is described as a single row arrangement, it can also be considered as a linear arrangement. Furthermore, although FIG. 5B is described as a double row arrangement, it can also be considered as a square, rectangle, or parallelogram.

[0049] As described above, the power conversion device of the third embodiment aims to dissipate heat from the semiconductor switches by appropriately arranging the semiconductor switches of the single-phase inverter. Therefore, the power conversion device of the third embodiment can achieve heat dissipation by ingeniously designing the structure in a single-phase inverter multi-series circuit composed of three or more single-phase inverters. Furthermore, heat dissipation can be achieved by appropriately arranging the semiconductor switches of the inverters.

[0050] Fourth Embodiment A power conversion device according to a fourth embodiment selects between a first control state and a second control state among a plurality of single-phase inverters, and aims to dissipate heat by appropriately arranging semiconductor switches in the plurality of single-phase inverters.

[0051] The power conversion device of embodiment 4 will be described, focusing on the differences from embodiment 1, based on Figures 10A and 10B which are explanatory diagrams of the operating states of multiple single-phase inverters (current paths coincident), Figures 11A and 11B which are explanatory diagrams of the operating states of multiple single-phase inverters (current paths inverted), Figures 12A, 12B, 13A, 13B, 14A, and 14B which are semiconductor switch layout diagrams of multiple single-phase inverters (current paths coincident), and Figures 15A, 15B, 16A, 16B, 17A, and 17B which are semiconductor switch layout diagrams of multiple single-phase inverters (current paths inverted). In the configuration diagrams of embodiment 4, parts that are the same as or equivalent to those of embodiment 1 are given the same reference numerals.

[0052] In the power conversion device of the fourth embodiment, two single-phase inverters INV(i) and INV(k) will be described. Note that i and k are integers between 1 and N, and i≠k holds true. In a power conversion device configured with two or more single-phase inverters INV(n), the zero voltage output state (first control state and second control state) of one single-phase inverter INV(i) is linked to the zero voltage output state of another single-phase inverter INV(k). In this case, the single-phase inverters INV(i) and INV(k) may select the same zero voltage output state (current path coincidence) or may select opposite zero voltage output states (current path reversal).

[0053] First, the case where the single-phase inverters INV(i) and INV(k) select the same zero-voltage output state (current path coincidence) will be described with reference to Figures 10A and 10B. Specifically, when the single-phase inverter INV(i) selects the first control state, the single-phase inverter INV(k) also selects the first control state, and when the single-phase inverter INV(i) selects the second control state, the single-phase inverter INV(k) also selects the second control state. In Figure 10A, both the single-phase inverters INV(i) and INV(k) select the first control state. In Figure 10B, both the single-phase inverters INV(i) and INV(k) select the second control state.

[0054] A case where the single-phase inverters INV(i) and INV(k) select opposite zero-voltage output states (current path reversal) will be described with reference to FIGS. 11A and 11B . Specifically, when the single-phase inverter INV(i) selects the first control state, the single-phase inverter INV(k) selects the second control state, and when the single-phase inverter INV(i) selects the second control state, the single-phase inverter INV(k) selects the first control state. In FIG. 11A , the single-phase inverter INV(i) selects the first control state, and the single-phase inverter INV(k) selects the second control state. In FIG. 11B , the single-phase inverter INV(i) selects the second control state, and the single-phase inverter INV(k) selects the first control state. By selecting the first control state and the second control state for multiple single-phase inverters as described above, the control unit 20 can easily select the first control state and the second control state. This simplifies the process. This reduces the load on the control unit 20.

[0055] Furthermore, by appropriately arranging the semiconductor switches in multiple single-phase inverters, heat can be dispersed. In either case, in the single-phase inverter INV(i) and the single-phase inverter INV(k), the semiconductor switches that simultaneously generate heat are arranged at a distance from each other to prevent the heat from concentrating in the semiconductor switches. Methods for arranging the semiconductor switches at a distance include the single-row arrangement, double-row arrangement, and L-shaped arrangement described in the third embodiment. This embodiment is characterized by extending and applying the single-row arrangement, double-row arrangement, and L-shaped arrangement, or a combination thereof, to two INV(i) and INV(k).

[0056] First, we will explain the arrangement of the semiconductor switches when the single-phase inverters INV(i) and INV(k) select the same zero-voltage output state (current path coincidence). For example, assume that both single-phase inverters INV(i) and INV(k) select the first control state. In this case, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) also generate heat. For example, assume that both single-phase inverters INV(i) and INV(k) select the second control state. In this case, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) also generate heat. For this reason, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) are arranged at a distance from each other.

[0057] As a specific example of a case where single-phase inverters INV(i) and INV(k) select the same zero-voltage output state (current path coincidence), an example of the arrangement of the semiconductor switches of single-phase inverter INV(i) and the semiconductor switches of single-phase inverter INV(k) is described with reference to Figures 12A, 12B, 13A, 13B, 14A, and 14B. In Figure 12A, the semiconductor switches of single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are also arranged in a row. Semiconductor switches Q4(i) and Q2(k), which generate heat at the same time, can be separated by sandwiching semiconductor switch Q1(k) between them. Similarly, semiconductor switches Q3(i) and Q1(k), which generate heat at the same time, can be separated by sandwiching semiconductor switch Q4(i) between them. 12B shows the semiconductor switches of the single-phase inverters INV(i) and INV(k) arranged in a single row, with the single-phase inverters INV(i) and INV(k) arranged in two rows. The semiconductor switches Q1(i) and Q3(k) and the semiconductor switches Q2(i) and Q4(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q3(k) and the semiconductor switches Q2(i) and Q2(k) which generate heat simultaneously are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q1(k) and the semiconductor switches Q4(i) and Q2(k) which generate heat simultaneously are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart.

[0058] In FIG. 13A, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are arranged at a right angle (L-shape). By placing semiconductor switch Q1(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q2(k), which generate heat at the same time, can be increased. In FIG. 13B, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in a row, and the single-phase inverters INV(i) and INV(k) are arranged in two rows, but with a staggered arrangement. By placing semiconductor switch Q3(i) at the corner of the L-shape, the distance between semiconductor switch Q2(i) and semiconductor switch Q4(k), which generate heat at the same time, can be increased. Furthermore, by placing semiconductor switch Q3(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q2(k), which generate heat at the same time, can be increased. Furthermore, semiconductor switches Q3(i) and Q3(k) and semiconductor switches Q4(i) and Q4(k), which generate heat at the same time, can be placed at diagonal corners of a rectangle with the semiconductor switches as vertices, thereby allowing them to be placed at a distance from each other.

[0059] In Figure 14A, the semiconductor switches of the single-phase inverters INV(i) and INV(k) are arranged in two rows, and the single-phase inverters INV(i) and INV(k) are arranged in a single row. The semiconductor switches Q2(i) and Q4(k), and the semiconductor switches Q3(i) and Q1(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing for spacing between them. In Figure 14B, the semiconductor switches of the single-phase inverter INV(i) are arranged in a single row, and the semiconductor switches of INV(k) are arranged in two rows, and the single-phase inverters INV(i) and INV(k) are arranged in a single row. By arranging the semiconductor switch Q1(k) at the corner of an L, the distance between the semiconductor switches Q4(i) and Q2(k), which generate heat simultaneously, can be increased.

[0060] 12A, 12B, 13A, 13B, 14A, and 14B are merely examples, and the single-phase inverters may be arranged in a single row, a double row, or an L-shape. The single-phase inverters may also be arranged in a single row, a double row, an L-shape, or offset. Although not shown, the spacing does not have to be constant. The semiconductor switches within the same single-phase inverter are arranged so that heat-generating semiconductor switches are spaced apart, as described in the third embodiment.

[0061] Next, the arrangement of the semiconductor switches when the single-phase inverters INV(i) and INV(k) select the opposite zero-voltage output state (current path reversal) will be described. For example, assume that the single-phase inverter INV(i) selects the first control state and INV(k) selects the second control state. In this case, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k) generate heat. Therefore, the semiconductor switches Q1(i) and Q3(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switches Q2(k) and Q4(k) of the single-phase inverter INV(k). For example, assume that the single-phase inverter INV(i) selects the second control state and INV(k) selects the first control state. In this case, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) generate heat, and the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k) also generate heat. For this reason, the semiconductor switches Q2(i) and Q4(i) of the single-phase inverter INV(i) are arranged at a distance from the semiconductor switches Q1(k) and Q3(k) of the single-phase inverter INV(k).

[0062] As a specific example of a case where the single-phase inverters INV(i) and INV(k) select different zero-voltage output states (current path reversal), examples of the arrangement of the semiconductor switches of the single-phase inverter INV(i) and the semiconductor switches of the single-phase inverter INV(k) are shown in Figures 15A, 15B, 16A, 16B, 17A, and 17B. In Figure 15A, the single-phase inverters INV(i) and INV(k) are arranged in a line, with the semiconductor switches arranged in different orders in a straight line. The semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(k) between them. Similarly, the semiconductor switches Q3(i) and Q4(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(i) between them. In Figure 15B, single-phase inverters INV(i) and INV(k) are arranged in a line, with semiconductor switches arranged in different orders in a straight line. However, the order of the semiconductor switches in single-phase inverter INV(k) is changed from that in Figure 14A. The semiconductor switches Q4(i) and Q1(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q2(k) between them. Similarly, the semiconductor switches Q3(i) and Q2(k), which generate heat at the same time, can be separated by sandwiching the semiconductor switch Q4(i) between them.

[0063] 16A shows single-phase inverters INV(i) and INV(k) arranged in two rows, with semiconductor switches arranged in different orders in one row. The semiconductor switches Q1(i) and Q4(k), and the semiconductor switches Q2(i) and Q1(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q2(i) and Q3(k), and the semiconductor switches Q3(i) and Q4(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q2(k), and the semiconductor switches Q4(i) and Q3(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. In Figure 16B, single-phase inverters INV(i) and INV(k) are arranged in two rows, with the semiconductor switches arranged in a different order in one row. However, the order of the semiconductor switches in the single-phase inverter INV(k) is changed from that in Figure 15A. The semiconductor switches Q1(i) and Q2(k), and the semiconductor switches Q2(i) and Q1(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q2(i) and Q3(k), and the semiconductor switches Q3(i) and Q2(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart. Similarly, the semiconductor switches Q3(i) and Q4(k), and the semiconductor switches Q4(i) and Q3(k), which generate heat simultaneously, are arranged diagonally in a rectangle with the semiconductor switches as vertices, allowing them to be spaced apart.

[0064] In FIG. 17A, single-phase inverters INV(i) and INV(k), each having semiconductor switches arranged in a row with different arrangement orders, are arranged at a right angle (L-shape). By arranging semiconductor switch Q4(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q1(k), which generate heat at the same time, can be increased. In FIG. 17B, single-phase inverters INV(i) and INV(k), each having semiconductor switches arranged in a row with different arrangement orders, are arranged at a right angle (L-shape). However, the arrangement order of the semiconductor switches of single-phase inverter INV(k) is changed from that of FIG. 16A. By arranging semiconductor switch Q2(k) at the corner of the L-shape, the distance between semiconductor switch Q4(i) and semiconductor switch Q3(k), which generate heat at the same time, can be increased.

[0065] As described above, the power conversion device of embodiment 4 controls the selection of the first control state and the second control state in multiple single-phase inverters as current path coincidence or current path reversal, thereby simplifying the calculation processing of the controller and dissipating heat. Furthermore, heat dissipation is achieved by appropriately arranging the semiconductor switches in the multiple single-phase inverters. Therefore, the power conversion device of embodiment 4 can achieve heat dissipation by ingeniously designing the structure in a single-phase inverter multi-series circuit composed of three or more single-phase inverters. Furthermore, heat dissipation can be further achieved by appropriately arranging the semiconductor switches in the multiple single-phase inverters.

[0066] The control unit 20 is configured with a processor 1000 and a storage device 1001, as shown in FIG. 18 , which illustrates an example of hardware. The storage device 1001 includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory, both not shown. Alternatively, a hard disk auxiliary storage device may be provided instead of the flash memory. The processor 1000 executes a program input from the storage device 1001. In this case, the program is input to the processor 1000 from the auxiliary storage device via the volatile storage device. The processor 1000 may output data such as calculation results to the volatile storage device of the storage device 1001, or may store the data in the auxiliary storage device via the volatile storage device.

[0067] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment.

[0068] 1 inverter unit, 10 load, 20 control unit, 100 power conversion device, 1000 processor, 1001 storage device, SV standard voltage single-phase inverter, HV high voltage single-phase inverter, INV(1), INV(2), INV(3), INV(i), INV(k), INV(n), INV(N) Single-phase inverter, Q1(1), Q2(1), Q3(1), Q4(1), Q1(2), Q2(2), Q3(2), Q4(2), Q1(3), Q2(3), Q3(3), Q4(3), Q1(4), Q2(4), Q3(4), Q4(4), Q1(i), Q2(i), Q3(i), Q4(i), Q1(k), Q2(k), Q3(k), Q4(k), Q1(n), Q2(n), Q3(n), Q4(n), Q1(N), Q2(Nn), Q3(N), Q4(N) Semiconductor switches, V(1), V(2), V(3), V(n), V(N) DC power supply, P1 (1), P1 (2), P1 (3), P1 (n), P1 (N) first midpoint, P2 (1), P2 (2), P2 (3), P2 (n), P2 (N) second midpoint.

Claims

1. N is an integer of 3 or more, and n is an integer of 1 to N, inclusive, in a power conversion device in which N single-phase inverters are connected in series, the power conversion device comprising: a single-phase inverter INV(n) in which one end of a semiconductor switch Q1(n) and one end of a semiconductor switch Q3(n) are connected to a high-potential terminal of a DC power source V(n), one end of a semiconductor switch Q2(n) and one end of a semiconductor switch Q4(n) are connected to a low-voltage terminal of the DC power source V(n), the other end of the semiconductor switch Q1(n) and the other end of the semiconductor switch Q2(n) are connected in series at a first midpoint P1(n), and the other end of the semiconductor switch Q3(n) and the other end of the semiconductor switch Q4(n) are connected in series at a second midpoint P2(n); a control unit that controls the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n), wherein, when a withstand voltage of a semiconductor switch in at least one of the single-phase inverters INV(n) is taken as a reference withstand voltage, in addition to a reference withstand voltage single-phase inverter that is a single-phase inverter having a semiconductor switch with a withstand voltage equal to or lower than the reference withstand voltage, the withstand voltages of the semiconductor switches in at least two of the single-phase inverters are composed of high-voltage semiconductor switches that are semiconductor switches with a withstand voltage higher than the reference withstand voltage, and the at least two high-voltage single-phase inverters composed of the high-voltage semiconductor switches are arranged with at least one of the standard withstand voltage single-phase inverters sandwiched between them, or are arranged on each of two sides of an L shape having at least one of the standard withstand voltage single-phase inverters as a corner.

2. The power conversion device according to claim 1, including a DC power supply having an output voltage of at least 2V or 3V, where V is the minimum value of the output voltage of the DC power supply.

3. The power conversion device according to claim 2, wherein the output voltage of said DC power supply is either a power of two or a power of three times the minimum output voltage of said DC power supply.

4. The power conversion device according to any one of claims 1 to 3, wherein at least one of the high-voltage single-phase inverters has the maximum output voltage of the DC power supply.

5. A power conversion device according to any one of claims 1 to 4, wherein the high-voltage single-phase inverter is the single-phase inverter whose output voltage from the DC power supply is maximum and the single-phase inverter whose output voltage is the second largest after the maximum voltage.

6. The control unit controls the semiconductor switches Q1(n) and Q3(n) to a first control state in which the semiconductor switches Q1(n) and Q3(n) are turned on and the semiconductor switches Q2(n) and Q4(n) are turned off, and a second control state in which the semiconductor switches Q2(n) and Q4(n) are turned on and the semiconductor switches Q1(n) and Q3(n) are turned off, and the control unit controls the semiconductor switches Q1(n) and Q4(n) to a first conduction state in which the semiconductor switches Q1(n) and Q4(n) are turned on and the semiconductor switches Q2(n) and Q3(n) are turned off, and a second conduction state in which the semiconductor switches Q2(n) and Q3(n) are turned on and the semiconductor switches Q1(n) and Q4(n) are turned off, and in at least one of the single-phase inverters INV(n), 6. The power conversion device according to claim 1, wherein when a zero voltage is output between the first midpoint P1(n) and the second midpoint P2(n), either the first control state or the second control state is selected.

7. The power conversion device according to claim 6, wherein for at least one of the single-phase inverters INV(n), at least three of the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) are arranged in a row, and either the semiconductor switch Q2(n) or the semiconductor switch Q4(n) is arranged between the semiconductor switch Q1(n) and the semiconductor switch Q3(n), or either the semiconductor switch Q1(n) or the semiconductor switch Q3(n) is arranged between the semiconductor switch Q2(n) and the semiconductor switch Q4(n).

8. The power conversion device according to claim 6, wherein, for at least one of the single-phase inverters INV(n), the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) are arranged in two rows, and the semiconductor switch Q1(n) and the semiconductor switch Q3(n), and the semiconductor switch Q2(n) and the semiconductor switch Q4(n) are arranged at diagonal corners of a rectangle having each of the semiconductor switches as its vertices.

9. The power conversion device according to claim 6, wherein, for at least one of the single-phase inverters INV(n), at least three of the semiconductor switch Q1(n), the semiconductor switch Q2(n), the semiconductor switch Q3(n), and the semiconductor switch Q4(n) are arranged in an L-shape, with the semiconductor switch Q1(n) or the semiconductor switch Q3(n) being arranged at a corner of the L-shape and the semiconductor switch Q2(n) or the semiconductor switch Q4(n) being arranged on two different sides of the L-shape; or the semiconductor switch Q2(n) or the semiconductor switch Q4(n) being arranged at a corner of the L-shape and the semiconductor switch Q1(n) or the semiconductor switch Q3(n) being arranged on two different sides of the L-shape.

10. n is at least i or k, and there is a relationship of i≠k, and there exists a state in which at least two of the single-phase inverters INV(n) simultaneously output zero voltage between the first midpoint P1(n) and the second midpoint P2(n), and for one single-phase inverter INV(i) outputting the zero voltage and another single-phase inverter INV(k) outputting the zero voltage, at least some of the semiconductor switches Q1(i), Q2(i), Q3(i), and Q4(i) of the single-phase inverter INV(i) are arranged in a single row, a double row, or an L-shaped arrangement, and at least some of the semiconductor switches Q1(k), Q2(k), Q3(k), and Q4(k) of the single-phase inverter INV(k) are arranged in a single row, a double row, or an L-shaped arrangement, and when the single-phase inverter INV(i) and the single-phase inverter INV(k) output the zero voltage, When one of the single-phase inverters INV(i) selects the first control state, the other of the single-phase inverters INV(k) also selects the first control state; when one of the single-phase inverters INV(i) selects the second control state, the other of the single-phase inverters INV(k) also selects the second control state, when the first control state is selected, the semiconductor switches Q1(n) and Q3(n) of the single-phase inverter INV(n) generate heat; when the second control state is selected, the semiconductor switches Q2(n) and Q4(n) of the single-phase inverter INV(n) generate heat; at least some of the semiconductor switches of one of the single-phase inverters INV(n) and the semiconductor switches of the other of the single-phase inverters INV(n) are arranged in a single row, a double row, or an L-shaped arrangement; 10. The power conversion device according to claim 6, wherein, in an arrangement between different single-phase inverters INV(n), the semiconductor switches that generate heat in the first control state or the second control state that are simultaneously selected are arranged so as to sandwich the other semiconductor switch that generates heat in the first control state or the second control state therebetween, so that the semiconductor switches that generate heat in the first control state or the second control state that are simultaneously selected are not adjacent to each other.

11. n is at least i or k, and there is a relationship of i≠k, there exists a state in which at least two single-phase inverters INV(n) simultaneously generate (output) zero voltage between the first midpoint P1(n) and the second midpoint P2(n), and for one single-phase inverter INV(i) that outputs the zero voltage and another single-phase inverter INV(k) that outputs the zero voltage, at least some of the semiconductor switches Q1(i), Q2(i), Q3(i), and Q4(i) of the single-phase inverter INV(i) are arranged in a single row, a double row, or an L-shaped arrangement, and at least some of the semiconductor switches Q1(k), Q2(k), Q3(k), and Q4(k) of the single-phase inverter INV(k) are arranged in a single row, a double row, or an L-shaped arrangement, 10. The power conversion device according to claim 6, wherein, when the single-phase inverter INV(i) and the single-phase inverter INV(k) output the zero voltage, when the first control state is selected, the semiconductor switches Q1(n) and Q3(n) of the single-phase inverter INV(n) generate heat, and when the second control state is selected, the semiconductor switches Q2(n) and Q4(n) of the single-phase inverter INV(n) generate heat, at least some of the semiconductor switches of one of the single-phase inverters INV(n) and the semiconductor switches of the other single-phase inverter INV(n) are arranged in a single row, a double row, or an L-shaped arrangement, and in an arrangement between different single-phase inverters INV(n), the semiconductor switches that generate heat in the first control state or the second control state that are simultaneously selected are arranged so that the other semiconductor switch that generates heat in the first control state or the second control state is sandwiched therebetween so that the semiconductor switches that generate heat in the first control state or the second control state that are simultaneously selected are not adjacent to each other.

12. The power conversion device according to any one of claims 6 to 11, wherein the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters every control period of the control unit or every integral multiple of the control period.

13. The power conversion device according to any one of claims 6 to 11, wherein in the single-phase inverters from which AC power is supplied to the load, the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters at intervals of an integer multiple of a period of the waveform of the AC power output from one or more of the single-phase inverters to the load.

14. The power conversion device according to any one of claims 6 to 11, wherein the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters after a certain period of time has elapsed.

15. The power conversion device according to claim 14, wherein the control unit switches the selection of the first control state or the second control state when the total time during which the first control state or the second control state is selected for at least one of the single-phase inverters matches the certain time.

16. The power conversion device according to any one of claims 6 to 11, wherein in a single-phase inverter in which AC power is supplied to the load, the control unit switches the selection between the first control state and the second control state for at least one of the single-phase inverters when the waveform supplied to the load is zero current or zero voltage.

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