Image sensor

Abstract

In this image sensor having a laminated structure, a circuit scale of a semiconductor chip which does not correspond to a light-receiving side is reduced.　A light-receiving region and a light-shielding region are provided to the light-receiving surface of a light-receiving chip. In the light-receiving region, at least a part of a first gradation pixel which generates, as a gradation signal, an analog signal having a voltage corresponding to an incident light amount and a part of a first detection pixel which detects whether a change amount of luminance exceeds a prescribed threshold value are arranged. In the light-shielding region, at least a part of a second gradation pixel and an invalidated second detection pixel are arranged. In a circuit chip, a remaining circuit of the first detection pixel and an analog-digital converter for converting the gradation signal into a digital signal are disposed.

Description

Image Sensor

[0001] The present technology relates to an image sensor, and more particularly to an image sensor that compares a change in luminance with a threshold value.

[0002] In recent years, in various fields such as transportation and robotics, there has been progress in the development and research of sensors that detect, for each pixel, an address event when a change in luminance exceeds a threshold. Such sensors are called dynamic vision sensors (DVS) or event-based vision sensors (EVS). For example, an image sensor has been proposed that detects an address event for each pixel and also generates a grayscale signal (see, for example, Non-Patent Document 1). This image sensor has a stacked structure in which multiple semiconductor chips are stacked, with some of the pixels located on the light-receiving (i.e., upper) semiconductor chip and the rest located on the lower semiconductor chip.

[0003] Atsumi Niwa, et al., A 2.97μm-Pitch Event-Based Vision Sensor with Shared Pixel Front-End Circuitry and Low-Noise Intensity Readout Mode, ISSCC 2023.

[0004] In the above-mentioned conventional technology, image data is generated by arranging grayscale signals by detecting address events for each pixel and generating grayscale signals. However, in the above-mentioned image sensor, part of the circuit for each pixel must be placed on the lower semiconductor chip, making it difficult to reduce the circuit scale of the semiconductor chip.

[0005] This technology was developed in light of these circumstances, and aims to reduce the circuit scale of semiconductor chips that do not correspond to the light-receiving side in stacked image sensors.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor including: a light-receiving chip having a light-receiving surface provided with a light-receiving region in which at least some of first gradation pixels that generate analog signals of voltages corresponding to the amount of incident light as gradation signals and some of first detection pixels that detect whether a change in luminance has exceeded a predetermined threshold are arranged, and a light-shielding region in which at least some of second gradation pixels and disabled second detection pixels are arranged, and a circuit chip having arranged thereon the remaining circuits of the first detection pixels and an analog-to-digital converter that converts the gradation signals into digital signals, thereby achieving the effect of reducing the circuit scale of the circuit chip.

[0007] In addition, in this first aspect, the first detection pixel may include a first current-voltage converter that converts a current signal into a voltage signal, a buffer that outputs the voltage signal, a subtractor that reduces the level of the voltage signal from the buffer, and a quantizer that quantizes the voltage signal from the subtractor to output a detection signal, wherein a part of the first current-voltage converter is arranged on the light-receiving chip, and the remaining circuit of the first current-voltage converter, the buffer, the subtractor, and the quantizer are arranged on the circuit chip. This brings about the effect that the circuits in the detection pixel are distributed and arranged on the light-receiving chip and the circuit chip.

[0008] In the first aspect, the second detection pixel may include a second current-voltage converter that converts a current signal into a voltage signal, thereby reducing the circuitry below the light-shielded area.

[0009] In addition, in this first aspect, each of the first gradation pixel and the second gradation pixel may include a photoelectric conversion element, a transfer transistor that transfers charge from the photoelectric conversion element to a floating diffusion layer in accordance with a transfer signal, an amplification transistor that outputs a voltage corresponding to the voltage of the floating diffusion layer, and a selection transistor that outputs a voltage signal from the amplification transistor to a vertical signal line in accordance with a selection signal, thereby producing an effect of generating a gradation signal.

[0010] In addition, in this first aspect, the photoelectric conversion element and the transfer transistor may be disposed on the light receiving chip, and the amplification transistor and the selection transistor may be disposed on the circuit chip, thereby providing an effect of reducing the circuit scale of the light receiving chip.

[0011] In addition, in this first aspect, the circuit chip may include first and second circuit chips stacked together, the amplifier transistor and the select transistor being disposed on the first circuit chip, and the analog-to-digital converter being disposed on the second circuit chip, thereby providing the effect of reducing the circuit scale of each chip.

[0012] In addition, in the first aspect, a plurality of effective pixels may be arranged in the light receiving region in a two-dimensional lattice pattern, and each of the effective pixels may include the first gradation pixel and the first detection pixel, thereby providing an effect of detecting an address event for each pixel.

[0013] In addition, in this first aspect, a predetermined number of pixel blocks may be arranged in the light receiving region, and each of the pixel blocks may include a predetermined number of the first gradation pixels and the first detection pixels, thereby providing an effect of periodically arranging the gradation pixels.

[0014] In addition, in this first aspect, the second detection pixel may include a current-voltage converter that converts a current signal into a voltage signal and a dummy circuit, the current-voltage converter being disposed on the light-receiving chip and the dummy circuit being disposed on the circuit chip, thereby improving the accuracy of OPB (optical black) correction.

[0015] In the first aspect, the dummy circuit may include a diode-connected pMOS (p-channel Metal Oxide Semiconductor) transistor, thereby improving the accuracy of OPB correction.

[0016] In this first aspect, the dummy circuit may include a pMOS transistor having a gate connected to a power supply voltage, thereby improving the accuracy of OPB correction.

[0017] In the first aspect, the dummy circuit may include a diode-connected nMOS (n-channel MOS) transistor, thereby improving the accuracy of OPB correction.

[0018] In this first aspect, the dummy circuit may include an nMOS transistor having a gate connected to a ground voltage, thereby improving the accuracy of OPB correction.

[0019] In addition, in this first aspect, a plurality of second detection pixels may be arranged in the light-shielding region, each of the plurality of second detection pixels may include a current-voltage converter that converts a current signal into a voltage signal, the current-voltage converters of the plurality of second detection pixels may be connected in common to a dummy circuit, the current-voltage converters may be arranged on the light-receiving chip, and the dummy circuit may be arranged on the circuit chip, thereby achieving an effect of reducing the circuit size compared to a case where a common circuit is not used.

[0020] In this first aspect, the dummy circuit may include a disabled current source, which provides the effect of reducing the circuit size compared to a case where the current source is not shared.

[0021] In this first aspect, the dummy circuit may further include an nMOS transistor having a short-circuited source and drain, thereby providing an effect of reducing the circuit size compared to a case where the dummy circuit is not shared.

[0022] In this first aspect, the dummy circuit may further include a source follower circuit having an input node connected to the current-voltage converter, thereby achieving an effect of reducing the circuit size compared to when the dummy circuit is not shared.

[0023] In the first aspect, the dummy circuit may further include a comparator connected to the output node of the source follower circuit, thereby improving the accuracy of OPB correction.

[0024] In this first aspect, the dummy circuit may further include a disabled pMOS transistor, and the pMOS transistor may be inserted between the comparator and a power supply voltage, thereby reducing the circuit size compared to when the comparator is not shared.

[0025] A second aspect of the present technology is an image sensor including: a light-receiving chip on a light-receiving surface, in which at least a portion of first gradation pixels are arranged, the first gradation pixels generating, as gradation signals, analog signals of voltages corresponding to the amount of incident light; and a light-shielding region in which at least a portion of second gradation pixels are arranged; a light-receiving chip on which some of detection pixels that detect whether a change in luminance has exceeded a predetermined threshold are arranged only in the light-receiving region and the light-shielding region; and a circuit chip on which the remaining circuits of the detection pixels and an analog-to-digital converter that converts the gradation signals into digital signals are arranged. This brings about the effect of reducing the circuit scale of the circuit chip.

[0026] 1 is a block diagram showing an example configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a diagram showing an example of a stacked structure of an image sensor according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example configuration of an image sensor according to the first embodiment of the present technology. FIG. 4 is an example plan view of a pixel array unit according to the first embodiment of the present technology. FIG. 5 is a circuit diagram showing an example configuration of an effective pixel according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example configuration of a subtractor and a quantizer according to the first embodiment of the present technology. FIG. 7 is an example plan view of an HOPB region according to the first embodiment of the present technology. FIG. 8 is a circuit diagram showing an example configuration of an OPB pixel according to the first embodiment of the present technology. FIG. 9 is an example cross-sectional view of an image sensor according to the first embodiment of the present technology. FIG. 10 is an example cross-sectional view of an effective pixel and an OPB pixel according to the first embodiment of the present technology. FIG. 11 is a circuit diagram showing an example configuration of an OPB pixel according to the second embodiment of the present technology. FIG. 12 is an example cross-sectional view of an image sensor according to the second embodiment of the present technology. FIG. 13 is an example plan view of a light receiving region according to a third embodiment of the present technology. FIG. 14 is a circuit diagram showing an example configuration of an effective pixel according to a fourth embodiment of the present technology. FIG. 15 is a circuit diagram showing an example configuration of an effective pixel according to a fifth embodiment of the present technology. 13 is a circuit diagram showing a configuration example of an OPB pixel in a sixth embodiment of the present technology. 14 is a circuit diagram showing a configuration example of a dummy circuit in the sixth embodiment of the present technology. 15 is a diagram for explaining a correction method using pixel signals in an HOPB region in the sixth embodiment of the present technology. 16 is a diagram for explaining a correction method using pixel signals in a VOPB region in the sixth embodiment of the present technology. 17 is an example of a plan view of a pixel array unit in a seventh embodiment of the present technology. 18 is a circuit diagram showing a configuration example of an EVS pixel in the seventh embodiment of the present technology. 19 is a circuit diagram showing a configuration example of a dummy circuit in the seventh embodiment of the present technology. 20 is a circuit diagram showing another example of a dummy circuit in the seventh embodiment of the present technology. 21 is a block diagram showing an example of a schematic configuration of a vehicle control system. 22 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which EVS pixels in a light-shielding region are disabled) 2. Second embodiment (an example in which EVS pixels in a light-shielding region are reduced) 3. Third embodiment (an example in which EVS pixels are periodically arranged in a light-receiving region and EVS pixels in a light-shielding region are disabled) 4. Fourth embodiment (an example in which some gradation pixels are arranged on an upper chip and EVS pixels in a light-shielding region are disabled) 5. Fifth embodiment (an example in which circuits are distributed across three chips and EVS pixels in a light-shielding region are disabled) 6. Sixth embodiment (an example in which dummy circuits are arranged in EVS pixels in a light-shielding region) 7. Seventh embodiment (an example in which a dummy circuit is shared by multiple EVS pixels in a light-shielding region) 8. Application example to a moving body

[0028] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 includes an imaging lens 110, an image sensor 200, a recording unit 120, and a control unit 130. The imaging device 100 is expected to be a camera mounted on an industrial robot, an in-vehicle camera, or the like.

[0029] The imaging lens 110 focuses incident light and guides it to the image sensor 200. The image sensor 200 photoelectrically converts the incident light to capture image data. The image sensor 200 performs predetermined signal processing, such as image recognition processing, on the captured image data, and outputs data indicating the processing results and a detection signal of an address event to the recording unit 120 via a signal line 209. A method for generating the detection signal will be described later.

[0030] The recording unit 120 records data from the image sensor 200. The control unit 130 controls the image sensor 200 to capture image data.

[0031] [Configuration Example of Image Sensor] Fig. 2 is a diagram showing an example of a stacked structure of an image sensor 200 according to the first embodiment of the present technology. This image sensor 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via connecting portions such as vias. Note that, in addition to vias, they can also be connected by Cu-Cu bonding or bumps.

[0032] 3 is a block diagram showing an example configuration of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a drive circuit 210, a signal processing unit 220, an arbiter 240, a column ADC (Analog to Digital Converter) 230, and a pixel array unit 300.

[0033] In the pixel array section 300, a plurality of pixels are arranged in a two-dimensional lattice pattern.

[0034] Each pixel generates a grayscale signal with a voltage corresponding to the amount of incident light. Each pixel also detects whether an address event has occurred based on whether the amount of change in luminance exceeds a predetermined threshold. When an address event occurs, the pixel outputs a request to the arbiter.

[0035] The drive circuit 210 drives each pixel to output a pixel signal to the column ADC 230 .

[0036] The arbiter 240 arbitrates requests from the pixels and transmits responses to the pixels based on the arbitration results. The pixels that receive the responses supply detection signals indicating the detection results to the drive circuit 210 and the signal processing unit 220.

[0037] The column ADC 230 has an ADC arranged for each column. The ADC converts analog grayscale signals from the corresponding columns into digital signals and supplies the digital signals to the signal processing unit 220.

[0038] The signal processing unit 220 performs various signal processing such as CDS (Correlated Double Sampling), noise correction, and image recognition on the digital signal from the column ADC 230. The signal processing unit 220 supplies data indicating the processing results and a detection signal to the recording unit 120 via a signal line 209.

[0039] 4 is an example of a plan view of the pixel array unit 300 according to the first embodiment of the present technology. The pixel array unit 300 includes a light receiving region 330, a VOPB region 310, and a HOPB region 320. These regions are provided on the light receiving surface of the photosensor chip 201.

[0040] The light receiving area 330 is an area that is not shielded from light, and in this area, a plurality of effective pixels 331 are arranged in a two-dimensional lattice pattern. Each of the effective pixels 331 includes a gradation pixel 410 and an EVS pixel 500.

[0041] The gradation pixel 410 generates a gradation signal of a voltage corresponding to the amount of incident light. The EVS pixel 500 detects whether or not the amount of change in luminance exceeds a predetermined threshold, and generates a detection signal.

[0042] Each gradation pixel 410 is provided with a color filter such as R (Red), G (Green), or B (Blue), and each pixel can receive red, green, or blue visible light. The gradation pixels 410 that receive red, green, and blue light are referred to as R pixels, G pixels, and B pixels. The G pixels include Gr pixels arranged in rows of R pixels and Gb pixels arranged in rows of B pixels. The R pixels, G pixels, and B pixels are arranged, for example, in a Bayer array.

[0043] The gradation pixel 410 is an example of a first gradation pixel as defined in the claims, and the EVS pixel 500 is an example of a first detection pixel as defined in the claims.

[0044] The VOPB region 310 and the HOPB region 320 are light-shielded regions. In the VOPB region 310, OPB pixels (not shown) are arranged for each column in the light-receiving region 330, and in the HOPB region 320, OPB pixels (not shown) are arranged for each row in the light-receiving region 330. Although both the VOPB region 310 and the HOPB region 320 are provided, only one of them may be provided.

[0045] In the following description, the axis parallel to the row direction of the pixel array unit 300 is referred to as the "X axis," the axis parallel to the column direction is referred to as the "Y axis," and the axis perpendicular to the X axis and the Y axis (in other words, the optical axis) is referred to as the "Z axis."

[0046] 5 is a circuit diagram showing an example of the configuration of the effective pixel 331 according to the first embodiment of the present technology. As described above, the effective pixel 331 includes the gradation pixel 410 and the EVS pixel 500.

[0047] The gradation pixel 410 includes a photoelectric conversion element 411, a transfer transistor 412, a reset transistor 413, a floating diffusion layer 414, an amplification transistor 417, and a selection transistor 418. For example, an nMOS transistor is used as the transistor in the gradation pixel 410. The EVS pixel 500 includes a photoelectric conversion element 510, a current-voltage conversion unit 520, a buffer 530, a subtractor 540, a quantizer 550, and a transfer unit 560.

[0048] In the gradation pixel 410, the photoelectric conversion element 411 generates electric charges by photoelectric conversion of incident light. The transfer transistor 412 transfers electric charges from the photoelectric conversion element 411 to the floating diffusion layer 414 in accordance with a transfer signal TRG from the drive circuit 210.

[0049] The reset transistor 413 extracts charges from the photoelectric conversion element 411 and the floating diffusion layer 414 in accordance with a reset signal RST from the drive circuit 210 to initialize the amount of accumulated charges.

[0050] The floating diffusion layer 414 accumulates electric charges and generates a voltage according to the amount of accumulated electric charges.

[0051] The amplifying transistor 417 constitutes a source follower circuit and outputs a voltage corresponding to the voltage of the floating diffusion layer 414 to the selection transistor 418 .

[0052] The selection transistor 418 outputs the pixel signal of the voltage from the amplification transistor 417 to the column ADC 230 via the vertical signal line VSL in accordance with the selection signal SEL from the drive circuit 210. The vertical signal line VSL is arranged for each column of the gradation pixels 410.

[0053] The circuit configuration of the gradation pixel 410 is not limited to the one illustrated in the figure, as long as it can generate a gradation signal.

[0054] At least some of the gradation pixels 410 described above are arranged on the light-receiving chip 201. In the example shown in the figure, all of the gradation pixels 410 are arranged on the light-receiving chip 201.

[0055] In the EVS pixel 500, the photoelectric conversion element 510 generates a current signal by photoelectric conversion of incident light.

[0056] The current-voltage converter 520 converts the current signal from the photoelectric conversion element 510 into a logarithmic voltage signal. The current-voltage converter 520 supplies the voltage signal to the buffer 530. The current-voltage converter 520 includes nMOS transistors 521, 522, 523, and 524, and a current source 525.

[0057] The nMOS transistors 521 and 522 are connected in series between the power supply voltage VDD and the photoelectric conversion element 510, with the nMOS transistor 521 on the power supply side. The current source 525, the nMOS transistors 523 and 524 are connected in series between the power supply voltage VDD and a ground terminal. The current source 525 supplies a constant current to the nMOS transistor 523.

[0058] The gate of nMOS transistor 521 is connected to the connection node of current source 525 and nMOS transistor 523. The gate of nMOS transistor 522 is connected to the connection node of nMOS transistors 523 and 524. The gate of nMOS transistor 523 is connected to the connection node of nMOS transistors 521 and 522. The gate of nMOS transistor 524 is connected to the connection node of nMOS transistor 522 and photoelectric conversion element 510.

[0059] The above-described circuit configuration converts the current of the photoelectric conversion element 510 into a logarithmic voltage signal. Note that the nMOS transistors 521 to 524 configure a two-stage loop circuit, but the loop can also be configured with one stage or three or more stages.

[0060] The buffer 530 outputs the voltage signal from the current-voltage conversion unit 520 to the subtractor 540. The buffer 530 can improve the driving force for driving the subsequent stage. The buffer 530 also ensures isolation from noise caused by the switching operation of the subsequent stage.

[0061] The buffer 530 includes nMOS transistors 531 and 532 connected in series between a power supply voltage VDD and a ground terminal. The nMOS transistor 531 is on the power supply side, and a voltage signal from the current-voltage conversion unit 520 is input to its gate. A bias voltage Vb is applied to the gate of the nMOS transistor 532. A voltage signal at the connection node between the nMOS transistors 531 and 532 is output to the subtractor 540.

[0062] The subtractor 540 reduces the level of the voltage signal from the buffer 530 in accordance with the row drive signal from the drive circuit 210. The subtractor 540 supplies the reduced voltage signal to the quantizer 550.

[0063] The quantizer 550 quantizes the voltage signal from the subtractor 540 into a digital signal and outputs it to the transfer section 560 as a detection signal.

[0064] The transfer unit 560 transfers the detection signal from the quantizer 550 to the signal processing unit 220 and the like. When an address event is detected, the transfer unit 560 supplies a request for transmission of the detection signal to the arbiter 240. Then, when the transfer unit 560 receives a response to the request from the arbiter 240, it supplies the detection signal to the drive circuit 210 and the signal processing unit 220.

[0065] A part of the EVS pixel 500 described above is arranged on the light receiving chip 201, and the remaining circuitry is arranged on the circuit chip 202. In the example shown in the figure, the photoelectric conversion element 510 and nMOS transistors 521 to 524 are arranged on the light receiving chip 201, and the circuitry from the current source 525 onwards is arranged on the circuit chip 202.

[0066] In the figure, a photoelectric conversion element is arranged in each of the gradation pixel 410 and the EVS pixel 500, but the present invention is not limited to this configuration. The gradation pixel 410 and the EVS pixel 500 may also share one photoelectric conversion element.

[0067] 6 is a circuit diagram showing an example configuration of the subtractor 540 and the quantizer 550 according to the first embodiment of the present technology. The subtractor 540 includes capacitors 541 and 543, an inverter 542, and a switch 544. The quantizer 550 includes a comparator 551.

[0068] One end of the capacitor 541 is connected to the output terminal of the buffer 530, and the other end is connected to the input terminal of the inverter 542. The capacitor 543 is connected in parallel to the inverter 542. The switch 544 opens and closes the path connecting both ends of the capacitor 543 in accordance with a drive signal.

[0069] The inverter 542 inverts the voltage signal input via the capacitor 541. The inverter 542 outputs the inverted signal to the non-inverting input terminal (+) of the comparator 551.

[0070] When the switch 544 is turned on, a voltage signal V ｉｎｉｔis input, and the opposite side becomes a virtual ground terminal. For convenience, the potential of this virtual ground terminal is set to zero. At this time, the potential Q stored in the capacitor 541 ｉｎｉｔ If the capacitance of the capacitor 541 is C1, then Q is expressed by the following equation. On the other hand, since both ends of the capacitor 543 are short-circuited, the accumulated charge thereon is zero. ｉｎｉｔ = C1 × V ｉｎｉｔ ...Formula 1

[0071] Next, the switch 544 is turned off, and the voltage on the buffer 530 side of the capacitor 541 changes to V ａｆｔｅｒ When the charge Q stored in the capacitor 541 is ａｆｔｅｒ is expressed by the following formula: ａｆｔｅｒ = C1 × V ａｆｔｅｒ ...Formula 2

[0072] On the other hand, the charge Q2 stored in the capacitor 543 reduces the output voltage to V ｏｕｔ Then, it is expressed by the following formula: Q2 = -C2 x V ｏｕｔ ...Formula 3

[0073] At this time, the total charge amount of the capacitors 541 and 543 does not change, so the following equation holds: Q ｉｎｉｔ =Q ａｆｔｅｒ +Q2...Formula 4

[0074] Substituting Equations 1 to 3 into Equation 4 and transforming it, the following equation is obtained: ｏｕｔ =-(C1 / C2)×(V ａｆｔｅｒ -V ｉｎｉｔ )...Equation 5

[0075] Equation 5 represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1 / C2. Since it is usually desirable to maximize the gain, it is preferable to design C1 large and C2 small. On the other hand, if C2 is too small, kTC noise increases and noise characteristics may deteriorate, so the reduction in the capacitance of C2 is limited to a range that allows for noise. Furthermore, since an EVS pixel 500 including a subtractor 540 is mounted for each effective pixel 331, there are area constraints on the capacitances C1 and C2. The values ​​of capacitances C1 and C2 are determined taking these factors into consideration.

[0076] The comparator 551 compares the voltage signal from the subtractor 540 with a threshold voltage Vth that indicates a predetermined threshold and is applied to the inverting input terminal (-). The comparator 551 outputs a signal that indicates the comparison result to the transfer unit 560 as a detection signal.

[0077] 7 is an example of a plan view of the HOPB region 320 according to the first embodiment of the present technology. In the HOPB region 320, one or more OPB pixels 321 are arranged for each row of the light receiving region 330. Note that in the VOPB region 310, one or more OPB pixels 321 are arranged for each column of the light receiving region 330.

[0078] Each of the OPB pixels 321 includes a grayscale pixel 420 and a disabled EVS pixel 600 .

[0079] The gradation pixel 420 is an example of a second gradation pixel as defined in the claims, and the EVS pixel 600 is an example of a second detection pixel as defined in the claims.

[0080] 8 is a circuit diagram showing an example of the configuration of the OPB pixel 321 according to the first embodiment of the present technology. As described above, the OPB pixel 321 includes the gradation pixel 420 and the EVS pixel 600.

[0081] The gradation pixel 420 includes a photoelectric conversion element 421, a transfer transistor 422, a reset transistor 423, a floating diffusion layer 424, an amplification transistor 427, and a selection transistor 428. The circuit configuration of the gradation pixel 420 is similar to that of the gradation pixel 410 in the light receiving region 330.

[0082] The EVS pixel 600 includes a photoelectric conversion element 610 and a current-voltage conversion unit 620. The current-voltage conversion unit 620 includes nMOS transistors 621, 622, 623, and 624. The circuit configuration of the EVS pixel 600 is similar to that of the EVS pixel 500 in the light-receiving region 330, except that the circuits after the current source are eliminated.

[0083] However, in the EVS pixel 600, the gates of the nMOS transistors 621 and 623 are shorted, and the gates of the nMOS transistors 622 and 623 are shorted. In addition, the gates of the nMOS transistors 622 and 624 are shorted, and the connection node between the nMOS transistor 622 and the photoelectric conversion element 610 is shorted to the source of the nMOS transistor 624. With this circuit configuration, the EVS pixel 600 is disabled.

[0084] Furthermore, the EVS pixel 600 is disposed on the light receiving chip 201, and the gate of the nMOS transistor 621 is connected to a terminal 630 in the circuit chip 202. In the EVS pixel 600, the circuitry subsequent to the current source is reduced.

[0085] 9 is an example of a cross-sectional view of the image sensor 200 according to the first embodiment of the present technology. This figure shows a cross-sectional view seen from the Y-axis direction.

[0086] The image sensor 200 includes a stacked light-receiving chip 201 and a circuit chip 202. The light-receiving surface of the light-receiving chip 201 is provided with a light-receiving region 330 that is not shielded from light, and a light-shielded region such as the HOPB region 320. The light-shielded region is shielded from light by a light-shielding member 431.

[0087] In the light receiving region 330, the gradation pixels and some of the EVS pixels are arranged on the light receiving chip 201, and the remaining circuits of the EVS pixels (such as the buffer 530 and the subtractor 540) are arranged on the circuit chip 202. The gray areas in the figure indicate areas where the gradation pixels are arranged, and the shaded areas indicate areas where the EVS pixels are arranged.

[0088] On the other hand, in a light-shielding region such as the HOPB region, gradation pixels and disabled EVS pixels are arranged on a light-receiving chip 201, and peripheral circuits are arranged on a circuit chip 202. The peripheral circuits include a drive circuit 210, a signal processing unit 220, a column ADC 230, an arbiter 240, and the like.

[0089] As a comparative example, a configuration in which the EVS pixels in the light-shielding region are effective is assumed. In this comparative example, the light-receiving side is positioned on the upper side, and circuits subsequent to the current source (such as the buffer 530 and the subtractor 540) must be arranged directly below the light-shielding region in the circuit chip 202. For this reason, in this comparative example, the chip area of ​​the light-receiving chip 201 is limited by the circuit chip 202.

[0090] In contrast, in the first embodiment, the EVS pixels in the light-shielded area are disabled by short-circuiting, so that the circuitry immediately below the current source and subsequent circuits can be reduced, thereby reducing the circuit scale and area of ​​the lower circuit chip 202 compared to the comparative example.

[0091] FIG. 10 is an example of a cross-sectional view of an effective pixel 331 and an OPB pixel 321 according to the first embodiment of the present technology.

[0092] An on-chip lens 433 is provided for each effective pixel 331, and a color filter 434 is provided below the on-chip lens 433. A photoelectric conversion element 411 is disposed below the color filter 434, and a transistor such as a transfer transistor is disposed below the photoelectric conversion element 411.

[0093] An on-chip lens 432 is provided for each OPB pixel 321, and a light-shielding member 431 is provided below the on-chip lens 432. A photoelectric conversion element 421 is disposed below the light-shielding member 431, and a transistor such as a transfer transistor is disposed below the photoelectric conversion element 421.

[0094] Although the color filter 434 is arranged for each effective pixel 331, the present invention is not limited to this configuration. It is also possible to configure the image sensor 200 to generate monochrome image data without arranging the color filter 434.

[0095] As described above, according to the first embodiment of the present technology, the gradation pixels 420 and the disabled EVS pixels 600 are arranged in a light-shielded area, so that the circuit scale of the circuit chip 202 can be reduced and its area can be made smaller.

[0096] 2. Second Embodiment In the first embodiment described above, the EVS pixels in the light-shielded region are disabled, but it is preferable to further reduce the circuit scale in the light-shielded region. The image sensor 200 in this second embodiment differs from the first embodiment in that the EVS pixels in the light-shielded region are reduced.

[0097] 11 is a circuit diagram showing a configuration example of an OPB pixel 321 according to a second embodiment of the present technology. The OPB pixel 321 according to the second embodiment differs from the first embodiment in that the EVS pixel is eliminated. Furthermore, the potential of the terminal 630 of the circuit chip 202 is connected to a floating potential. Alternatively, the potential of the terminal 630 is fixed to a predetermined potential.

[0098] FIG. 12 is an example of a cross-sectional view of an image sensor 200 according to the second embodiment of the present technology.

[0099] In the second embodiment, the configuration of the light receiving region 330 is the same as in the first embodiment. That is, the gradation pixels and some of the EVS pixels are arranged on the light receiving chip 201, and the remaining circuits of the EVS pixels are arranged on the circuit chip 202.

[0100] On the other hand, in the light-shielding region such as HOPB 320, EVS pixels are removed from the light-receiving chip 201, and only gradation pixels are arranged. In other words, some of the EVS pixels are arranged only in the light-receiving region 330. By removing the EVS pixels in the light-shielding region, the circuit scale of the light-receiving chip 201 can be further reduced, and its area can be made smaller.

[0101] As described above, according to the second embodiment of the present technology, a portion of the EVS pixels is arranged only in the light receiving region 330, so that the circuit scale of the light receiving chip 201 can be further reduced, and the area thereof can be made smaller.

[0102] 3. Third Embodiment In the first embodiment described above, the gradation pixels 410 and the EVS pixels 500 are arranged for each effective pixel 331 in the light receiving region 330, but the EVS pixels 500 may also be arranged periodically. The image sensor 200 in this third embodiment differs from the first embodiment in that the EVS pixels 500 are arranged periodically.

[0103] 13 is an example of a plan view of a light receiving region 330 according to the third embodiment of the present technology. A predetermined number of pixel blocks 332 are arranged in the light receiving region 330. Each of the pixel blocks 332 includes three gradation pixels 410 of the same color and an EVS pixel 500.

[0104] If only gradation pixels 410 were arranged within the pixel block 332, four R pixels, four G pixels, and four B pixels would be arranged adjacent to each other. This type of arrangement is called a Quad Bayer arrangement. The light receiving area 330 in the same figure corresponds to this Quad Bayer arrangement in which one of the four gradation pixels 410 of the same color is replaced with an EVS pixel 500. For example, in the R pixel block, the EVS pixel 500 is arranged at the bottom right, and in the Gb pixel block, the EVS pixel 500 is arranged at the top right. In the Gr pixel block, the EVS pixel 500 is arranged at the bottom left, and in the B pixel block, the EVS pixel 500 is arranged at the top left.

[0105] As illustrated in the figure, by arranging pixel blocks 332 each including three gradation pixels 410 of the same color and an EVS pixel 500, it is possible to reduce the circuit size of the light receiving chip 201 compared to when an EVS pixel 500 is arranged for each effective pixel 331. By reducing the circuit size of the light receiving chip 201, it is possible to increase the area of ​​the photoelectric conversion elements 411 and 510 accordingly.

[0106] The second embodiment can also be applied to the third embodiment.

[0107] As described above, according to the third embodiment of the present technology, the pixel block 332 including three gradation pixels 410 of the same color and the EVS pixel 500 is arranged within the light receiving area 330, thereby making it possible to reduce the circuit size of the light receiving chip 201.

[0108] 4. Fourth Embodiment In the above-described first embodiment, all of the gradation pixels 410 are arranged on the light-receiving chip 201, but it is preferable to further reduce the circuit scale of the light-receiving chip 201. The image sensor 200 in this fourth embodiment differs from the first embodiment in that some of the gradation pixels 410 are arranged on the light-receiving chip 201 and the remaining circuitry is arranged on the circuit chip 202.

[0109] 14 is a circuit diagram showing a configuration example of an effective pixel 331 according to the fourth embodiment of the present technology. The effective pixel 331 according to the fourth embodiment differs from the first embodiment in that a part of the gradation pixels 410 is arranged on the light receiving chip 201 and the remaining circuit is arranged on the circuit chip 202.

[0110] For example, the photoelectric conversion element 411 and the transfer transistor 412 are disposed on the light receiving chip 201 , and the remaining circuits are disposed on the circuit chip 202 .

[0111] The circuits and elements arranged on the light-receiving chip 201 and the circuit chip 202 are not limited to those shown in the figure.

[0112] As shown in the figure, by arranging some of the gradation pixels 410 on the light-receiving chip 201 and arranging the remaining circuit on the circuit chip 202, it is possible to reduce the circuit scale of the light-receiving chip 201 compared to when all of the effective pixels 331 are arranged on the light-receiving chip 201. By reducing the circuit scale of the light-receiving chip 201, it is possible to increase the area of ​​the photoelectric conversion element 411 accordingly.

[0113] It should be noted that the second and third embodiments can be applied to the fourth embodiment.

[0114] As described above, according to the fourth embodiment of the present technology, a portion of the gradation pixels 410 are arranged on the light receiving chip 201, and the remaining circuitry is arranged on the circuit chip 202, thereby enabling the circuit size of the light receiving chip 201 to be reduced.

[0115] 5. Fifth Embodiment In the first embodiment described above, the circuits are distributed across the light receiving chip 201 and the circuit chip 202, but the circuits may also be distributed across three stacked semiconductor chips. The image sensor 200 in this fifth embodiment differs from the first embodiment in that the circuits are distributed across three stacked semiconductor chips.

[0116] FIG. 15 is a circuit diagram showing a configuration example of an effective pixel 331 according to the fifth embodiment of the present technology.

[0117] In the fifth embodiment, the image sensor 200 further includes a circuit chip 203 stacked below the circuit chip 202 .

[0118] A part of the gradation pixel 410 is arranged on the light receiving chip 201, and the remaining circuitry is arranged on the circuit chip 202. For example, the photoelectric conversion element 411 and the transfer transistor 412 are arranged on the light receiving chip 201, and the remaining circuitry is arranged on the circuit chip 202. In the EVS pixel 500, for example, the photoelectric conversion element 510 is arranged on the light receiving chip 201, the nMOS transistors 521 to 524 are arranged on the circuit chip 202, and the remaining circuitry is arranged on the circuit chip 203.

[0119] Peripheral circuits such as the drive circuit 210, the signal processing unit 220, the column ADC 230, and the arbiter 240 are arranged on the circuit chip 203. The circuit chips 202 and 203 are examples of the first and second circuit chips set forth in the claims.

[0120] As illustrated in the figure, by distributing the circuits across three semiconductor chips (i.e., light receiving chip 201, circuit chip 202, and circuit chip 203), the circuit size per chip can be reduced compared to distributing the circuits across two chips.

[0121] It should be noted that the second and third embodiments can be applied to the fifth embodiment.

[0122] As described above, according to the fifth embodiment of the present technology, the circuits are distributed among the light receiving chip 201, the circuit chip 202, and the circuit chip 203, and therefore the circuit size per chip can be reduced compared to when the circuits are distributed among two chips.

[0123] 6. Sixth Embodiment In the first embodiment described above, the circuits of the lower circuit chip 202 were reduced in the light-shielded areas (VOPB area and HOPB area), but this configuration may cause the characteristics of the gradation pixels in the light-shielded area and the gradation pixels in the light-receiving area 330 to differ from each other. This may result in a decrease in the accuracy of OPB correction. The image sensor 200 in this sixth embodiment differs from the first embodiment in that dummy circuits are arranged on the circuit chip 202 in the light-shielded area.

[0124] 16 is a circuit diagram showing an example configuration of an OPB pixel 321 according to a sixth embodiment of the present technology. The OPB pixel 321 includes a gradation pixel 420 and an EVS pixel 600. In each embodiment of the present invention, the OPB pixel 321 can be shielded from light by, for example, a metal plate. The gray portion in the figure indicates the metal plate. The circuit configuration of the gradation pixel 420 according to the sixth embodiment is the same as that of the first embodiment.

[0125] The EVS pixel 600 of the sixth embodiment includes a photoelectric conversion element 610, a current-voltage conversion unit 620, and a dummy circuit 700. The photoelectric conversion element 610 and the current-voltage conversion unit 620 are disposed on the light-receiving chip 201, and the dummy circuit 700 is disposed on the circuit chip 202. The disposition of the dummy circuit 700 makes it easier for the characteristics of the gradation pixels in the light-shielding region and the gradation pixels in the light-receiving region 330 to match, compared to the first embodiment. This improves the accuracy of correcting horizontal streaking noise and black levels using the gradation signals of the OPB pixels 321.

[0126] The current-voltage conversion section 620 is provided with nMOS transistors 621 to 624. The connection configuration between the photoelectric conversion element 610 and the nMOS transistors 621 to 624 is the same as in the first embodiment.

[0127] The dummy circuit 700 includes a current source 711. For example, a diode-connected pMOS transistor is used as the current source 711. The drain of the pMOS transistor is connected to the current-voltage conversion unit 620.

[0128] 3 and 16, the gradation pixels 410 in the light-receiving region and the gradation pixels 420 in the light-shielding region are connected to the same circuit (such as an ADC), while the EVS pixels 500 in the light-receiving region and the EVS pixels 600 in the light-shielding region are connected to different circuits.

[0129] As shown in FIG. 17A, a pMOS transistor whose gate is connected to the power supply voltage VDD can be disposed as a current source 711 in the dummy circuit 700 .

[0130] Also, as shown in FIG. 7B, a diode-connected nMOS transistor can be disposed as a current source 711 in the dummy circuit 700 .

[0131] Alternatively, as shown in FIG. 7c, an nMOS transistor having a gate connected to the ground voltage can be disposed as a current source 711 in the dummy circuit 700 .

[0132] Next, OPB correction will be described with reference to Fig. 18 and Fig. 19. It is assumed that gradation signals are read out by the column ADC 230 from the OPB pixels in the VOPB area 310 and the HOPB area 320 and the effective pixels in the light receiving area 330 illustrated in Fig. 4. Fig. 18 will be described focusing on OPB correction using the gradation signals in the HOPB area 320, and Fig. 19 will be described focusing on OPB correction using the gradation signals in the VOPB area 310.

[0133] 18A shows an example of an image in which the gradation signals of OPB pixels in the HOPB region 320 and the gradation signals of effective pixels in the light receiving region 330 are arranged. The gradation signals of the effective pixels are arranged in an area 802. The gradation signals of the OPB pixels in the HOPB region 320 are arranged in areas 801 and 803 on the left and right of the area 802, respectively. As shown in the example of FIG. 18A, horizontal line noise may occur in the area 802.

[0134] The signal processing unit 220 performs OPB correction on the gradation signals of the effective pixels for each row using the gradation signals of the OPB pixels. For example, the signal processing unit 220 calculates the average value of the gradation signals of the OPB pixels in the row to be corrected as a clamp value, and performs OPB correction by subtracting the clamp value from the gradation signals of the effective pixels in that row.

[0135] 8B shows an image obtained by performing OPB correction on the image in FIG. 8A. As shown in FIG. 8B, the horizontal noise in the area 802 can be suppressed by OPB correction using the gradation signal in the HOPB region 320.

[0136] 19A shows an example of the nth (n is an integer) frame in which the gradation signals of the OPB pixels in the VOPB area 310 and the gradation signals of the effective pixels in the light-receiving area 330 are arranged. The gradation signals of the OPB pixels in the VOPB area 310 are arranged in areas 804 and 805 above and below the area 802, respectively. The b in the figure shows the next n+1th frame. In the b in the figure, the entire frame is dark, even though the actual brightness is unchanged compared to the previous nth frame. This is because the black level has fluctuated due to factors such as a temperature difference.

[0137] The signal processing unit 220 performs OPB correction on the gradation signals of the effective pixels for each column using the gradation signals of the OPB pixels. For example, the signal processing unit 220 calculates the average value of the gradation signals of the OPB pixels in the column to be corrected as a clamp value, and performs OPB correction by subtracting the clamp value from the gradation signals of the effective pixels in that column.

[0138] In the figure, c shows an image obtained by performing OPB correction on image a, and d shows an image obtained by performing OPB correction on image b. As shown in d, the black level in area 802 is corrected to an appropriate value by OPB correction using the gradation signal in VOPB region 310, so the brightness of the (n+1)th frame is approximately the same as that of the previous frame.

[0139] The above-described OPB correction is performed in each of the embodiments of the present invention. In the sixth embodiment, the accuracy of the OPB correction can be improved by arranging the dummy circuits as described above.

[0140] It should be noted that the third, fourth and fifth embodiments can each be applied to the sixth embodiment.

[0141] As described above, according to the sixth embodiment of the present technology, the dummy circuits 700 of the EVS pixels 600 are arranged on the circuit chip 202 in the light-shielded region, and therefore, the accuracy of OPB correction can be improved.

[0142] 7. Seventh Embodiment In the sixth embodiment described above, a dummy circuit 700 is provided for each EVS pixel, but it is preferable to further reduce the circuit size. The image sensor 200 in this seventh embodiment differs from the sixth embodiment in that a plurality of EVS pixels share the dummy circuit 700.

[0143] 20 is an example of a plan view of a pixel array unit 300 according to the seventh embodiment of the present technology. In the seventh embodiment, gradation pixels 410 such as R pixels, G pixels, and B pixels and a predetermined number of EVS pixels 500 are arranged in the light receiving region 330.

[0144] If only gradation pixels 410 were arranged within the pixel block 332, R pixels, G pixels, and B pixels would be arranged in groups of four adjacent pixels each. This type of arrangement is called a Quad Bayer arrangement. The light receiving area 330 in the figure corresponds to this Quad Bayer arrangement in which one of the four gradation pixels 410 of the same color is replaced with an EVS pixel 500.

[0145] Even in a light-shielding region such as the HOPB region 320, one of the four gradation pixels 410 of the same color in the Quad Bayer arrangement is replaced with an EVS pixel such as EVS pixel 500-1 or 500-2. Furthermore, in the light-shielding region, multiple EVS pixels (for example, EVS pixels 500-1 and 500-2) share a dummy circuit. The number of pixels sharing the dummy circuit is not limited to two pixels, and may be four pixels, for example.

[0146] 21 is a circuit diagram showing a configuration example of an EVS pixel according to the seventh embodiment of the present technology. A photoelectric conversion element 510-1 and a current-voltage conversion unit 620-1, and a photoelectric conversion element 510-2 and a current-voltage conversion unit 620-2 are arranged on a light receiving chip 201. A dummy circuit 700 connected in common to the current-voltage conversion units 620-1 and 620-2 is arranged on a circuit chip 202.

[0147] The photoelectric conversion element 510-1 and the current-voltage conversion unit 620-1 are arranged in the EVS pixel 500-1, and the photoelectric conversion element 510-2 and the current-voltage conversion unit 620-2 are arranged in the EVS pixel 500-2. The dummy circuit 700 is shared by the current-voltage conversion units 620-1 and 620-2. In this way, the dummy circuit 700 is shared by multiple EVS pixels, so the circuit size of the circuit chip 202 can be reduced compared to when the dummy circuit 700 is not shared.

[0148] The dummy circuit 700 includes, for example, a current source 711. As this current source 711, for example, various circuits shown in FIGS.

[0149] 22A, in addition to the current source 711, an nMOS transistor 721 can be provided in the dummy circuit 700. The gate of this nMOS transistor 721 is connected to the current-voltage conversion unit 620 (not shown) of the photosensor chip 201, and the source and drain are short-circuited.

[0150] Furthermore, as illustrated in FIG. 1B, in addition to the current source 711, a source follower circuit 720 can be provided in the dummy circuit 700. This source follower circuit 720 includes nMOS transistors 721 and 722 connected in series to the power supply voltage VDD. The gate of the nMOS transistor 721 (in other words, the input node) is connected to the photosensor chip 201. Nothing is connected to the connection node (in other words, the output node) of the nMOS transistors 721 and 722, and the subsequent circuitry is eliminated. The nMOS transistor 722 may be turned on by applying a predetermined bias voltage or by diode connection, or may be turned off by grounding the gate.

[0151] Furthermore, as shown in FIG. 1C, in addition to the current source 711 and the source follower circuit 720, a comparator 730 can be provided in the dummy circuit 700. This comparator 730 includes a capacitor 731, a pMOS transistor 732, a switch 733, and a current source 734. The switch 733 and the current source 734 are controlled to an off state. For example, an nMOS transistor is used as the switch 733 and the current source 734, and their gates are grounded.

[0152] A capacitor 731 is inserted between the output node of the source follower circuit 720 and the gate of a pMOS transistor 732. The pMOS transistor 732 and a current source 734 are connected in series to a power supply voltage VDD. A switch 733 is connected to the gate of the pMOS transistor 732 and the connection node (in other words, the output node) of the pMOS transistor 732 and the current source 734. Nothing is connected to the output node of the comparator 730, and subsequent circuits are omitted.

[0153] 23, a pMOS transistor 740 can be provided in the dummy circuit 700 in addition to the current source 711, the source follower circuit 720, and the comparator 730. The pMOS transistor 740 is in an off state due to the connection of the power supply voltage to the gate, and is inserted between the comparator 730 and the power supply voltage VDD.

[0154] It should be noted that the fourth and fifth embodiments can be applied to the seventh embodiment.

[0155] As described above, according to the seventh embodiment of the present technology, since a plurality of EVS pixels share the dummy circuit 700, the circuit scale of the circuit chip 202 can be reduced compared to when the dummy circuit 700 is not shared.

[0156] 8. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0157] FIG. 24 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0158] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 24, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0159] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0160] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0161] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0162] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0163] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0164] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0165] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0166] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0167] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 24, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0168] FIG. 25 is a diagram showing an example of the installation position of the imaging unit 12031.

[0169] In FIG. 25, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0170] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0171] 25 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0172] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0173] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0174] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0175] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0176] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to reduce the circuit scale of the lower semiconductor chip and the area of ​​the image sensor 200.

[0177] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0178] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0179] The present technology may also be configured as follows: (1) An image sensor including: a light-receiving chip having, on its light-receiving surface, a light-receiving region in which at least some of first gradation pixels that generate, as gradation signals, analog signals of voltages corresponding to the amount of incident light and some of first detection pixels that detect whether a change in luminance has exceeded a predetermined threshold are arranged, and a light-shielding region in which at least some of second gradation pixels and disabled second detection pixels are arranged; and a circuit chip in which the remaining circuits of the first detection pixels and an analog-to-digital converter that converts the gradation signals into digital signals are arranged. (2) The image sensor according to (1), wherein the first detection pixel comprises: a first current-voltage converter that converts a current signal into a voltage signal, a buffer that outputs the voltage signal, a subtractor that reduces the level of the voltage signal from the buffer, and a quantizer that quantizes the voltage signal from the subtractor and outputs a detection signal, and a part of the first current-voltage converter is disposed on the light-receiving chip, and the remaining circuit of the first current-voltage converter, the buffer, the subtractor, and the quantizer are disposed on the circuit chip. (3) The image sensor according to (1) or (2), wherein the second detection pixel comprises a second current-voltage converter that converts a current signal into a voltage signal. (4) The image sensor according to any one of (1) to (3), wherein each of the first gradation pixel and the second gradation pixel comprises: a photoelectric conversion element; a transfer transistor that transfers charge from the photoelectric conversion element to a floating diffusion layer in accordance with a transfer signal; an amplification transistor that outputs a voltage corresponding to the voltage of the floating diffusion layer; and a selection transistor that outputs a voltage signal from the amplification transistor to a vertical signal line in accordance with a selection signal. (5) The image sensor according to (4), wherein the photoelectric conversion element and the transfer transistor are disposed on the light receiving chip, and the amplification transistor and the selection transistor are disposed on the circuit chip. (6) The image sensor according to (4), wherein the circuit chip includes first and second circuit chips that are stacked, wherein the amplification transistor and the selection transistor are disposed on the first circuit chip, and the analog-to-digital converter is disposed on the second circuit chip.(7) The image sensor according to any one of (1) to (6), wherein the light receiving region has a plurality of effective pixels arranged in a two-dimensional lattice pattern, and each of the plurality of effective pixels includes the first gradation pixel and the first detection pixel. (8) The image sensor according to any one of (1) to (6), wherein the light receiving region has a predetermined number of pixel blocks arranged, and each of the pixel blocks includes a predetermined number of the first gradation pixels and the first detection pixel. (9) The image sensor according to (1), wherein the second detection pixel includes a current-voltage converter that converts a current signal into a voltage signal and a dummy circuit, and the current-voltage converter is connected to the dummy circuit, and the current-voltage converter is disposed on the light receiving chip, and the dummy circuit is disposed on the circuit chip. (10) The image sensor according to (9), wherein the dummy circuit includes a diode-connected pMOS (p-channel Metal Oxide Semiconductor) transistor. (11) The image sensor according to (9), wherein the dummy circuit comprises a pMOS transistor having a gate connected to a power supply voltage. (12) The image sensor according to (9), wherein the dummy circuit comprises a diode-connected nMOS (n-channel MOS) transistor. (13) The image sensor according to (9), wherein the dummy circuit comprises an nMOS transistor having a gate connected to a ground voltage. (14) The image sensor according to (1), wherein a plurality of second detection pixels are arranged in the light-shielding region, each of the plurality of second detection pixels comprises a current-voltage converter that converts a current signal into a voltage signal, the current-voltage converter of each of the plurality of second detection pixels being commonly connected to a dummy circuit, the current-voltage converter being disposed on the light-receiving chip, and the dummy circuit being disposed on the circuit chip. (15) The image sensor according to (14), wherein the dummy circuit comprises a disabled current source. (16) The image sensor according to (15), wherein the dummy circuit further comprises an nMOS transistor whose source and drain are short-circuited. (17) The image sensor according to (15), wherein the dummy circuit further includes a source follower circuit having an input node connected to the current-voltage conversion unit.(18) The image sensor according to (17), wherein the dummy circuit further comprises a comparator connected to an output node of the source follower circuit. (19) The image sensor according to (18), wherein the dummy circuit further comprises a disabled pMOS transistor, the pMOS transistor being inserted between the comparator and a power supply voltage. (20) An image sensor comprising: a light-receiving chip on a light-receiving surface thereof having a light-receiving region in which at least a portion of first gradation pixels are arranged, the first gradation pixels generating, as a gradation signal, an analog signal having a voltage corresponding to an amount of incident light, and a light-shielding region in which at least a portion of second gradation pixels are arranged, the light-receiving region including first gradation pixels and second gradation pixels, the first gradation pixels generating, as a gradation signal, an analog signal having a voltage corresponding to an amount of incident light, and a light-shielding region including second gradation pixels, the light-receiving region including first gradation pixels and second gradation pixels, the first gradation pixels being arranged only in the light-receiving region and the light-shielding region, the light-receiving region including second gradation pixels, the first gradation pixels detecting whether a change in luminance exceeds a predetermined threshold; and a circuit chip on which the remaining circuits of the detection pixels and an analog-to-digital converter converting the gradation signal into a digital signal are arranged.

[0180] 100 Imaging device 110 Imaging lens 120 Recording unit 130 Control unit 200 Image sensor 201 Light receiving chip 202, 203 Circuit chip 210 Drive circuit 220 Signal processing unit 230 Column ADC 240 Arbiter 300 Pixel array unit 310 VOPB area 320 HOPB area 321 OPB pixel 330 Light receiving area 331 Effective pixel 332 Pixel block 410, 420 Gradation pixel 411, 421, 510, 510-1, 510-2, 610 Photoelectric conversion element 412, 422 Transfer transistor 413, 423 Reset transistor 414, 424 Floating diffusion layer 417, 427 Amplification transistor 418, 428 Selection transistor 431 Light-shielding member 432, 433 On-chip lens 434 Color filter 500, 500-1, 500-2, 600 EVS pixel 520, 620, 620-1, 620-2 Current-voltage conversion unit 521 to 524, 531, 532, 621 to 624, 721, 722 nMOS transistor 525, 711, 734 Current source 530 Buffer 540 Subtractor 541, 543, 731 Capacitor 542 Inverter 544, 733 Switch 550 Quantizer 551, 730 Comparator 560 Transfer unit 630 Terminal 700 Dummy circuit 720 Source follower circuit 732, 740 pMOS transistor 12031 Imaging unit

Claims

1. An image sensor comprising: a light-receiving chip on the light-receiving surface of which are arranged a light-receiving region in which at least a portion of first gradation pixels that generate analog signals of voltage corresponding to the amount of incident light as gradation signals and a portion of first detection pixels that detect whether a change in brightness has exceeded a predetermined threshold are arranged; and a light-shielding region in which at least a portion of second gradation pixels and disabled second detection pixels are arranged; and a circuit chip on which are arranged the remaining circuits of the first detection pixels and an analog-to-digital converter that converts the gradation signals into digital signals.

2. The image sensor of claim 1, wherein the first detection pixel comprises: a first current-voltage conversion unit that converts a current signal into a voltage signal; a buffer that outputs the voltage signal; a subtractor that reduces the level of the voltage signal from the buffer; and a quantizer that quantizes the voltage signal from the subtractor and outputs a detection signal; and wherein a part of the first current-voltage conversion unit is arranged on the light-receiving chip, and the remaining circuitry of the first current-voltage conversion unit, the buffer, the subtractor, and the quantizer are arranged on the circuit chip.

3. The image sensor according to claim 1, wherein the second detection pixel includes a second current-voltage converter that converts a current signal into a voltage signal.

4. The image sensor according to claim 1, wherein each of the first and second gradation pixels comprises a photoelectric conversion element, a transfer transistor that transfers charges from the photoelectric conversion element to a floating diffusion layer in accordance with a transfer signal, an amplification transistor that outputs a voltage corresponding to the voltage of the floating diffusion layer, and a selection transistor that outputs a voltage signal from the amplification transistor to a vertical signal line in accordance with a selection signal.

5. The image sensor according to claim 4, wherein the photoelectric conversion element and the transfer transistor are disposed on the light receiving chip, and the amplification transistor and the selection transistor are disposed on the circuit chip.

6. The image sensor according to claim 4, wherein the circuit chip includes first and second stacked circuit chips, the amplification transistor and the selection transistor are disposed on the first circuit chip, and the analog-to-digital converter is disposed on the second circuit chip.

7. An image sensor according to claim 1, wherein a plurality of effective pixels are arranged in a two-dimensional grid pattern in the light receiving area, and each of the plurality of effective pixels includes the first gradation pixel and the first detection pixel.

8. The image sensor according to claim 1, wherein a predetermined number of pixel blocks are arranged in the light receiving region, and each of the pixel blocks includes a predetermined number of the first gradation pixels and the first detection pixels.

9. The image sensor according to claim 1, wherein the second detection pixel comprises a current-voltage conversion unit that converts a current signal into a voltage signal, and a dummy circuit, the current-voltage conversion unit being disposed on the light-receiving chip, and the dummy circuit being disposed on the circuit chip.

10. The image sensor of claim 9, wherein the dummy circuit comprises a diode-connected p-channel metal oxide semiconductor (pMOS) transistor.

11. The image sensor according to claim 9, wherein the dummy circuit comprises a pMOS transistor having a gate connected to a power supply voltage.

12. The image sensor according to claim 9, wherein the dummy circuit comprises a diode-connected nMOS (n-channel MOS) transistor.

13. The image sensor according to claim 9, wherein the dummy circuit comprises an nMOS transistor having a gate connected to a ground voltage.

14. The image sensor according to claim 1, wherein a plurality of second detection pixels are arranged in the light-shielding region, each of the plurality of second detection pixels includes a current-voltage conversion unit that converts a current signal into a voltage signal, the current-voltage conversion units of each of the plurality of second detection pixels are commonly connected to a dummy circuit, the current-voltage conversion unit is disposed on the light-receiving chip, and the dummy circuit is disposed on the circuit chip.

15. The image sensor of claim 14, wherein the dummy circuitry comprises a disabled current source.

16. The image sensor according to claim 15, wherein the dummy circuit further comprises an nMOS transistor whose source and drain are shorted.

17. The image sensor according to claim 15, wherein the dummy circuit further comprises a source follower circuit having an input node connected to the current-voltage conversion unit.

18. The image sensor according to claim 17, wherein the dummy circuit further comprises a comparator connected to an output node of the source follower circuit.

19. The image sensor according to claim 18, wherein the dummy circuit further comprises a disabled pMOS transistor, the pMOS transistor being inserted between the comparator and a power supply voltage.

20. An image sensor comprising: a light-receiving chip on whose light-receiving surface are arranged a light-receiving region in which at least a portion of first gradation pixels are arranged, the first gradation pixels generating analog voltage signals corresponding to the amount of incident light as gradation signals, and a light-shielding region in which at least a portion of second gradation pixels are arranged; a light-receiving chip on which some of the detection pixels that detect whether the amount of change in luminance has exceeded a predetermined threshold are arranged only in the light-receiving region out of the light-receiving region and the light-shielding region; and a circuit chip on which are arranged the remaining circuits of the detection pixels and an analog-to-digital converter that converts the gradation signals into digital signals.

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