Epitaxial silicon wafer and manufacturing method therefor

Abstract

The present application provides an epitaxial silicon wafer and a manufacturing method therefor. During the growth process of an epitaxial layer, the step of growing a homoepitaxial layer on one side of a substrate material in stages comprises: providing a silicon wafer serving as a substrate; depositing a middle epitaxial layer on the silicon wafer substrate, and then performing edge topography flatness compensation on the middle epitaxial layer; and depositing a top epitaxial layer on the middle epitaxial layer. The method comprises at least one stage I and a stage II.

Description

Epitaxial silicon wafers and their manufacturing methods

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410559808.7, filed in China on May 8, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial silicon wafer and a method for manufacturing the same. Background Technology

[0004] Growing a single-crystal thin film on a polished single-crystal wafer is called epitaxial silicon wafer. Compared to polished wafers, epitaxial silicon wafers have fewer surface defects, better crystallinity, and controllable resistivity, and are widely used in the fabrication of highly integrated integrated circuit (IC) devices and metal-oxide-semiconductor field-effect transistors (MOS). Epitaxial growth is generally performed on wafers using chemical vapor deposition (CVD). First, the wafer is transferred to a substrate in a reaction chamber. Then, the reaction chamber is heated to a preset temperature, and a cleaning gas (such as hydrogen) is introduced to remove the native oxides on the wafer surface. Next, a silicon source gas is introduced to continuously and uniformly grow an epitaxial layer on the front side of the wafer.

[0005] Figure 1 is a schematic diagram of the wafer epitaxial layer fabrication process. As shown in Figure 1, the wafer epitaxial layer fabrication mainly consists of two stages. The first stage involves chamber etching, in which hydrogen (H2) and etching gas (HCl) are introduced. Hydrogen acts as the main gas flow, carrying the etching gas (HCl) to react with the byproducts deposited in the reaction chamber, thus cleaning the reaction chamber. The second stage involves epitaxial layer growth, in which hydrogen (H2), silicon source gas (SiHCl3 / H2), and doping gas (B2H6 / H2) are introduced. In the hydrogen baking step, hydrogen reacts with the natural oxide layer on the wafer surface to obtain a clean epitaxial substrate. In the epitaxial deposition step, hydrogen acts as the main gas flow, carrying the film-forming gas and doping gas to grow an epitaxial layer with controllable resistivity on the wafer surface.

[0006] With the continuous development of semiconductor manufacturing processes, the flatness requirements for epitaxial silicon wafers are becoming increasingly stringent. Poor flatness of epitaxial silicon wafers can lead to defocusing and may even affect the Chemical Mechanical Polishing (CMP) process, impacting product yield. When the flatness of an epitaxial silicon wafer is poor in a localized area, over-polishing or under-polishing can occur; over-polishing may lead to early device breakdown, while under-polishing may result in errors in device contact. Summary of the Invention

[0007] To address the aforementioned technical problems, this application provides an epitaxial silicon wafer and a method for manufacturing the same, which can improve the flatness of the epitaxial silicon wafer.

[0008] To achieve the above objectives, the technical solution adopted in the embodiments of this application is as follows:

[0009] A method for manufacturing an epitaxial silicon wafer, comprising the step of growing a homogeneous epitaxial layer in stages on one side of a substrate material during the epitaxial layer growth process, including:

[0010] Provide substrate silicon wafers;

[0011] Phase 1: Deposit an intermediate epitaxial layer on the substrate silicon wafer, and then perform edge morphology flatness compensation on the intermediate epitaxial layer;

[0012] Phase 2: Deposit the top epitaxial layer on the intermediate epitaxial layer;

[0013] The method includes at least one Phase 1 and one Phase 2.

[0014] In some embodiments, in stage one, the intermediate epitaxial layer is etched to compensate for edge topography flatness, so that the frontal reference least squares deviation (ESFQD) value of the edge portion of the intermediate epitaxial layer is in the range of -40 nm to 0 nm.

[0015] In some embodiments, in stage one, after depositing at least one intermediate epitaxial layer on the substrate silicon wafer, an etching gas is introduced to etch the intermediate epitaxial layer.

[0016] In some embodiments, the intermediate epitaxial layer is etched by extending the reaction time of the etching gas.

[0017] This application also provides an epitaxial silicon wafer manufactured using the method described above, wherein the ESFQR value of the frontal reference least squares range at the edge of the epitaxial silicon wafer ranges from 0 nanometers to 60 nanometers.

[0018] In some embodiments, when the thickness of the epitaxial layer is 3 to 5 micrometers, the maximum ESFQR of the epitaxial silicon wafer is 24.6 nanometers.

[0019] In some embodiments, when the thickness of the epitaxial layer is 6 micrometers to 9 micrometers, the maximum ESFQR of the epitaxial silicon wafer is 55.8 nanometers.

[0020] In some embodiments, when the thickness of the epitaxial layer is greater than 9 micrometers, the maximum ESFQR of the epitaxial silicon wafer is 60 nanometers.

[0021] The beneficial effects of this application are:

[0022] In the epitaxial layer growth process, a homogeneous epitaxial layer is grown in stages on one side of the substrate material. An intermediate epitaxial layer is deposited on the substrate silicon wafer, and then the edge morphology flatness of the intermediate epitaxial layer is compensated. Finally, a top epitaxial layer is deposited on the intermediate epitaxial layer. This allows the morphology of the top epitaxial layer to match that of the intermediate epitaxial layer. After the top epitaxial layer is formed on the intermediate epitaxial layer, the flatness of the epitaxial silicon wafer can be improved, resulting in an epitaxial silicon wafer with good flatness. Attached Figure Description

[0023] Figures 1 and 2 show schematic diagrams of the process of preparing wafer epitaxial layers using related technologies;

[0024] Figure 3 shows a schematic diagram of the edge morphology of the silicon wafer;

[0025] Figure 4 shows a schematic diagram of the fabrication of epitaxial silicon wafers with thin epitaxial layers using related technologies;

[0026] Figure 5 shows a schematic diagram of the fabrication of epitaxial silicon wafers with a relatively thick epitaxial layer using related technologies;

[0027] Figure 6 is a schematic diagram of the process of preparing the wafer epitaxial layer in an embodiment of this application;

[0028] Figure 7 shows a schematic diagram of the preparation of the intermediate epitaxial layer in an embodiment of this application;

[0029] Figure 8 shows a schematic diagram of the intermediate epitaxial layer after etching according to an embodiment of this application;

[0030] Figure 9 shows a schematic diagram of the preparation of the top epitaxial layer in an embodiment of this application;

[0031] Figure 10 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer with an epitaxial layer thickness of 4 micrometers in the related technology;

[0032] Figure 11 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer with an epitaxial layer thickness of 4 micrometers according to an embodiment of this application.

[0033] Figure 12 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer with an epitaxial layer thickness of 8 micrometers in the related technology;

[0034] Figure 13 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer with an epitaxial layer thickness of 8 micrometers according to an embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application are within the scope of protection of this application.

[0036] The flatness of epitaxial silicon wafers typically includes flatness metrics such as Edge Site Frontsurface referenced least sQuares / Range (ESFQR), Site Frontsurface referenced least sQuares / Range (SFQR), Edge Site Frontsurface referenced least sQuares / Deviation (ESFQD), and Global Backsurface-referenced Ideal plane / Range (GBIR). Among these, ESFQR and ESFQD are used to measure the flatness of the silicon wafer edge morphology.

[0037] As shown in Figure 2, the susceptor edge of the silicon substrate is designed as a slope. During epitaxial growth, the process gas passes sequentially through the susceptor edge and the silicon substrate, with the process gas first contacting the edge of the silicon substrate to initiate a film formation reaction. As shown in Figure 3, ESFQD represents the change in the roll-up and roll-off of the silicon wafer edge relative to the reference plane. The edge morphology of the silicon substrate can be intuitively characterized by the "+" or "-" change relative to the reference plane. In this embodiment, the edge morphology of the silicon substrate is roll-off, and the ESFQD value of the silicon substrate ranges from -60 nm to 0 nm. ESFQR represents the range of thickness variation along the radial length, which is the range of variation of the silicon wafer edge region relative to the least squares reference plane. Generally, after removing 2mm from the silicon wafer edge, the entire silicon wafer edge region is divided into 72 equal sectors, each sector with a chord length of 15mm. The value of ESFQR is the variation of each sector edge region relative to the least squares reference plane. ESFQR is equal to the sum of the absolute values ​​of ESFQD(+) and ESFQD(-), and the value of ESFQR is always greater than 0.

[0038] In related technologies, as shown in Figures 4 and 5, when preparing an epitaxial silicon wafer, a substrate silicon wafer 01 is provided, and an epitaxial layer 02 is epitaxially grown on the substrate silicon wafer 01 to obtain an epitaxial silicon wafer. As can be seen from Figures 4 and 5, the thickness of the edge region of the substrate silicon wafer 01 is less than the thickness of the central region. Furthermore, because the process gas first contacts the edge of the substrate silicon wafer during epitaxial growth, the growth rate of the epitaxial layer in the edge region of the substrate silicon wafer 01 is greater than the growth rate of the epitaxial layer in other regions. This results in the thickness of the epitaxial layer 02 at the edge region being greater than the thickness in other regions; that is, the edge morphology of the grown epitaxial layer 02 is generally roll-up. To further improve the surface flatness and edge flatness of the epitaxial silicon wafer, a substrate silicon wafer 01 with a morphology matching that of the epitaxial layer 02 needs to be provided; that is, the edge morphology of the substrate silicon wafer 01 should be roll-off. When forming a relatively thin epitaxial layer 02, such as less than 3 micrometers, as shown in Figure 4, the formation of the epitaxial layer 02 has a limited impact on the surface flatness and edge flatness of the epitaxial silicon wafer, and can form an epitaxial silicon wafer with good surface flatness. However, as the thickness of the epitaxial layer increases, when forming a relatively thick epitaxial layer 02, such as more than 4 micrometers, as shown in Figure 5, due to the longer growth time of the epitaxial layer 02, the thickness difference between the edge region and other regions of the epitaxial layer 02 is relatively large, and the morphology roll-up trend of the epitaxial layer 02 is more significant, resulting in poor surface flatness and poor edge flatness quality of the epitaxial silicon wafer.

[0039] To address the aforementioned issues, this application provides an epitaxial silicon wafer and a method for manufacturing the same, which improves the flatness of the epitaxial silicon wafer and provides an epitaxial silicon wafer with good flatness.

[0040] As shown in Figure 6, the epitaxial silicon wafer manufacturing method of this application generally involves two steps in the preparation of the epitaxial layer. The first step is chamber etching, in which hydrogen (H2) and etching gas (HCl) are introduced. Hydrogen (H2) acts as the main gas flow to carry the etching gas (HCl) and react with the byproducts deposited in the reaction chamber, thus self-cleaning the reaction chamber. The second step is epitaxial layer growth, specifically including: loading the substrate silicon wafer: introducing hydrogen (H2), silicon source gas (SiHCl3 / H2), and dopant gas (B2H6 / H2) to load the substrate silicon wafer into the reaction chamber; hydrogen baking: the epitaxial reaction chamber is baked under high temperature conditions with hydrogen to remove the oxide film on the surface of the substrate silicon wafer, obtaining a clean epitaxial substrate silicon wafer; first surface etching: the substrate silicon wafer is surface etched using etching gas (HCl) to obtain a clean substrate silicon wafer. The process involves: First-stage epitaxial growth: Epitaxial growth is performed on the substrate silicon wafer to deposit an intermediate epitaxial layer; Edge flatness compensation (second surface etching): After depositing the intermediate epitaxial layer, an etching gas (HCl) is introduced to etch the surface of the intermediate epitaxial layer, changing its morphology so that the thickness of the edge region is less than the thickness of the center region, the ESFQD value of the intermediate epitaxial layer is less than 0 nanometers, and the edge morphology of the intermediate epitaxial layer is roll-off; Second-stage epitaxial growth: Epitaxial growth is performed after the second surface etching step to deposit a top epitaxial layer. The edge morphology of the top epitaxial layer is roll-up, matching the morphology of the top epitaxial layer with that of the intermediate epitaxial layer; This yields an epitaxial silicon wafer with good surface flatness, which is then unloaded.

[0041] Specifically, the process involves: hydrogen baking: Hydrogen gas is introduced into the epitaxial reaction chamber at 1100–1200°C at a flow rate of 70,000–90,000 sccm to bake the substrate silicon wafer, removing the oxide film on the surface and obtaining a clean epitaxial substrate silicon wafer; first surface etching: An etching gas (HCl) is introduced at 1000–1200°C at a flow rate of 1100–1300 sccm for 5–15 seconds to etch the surface of the substrate silicon wafer, resulting in a clean substrate silicon wafer; first-stage epitaxial growth: During the reaction… Under conditions of a chamber temperature of 1000–1200℃, a hydrogen flow rate of 70,000–90,000 sccm, a SiHCl3 / H2 film-forming gas flow rate of 5,000–7,000 sccm, and a B2H6 / H2 doping gas flow rate of 200–300 sccm, the first stage of epitaxial growth is performed on the substrate silicon wafer to deposit an intermediate epitaxial layer; edge morphology flatness compensation (second surface etching) is then performed: after depositing the intermediate epitaxial layer, under the conditions of a reaction chamber temperature of 1000–1200℃ and a hydrogen flow rate of… Under conditions of 70,000–90,000 sccm and HCl flow rate of 1100–1300 sccm, surface etching of the intermediate epitaxial layer is performed for 15–30 s to modify its morphology. This alters the thickness of the edge region of the intermediate epitaxial layer to be less than that of the central region, resulting in an ESFQD value of -40 nm to 0 nm and a roll-off edge morphology. The second stage of epitaxial growth occurs after the second surface etching step, within the reaction chamber. Under conditions of a chamber temperature of 1000–1200℃, a hydrogen flow rate of 70000–90000 sccm, a SiHCl3 / H2 film-forming gas flow rate of 5000–7000 sccm, and a B2H6 / H2 doping gas flow rate of 200–300 sccm, a top epitaxial layer is deposited. The edge morphology of the top epitaxial layer is roll-up, so that the morphology of the top epitaxial layer matches the morphology of the middle epitaxial layer. This can yield an epitaxial silicon wafer with good surface flatness, after which the epitaxial silicon wafer is unloaded.

[0042] The epitaxial layer growth process in the manufacturing method of the epitaxial silicon wafer of this application is illustrated in Figures 7-9. Specifically, it includes: As shown in Figure 7, Stage 1: Providing a substrate silicon wafer 11, the thickness of the edge region of the substrate silicon wafer 11 is less than the thickness of the center region, the edge morphology of the substrate silicon wafer 11 is roll-off, and the ESFQD value of the substrate silicon wafer 11 is between -60 nm and 0 nm, for example, between -40 nm and 0 nm; Depositing an intermediate epitaxial layer 12 on the substrate silicon wafer, the growth rate of the edge region of the intermediate epitaxial layer 12 is greater than the growth rate of other regions, the thickness of the edge region of the intermediate epitaxial layer 12 is greater than the thickness of other regions, the edge morphology of the intermediate epitaxial layer 12 is roll-up, and the morphology of the intermediate epitaxial layer 12 matches the morphology of the substrate silicon wafer 11. The surface of the intermediate epitaxial layer 12 away from the substrate silicon wafer 11 is flat. Then, as shown in Figure 8, edge morphology flatness compensation is performed on the intermediate epitaxial layer to make the edge morphology of the intermediate epitaxial layer 12 roll-off. The ESFQD value of the intermediate epitaxial layer 12 is between -40 nm and 0 nm, for example, it can be between -20 nm and -15 nm. The thickness of the edge region of the intermediate epitaxial layer 12 is less than the thickness of the center region. If the intermediate epitaxial layer 12 is not etched, the morphology (roll-up) of the continued growing epitaxial layer does not match the morphology of the intermediate epitaxial layer 12 (the surface of the intermediate epitaxial layer 12 away from the substrate silicon wafer 11 is flat). The edge morphology of the obtained epitaxial silicon wafer will be as shown in Figure 5, resulting in poor surface flatness of the epitaxial silicon wafer. As shown in Figure 9, in stage two, a top epitaxial layer 13 is deposited on the intermediate epitaxial layer 12. The growth rate of the edge region of the top epitaxial layer 13 is greater than that of other regions, and the thickness of the edge region of the top epitaxial layer 13 is greater than that of other regions. The edge morphology of the top epitaxial layer 13 is roll-up, and the morphology of the top epitaxial layer 13 matches that of the intermediate epitaxial layer 12. The top epitaxial layer 13 and the intermediate epitaxial layer 12 together form the epitaxial layer 14 of the epitaxial silicon wafer, which gives the epitaxial silicon wafer good surface flatness.

[0043] In some embodiments, at least one of the phase one and one phase two may be included.

[0044] In some embodiments, the thickness of the intermediate epitaxial layer and the top epitaxial layer may not exceed 4 micrometers, because when the thickness of the epitaxial layer grown each time is greater than 4 micrometers, the edge flatness of the epitaxial layer will deteriorate. Therefore, optionally, the thickness of the epitaxial layer grown each time is not greater than 4 micrometers.

[0045] In some embodiments, the thickness of the intermediate epitaxial layer 12 and the top epitaxial layer 13 can be equal; of course, the thickness of the intermediate epitaxial layer and the top epitaxial layer can also be unequal.

[0046] In this embodiment, the number of stages in Stage 1 can be determined based on the required total thickness of the epitaxial layer. For example, if the required total thickness of the epitaxial layer is 15 micrometers, then four Stage 1 stages and one Stage 2 stages can be set, with the thickness of the intermediate and top epitaxial layers deposited in each Stage 1 and Stage 2 stages being 3 micrometers. Alternatively, if the required total thickness of the epitaxial layer is 12 micrometers, then three Stage 1 stages and one Stage 2 stages can be set, with the thickness of the intermediate and top epitaxial layers deposited in each Stage 1 and Stage 2 stages being 3 micrometers. Another example is if the required total thickness of the epitaxial layer is 9 micrometers, then two Stage 1 stages and one Stage 2 stages can be set, with the thickness of the intermediate and top epitaxial layers deposited in each Stage 1 and Stage 2 stages being 3 micrometers. If the required total thickness of the epitaxial layer is 6 micrometers, then one... The process involves two stages: Stage 1 and Stage 2. The thickness of the intermediate and top epitaxial layers deposited in each stage is 3 micrometers. If the total thickness of the epitaxial layers required is 4 micrometers, then one Stage 1 and one Stage 2 can be used. Stage 1 deposits an intermediate epitaxial layer with a thickness of 2.5 micrometers, and Stage 2 deposits a top epitaxial layer with a thickness of 1.5 micrometers. Therefore, by adopting the technical solution of this embodiment, even when preparing epitaxial silicon wafers with thicker epitaxial layers (e.g., thickness greater than 6 micrometers), good surface flatness of the epitaxial silicon wafer can be guaranteed.

[0047] As shown in Figure 2, the susceptor edge of the substrate silicon wafer is designed as a slope. During epitaxial growth, the process gas passes through the susceptor edge and the substrate silicon wafer in sequence. The process gas first contacts the edge of the substrate silicon wafer and undergoes a film formation reaction, thus forming a roll-up morphology at the edge of the epitaxial layer. In order to ensure the overall flatness of the epitaxial silicon wafer, the edge morphology of the substrate silicon wafer is required to be roll-off, that is, the maximum value of ESFQD is less than 0. This allows the edge morphology of the epitaxial layer to match the edge morphology of the substrate silicon wafer.

[0048] When growing epitaxial layers of the same thickness, the maximum ESFQR of the epitaxial silicon wafer and the maximum ESFQD of the substrate silicon wafer are linearly correlated. To obtain epitaxial silicon wafers with good flatness, it is desirable for the edge morphology of the substrate silicon wafer to remain consistent, with ESFQD fluctuating within a very small range (±5nm). However, due to limitations in the front-end processing capabilities, the ESFQD of the substrate silicon wafer can fluctuate within a certain range, for example, from -40 nm to 0 nm. Generally, when preparing epitaxial silicon wafers with an epitaxial layer thickness of 2 to 6 micrometers, when the substrate silicon wafer ESFQD is less than -40 nm, the ESFQR of the epitaxial silicon wafer is greater than 40 nm, indicating poor flatness. When the ESFQD value of the substrate silicon wafer is within the range of -40 nm to 0 nm, the edge morphology of the substrate silicon wafer can be matched with the edge morphology of the epitaxial layer, resulting in an epitaxial silicon wafer with better flatness. In this embodiment, when forming the top epitaxial layer, the intermediate epitaxial layer serves as the substrate of the top epitaxial layer. Therefore, the ESFQD value of the intermediate epitaxial layer can be selected from -40 nanometers to 0 nanometers.

[0049] In some embodiments, the maximum ESFQD of the intermediate epitaxial layer can be from -20 nm to -15 nm, for example, it can be -20 nm, -19 nm, -18 nm, -17 nm, -16 nm or -15 nm.

[0050] Since the edges of the silicon wafer are nearly horizontal or convex after the epitaxial growth of the intermediate epitaxial layer on the substrate silicon wafer, a longer etching time is required to form the edge morphology of the intermediate epitaxial layer as roll off. Therefore, the intermediate epitaxial layer is etched by extending the reaction time of the etching gas (HCl).

[0051] In related technologies, when fabricating epitaxial layers with a thickness of 3 to 5 micrometers on a silicon substrate, the maximum ESFQR of the epitaxial silicon wafer can reach 28 to 30 nanometers. Figure 10 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer with an epitaxial layer thickness of 4 micrometers in related technologies. Figure 10 shows the ESFQR values ​​of various edge regions of the epitaxial silicon wafer. In Figure 10, the horizontal axis is the angular coordinate corresponding to each edge region, and the vertical axis is the ESFQR value corresponding to each edge region, with the unit being nanometers (nm). For example, if the angle between the radius of the center point of an edge region of the epitaxial silicon wafer and the reference radius of the epitaxial silicon wafer is 45°, then the angular coordinate corresponding to that edge region is 45°. It can be seen that the ESFQR value of the fabricated epitaxial silicon wafer is 9.8 to 28.7 nanometers, with a maximum ESFQR of 28.7 nanometers, indicating poor surface flatness of the epitaxial silicon wafer.

[0052] In the technical solution of this embodiment, when the thickness of the epitaxial layer is 3 micrometers to 5 micrometers, by improving the epitaxial layer deposition process, through a first-stage epitaxial growth and a second-stage epitaxial growth, and by etching the intermediate epitaxial layer in the first-stage epitaxial growth, the edge morphology of the intermediate epitaxial layer is made to be roll-off. When the ESFQD value of the intermediate epitaxial layer is controlled in the range of -40 nanometers to 0 nanometers, the maximum value of the overall ESFQR of the epitaxial silicon wafer can be reduced to less than 24.6 nanometers, thereby improving the surface flatness of the epitaxial silicon wafer.

[0053] In specific example 1, a 2-micrometer-thick intermediate epitaxial layer is deposited on a silicon substrate. The intermediate epitaxial layer is then etched to achieve a roll-off edge morphology. The ESFQD value of the intermediate epitaxial layer ranges from -25 nm to -15 nm. Subsequently, a 2-micrometer-thick top epitaxial layer is deposited on the intermediate epitaxial layer. The top epitaxial layer has a roll-up edge morphology, matching the morphology of the intermediate epitaxial layer. The edge flatness of the epitaxial silicon wafer is shown in Figure 11. The ESFQR values ​​of each edge region of the epitaxial silicon wafer are shown in Figure 11. The horizontal axis of Figure 11 represents the angular coordinates of each edge region, and the vertical axis represents the ESFQR value of each edge region. For example, if the angle between the radius of the center point of an edge region and the reference radius of the epitaxial silicon wafer is 90°, then the angular coordinate of that edge region is 90°. It can be seen that the maximum ESFQR of the epitaxial silicon wafer is reduced to 22.9 nanometers. Compared with related technologies, the surface flatness of the epitaxial silicon wafer is improved.

[0054] In specific example 2, a 2.5-micrometer-thick intermediate epitaxial layer is deposited on a substrate silicon wafer. The intermediate epitaxial layer is then etched to make its edge morphology roll-off. The ESFQD value of the intermediate epitaxial layer ranges from -20 nanometers to -10 nanometers. Subsequently, a 1.5-micrometer-thick top epitaxial layer is deposited on the intermediate epitaxial layer. The edge morphology of the top epitaxial layer is roll-up, and the morphology of the top epitaxial layer matches that of the intermediate epitaxial layer. The maximum ESFQR of the epitaxial silicon wafer is 23.8 nanometers. Compared with forming an epitaxial layer with a thickness of 4 micrometers directly on the substrate silicon wafer (the maximum ESFQR is 28.7 nanometers), this improves the surface flatness of the epitaxial silicon wafer.

[0055] In specific example 3, an intermediate epitaxial layer with a thickness of 1.5 micrometers is deposited on a substrate silicon wafer. The intermediate epitaxial layer is then etched to make its edge morphology roll-off. The ESFQD value of the intermediate epitaxial layer is between -30 nanometers and -20 nanometers. Subsequently, a top epitaxial layer with a thickness of 2.5 micrometers is deposited on the intermediate epitaxial layer. The edge morphology of the top epitaxial layer is roll-up. The morphology of the top epitaxial layer matches that of the intermediate epitaxial layer. The maximum ESFQR of the epitaxial silicon wafer is 24.6 nanometers. Compared with forming an epitaxial layer with a thickness of 4 micrometers directly on the substrate silicon wafer (the maximum ESFQR is 28.7 nanometers), this improves the surface flatness of the epitaxial silicon wafer.

[0056] In related technologies, when fabricating epitaxial layers with a thickness of 6 to 9 micrometers on a silicon substrate, the maximum ESFQR of the epitaxial silicon wafer can reach 70 to 74 nanometers. Figure 12 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer with an epitaxial layer thickness of 8 micrometers in related technologies. Figure 12 shows the ESFQR values ​​of various edge regions of the epitaxial silicon wafer. In Figure 12, the horizontal axis is the angular coordinate corresponding to each edge region, and the vertical axis is the ESFQR value corresponding to each edge region, with the unit being nanometers (nm). For example, if the angle between the radius of the center point of an edge region of the epitaxial silicon wafer and the reference radius of the epitaxial silicon wafer is 135°, then the angular coordinate corresponding to that edge region is 135°. It can be seen that the maximum ESFQR of the fabricated epitaxial silicon wafer is 72.4 nanometers, indicating poor surface flatness of the epitaxial silicon wafer.

[0057] In the technical solution of this embodiment, when the thickness of the epitaxial layer is 6 micrometers to 9 micrometers, by improving the epitaxial layer deposition process, through a first-stage epitaxial growth and a second-stage epitaxial growth, and by etching the intermediate epitaxial layer in the first-stage epitaxial growth, the edge morphology of the intermediate epitaxial layer is made to be roll-off. When the ESFQD value of the intermediate epitaxial layer is controlled in the range of -40 nanometers to 0 nanometers, the maximum value of the overall ESFQR of the epitaxial silicon wafer can be reduced to less than 55.8 nanometers, thereby improving the surface flatness of the epitaxial silicon wafer.

[0058] In specific example 4, a 4-micrometer-thick intermediate epitaxial layer is deposited on a silicon substrate. The intermediate epitaxial layer is then etched to achieve a roll-off edge morphology. The ESFQD value of the intermediate epitaxial layer ranges from -35 nm to -25 nm. Subsequently, a 4-micrometer-thick top epitaxial layer is deposited on the intermediate epitaxial layer. The top epitaxial layer has a roll-up edge morphology, matching the morphology of the intermediate epitaxial layer. The edge flatness of the epitaxial silicon wafer is shown in Figure 13. Figure 13 shows... The ESFQR values ​​of each edge region of the epitaxial silicon wafer were calculated. In Figure 13, the horizontal axis represents the angular coordinates of each edge region, and the vertical axis represents the ESFQR value of each edge region. For example, if the angle between the radius of the center point of an edge region and the reference radius of the epitaxial silicon wafer is 180°, then the angular coordinate of that edge region is 180°. It can be seen that the maximum ESFQR of the epitaxial silicon wafer is reduced to 55.8 nanometers. Compared with related technologies, the surface flatness of the epitaxial silicon wafer is improved.

[0059] In specific example 5, a first intermediate epitaxial layer with a thickness of 4 micrometers is deposited on a substrate silicon wafer. The first intermediate epitaxial layer is then etched to achieve a roll-off edge morphology. The ESFQD value of the first intermediate epitaxial layer ranges from -25 nanometers to -15 nanometers. Subsequently, a second intermediate epitaxial layer with a thickness of 2 micrometers is deposited on the first intermediate epitaxial layer. The second intermediate epitaxial layer is then etched to achieve a roll-off edge morphology. The ESFQD value of the second intermediate epitaxial layer also ranges from -25 nanometers to -15 nanometers. Finally, a top epitaxial layer with a thickness of 2 micrometers is deposited on the second intermediate epitaxial layer, with a roll-up edge morphology. The final maximum ESFQR value of the epitaxial silicon wafer is 52.6 nanometers. Compared to directly forming an 8-micrometer thick epitaxial layer on the substrate silicon wafer (with a maximum ESFQR of 72.4 nanometers), this improves the surface flatness of the epitaxial silicon wafer.

[0060] In specific example 6, a first intermediate epitaxial layer with a thickness of 3 micrometers is deposited on a substrate silicon wafer. The first intermediate epitaxial layer is then etched to achieve a roll-off edge morphology. The ESFQD value of the first intermediate epitaxial layer ranges from -30 nanometers to -20 nanometers. Subsequently, a second intermediate epitaxial layer with a thickness of 3 micrometers is deposited on the first intermediate epitaxial layer. The second intermediate epitaxial layer is then etched to achieve a roll-off edge morphology. The ESFQD value of the second intermediate epitaxial layer ranges from -25 nanometers to -15 nanometers. Finally, a top epitaxial layer with a thickness of 2 micrometers is deposited on the second intermediate epitaxial layer, with a roll-up edge morphology. The final maximum ESFQR value of the epitaxial silicon wafer is 50.8 nanometers. Compared to directly forming an 8-micrometer thick epitaxial layer on the substrate silicon wafer (with a maximum ESFQR of 72.4 nanometers), this improves the surface flatness of the epitaxial silicon wafer.

[0061] In specific example 7, an intermediate epitaxial layer with a thickness of 4 micrometers is deposited on a substrate silicon wafer. The intermediate epitaxial layer is then etched to make its edge morphology roll-off. The ESFQD value of the intermediate epitaxial layer is between -25 nanometers and -15 nanometers. Subsequently, a top epitaxial layer with a thickness of 2 micrometers is deposited on the intermediate epitaxial layer. The edge morphology of the top epitaxial layer is roll-up. The morphology of the top epitaxial layer matches that of the intermediate epitaxial layer. The maximum ESFQR of the epitaxial silicon wafer is 42.7 nanometers, which improves the surface flatness of the epitaxial silicon wafer.

[0062] In specific example 8, a 2-micrometer-thick intermediate epitaxial layer is deposited on a substrate silicon wafer. The intermediate epitaxial layer is then etched to make its edge morphology roll-off. The ESFQD value of the intermediate epitaxial layer is between -40 nm and -30 nm. Subsequently, a 5-micrometer-thick top epitaxial layer is deposited on the intermediate epitaxial layer. The edge morphology of the top epitaxial layer is roll-up. The morphology of the top epitaxial layer matches that of the intermediate epitaxial layer. The maximum ESFQR of the epitaxial silicon wafer is 53.8 nm, which improves the surface flatness of the epitaxial silicon wafer.

[0063] In related technologies, when an epitaxial layer with a thickness greater than 9 micrometers is prepared on a substrate silicon wafer, the maximum ESFQR of the epitaxial silicon wafer is greater than 80 nanometers, and the surface flatness of the epitaxial silicon wafer is poor.

[0064] In the technical solution of this embodiment, when the thickness of the epitaxial layer is greater than 9 micrometers, by improving the epitaxial layer deposition process, through a first-stage epitaxial growth and a second-stage epitaxial growth, and by etching the intermediate epitaxial layer in the first-stage epitaxial growth, the edge morphology of the intermediate epitaxial layer is made to be roll-off. When the ESFQD value of the intermediate epitaxial layer is controlled in the range of -40 nanometers to 0 nanometers, the maximum value of the overall ESFQR of the epitaxial silicon wafer can be reduced to less than 60 nanometers, thereby improving the surface flatness of the epitaxial silicon wafer.

[0065] In specific example 9, a first intermediate epitaxial layer with a thickness of 3 micrometers is deposited on a substrate silicon wafer. The first intermediate epitaxial layer is then etched to make its edge morphology roll-off. The ESFQD value of the first intermediate epitaxial layer ranges from -30 nanometers to -20 nanometers. Subsequently, a second intermediate epitaxial layer with a thickness of 3 micrometers is deposited on the first intermediate epitaxial layer. The second intermediate epitaxial layer is then etched to make its edge morphology roll-off. The ESFQD value of the second intermediate epitaxial layer ranges from -35 nanometers to -25 nanometers. Finally, a top epitaxial layer with a thickness of 4 micrometers is deposited on the second intermediate epitaxial layer. The edge morphology of the top epitaxial layer is roll-up. The final maximum ESFQR value of the epitaxial silicon wafer is 59.6 nanometers.

[0066] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0067] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0068] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0069] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0070] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for manufacturing an epitaxial silicon wafer, comprising the step of growing a homogeneous epitaxial layer in stages on one side of a substrate material during the epitaxial layer growth process, including: Provide substrate silicon wafers; Phase 1: Deposit an intermediate epitaxial layer on the substrate silicon wafer, and then perform edge morphology flatness compensation on the intermediate epitaxial layer; Phase 2: Deposit the top epitaxial layer on the intermediate epitaxial layer; The method includes at least one Phase 1 and one Phase 2.

2. The method for manufacturing an epitaxial silicon wafer according to claim 1, wherein, In the first stage, the edge topography flatness of the intermediate epitaxial layer is compensated by an etching step, so that the range of the frontal reference least squares deviation (ESFQD) value of the edge portion of the intermediate epitaxial layer is -40 nm to 0 nm.

3. The method for manufacturing an epitaxial silicon wafer according to claim 2, wherein, In the first stage, after depositing at least one intermediate epitaxial layer on the substrate silicon wafer, an etching gas is introduced to etch the intermediate epitaxial layer.

4. The method for manufacturing an epitaxial silicon wafer according to claim 3, wherein, The intermediate epitaxial layer is etched by extending the reaction time of the etching gas.

5. An epitaxial silicon wafer manufactured by a method for manufacturing an epitaxial silicon wafer according to any one of claims 1-4, wherein the ESFQR value of the frontal reference least squares range at the edge of the epitaxial silicon wafer ranges from 0 nanometers to 60 nanometers.

6. The epitaxial silicon wafer according to claim 5, wherein, When the thickness of the epitaxial layer is 3 to 5 micrometers, the maximum ESFQR of the epitaxial silicon wafer is 24.6 nanometers.

7. The epitaxial silicon wafer according to claim 5, wherein, When the thickness of the epitaxial layer is 6 micrometers to 9 micrometers, the maximum ESFQR of the epitaxial silicon wafer is 55.8 nanometers.

8. The epitaxial silicon wafer according to claim 5, wherein, When the thickness of the epitaxial layer is greater than 9 micrometers, the maximum ESFQR of the epitaxial silicon wafer is 60 nanometers.

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