Back contact cell having low-cost metal electrode, manufacturing method therefor, and battery module

Abstract

The embodiments of the present disclosure belong to the technical field of back contact cells, and specifically relate to a back contact cell having a low-cost metal electrode, a manufacturing method therefor, and a battery module. The back contact cell comprises a silicon wafer and, disposed on a back surface of the silicon wafer, a semiconductor distribution layer and a conductive film layer. The semiconductor distribution layer comprises first semiconductor layers and second semiconductor layers, second semiconductor opening areas being formed between adjacent first semiconductor layers. The back contact cell further comprises a metal conductive film layer and a solderable conductive film layer which are successively disposed on an outer surface of the conductive film layer, as well as first insulating ink and second insulating ink. Isolation trenches are formed in the conductive film layer corresponding to edge areas of the second semiconductor opening areas, the isolation trenches extending outwards to penetrate through the metal conductive film layer and the solderable conductive film layer in the corresponding areas. The embodiments of the present disclosure greatly reduce the thickness of the insulating ink, reduce the amount of the insulating ink used, greatly reduce the height of grid lines, and do not require silver paste fingers and busbars, thereby significantly reducing cell cost while ensuring excellent cell performance.

Description

Low-cost metal electrode back contact battery, its fabrication method and battery module

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024105661678, filed on May 9, 2024, entitled “Back Contact Battery with Low-Cost Metal Electrode and its Preparation Method and Battery Module,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure belongs to the field of back contact battery technology, specifically relating to a low-cost metal electrode back contact battery, its preparation method, and battery module. Background Technology

[0004] Currently, back-contact batteries have the following problems: 1. The metal electrodes of back-contact batteries generally use silver paste grid electrodes, which consume a very large amount of silver paste, resulting in high costs. 2. The metal electrodes of back-contact batteries are all on the back of the battery. The metal electrodes generally need to be formed in the following order: first, printing silver paste fine grids, then printing insulating ink, and finally printing silver paste main grids. Because the silver paste fine grids are quite high and uneven (exceeding 25μm), the insulating ink, to ensure insulation effectiveness, generally needs to be at least 30μm thick. This significantly increases the amount of insulating ink used and the difficulty of connecting the main grid to the fine grids. Furthermore, during module manufacturing, the gap between the tin alloy layer and the conductive film layer is very large before the solder ribbon melts. Without a main grid or a high solder joint layer, it is difficult for the solder ribbon to connect well to the conductive film layer, causing the current in the corresponding area to be unable to be drawn out through the solder ribbon, thus affecting module performance. 3. The main grid electrode of the back contact battery is connected to the fine grid electrode of the same polarity. During module manufacturing, the solder ribbon is connected to the main grid to form a battery string. The main grid electrode is generally formed by printing silver paste, which further increases the amount of silver paste used. 4. If the metal electrode adopts the copper electroplating process, it requires masking, exposure and development, electroplating, and film removal processes, which significantly increases the equipment cost and seriously affects the battery production yield.

[0005] It should be noted that this part of the disclosure only provides background technology related to this disclosure, and does not necessarily constitute prior art or publicly known technology. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of existing technologies, such as the large amount of silver paste and insulating ink used in back contact batteries, resulting in high battery costs and the inability to achieve good battery production yield and other battery performance issues. This disclosure provides a low-cost metal electrode back contact battery, its preparation method, and battery module. This disclosure significantly reduces the thickness and amount of insulating ink, significantly reduces the height of the grid lines, eliminates the need for silver paste fine grids and main grids, significantly reduces battery costs, and ensures excellent battery performance.

[0007] To achieve the above objectives, in a first aspect, embodiments of this disclosure provide a low-cost metal electrode back contact battery, comprising a silicon wafer, a semiconductor distribution layer disposed on the back side of the silicon wafer, and a conductive film layer disposed on the outer surface of the semiconductor distribution layer. The semiconductor distribution layer includes a first semiconductor layer and a second semiconductor layer alternately disposed along the back side, with a second semiconductor opening region formed between adjacent first semiconductor layers. It also includes a metal conductive film layer and a solderable conductive film layer sequentially disposed on the outer surface of the conductive film layer, as well as a first insulating ink and a second insulating ink. An isolation groove is formed on the conductive film layer corresponding to the edge region of the second semiconductor opening region, and the isolation groove extends outward through the metal conductive film layer and the solderable conductive film layer in the corresponding region.

[0008] The first insulating ink is disposed on the outer surface of the solderable conductive film layer corresponding to the first semiconductor layer and is spaced apart along the length direction of the first semiconductor layer. The first insulating ink crosses the isolation grooves on both sides of the first semiconductor layer and extends to at least cover the outer surface of the edge of the solderable conductive film layer corresponding to the adjacent second semiconductor opening area. The second insulating ink is disposed on the outer surface of the solderable conductive film layer corresponding to the second semiconductor opening area and is spaced apart along the length direction of the second semiconductor layer. The second insulating ink crosses the isolation grooves on both sides of the second semiconductor opening area and extends to at least cover the outer surface of the edge of the solderable conductive film layer corresponding to the adjacent first semiconductor layer. The first insulating ink and the second insulating ink are alternately disposed along the length direction.

[0009] The thickness of the weldable conductive film layer is 10-100nm, and the maximum thickness of the first insulating ink and the second insulating ink are each 1-5μm.

[0010] In some preferred embodiments of this disclosure, the weldable conductive film layer is at least one of metallic tin, tin alloy, metallic nickel, nickel alloy, indium, and indium alloy.

[0011] In some preferred embodiments of this disclosure, the metal conductive film layer is at least one of aluminum, copper, silver, and titanium.

[0012] In some preferred embodiments of this disclosure, the outer surface of the weldable conductive film layer is entirely located on the same plane.

[0013] In some preferred embodiments of this disclosure, the metal conductive film layer fills the corresponding semiconductor opening region while the overall outer surface is flush.

[0014] In some preferred embodiments of this disclosure, the total thickness of the metal conductive film layer and the solderable conductive film layer does not exceed 1 μm.

[0015] In some preferred embodiments of this disclosure, the thickness of the metal conductive film is 90-500 nm.

[0016] In some preferred embodiments of this disclosure, the thickness of the conductive film is 30-100 nm.

[0017] In some preferred embodiments of this disclosure, the sheet resistance of the stack of the metal conductive film layer and the solderable conductive film layer is less than 0.3 Ω / □.

[0018] In some preferred embodiments of this disclosure, the width W3 of the isolation groove is 50-400 μm.

[0019] In some preferred embodiments of this disclosure, the first semiconductor layer includes a first passivation layer and a first doped polysilicon layer, and the second semiconductor layer is a second passivation layer and a second doped silicon layer; one of the first doped polysilicon layer and the other of the second doped silicon layer is N-type and the other is P-type; the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0020] In some preferred embodiments of this disclosure, the two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. The second semiconductor opening region and the first semiconductor opening region are arranged alternately, and the area between them is a gap region.

[0021] Optionally, a mask layer may be provided or not provided between the first semiconductor layer and the second semiconductor layer within the spacing region.

[0022] In some preferred embodiments of this disclosure, the back contact cell of the low-cost metal electrode further includes a front passivation layer and an antireflection layer disposed on the front side of the silicon wafer.

[0023] Secondly, embodiments of this disclosure provide a method for preparing a low-cost metal electrode back contact battery, configured to prepare the low-cost metal electrode back contact battery described in the first aspect. The method for preparing the low-cost metal electrode back contact battery includes the following steps:

[0024] S100, A back contact semi-finished battery is provided in which a semiconductor distribution layer is formed on the back side of a silicon wafer, wherein a second semiconductor opening region arranged at intervals is etched on the first semiconductor layer;

[0025] S101. A conductive film layer, a metal conductive film layer, and a solderable conductive film layer are deposited sequentially to fully cover the back of the back of the semi-finished battery in back contact.

[0026] S102. An opening is etched in the conductive film layer corresponding to the edge region of the second semiconductor opening area and the corresponding metal conductive film layer and solderable conductive film layer thereon to form an isolation trench.

[0027] S103, First insulating ink and second insulating ink are alternately formed on the outer surfaces of the corresponding regions of the first semiconductor opening region and the second semiconductor opening region, respectively.

[0028] In some preferred embodiments of this disclosure, S100 further includes: forming a front passivation layer and an antireflection layer on the front side of the silicon wafer.

[0029] In some preferred embodiments of this disclosure, the process of providing a back contact semi-finished battery with a semiconductor distribution layer formed on the back side of a silicon wafer in step S100 includes:

[0030] A first semiconductor layer and a mask layer are formed on the back side of the silicon wafer. A first etching opening is made on the first semiconductor layer and its corresponding mask layer to form a second semiconductor opening region arranged at intervals.

[0031] Then, a second semiconductor layer is formed on the back side, and a second etching opening is made on the second semiconductor layer and the corresponding mask layer below it to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0032] Thirdly, embodiments of this disclosure provide a battery module, including a back contact battery with a low-cost metal electrode as described in the first aspect or a back contact battery with a low-cost metal electrode as described in the second aspect, and solder strips arranged in series on the outer surface of the back insulating ink; the solder strips include metallic copper and tin alloy coatings disposed on both sides of the metallic copper, and a weldable conductive film layer is connected to a corresponding portion of the tin alloy coating.

[0033] In some preferred embodiments of this disclosure, the tin alloy coating further has at least one of the following characteristics:

[0034] Feature 1: The thickness T2 of the tin alloy coating is 15-30 μm;

[0035] Feature 2: The thickness T2 of the tin alloy coating is 4-20 times the maximum thickness T1 of the corresponding insulating ink;

[0036] Feature 3: The melting point of the tin alloy coating is 100-250℃. Beneficial effects:

[0037] The embodiments of this disclosure, through the above-described technical solutions, particularly by using a metal conductive film layer and a solderable conductive film layer to replace the silver paste fine grid lines and main grid, significantly reduce the thickness and amount of insulating ink, and substantially reduce the height of the grid lines. This disclosure eliminates the need for silver paste fine grid lines and main grid lines, significantly reducing battery costs. Furthermore, the solderable conductive film layer of this disclosure, with its suitable thickness, exhibits excellent miscibility with the tin alloy coating of the solder ribbon, enabling a good connection. Combined with specifically designed isolation grooves and corresponding insulating ink, this helps to ensure excellent battery performance. In contrast, existing back-contact batteries can have silver paste fine grid lines with a height exceeding 20 μm, requiring a thick insulating ink layer to cover the silver paste fine grid lines, resulting in high costs.

[0038] When manufacturing battery modules using the back contact battery disclosed herein, the solder ribbon and the solderable conductive film layer can form a good connection. Furthermore, due to the thinness of the insulating ink (which can be much smaller than the thickness of the tin alloy coating on the solder ribbon and within the aforementioned suitable multiple range), the gap between the tin alloy coating on the solder ribbon and the solderable conductive film layer is very small. After the thicker tin alloy coating on the surface of the solder ribbon melts, it can easily contact the solderable conductive film layer, which helps to improve the reliability of battery connection. Moreover, there is no need to manufacture silver paste grids, thereby significantly reducing the cost of battery metal electrodes. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 is a cross-sectional schematic diagram of the semi-finished battery with back contact provided in this disclosure;

[0041] Figure 2 is a cross-sectional schematic diagram of the conductive film layer, the metal conductive film layer and the solderable conductive film layer formed on the back side of the back contact semi-finished battery of this disclosure.

[0042] Figure 3 is a cross-sectional schematic diagram of the isolation groove formed on the back of the battery according to the present disclosure;

[0043] Figure 4a is a cross-sectional schematic diagram of the first insulating ink formed on the outer surface of the first semiconductor opening area on the back of the battery according to the present disclosure;

[0044] Figure 4b is a cross-sectional schematic diagram of the second insulating ink formed on the outer surface of the second semiconductor opening region on the back of the battery according to the present disclosure.

[0045] Figure 5 is a cross-sectional schematic diagram of the corresponding solder strip for the battery module fabricated according to this disclosure;

[0046] Figure 6a is a schematic cross-sectional view of the connection between the solder strip of this disclosure and the solderable conductive film layer on the outer surface of the second semiconductor layer on the back of the battery.

[0047] Figure 6b is a cross-sectional schematic diagram showing the connection between the solder strip of this disclosure and the solderable conductive film layer on the outer surface of the first semiconductor layer on the back of the battery.

[0048] Figure 7 is a cross-sectional schematic diagram of the battery module in Comparative Example 1.

[0049] Figure 8 is a schematic diagram of the structure of the first insulating ink and the second insulating ink on the back of the battery.

[0050] Figure 9 is a schematic diagram of the connection between the welding strip and the weldable conductive film layer on the back of the battery.

[0051] Explanation of reference numerals in the attached figures: 1. Silicon wafer; 2. Tunneling oxide layer; 3. N-type doped polycrystalline silicon layer; 4. Mask layer; 5. Intrinsically doped amorphous silicon layer; 6. P-type doped amorphous silicon layer; 7. Antireflection layer; 8. Transparent conductive film layer; 9. Metallic conductive film layer; 10. Solderable conductive film layer; 11N. First insulating ink; 11P. Second insulating ink; 200. Solder ribbon; 201. Metallic copper; 202. Tin alloy coating; 9A. Silver paste fine gate electrode; 9B. Silver paste main gate electrode; 11m. Insulating ink. Detailed Implementation

[0052] In this disclosure, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are generally used to refer to the orientation as shown in the accompanying drawings and in practical applications.

[0053] Furthermore, the terms "first" and "second" are configured for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0055] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "discretionary" mean that they may or may not be included (or may or may not be present).

[0056] In the embodiments disclosed herein, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside.

[0057] In a first aspect, embodiments of this disclosure provide a low-cost metal electrode back-contact battery, comprising a silicon wafer, a semiconductor distribution layer disposed on the back side of the silicon wafer, and a conductive film layer disposed on the outer surface of the semiconductor distribution layer. The semiconductor distribution layer includes a first semiconductor layer and a second semiconductor layer alternately disposed along the back side, with a second semiconductor opening region formed between adjacent first semiconductor layers. The battery also includes a metal conductive film layer and a solderable conductive film layer sequentially disposed on the outer surface of the conductive film layer, as well as a first insulating ink and a second insulating ink. An isolation trench is formed on the conductive film layer corresponding to the edge region of the second semiconductor opening region, extending outward through the metal conductive film layer and the solderable conductive film layer in the corresponding region. The isolation trench spans the edge region of the second semiconductor opening region, which can reduce leakage current between the first and second semiconductors and improve battery conversion efficiency.

[0058] It is understandable that the isolation groove has a through opening in the integral film layer formed by the conductive film layer, the metal conductive film layer, and the solderable conductive film layer.

[0059] The first insulating ink is disposed on the outer surface of the corresponding solderable conductive film layer of the first semiconductor layer and spaced apart along the length of the first semiconductor layer. The first insulating ink crosses the isolation grooves on both sides of the first semiconductor layer and extends to at least cover the outer surface of the edge of the solderable conductive film layer corresponding to the adjacent second semiconductor opening area. The second insulating ink is disposed on the outer surface of the corresponding solderable conductive film layer of the second semiconductor opening area and spaced apart along the length of the second semiconductor layer. The second insulating ink crosses the isolation grooves on both sides of the second semiconductor opening area and extends to at least cover the outer surface of the edge of the solderable conductive film layer corresponding to the adjacent first semiconductor layer. The first and second insulating inks are alternately disposed along the length. By having each insulating ink cross the corresponding isolation groove and extend to at least cover the outer surface of the edge of the adjacent solderable conductive film layer, the risk of short circuits between the solder ribbon and conductive film layers of opposite polarity can be reduced, thus improving the yield of solder ribbon connections.

[0060] The thickness of the solderable conductive film layer is 10-100 nm, optionally 40-100 nm, and the maximum thickness of the first insulating ink and the second insulating ink is independently 1-5 μm, optionally 1-4 μm. The back contact battery structure disclosed herein can use ultra-thin insulating ink, combined with a suitable thin solderable conductive film layer, which can reduce the amount of insulating ink used and help reduce the cost of insulating ink.

[0061] The term "solderable conductive film layer" in this disclosure refers to a conductive film layer that can be soldered, such as a metal-containing film layer. In some preferred embodiments of this disclosure, the solderable conductive film layer is at least one of metallic tin, tin alloy, metallic nickel, nickel alloy, indium, or indium alloy.

[0062] The optional solderable conductive film layer can be made of metallic tin or tin alloy, which is more conducive to good connection with the solder strip.

[0063] In some preferred embodiments of this disclosure, the metallic conductive film layer is at least one of aluminum, copper, or silver. Using these optional materials for the metallic conductive film layer is more conducive to reducing the conductive film's transmission resistance and power loss.

[0064] In some preferred embodiments of this disclosure, the outer surface of the solderable conductive film layer is entirely located on the same plane, which allows the use of ultra-thin insulating ink. When manufacturing the battery module, the gap between the solder ribbon tin alloy coating and the solderable conductive film layer is very small. After the thicker tin alloy coating on the solder ribbon surface melts, it can easily contact the solderable conductive film layer, which is more conducive to improving the reliability of battery connection and thus improving the production yield of battery module.

[0065] In some preferred embodiments of this disclosure, the metal conductive film layer fills the corresponding semiconductor opening region while the overall outer surface is flush.

[0066] In some preferred embodiments of this disclosure, the total thickness of the metal conductive film layer and the solderable conductive film layer does not exceed 1 μm. Replacing the fine silver paste grid lines with a metal conductive film layer and a solderable conductive film layer, with the overall thickness of the metal conductive film layer and the solderable conductive film layer not exceeding 1 μm, facilitates the reduction of the insulating ink thickness, thereby improving the reliability of the connection between the solder strip and the solderable conductive film layer, and ultimately increasing the production yield of the battery module.

[0067] In some preferred embodiments of this disclosure, the thickness of the metal conductive film layer is 90-500 nm, optionally 120-500 nm.

[0068] In some preferred embodiments of this disclosure, the thickness of the conductive film is 30-100 nm.

[0069] In some preferred embodiments of this disclosure, the sheet resistance of the stack of the metal conductive film layer and the solderable conductive film layer is less than 0.3 Ω / □.

[0070] The conductive film layer described in the embodiments of this disclosure can be made of any conductive material in the art that meets the aforementioned sheet resistance range. For example, the material of the conductive film layer can be an indium oxide-based thin film doped with at least one of tin, tungsten, titanium, zinc or silicon, or a zinc oxide-based thin film doped with aluminum, boron or gallium.

[0071] In some preferred embodiments of this disclosure, the width W3 of the isolation groove is 50-400 μm.

[0072] In some preferred embodiments of this disclosure, the first semiconductor layer includes a first passivation layer and a first doped polysilicon layer, and the second semiconductor layer is a second passivation layer and a second doped silicon layer; one of the first doped polysilicon layer and the other of the second doped silicon layer is N-type and the other is P-type; the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0073] The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer can be intrinsic amorphous silicon or intrinsic microcrystalline silicon.

[0074] Optionally, in this disclosure, the first passivation layer is a tunneling oxide layer, and the second passivation layer is an intrinsically doped amorphous silicon layer. Employing the combined passivation structure of this disclosure is more conducive to improving the production yield of the battery.

[0075] The thicknesses and corresponding doping concentrations of the tunneling oxide layer or intrinsic silicon layer, the first doped polysilicon layer, and the second doped silicon layer described in the embodiments of this disclosure can all refer to the range of existing technologies and can all be configured as disclosed herein. For example, the thickness of the tunneling oxide layer is 1-2 nm, the thickness of the intrinsic silicon layer is 3-10 nm, and the thickness of the second doped silicon layer is 7-15 nm with an effective doping concentration of 5e18 cm⁻¹. -3 -1e20cm -3 The thickness of the first doped polycrystalline silicon layer is 30-250 nm, and the effective doping concentration is greater than 9e18 cm⁻¹. -3 .

[0076] In some preferred embodiments of this disclosure, the two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. The second semiconductor opening region and the first semiconductor opening region are arranged alternately, and the area between them is a gap region.

[0077] The widths of the second semiconductor opening region, the first semiconductor opening region, and the spacer region can be based on existing technologies. Optionally, the width W1 of the first semiconductor opening region is 100-300 μm, the width W2 of the second semiconductor opening region is 300-700 μm, and the width W3 of the spacer region is 50-400 μm.

[0078] Optionally, a mask layer may be provided or not provided between the first semiconductor layer and the second semiconductor layer within the spacing region.

[0079] In some preferred embodiments of this disclosure, the back contact cell of the low-cost metal electrode further includes a front passivation layer and an antireflection layer disposed on the front side of the silicon wafer.

[0080] The types and thicknesses of the front passivation layer, antireflection layer, and mask layer described in the embodiments of this disclosure can all refer to existing technologies and can all be configured as disclosed herein. For example, the front passivation layer is at least one of amorphous silicon, microcrystalline silicon, silicon oxide, or polycrystalline silicon; the antireflection layer and mask layer are silicon dielectric layers, and the silicon dielectric layer is at least one of silicon nitride, silicon oxide, silicon oxynitride, or intrinsic amorphous silicon.

[0081] Optionally, the front side of the silicon wafer is textured, and the back side is polished.

[0082] Secondly, embodiments of this disclosure provide a method for preparing a low-cost metal electrode back contact battery, configured to prepare the low-cost metal electrode back contact battery described in the first aspect. The method for preparing the low-cost metal electrode back contact battery includes the following steps:

[0083] S100, A back contact semi-finished battery is provided in which a semiconductor distribution layer is formed on the back side of a silicon wafer, wherein a second semiconductor opening region arranged at intervals is etched on the first semiconductor layer;

[0084] S101. A conductive film layer, a metal conductive film layer, and a solderable conductive film layer are deposited sequentially to fully cover the back of the back of the semi-finished battery in back contact.

[0085] S102. An opening is etched in the conductive film layer corresponding to the edge region of the second semiconductor opening area and the corresponding metal conductive film layer and solderable conductive film layer thereon to form an isolation trench.

[0086] S103, First insulating ink and second insulating ink are alternately formed on the outer surfaces of the corresponding regions of the first semiconductor opening region and the second semiconductor opening region, respectively.

[0087] In some preferred embodiments of this disclosure, S100 further includes: forming a front passivation layer and an antireflection layer on the front side of the silicon wafer.

[0088] In some preferred embodiments of this disclosure, the process of providing a back contact semi-finished battery with a semiconductor distribution layer formed on the back side of a silicon wafer in step S100 includes:

[0089] A first semiconductor layer and a mask layer are formed on the back side of the silicon wafer. A first etching opening is made on the first semiconductor layer and its corresponding mask layer to form a second semiconductor opening region arranged at intervals.

[0090] Then, a second semiconductor layer is formed on the back side, and a second etching opening is made on the second semiconductor layer and the corresponding mask layer below it to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0091] Optionally, the process of providing a back contact semi-finished battery with a semiconductor distribution layer formed on the back side of the silicon wafer as described in S100 can be carried out by a conventional texturing method or by a post-texturing method (for example, the method in CN115312633B can be referred to).

[0092] For example, a method for pre-forming flocking may include:

[0093] S101, double-sided polishing of silicon wafers;

[0094] S102, The back of the silicon wafer is protected by a first mask layer;

[0095] S103, Silicon wafer texturing and cleaning: A pyramid textured surface is formed opposite to the first mask layer. Then the first mask layer is removed to form a silicon wafer with a front textured and back polished structure.

[0096] S104. A first semiconductor layer and a second mask layer are sequentially deposited on the back of the silicon wafer;

[0097] S105. Laser or etch an opening on the back of the silicon wafer to remove the second mask layer and part of the first semiconductor layer, forming a second semiconductor opening region;

[0098] S106. Silicon wafer cleaning to remove the residual first semiconductor layer in the second semiconductor opening area;

[0099] S107. A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and a second semiconductor layer is formed on the back side.

[0100] S108, Laser or etched openings on the back of the silicon wafer to form first semiconductor opening regions that are alternately arranged with the second semiconductor opening region;

[0101] S109. Silicon wafer cleaning to remove the second mask layer in the first semiconductor opening area.

[0102] Thirdly, embodiments of this disclosure provide a battery module, including a back contact battery with a low-cost metal electrode as described in the first aspect or a back contact battery with a low-cost metal electrode as described in the second aspect, and solder ribbons arranged in series disposed on the outer surface of the back insulating ink.

[0103] The solder strip comprises metallic copper and a tin alloy coating disposed on both sides of the metallic copper. A solderable conductive film layer is connected to a corresponding portion of the tin alloy coating. This structure of the solder strip and the solderable conductive film layer facilitates increased tensile strength at the connection, thereby improving the reliability of the connection.

[0104] Specifically, the connection between the weldable conductive film layer and the corresponding portion of the tin alloy coating can be welding or high-temperature melting connection. In the weldable conductive film layer scheme with optional materials disclosed in this invention, the weldable conductive film layer and the corresponding portion of the tin alloy coating can melt to form an alloy contact.

[0105] In some preferred embodiments of this disclosure, the thickness T2 of the tin alloy coating is 15-30 μm. Using a suitable thickness range for the tin alloy coating thickness T2 is more conducive to improving the reliability of the connection between the solder strip and the solderable conductive film layer.

[0106] In some preferred embodiments of this disclosure, the thickness T2 of the tin alloy coating is 4-20 times the maximum thickness T1 of the corresponding insulating ink. This alternative approach is more conducive to improving the connection tensile strength between the solder strip and the solderable conductive film layer, thereby improving the reliability of the connection.

[0107] This disclosure does not impose any special restrictions on the thickness of the copper in the solder strip, which can be selected according to actual needs. For example, the thickness of the copper is 5-200 μm.

[0108] In some preferred embodiments of this disclosure, the melting point of the tin alloy coating is 100-250°C, optionally 130-170°C. The specific composition of the tin alloy coating can be selected based on its melting point. Using a tin alloy coating with a suitable melting point further improves the reliability of the weld.

[0109] The embodiments of this disclosure described below are exemplary and configured only to explain this disclosure, and should not be construed as limiting this disclosure.

[0110] Example 1

[0111] A low-cost metal electrode back contact battery is prepared by the following steps:

[0112] S100, as shown in Figure 1, a back-contact semi-finished battery is provided, in which a front passivation layer and an anti-reflection layer 7 are formed on the front side of a silicon wafer 1, and a first semiconductor layer, a second semiconductor layer, and a mask layer 4 are formed on the back side. The two ends of the second semiconductor layer extend outwards to cover portions of the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back side of the first semiconductor layer. The second semiconductor opening regions and the first semiconductor opening regions are spaced apart, with the area between them forming a gap region. A mask layer 4 is disposed between the first semiconductor layer and the second semiconductor layer within the gap region. The front passivation layer is amorphous silicon, and the anti-reflection layer and mask layer are silicon nitride. The first semiconductor layer is a tunneling oxide layer 2 with a thickness of 1.5 nm and an N-type doped polycrystalline silicon layer 3 (thickness of 100 nm, effective doping concentration 9e19cm). -3 The second semiconductor layer consists of an intrinsically doped amorphous silicon layer 5 with a thickness of 5 nm and a p-type doped amorphous silicon layer 6 (with a thickness of 12 nm and an effective doping concentration of 1e20 cm⁻¹). -3 The width W1 of the first semiconductor opening region is 200 μm, the width W2 of the second semiconductor opening region is 400 μm, and the width Wg of the gap region between the first semiconductor opening region and the second semiconductor opening region is 100 μm.

[0113] S101. As shown in Figure 2, a transparent conductive film layer 8, a metal conductive film layer 9, and a solderable conductive film layer 10 are deposited on the back side of the back-contact semi-finished battery. The transparent conductive film layer 8 is tin-doped indium oxide with a thickness of 40 nm. The metal conductive film layer 9 is metallic copper with a thickness of 200 nm. The solderable conductive film layer 10 is metallic tin with a thickness of 80 nm. The sheet resistance of the stack of the metal conductive film layer and the solderable conductive film layer is 0.05 Ω / □.

[0114] S102, As shown in Figure 3, an isolation trench with a width W3 of 60 μm is formed on the outer surface of the region corresponding to the edge of the second semiconductor opening region.

[0115] S103. As shown in Figures 4a, 4b, and 8, insulating inks are alternately formed on the outer surfaces of the corresponding regions of the first semiconductor layer and the second semiconductor layer. The insulating inks include a first insulating ink 11N and a second insulating ink 11P. The first insulating ink 11N corresponding to the first semiconductor layer crosses the isolation trenches on the corresponding adjacent sides and extends to cover the solderable conductive film layer 10 on the outer surface of the corresponding region of the adjacent second semiconductor opening region. The second insulating ink 11P corresponding to the second semiconductor layer crosses the isolation trenches on the corresponding adjacent sides and extends to cover the solderable conductive film layer 10 on the outer surface of the corresponding region of the adjacent first semiconductor opening region. The maximum thickness T1N of the first insulating ink 11N and the maximum thickness T1P of the second insulating ink 11P are both 3μm.

[0116] Figure 5 shows a schematic diagram of the solder ribbon 200 used in the fabrication of the battery module. The solder ribbon 200 consists of copper 201 and a tin alloy coating 202. The thickness T2 of the tin alloy coating is 21 μm, which is 7 times the maximum thickness T1 of any insulating ink. The thickness of the copper 201 is 150 μm, and the melting point of the tin alloy coating is 140°C. Figures 6a, 6b, and 9 show schematic diagrams illustrating the connection between the tin alloy coating 202 on the surface of the solder ribbon 200 and the solderable conductive film layer 10 on the back of the silicon wafer 1 to achieve battery interconnection. After the tin alloy coating 202 on the surface of the solder ribbon 200 is heated and melted, it makes full contact with the solderable conductive film layer 10.

[0117] Example 2

[0118] The method is the same as in Example 1, except that the thickness of the weldable conductive film is 50 nm.

[0119] Example 3

[0120] The method is the same as in Example 1, except that the maximum thickness of both the first insulating ink and the second insulating ink is 5 μm.

[0121] Example 4

[0122] The method is the same as in Example 1, except that the weldable conductive film layer is metallic nickel, while the thickness remains the same.

[0123] Example 5

[0124] The method of Example 1 is followed, except that the metal conductive film layer is aluminum, while the thickness remains the same.

[0125] Example 6

[0126] The method was carried out in accordance with Example 1, except that the thickness of the metal conductive film was 100 nm.

[0127] Example 7

[0128] The method is the same as in Example 1, except that the first semiconductor layer includes an intrinsic amorphous silicon layer with a thickness of 7 nm and an N-type doped amorphous silicon layer with a thickness of 12 nm (doping concentration is the same as in Example 1).

[0129] Example 8

[0130] The method is the same as in Example 1, except that the thickness of the weldable conductive film is 30 nm.

[0131] Comparative Example 1

[0132] A back-contact battery, as shown in Figure 7, is manufactured as follows:

[0133] S01, silicon wafer 1 is polished on both sides;

[0134] S02, The back of silicon wafer 1 is protected by a first mask layer, which is silicon nitride;

[0135] S03. Texturing and cleaning of silicon wafer 1: A pyramid textured surface is formed on the opposite side of the first mask layer (i.e., the front side of silicon wafer 1). Then, the first mask layer is removed to form silicon wafer 1 with a single-sided texturing and single-sided polishing structure.

[0136] S04. A first semiconductor layer and a second mask layer are sequentially deposited on the back side of silicon wafer 1. The first semiconductor layer is formed by PECVD and includes an intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer (the thickness and doping concentration are the same as the first semiconductor layer in Example 7). The second mask layer is silicon nitride.

[0137] S05. Laser an opening is made on the back side of silicon wafer 1 to remove the second mask layer and part of the first semiconductor layer, forming a second semiconductor opening region;

[0138] S06, Silicon wafer 1 is cleaned to remove the first semiconductor layer in the second semiconductor opening region;

[0139] S07. A passivation layer and an anti-reflection layer are sequentially formed on the front side of silicon wafer 1 (the front structure is the same as in Example 1). A second semiconductor layer is formed on the back side. The second semiconductor layer is formed by PECVD. The second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer (the thickness and doping concentration are the same as the first semiconductor layer in Example 1).

[0140] S08, Laser opening on the back of silicon wafer 1 forms a first semiconductor opening region that alternates with the second semiconductor opening region;

[0141] S09, Silicon wafer 1 is cleaned to remove the second mask layer in the first semiconductor opening area;

[0142] S10, A transparent conductive film layer 8 (thickness same as in Example 1) is deposited on the back of silicon wafer 1;

[0143] S11. An isolation trench is formed between the first semiconductor opening region and the second semiconductor opening region by means of laser;

[0144] S12. A silver paste fine gate electrode 9A with a thickness of 20 μm is formed on the outer surface of the corresponding regions of the first semiconductor opening region and the second semiconductor opening region of silicon wafer 1. An insulating ink 11m with a thickness of 40 μm is alternately formed on the outer surface of the corresponding regions of the first semiconductor opening region and the second semiconductor opening region. A silver paste main gate electrode 9B with a thickness of 15 μm is formed in the insulating ink region.

[0145] When manufacturing battery modules, the tin alloy coating of the solder strip (whose structure is the same as in Example 1) is connected to the silver paste grid to form a battery string.

[0146] Comparative Example 2

[0147] The method was the same as in Comparative Example 1, except that the metal electrodes were formed by copper electroplating.

[0148] Test case

[0149] The back-contact batteries and battery modules obtained from the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The battery conversion efficiency and yield, as well as the module yield and conversion efficiency, of each embodiment and comparative example were calculated using Embodiment 1 as a reference benchmark. The data in Embodiment 1 is a normalized benchmark of 1, and other examples are calculated based on Embodiment 1. For example, the battery conversion efficiency of Comparative Example 1 / the battery conversion efficiency of Embodiment 1 is 1.01.

[0150] Table 1

[0151] The results above show that, compared with the comparative example, the embodiments of this disclosure significantly reduce the thickness and amount of insulating ink, significantly reduce the height of the grid lines, eliminate the need for silver paste fine grids and main grids, significantly reduce battery costs, and ensure excellent battery performance, especially battery conversion efficiency and yield, as well as module yield and conversion efficiency.

[0152] Optionally, as can be seen from Embodiments 1 and 2-8, the scheme using the optional battery structure of this disclosure is more conducive to improving battery performance.

[0153] The preferred embodiments of this disclosure have been described in detail above; however, this disclosure is not limited thereto. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, including combining the various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in this disclosure and all fall within the protection scope of this disclosure. Industrial applicability

[0154] This disclosure, through the above-mentioned technical solution, especially by setting a metal conductive film layer and a solderable conductive film layer to replace the silver paste fine grid lines and main grid, significantly reduces the thickness and amount of insulating ink, and significantly reduces the height of the grid lines. The embodiments of this disclosure do not require the setting of silver paste fine grid lines and main grid lines, thus significantly reducing battery costs. Furthermore, the embodiments of this disclosure use a solderable conductive film layer of suitable thickness, which has excellent miscibility with the tin alloy coating of the solder ribbon, enabling good connection. Combined with the specifically set isolation grooves and corresponding insulating ink, it is beneficial to ensure excellent battery performance.

Claims

1. A low-cost metal electrode back-contact battery, comprising a silicon wafer, a semiconductor distribution layer disposed on the back side of the silicon wafer, a conductive film layer disposed on the outer surface of the semiconductor distribution layer, the semiconductor distribution layer comprising a first semiconductor layer and a second semiconductor layer alternately disposed along the back side, a second semiconductor opening region being formed between adjacent first semiconductor layers, characterized in that, It also includes a metal conductive film layer and a solderable conductive film layer sequentially disposed on the outer surface of the conductive film layer, as well as a first insulating ink and a second insulating ink, and an isolation groove is formed on the conductive film layer corresponding to the edge region of the second semiconductor opening region, the isolation groove extending outward and penetrating the metal conductive film layer and the solderable conductive film layer in the corresponding region; The first insulating ink is disposed on the outer surface of the solderable conductive film layer corresponding to the first semiconductor layer and is spaced apart along the length direction of the first semiconductor layer. The first insulating ink crosses the isolation grooves on both sides of the first semiconductor layer and extends to at least cover the outer surface of the edge of the solderable conductive film layer corresponding to the adjacent second semiconductor opening area. The second insulating ink is disposed on the outer surface of the solderable conductive film layer corresponding to the second semiconductor opening area and is spaced apart along the length direction of the second semiconductor layer. The second insulating ink crosses the isolation grooves on both sides of the second semiconductor opening area and extends to at least cover the outer surface of the edge of the solderable conductive film layer corresponding to the adjacent first semiconductor layer. The first insulating ink and the second insulating ink are alternately disposed along the length direction. The thickness of the weldable conductive film is 10-100nm, and the thickness of the first insulating ink and the second insulating ink are each 1-5μm.

2. The low-cost metal electrode back contact battery according to claim 1, characterized in that, The solderable conductive film layer is at least one of metallic tin, tin alloy, metallic nickel, nickel alloy, indium, and indium alloy, and / or the metallic conductive film layer is at least one of metallic aluminum, metallic copper, metallic silver, and metallic titanium.

3. The low-cost metal electrode back contact battery according to claim 1, characterized in that, The outer surface of the solderable conductive film is entirely on the same plane, and / or the metal conductive film fills the corresponding semiconductor opening area while the overall outer surface is flush.

4. The low-cost metal electrode back contact battery according to claim 1, characterized in that, The total thickness of the metallic conductive film and the solderable conductive film does not exceed 1 μm; And / or, the thickness of the metal conductive film is 90-500 nm.

5. The low-cost metal electrode back contact battery according to claim 1, characterized in that, The thickness of the conductive film layer is 30-100nm, and the sheet resistance of the stack of the metal conductive film layer and the solderable conductive film layer is less than 0.3Ω / □; And / or, the width W3 of the isolation groove is 50-400μm.

6. The low-cost metal electrode back contact battery according to claim 1, characterized in that, The first semiconductor layer includes a first passivation layer and a first doped polysilicon layer, and the second semiconductor layer is a second passivation layer and a second doped silicon layer; one of the first doped polysilicon layer and the other of the second doped silicon layer is N-type and the other is P-type; the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. And / or, The two ends of the second semiconductor layer extend outward to cover the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer. The second semiconductor opening region and the first semiconductor opening region are arranged alternately, and the area between them is a gap region. In the gap region, a mask layer is provided between the first semiconductor layer and the second semiconductor layer or no mask layer is provided. The back contact cell of the low-cost metal electrode also includes a front passivation layer and an anti-reflection layer provided on the front side of the silicon wafer.

7. A method for preparing a low-cost metal electrode back contact battery, characterized in that, It is configured to prepare a back contact battery with a low-cost metal electrode as described in any one of claims 1-6, and the method for preparing the back contact battery with the low-cost metal electrode includes the following steps: S100, A back contact semi-finished battery is provided in which a semiconductor distribution layer is formed on the back side of a silicon wafer, wherein a second semiconductor opening region arranged at intervals is etched on the first semiconductor layer; S101. A conductive film layer, a metal conductive film layer, and a solderable conductive film layer are deposited sequentially to fully cover the back of the back of the semi-finished battery in back contact. S102. An opening is etched in the conductive film layer corresponding to the edge region of the second semiconductor opening area and the corresponding metal conductive film layer and solderable conductive film layer thereon to form an isolation trench. S103, First insulating ink and second insulating ink are alternately formed on the outer surfaces of the corresponding regions of the first semiconductor opening region and the second semiconductor opening region, respectively.

8. The method for preparing a low-cost metal electrode back contact battery according to claim 7, characterized in that, S100 also includes: forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer; And / or, S100 describes the process of providing a back contact semi-finished battery in which a semiconductor distribution layer is formed on the back side of a silicon wafer, including: A first semiconductor layer and a mask layer are formed on the back side of the silicon wafer. A first etching opening is made on the first semiconductor layer and its corresponding mask layer to form a second semiconductor opening region arranged at intervals. Then, a second semiconductor layer is formed on the back side, and a second etching opening is made on the second semiconductor layer and the corresponding mask layer below it to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

9. A battery module, characterized in that, The back contact battery includes a low-cost metal electrode back contact battery as described in any one of claims 1-6 or a back contact battery prepared by the method of low-cost metal electrode back contact battery as described in claims 7 or 8, and solder strips arranged in series on the outer surface of the back insulating ink; the solder strips include metallic copper and tin alloy coatings disposed on both sides of the metallic copper, and the conductive film layer can be soldered to the corresponding portion of the tin alloy coating.

10. The battery module according to claim 9, characterized in that, The tin alloy coating also has at least one of the following characteristics: Feature 1: The thickness T2 of the tin alloy coating is 15-30 μm; Feature 2: The thickness T2 of the tin alloy coating is 4-20 times the maximum thickness T1 of the corresponding insulating ink; Feature 3: The melting point of the tin alloy coating is 100-250℃.

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