Power device and preparation method therefor, and power module, power conversion circuit and vehicle

Abstract

Disclosed in the present application are a power device and a preparation method therefor, and a power module, a power conversion circuit and a vehicle. The power device comprises: a silicon carbide substrate; a first silicon carbide epitaxial layer, which is located on one side of the silicon carbide substrate; a mobility-enhanced semiconductor layer, which is located on the side of the first silicon carbide epitaxial layer that is away from the silicon carbide substrate, wherein at the same preset temperature, the mobility of the mobility-enhanced semiconductor layer is greater than the mobility of silicon carbide; a second silicon carbide epitaxial layer, which is located on the side of the mobility-enhanced semiconductor layer that is away from the first silicon carbide epitaxial layer, wherein a body region and an active region are arranged on the surface of the second silicon carbide epitaxial layer that is away from the mobility-enhanced semiconductor layer; and a planar gate structure, which is located on the surface of the second silicon carbide epitaxial layer that is away from the mobility-enhanced semiconductor layer.

Description

Power device and manufacturing method, power module, power conversion circuit, and vehicle

[0001] This application claims priority to the Chinese patent application No. 202410655841.X, filed on May 24, 2024, with the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor technology, for example to a power device and manufacturing method, a power module, a power conversion circuit, and a vehicle. BACKGROUND

[0003] The planar silicon carbide metal-oxide field effect transistor (SiC MOSFET) power device is widely used in the field of electronic devices due to its large band gap, high critical breakdown field, and high temperature resistance.

[0004] However, the on-resistance of the planar silicon carbide metal-oxide field effect transistor power device is relatively large.

[0005] SUMMARY

[0006] The present application provides a power device and manufacturing method, a power module, a power conversion circuit, and a vehicle to reduce the on-resistance of the power device.

[0007] According to an aspect of the present application, a power device is provided, comprising:

[0008] a silicon carbide substrate;

[0009] a first silicon carbide epitaxial layer, wherein the first silicon carbide epitaxial layer is located on one side of the silicon carbide substrate;

[0010] a mobility-enhanced semiconductor layer, wherein the mobility-enhanced semiconductor layer is located on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, and the mobility of the mobility-enhanced semiconductor layer is greater than the mobility of silicon carbide at the same preset temperature;

[0011] a second silicon carbide epitaxial layer, wherein the second silicon carbide epitaxial layer is located on a side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer, and a body region and an active region are arranged on a surface of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer;

[0012] a planar gate structure, wherein the planar gate structure is located on the surface of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer;

[0013] a source electrode, wherein the source electrode is located on the surface of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer;

[0014] The drain electrode is located on the side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

[0015] For example, the mobility-enhancing semiconductor layer includes a semiconductor epitaxial graphene buffer layer;

[0016] The semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are connected by orderly covalent bonding.

[0017] For example, the thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2 nm and less than or equal to 0.3 nm.

[0018] For example, at the same preset temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than that of silicon.

[0019] For example, it also includes a protective layer located on the side of the mobility-enhancing semiconductor layer away from the first silicon carbide epitaxial layer.

[0020] For example, the protective layer may include a gold protective layer or an aluminum oxide protective layer.

[0021] According to another aspect of this application, a method for fabricating a power device is provided, comprising:

[0022] Provide silicon carbide substrates;

[0023] A first silicon carbide epitaxial layer is formed on one side of the silicon carbide substrate;

[0024] A mobility enhancement semiconductor layer is formed on the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein, at the same preset temperature, the mobility of the mobility enhancement semiconductor layer is greater than the mobility of silicon carbide.

[0025] A second silicon carbide epitaxial layer is formed on the side of the mobility enhancement semiconductor layer away from the first silicon carbide epitaxial layer, wherein a body region and an active region are disposed on the surface of the second silicon carbide epitaxial layer away from the mobility enhancement semiconductor layer;

[0026] A planar gate structure is formed on the side of the second silicon carbide epitaxial layer away from the mobility-enhancing semiconductor layer;

[0027] A source electrode is formed on the side of the second silicon carbide epitaxial layer away from the mobility-enhancing semiconductor layer;

[0028] A drain electrode is formed on the side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

[0029] For example, forming a mobility-enhancing semiconductor layer on the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate includes:

[0030] heating a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates to form a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the semiconductor epitaxial graphene buffer layer serves as the mobility-enhanced semiconductor layer, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are connected by ordered bonding through covalent bonds.

[0031] For example, heating a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates to form a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, includes:

[0032] providing a silicon carbide semiconductor layer, and oppositely arranging a carbon face of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate;

[0033] heating the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate and the silicon carbide semiconductor layer to a preset temperature, so that the carbon face of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate provide a condition for quasi-equilibrium between the carbon face and the silicon face at the preset temperature; wherein the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is a silicon face;

[0034] The silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates to form a semiconductor epitaxial graphene buffer layer with a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

[0035] For example, before forming a second silicon carbide epitaxial layer on a side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer, further comprising:

[0036] forming a protective layer on a side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer by an atomic layer deposition process.

[0037] According to another aspect of the present application, a power module is provided, comprising a substrate and at least one power device as described in any embodiment of the present application, the substrate is arranged to carry the power device.

[0038] According to another aspect of the present application, a power conversion circuit is provided, the power conversion circuit is arranged to perform at least one of the following operations: current conversion, voltage conversion, and power factor correction.

[0039] The power conversion circuit includes a circuit board and at least one power device as any of the embodiments of the present application, and the power device is electrically connected with the circuit board.

[0040] According to another aspect of the present application, a vehicle is provided, including a load and a power conversion circuit as any of the embodiments of the present application, and the power conversion circuit is configured to input to the load after current conversion as follows: converting alternating current into alternating current; converting alternating current into direct current; converting direct current into alternating current; and converting direct current into direct current.

[0041] The technical scheme provided by the embodiments of the present application sets a mobility-enhancing semiconductor layer with mobility greater than that of silicon carbide between the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer of the planar silicon carbide metal-oxide field effect transistor power device, and the mobility-enhancing semiconductor layer is located in the on-conducting channel under the planar gate structure, which significantly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device, improving the on-current and power density, reducing power loss, enhancing heat dissipation performance and device reliability; the power device has a faster migration rate of the carrier, so that the power device has a faster corresponding speed. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 is a structural schematic diagram of a planar silicon carbide metal-oxide field effect transistor power device provided by the related art;

[0043] FIG. 2 is a structural schematic diagram of a power device provided by the embodiments of the present application;

[0044] FIG. 3 is a structural schematic diagram of another power device provided by the embodiments of the present application;

[0045] FIG. 4 is a flowchart of a preparation method of a power device provided by the embodiments of the present application;

[0046] FIGS. 5-9 are structural schematic diagrams corresponding to multiple steps in FIG. 4;

[0047] FIG. 10 is a flowchart of another preparation method of a power device provided by the embodiments of the present application;

[0048] FIG. 11 is a flowchart included in S1301 in FIG. 10;

[0049] FIG. 12 is a structural schematic diagram corresponding to multiple steps in FIG. 11;

[0050] FIG. 13 is a flowchart of another preparation method of a power device provided by the embodiments of the present application;

[0051] FIG. 14-FIG. 16 are structural schematic diagrams corresponding to the steps S1401-S170 in FIG. 13. DETAILED DESCRIPTION

[0052] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and above-described accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a list of steps or components does not necessarily limit those steps or components to those clearly listed, but can include other steps or components that are not clearly listed or inherent to such processes, methods, products, or devices.

[0053] As described in the above background, the on-resistance of the planar silicon carbide metal-oxide field effect transistor power device is relatively large. As shown in FIG. 1, FIG. 1 is a structural schematic diagram of a planar silicon carbide metal-oxide field effect transistor power device provided by the related art, which includes a substrate 001, an epitaxial layer 002, a planar gate structure 003, a source 004, and a drain 005, wherein the epitaxial layer 002 is provided with a drift region 006, a body region 007, and an active region 008. The planar gate structure 003 includes a gate dielectric layer 009 and a gate 010. The JFET (Junction Field Effect Transistor) resistance exists in the drift region 006 between the two active regions 008, which is relatively large, resulting in a relatively large on-resistance of the entire planar silicon carbide metal-oxide field effect transistor power device. Limited by the size of the planar silicon carbide metal-oxide field effect transistor power device, the on-resistance of the power device cannot be reduced by thinning the thickness of the substrate 001 or the epitaxial layer 002.

[0054] Embodiments of the present application provide the following technical solutions:

[0055] As shown in FIG. 2, FIG. 2 is a structural diagram of a power device according to an embodiment of the present application. The power device comprises: a silicon carbide substrate 100; a first silicon carbide epitaxial layer 101, wherein the first silicon carbide epitaxial layer 101 is located on one side of the silicon carbide substrate 100; a mobility-enhanced semiconductor layer 102, wherein the mobility-enhanced semiconductor layer 102 is located on a side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and the mobility of the mobility-enhanced semiconductor layer 102 is greater than the mobility of silicon carbide at the same preset temperature; a second silicon carbide epitaxial layer 103, wherein the second silicon carbide epitaxial layer 103 is located on a side of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101; a body region 104 and an active region 105 are arranged on a surface of the second silicon carbide epitaxial layer 103 away from the mobility-enhanced semiconductor layer 102; a planar gate structure 106 is located on a side of the second silicon carbide epitaxial layer 103 away from the mobility-enhanced semiconductor layer 102; a source electrode 107 is located on a side of the second silicon carbide epitaxial layer 103 away from the mobility-enhanced semiconductor layer 102; and a drain electrode 108 is located on a side of the silicon carbide substrate 100 away from the first silicon carbide epitaxial layer 101.

[0056] In an example, the active region 105 comprises a first conductive type active region 109 and a second conductive type active region 110, and the conductive type of the first conductive type active region 109 is opposite to the conductive type of the body region 104. The conductive type of the second conductive type active region 110 is the same as the conductive type of the body region 104. In other embodiments, the active region 105 can only comprise the first conductive type active region 109. The planar gate structure 106 comprises a gate dielectric layer 111 and a gate electrode 112.

[0057] It should be noted that the mobility of the same semiconductor material changes with temperature. In the present application, it is defined that the mobility of the mobility-enhanced semiconductor layer 102 is greater than the mobility of silicon carbide at the same preset temperature. That is, the resistance to electron movement in the mobility-enhanced semiconductor layer 102 is less than the resistance to carrier movement in silicon carbide at the same preset temperature, thereby significantly increasing the channel carrier mobility in the power device and reducing the on-resistance of the power device.

[0058] The technical scheme provided by the embodiment of the application is that a mobility-enhancing semiconductor layer 102 with a mobility greater than that of silicon carbide is arranged between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 of the planar silicon carbide metal-oxide field effect transistor power device, and the mobility-enhancing semiconductor layer 102 is located in the on-state channel under the planar gate structure 106, thereby significantly increasing the channel carrier mobility in the power device, reducing the on-state resistance of the power device, improving the on-state current and power density, reducing the power loss, and enhancing the heat dissipation performance and device reliability; the carriers in the power device have a faster migration rate, so that the power device has a faster corresponding speed.

[0059] It should be noted that, in the embodiment of the application, the planar silicon carbide metal-oxide field effect transistor power device can include an N-channel planar silicon carbide metal-oxide field effect transistor power device or a P-channel planar silicon carbide metal-oxide field effect transistor power device. For the N-channel planar silicon carbide metal-oxide field effect transistor power device, the mobility-enhancing semiconductor layer 102 with a mobility greater than that of silicon carbide is arranged between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103, thereby significantly increasing the mobility of electrons in the channel in the power device. For the P-channel planar silicon carbide metal-oxide field effect transistor power device, the mobility-enhancing semiconductor layer 102 with a mobility greater than that of silicon carbide is arranged between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103, thereby significantly increasing the mobility of holes in the channel in the power device. For example, for the N-channel planar silicon carbide metal-oxide field effect transistor power device, the silicon carbide substrate 100 is an N-substrate, the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 are N-silicon carbide epitaxial layers, the first conductive type active region 109 is an N++ active region, the second conductive type active region 110 is a P++ active region, and the body region 104 is a P-type body region.

[0060] For example, as shown in FIG. 2, the mobility-enhancing semiconductor layer 102 includes a semiconductor epitaxial graphene buffer layer; the semiconductor epitaxial graphene buffer layer is connected between the mobility-enhancing semiconductor layer 102 and the first silicon carbide epitaxial layer 101 through ordered bonding by covalent bonds.

[0061] For example, the preparation of the semiconductor epitaxial graphene buffer layer uses a heated first silicon carbide epitaxial layer 101, and during the heating process, silicon is evaporated before carbon, so that the semiconductor epitaxial graphene buffer layer is spontaneously crystallized on the surface of the first silicon carbide epitaxial layer 101. Among them, the semiconductor epitaxial graphene buffer layer is connected between the first silicon carbide epitaxial layer 101 through covalent bonding during growth, without the need to form a bonding layer, simplifying the preparation process and reducing the preparation cost. The semiconductor epitaxial graphene buffer layer as a mobility-enhanced semiconductor layer 102 is a two-dimensional semiconductor material, and the mobility-enhanced semiconductor layer 102 and the first silicon carbide epitaxial layer 101 are connected through covalent bonding. The semiconductor epitaxial graphene buffer layer has very high mobility, so the technical solution of setting the epitaxial graphene buffer layer between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 greatly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device. And the semiconductor epitaxial graphene buffer layer also has the advantages of high strength and high thermal conductivity.

[0062] For example, as shown in FIG. 2, when the semiconductor epitaxial graphene buffer layer is used as a mobility-enhanced semiconductor layer 102, its thickness is greater than or equal to 0.2 nm and less than or equal to 0.3 nm.

[0063] For example, when the semiconductor epitaxial graphene buffer layer is used as a mobility-enhanced semiconductor layer 102, the semiconductor epitaxial graphene buffer layer is essentially a single layer of carbon atoms in the silicon carbide epitaxial layer, and its thickness is equivalent to that of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2 nm and less than or equal to 0.3 nm, and its average thickness is about 0.25 nm. The bonding between the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer 101 is ordered and periodically arranged, which can ensure that the semiconductor epitaxial graphene buffer layer as a mobility-enhanced semiconductor layer 102 is a two-dimensional semiconductor material. The band gap of the semiconductor epitaxial graphene buffer layer is smaller than that of silicon, about 0.6 ev.

[0064] For example, at the same preset temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than that of silicon.

[0065] For example, at the same selected room temperature, the room temperature mobility of the semiconductor epitaxial graphene buffer layer is greater than that of silicon, and the maximum mobility can reach 5500 cm 2 V -1 s -1The room temperature is also called normal temperature or general temperature, which is generally defined as 25 degrees Celsius, and sometimes is set as 300K (about 27 degrees Celsius).

[0066] For example, as shown in FIG. 3, FIG. 3 is a structural schematic diagram of another power device provided by the embodiment of the present application, and the power device further includes a protective layer 113 located on a side of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101.

[0067] For example, the protective layer 113 is a thin film formed by an atomic layer deposition process, and is arranged to protect the surface of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101, so as to avoid damaging the mobility-enhanced semiconductor layer 102 in the process of epitaxially forming the second silicon carbide epitaxial layer 103 and subsequent film layers, thereby ensuring that the mobility-enhanced semiconductor layer 102 has high mobility, and thereby increasing the structural stability of the power device. For example, the protective layer 113 is relatively thin, and the minimum thickness of the protective layer 113 is 5 nm, which has little effect on the on-resistance of the power device while achieving the effect of protecting the surface of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101.

[0068] For example, as shown in FIG. 3, the protective layer 113 includes a gold protective layer or an aluminum oxide protective layer.

[0069] For example, the gold protective layer or the aluminum oxide protective layer has stable physical and chemical properties, and can achieve the effect of protecting the surface of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101, so as to avoid damaging the mobility-enhanced semiconductor layer 102 in the process of epitaxially forming the second silicon carbide epitaxial layer 103 and subsequent film layers.

[0070] The embodiment of the present application further provides a preparation method of a power device. As shown in FIG. 4, FIG. 4 is a flow chart of the preparation method of the power device provided by the embodiment of the present application, and the preparation method of the power device includes the following steps.

[0071] S110, providing a silicon carbide substrate.

[0072] As shown in FIG. 5, the silicon carbide substrate 100 is provided.

[0073] S120, forming a first silicon carbide epitaxial layer on one side of the silicon carbide substrate.

[0074] As shown in FIG. 6, a first silicon carbide epitaxial layer 101 is formed on one side of a silicon carbide substrate 100 by an epitaxial process. The epitaxial process mainly includes at least one of evaporation epitaxial growth, liquid phase epitaxial growth (LPE), molecular beam epitaxial growth (MBE), and chemical vapor deposition (CVD).

[0075] S130, a mobility-enhanced semiconductor layer is formed on the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the mobility of the mobility-enhanced semiconductor layer is greater than the mobility of silicon carbide at the same preset temperature.

[0076] It should be noted that the mobility of the same semiconductor material changes with temperature. In the embodiments of the present application, it is limited that the mobility of the mobility-enhanced semiconductor layer 102 is greater than the mobility of silicon carbide at the same preset temperature. That is, at the same preset temperature, the resistance of electron movement in the mobility-enhanced semiconductor layer 102 is less than the resistance of carrier movement in silicon carbide, thereby significantly increasing the channel carrier mobility in the power device and reducing the on-resistance of the power device.

[0077] As shown in FIG. 7, a mobility-enhanced semiconductor layer 102 having a mobility greater than that of silicon carbide is formed on the side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, and the resistance of carrier movement in the mobility-enhanced semiconductor layer 102 is less than the resistance of carrier movement in the first silicon carbide epitaxial layer 101, thereby significantly increasing the channel carrier mobility in the power device and reducing the on-resistance of the power device.

[0078] S140, a second silicon carbide epitaxial layer is formed on the side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer, wherein the second silicon carbide epitaxial layer is provided with a body region and an active region away from the surface of the mobility-enhanced semiconductor layer.

[0079] As shown in FIG. 8, a second silicon carbide epitaxial layer 103 is formed on the side of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101 by an epitaxial process, wherein the second silicon carbide epitaxial layer 103 is provided with a body region 104 and an active region 105 away from the surface of the mobility-enhanced semiconductor layer 102. For example, the active region 105 includes a first conductive type active region 109 and a second conductive type active region 110, and the conductive type of the first conductive type active region 109 is opposite to the conductive type of the body region 104. The conductive type of the second conductive type active region 110 is the same as the conductive type of the body region 104. In other embodiments, the active region 105 can only include the first conductive type active region 109.

[0080] S150, a planar gate structure is formed on the side of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer.

[0081] As shown in FIG. 9, a planar gate structure 106 is formed on the surface of the second silicon carbide epitaxial layer 103 away from the mobility-enhanced semiconductor layer 102. The planar gate structure 106 includes a gate dielectric layer 111 and a gate 112. The gate dielectric layer 111 can be prepared by an atomic layer deposition (ALD) process, and the gate 112 can be a polysilicon gate which can be prepared by a low pressure chemical vapor deposition (LPCVD) process.

[0082] S160, forming a source on the side of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer.

[0083] As shown in FIG. 9, a source 107 is formed on the surface of the second silicon carbide epitaxial layer 103 away from the mobility-enhanced semiconductor layer 102. The source 107 is connected to the active region 105, and can be formed by a sputtering process.

[0084] S170, forming a drain on the side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

[0085] As shown in FIG. 2, a drain 108 is formed on the side of the silicon carbide substrate 100 away from the first silicon carbide epitaxial layer 101 by a sputtering process. For example, the drain 108 includes a Ti / Ni / Ag stack. For example, the silicon carbide substrate 100 can be thinned before forming the drain 108 to improve the heat dissipation performance of the power device.

[0086] The technical scheme provided by the embodiments of the present application forms a mobility-enhanced semiconductor layer 102 with a mobility greater than that of silicon carbide between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 of the planar silicon carbide metal-oxide field effect transistor power device, and the mobility-enhanced semiconductor layer 102 is located in the on-state channel under the planar gate structure 106, which significantly increases the channel carrier mobility in the power device, thereby reducing the on-state resistance of the power device, improving the on-state current and power density, reducing the power loss, and enhancing the heat dissipation performance and device reliability; the power device has a faster migration rate of the carrier, so that the power device has a faster corresponding speed.

[0087] For example, as shown in FIG. 10, FIG. 10 is a flowchart of another method for preparing a power device provided by the embodiments of the present application. The difference between the method for preparing a power device shown in FIG. 10 and the method for preparing a power device shown in FIG. 4 is that FIG. 10 further limits S130 in FIG. 1, wherein S130 includes the following steps:

[0088] S1301, heat the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that the silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, to form a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the semiconductor epitaxial graphene buffer layer is a mobility-enhanced semiconductor layer, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are connected by covalent bonding.

[0089] As shown in FIG. 7, the side of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is heated to a preset temperature, so that the silicon on the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 evaporates, to form a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100, wherein the semiconductor epitaxial graphene buffer layer is a mobility-enhanced semiconductor layer 102, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer 101 are connected by covalent bonding.

[0090] For example, the preparation of the semiconductor epitaxial graphene buffer layer uses the heated first silicon carbide epitaxial layer 101, and during the heating process, the silicon evaporates before the carbon, to spontaneously crystallize on the surface of the first silicon carbide epitaxial layer 101 to generate the semiconductor epitaxial graphene buffer layer. In this way, the semiconductor epitaxial graphene buffer layer is connected to the first silicon carbide epitaxial layer 101 by covalent bonding during the growth process, without the need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The semiconductor epitaxial graphene buffer layer, as the mobility-enhanced semiconductor layer 102, is a two-dimensional semiconductor material, and the mobility-enhanced semiconductor layer 102 and the first silicon carbide epitaxial layer 101 are connected by covalent ordered bonding. The semiconductor epitaxial graphene buffer layer has very high mobility, so the technical solution of arranging the epitaxial graphene buffer layer between the first silicon carbide epitaxial layer 101 and the second silicon carbide epitaxial layer 103 greatly increases the channel carrier mobility in the power device, thereby reducing the on-resistance of the power device. In addition, the semiconductor epitaxial graphene buffer layer also has the advantages of high strength and high thermal conductivity.

[0091] For example, as shown in FIG. 11, which is a flowchart included in S1301 of FIG. 10, S1301 heats the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that the silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates, to form a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, including:

[0092] S1301a, providing a silicon carbide semiconductor layer, and arranging the carbon surface of the silicon carbide semiconductor layer opposite to the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

[0093] As shown in FIG. 12, a silicon carbide semiconductor layer 114 is provided. The carbon face of the silicon carbide semiconductor layer 114 is arranged opposite to the silicon face of the first silicon carbide epitaxial layer 101.

[0094] S1301b, the first silicon carbide epitaxial layer 101 away from the side of the silicon carbide substrate and the silicon carbide semiconductor layer 114 are heated to a preset temperature, so that the carbon face of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate are provided at a preset temperature to establish the condition of quasi-equilibrium between the carbon face and the silicon face; wherein the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is the silicon face.

[0095] As shown in FIG. 12, the first silicon carbide epitaxial layer 101 away from the side of the silicon carbide substrate 100 and the silicon carbide semiconductor layer 114 are heated to a preset temperature, so that the carbon face of the silicon carbide semiconductor layer 114 and the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 are provided at a preset temperature to establish the condition of quasi-equilibrium between the carbon face and the silicon face; wherein the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 is the silicon face.

[0096] S1301c, the silicon evaporation of the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, so as to form a semiconductor epitaxial graphene buffer layer with a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

[0097] As shown in FIG. 12, during the heating process, silicon is made to evaporate before carbon, to produce a semiconductor epitaxial graphene buffer layer by spontaneous crystallization on the surface of the first silicon carbide epitaxial layer 101, wherein the semiconductor epitaxial graphene buffer layer is connected to the first silicon carbide epitaxial layer 101 by covalent bonding during the growth process, without the need to form a bonding layer, simplifying the preparation process and reducing the preparation cost. Since the carbon surface of the silicon carbide semiconductor layer 114 and the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100 provide conditions for quasi-equilibrium between the carbon surface and the silicon surface at a predetermined temperature, a semiconductor epitaxial graphene buffer layer with a thickness equal to the thickness of a single layer of carbon atoms can be formed on the surface of the first silicon carbide epitaxial layer 101 away from the silicon carbide substrate 100. When the semiconductor epitaxial graphene buffer layer is used as the mobility enhancement semiconductor layer 102, the semiconductor epitaxial graphene buffer layer is essentially a single layer of carbon atoms in the silicon carbide epitaxial layer, with a thickness equivalent to that of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor epitaxial graphene buffer layer is greater than or equal to 0.2 nm and less than or equal to 0.3 nm, with an average thickness of about 0.25 nm. The bonding between the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer 101 is ordered and periodically arranged, which can ensure that the semiconductor epitaxial graphene buffer layer is a two-dimensional semiconductor material when used as the mobility enhancement semiconductor layer 102. The band gap of the semiconductor epitaxial graphene buffer layer is smaller than that of silicon, approximately 0.6 ev.

[0098] For example, after the first silicon carbide epitaxial layer 101 spontaneously crystallizes to produce a semiconductor epitaxial graphene buffer layer (mobility enhancement semiconductor layer 102), the silicon carbide semiconductor layer 114 can be removed, and the step of S140 can be performed to form a second silicon carbide epitaxial layer 103 on the side of the mobility enhancement semiconductor layer 102 away from the first silicon carbide epitaxial layer 101.

[0099] For example, at the same predetermined temperature, the mobility of the semiconductor epitaxial graphene buffer layer is greater than that of silicon.

[0100] For example, at the same selected room temperature, the room temperature mobility of the semiconductor epitaxial graphene buffer layer is greater than that of silicon, and the maximum mobility can reach 5500 cm 2 V -1 s -1 , which is about 10 times the room temperature mobility of silicon, greatly increasing the channel carrier mobility in power devices, thereby reducing the on-resistance of the power device. Room temperature is also known as normal temperature or general temperature, and is generally defined as 25 degrees Celsius, and sometimes as 300K (about 27 degrees Celsius).

[0101] For example, as shown in FIG. 13, FIG. 13 is a flow chart of another method for manufacturing a power device according to an embodiment of the present application. The method for manufacturing a power device shown in FIG. 13 is different from the methods shown in FIG. 4 and FIG. 9 in that a protective layer is formed before S140. For example, S140 further includes the following before forming the second silicon carbide epitaxial layer away from the side of the mobility-enhanced semiconductor layer from the first silicon carbide epitaxial layer:

[0102] S1401, forming a protective layer on the side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer by an atomic layer deposition process.

[0103] As shown in FIG. 14, a protective layer 113 is formed on the side of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101 by an atomic layer deposition process. The protective layer 113 is a thin film formed by an atomic layer deposition process. Due to the highly controllable deposition parameters (thickness, composition and structure) of the protective layer 113, the protective layer 113 has excellent deposition uniformity and consistency. The protective layer 113 is arranged to protect the surface of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101, so as to avoid damaging the mobility-enhanced semiconductor layer 102 during the epitaxial formation of the second silicon carbide epitaxial layer 103 and the subsequent film layer process, thereby ensuring that the mobility-enhanced semiconductor layer 102 has high mobility, thereby increasing the structural stability of the power device. For example, the thickness of the protective layer 113 is relatively thin, and the minimum thickness of the protective layer 113 is 5 nm. On the basis of achieving the effect of protecting the surface of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101, the protective layer 113 has little effect on the on-resistance of the power device.

[0104] For example, the protective layer 113 formed on the side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer 101 by an atomic layer deposition process includes a gold protective layer or an aluminum oxide protective layer.

[0105] For example, the gold protective layer or the aluminum oxide protective layer has stable physical and chemical properties, and can achieve the effect of protecting the surface of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101, so as to avoid damaging the mobility-enhanced semiconductor layer 102 during the epitaxial formation of the second silicon carbide epitaxial layer 103 and the subsequent film layer process.

[0106] As shown in FIG. 15, after the protective layer 113 is formed on the side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer 101 by an atomic layer deposition process, the method further includes: forming a second silicon carbide epitaxial layer 103 on the side of the mobility-enhanced semiconductor layer 102 away from the first silicon carbide epitaxial layer 101 by an epitaxial process, wherein the second silicon carbide epitaxial layer 103 is arranged with a body region 104 and an active region 105 away from the surface of the mobility-enhanced semiconductor layer 102.

[0107] As shown in FIG. 16, a planar gate structure 106 is formed on the surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancement semiconductor layer 102. A source 107 is formed on the surface of the second silicon carbide epitaxial layer 103 away from the mobility enhancement semiconductor layer 102. As shown in FIG. 3, a drain 108 is formed on the side of the silicon carbide substrate 100 away from the first silicon carbide epitaxial layer 101 by a sputtering process.

[0108] The embodiment of the present application further provides a power module, which comprises a substrate and at least one power device according to any of the above-mentioned embodiments, and the substrate is configured to support the power device. Therefore, the power module provided by the embodiment of the present application also has the beneficial effects described in the above-mentioned embodiments, which will not be repeated here.

[0109] The embodiment of the present application further provides a power conversion circuit, which is configured to perform at least one of the following operations: current conversion, voltage conversion, and power factor correction; and the power conversion circuit comprises a circuit board and a power device according to any of the above-mentioned embodiments, and the power device is electrically connected to the circuit board. Therefore, the power conversion circuit provided by the embodiment of the present application also has the beneficial effects described in the above-mentioned embodiments, which will not be repeated here.

[0110] The embodiment of the present application further provides a vehicle, which comprises a load and a power conversion circuit according to any of the above-mentioned embodiments, and the power conversion circuit is configured to convert alternating current and / or direct current into alternating current and / or direct current and then input to the load. Wherein, the scheme in which the power conversion circuit is configured to convert alternating current and / or direct current into alternating current and / or direct current and then input to the load includes: the power conversion circuit is configured to convert alternating current into alternating current and then input to the load. The power conversion circuit is configured to convert alternating current into direct current and then input to the load. The power conversion circuit is configured to convert direct current into alternating current and then input to the load. The power conversion circuit is configured to convert direct current into direct current and then input to the load. Therefore, the vehicle provided by the embodiment of the present application also has the beneficial effects described in the above-mentioned embodiments, which will not be repeated here.

[0111] It should be understood that the above-mentioned various forms of flow can be used to reorder, add or delete steps. For example, the steps described in the present application can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions of the present application can be achieved, which will not be limited herein.

Claims

1. A power device, comprising: a silicon carbide substrate; a first silicon carbide epitaxial layer, wherein the first silicon carbide epitaxial layer is located on one side of the silicon carbide substrate; a mobility-enhanced semiconductor layer, wherein the mobility-enhanced semiconductor layer is located on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, and wherein the mobility-enhanced semiconductor layer has a mobility greater than that of silicon carbide at a same preset temperature; a second silicon carbide epitaxial layer, wherein the second silicon carbide epitaxial layer is located on a side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer, and wherein the second silicon carbide epitaxial layer has a body region and an active region on a surface thereof away from the mobility-enhanced semiconductor layer; a planar gate structure, wherein the planar gate structure is located on a side of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer; a source electrode, wherein the source electrode is located on a side of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer; a drain electrode, wherein the drain electrode is located on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

2. The power device of claim 1, wherein, The mobility-enhanced semiconductor layer comprises a semiconductor epitaxial graphene buffer layer. The semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are connected by covalent bond ordering.

3. The power device of claim 2, wherein, The semiconductor epitaxial graphene buffer layer has a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm.

4. The power device according to claim 2 or 3, wherein, The semiconductor epitaxial graphene buffer layer has a mobility greater than that of silicon at a same preset temperature. 5.The power device of claim 1, further comprising a protective layer, wherein the protective layer is located on a side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer.

6. The power device of claim 5, wherein, The protective layer comprises a gold protective layer or an aluminum oxide protective layer. 7.A method for manufacturing a power device, comprising: providing a silicon carbide substrate; forming a first silicon carbide epitaxial layer on one side of the silicon carbide substrate; forming a mobility-enhanced semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the mobility-enhanced semiconductor layer has a mobility greater than that of silicon carbide at a same preset temperature; forming a second silicon carbide epitaxial layer on a side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer, wherein the second silicon carbide epitaxial layer has a body region and an active region on a surface thereof away from the mobility-enhanced semiconductor layer; forming a planar gate structure on a side of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer; forming a source electrode on a side of the second silicon carbide epitaxial layer away from the mobility-enhanced semiconductor layer; forming a drain electrode on a side of the silicon carbide substrate away from the first silicon carbide epitaxial layer.

8. The method of producing a power device according to claim 7, wherein The forming of the mobility-enhanced semiconductor layer on a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate comprises: heating a side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to a preset temperature, so that silicon on a surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates to form a semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, wherein the semiconductor epitaxial graphene buffer layer serves as the mobility-enhanced semiconductor layer, and the semiconductor epitaxial graphene buffer layer and the first silicon carbide epitaxial layer are connected by ordered bonding through covalent bonds.

9. The method of producing a power device according to claim 8, wherein, The heating of the side of the first silicon carbide epitaxial layer away from the silicon carbide substrate to the preset temperature, so that the silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates to form the semiconductor epitaxial graphene buffer layer on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate, includes: providing a silicon carbide semiconductor layer, and oppositely arranging a carbon surface of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate; heating the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate and the silicon carbide semiconductor layer to a preset temperature, so that the carbon surface of the silicon carbide semiconductor layer and the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate provide a condition for quasi-equilibrium between the carbon surface and the silicon surface at the preset temperature; wherein the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate is a silicon surface; The silicon on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate evaporates to form a semiconductor epitaxial graphene buffer layer with a thickness greater than or equal to 0.2 nm and less than or equal to 0.3 nm on the surface of the first silicon carbide epitaxial layer away from the silicon carbide substrate.

10. The method of producing a power device according to Claim 7, wherein The forming of the second silicon carbide epitaxial layer on the side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer further includes: forming a protective layer on the side of the mobility-enhanced semiconductor layer away from the first silicon carbide epitaxial layer by an atomic layer deposition process.

11. A power module comprising a substrate and at least one power device as claimed in any one of claims 1 to 6, the substrate being arranged to carry the power device.

12. A power conversion circuit, the power conversion circuit being arranged to perform at least one of: current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one power device as claimed in any one of claims 1 to 6, the power device being electrically connected to the circuit board.

13. A vehicle comprising a load and a power conversion circuit as claimed in claim 12, the power conversion circuit being arranged to input to the load after performing at least one of: converting alternating current to alternating current; converting alternating current to direct current; converting direct current to alternating current; and converting direct current to direct current. ​

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