Memory and operation method therefor, storage system, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and disclose a memory and an operation method therefor, a storage system, and an electronic device. The memory comprises a peripheral circuit and a plurality of memory arrays. The peripheral circuit comprises a memory array controller and a first gate, and the memory array controller is connected to the first gate. The plurality of memory arrays are stacked in the thickness direction of the peripheral circuit, and the plurality of memory arrays are respectively connected to the first gate. The plurality of memory arrays comprises a first memory array. The memory array controller is configured to control the first gate to select the first memory array so as to output a driving signal to the selected first memory array. The plurality of memory arrays are stacked, thereby greatly increasing the storage density and the storage capacity of the memory. The memory array controller and the first gate are additionally configured, and the plurality of memory arrays are respectively and independently connected to the first gate, thereby allowing for selection, independent control and management, and independent operation for the plurality of memory arrays.

Description

Memory, operation method thereof, storage system and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410635276.0, filed on May 21, 2024, and entitled "Memory, operation method thereof, storage system and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a memory, an operation method thereof, a storage system and an electronic device. BACKGROUND

[0003] Three-dimensional memory, which is usually formed by vertically stacking multiple layers of memory cells, is used to solve the limitations of two-dimensional or planar memory to support higher storage capacity in a smaller space.

[0004] With the continuous evolution of integrated circuit technology, the demand for storage capacity of memory is increasing, and the number of stacked layers of memory cells in three-dimensional memory is also increasing. However, due to the limitations of process etching capability and channel current transmission capability, there is an upper limit to the number of stacked layers of memory cells in three-dimensional memory, which also limits the growth of storage capacity. SUMMARY

[0005] Embodiments of the present application provide a memory, an operation method thereof, a storage system and an electronic device to improve the storage capacity of the memory.

[0006] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a memory is provided, comprising: a peripheral circuit and a plurality of memory arrays. The peripheral circuit comprises a memory array controller and a first gate, and the memory array controller is connected to the first gate. The plurality of memory arrays are stacked along the thickness direction of the peripheral circuit, and the plurality of memory arrays are respectively connected to the first gate. The plurality of memory arrays comprise a first memory array. The memory array controller is configured to control the first gate to select the first memory array to output a driving signal to the selected first memory array.

[0008] The memory provided by some embodiments of the present application can greatly increase the number of vertically stacked memory cells and the storage density and storage capacity of the memory by stacking the plurality of memory arrays along the thickness direction of the peripheral circuit to form a multi-memory array wafer stacking architecture, thereby removing the limitation on the number of stacked gate layers in the stacked structure of the memory array, and removing the limitations of process etching capability and channel current transmission capability.

[0009] Moreover, the embodiment of the application can realize independent selection and operation of the plurality of memory arrays by the memory array controller and the first gate, and realize separate control management and driving operation of each memory array. In addition, the transmission path between the driving signal and the selected first memory array can be shortened, and the time delay of the memory and the storage system to which the memory is applied can be reduced.

[0010] In a possible implementation of the first aspect, the number of the peripheral circuits is a plurality, and the plurality of peripheral circuits are located on the same side of the plurality of memory arrays. In this way, on the one hand, the arrangement regularity of the peripheral circuits and the memory arrays in the memory can be improved, and the internal space of the memory can be reasonably designed; on the other hand, the memory array controllers of the plurality of peripheral circuits can be provided with a coordination mechanism, so as to facilitate coordinated control, management and driving of the plurality of memory arrays, and improve the performance of the memory.

[0011] In a possible implementation of the first aspect, the two adjacent peripheral circuits are a first peripheral circuit and a second peripheral circuit, and the first peripheral circuit is located between the second peripheral circuit and the plurality of memory arrays. The memory further includes a conductive channel, the conductive channel penetrating through the first peripheral circuit and connecting the output end of the first gate in the first peripheral circuit and the output end of the first gate in the second peripheral circuit. In this way, the connection between the second peripheral circuit and each memory array can also be realized through the conductive channel; and the second peripheral circuit and the first peripheral circuit can share the same set of interconnection structures (including the word line interconnection conductive column, the bit line interconnection conductive column and the source line interconnection conductive column mentioned below), so as to simplify the structure of the memory.

[0012] In a possible implementation of the first aspect, the number of the peripheral circuits is a plurality, and the plurality of peripheral circuits are located on opposite sides of the plurality of memory arrays. In this way, on the one hand, the connection between each peripheral circuit and the memory array can be realized, and the reliability and yield of the memory can be improved; on the other hand, the memory array controllers of the plurality of peripheral circuits can be provided with a coordination mechanism, so as to facilitate coordinated control, management and driving of the plurality of memory arrays, and improve the performance of the memory.

[0013] In a possible implementation of the first aspect, the plurality of peripheral circuits comprises: a first peripheral circuit and a second peripheral circuit located at opposite sides of the plurality of memory arrays respectively. The memory further comprises an interconnection via connecting the first memory array and the first gate. The interconnection via connecting the first peripheral circuit and the first memory array of the first gate is connected with the interconnection via connecting the second peripheral circuit and the first memory array of the first gate. In this way, the interconnection via connecting the first peripheral circuit and the first memory array of the first gate and the interconnection via connecting the second peripheral circuit and the first memory array of the first gate can share various types of contacts and various types of interconnection lines in the memory array, which is beneficial to simplify the structure of the memory array.

[0014] In a possible implementation of the first aspect, the number of the first memory arrays is a plurality, and the plurality of peripheral circuits comprises a first peripheral circuit and a second peripheral circuit. The memory array controller of the first peripheral circuit is configured to control the first gate of the first peripheral circuit to select a part of the plurality of first memory arrays to output a driving signal to the selected part of the plurality of first memory arrays. The memory array controller of the second peripheral circuit is configured to control the first gate of the second peripheral circuit to select another part of the plurality of first memory arrays to output a driving signal to the selected another part of the plurality of first memory arrays. In this way, on the one hand, the plurality of types of commands can be supported and executed synchronously in the case that the plurality of types of commands are received by the peripheral circuit; on the other hand, a better command execution path can be selected preferentially according to actual conditions; and on the other hand, the operability of the memory can be ensured in the case that a part of the peripheral circuit fails.

[0015] In a possible implementation of the first aspect, the first memory array comprises: a laminated structure, a word line contact and a word line interconnection line. The laminated structure comprises a plurality of gate layers and a plurality of gate dielectric layers alternately laminated along a thickness direction of the peripheral circuit. The word line contact extends along the thickness direction of the peripheral circuit and is connected with the gate layer. The word line interconnection line extends along a direction perpendicular to the thickness direction of the peripheral circuit and is connected with the word line contact. The memory further comprises a word line interconnection via extending along the thickness direction of the peripheral circuit. The word line interconnection via connects the first gate and the word line interconnection line. In this way, the memory array controller can be used to select and independently operate at least one gate layer in the first memory array.

[0016] In a possible implementation of the first aspect, the first storage array further includes a channel structure, a bit line contact and a bit line interconnection line. The channel structure penetrates the stack structure. The bit line contact extends along a thickness direction of the peripheral circuit and is connected with the channel structure. The bit line interconnection line extends along a direction perpendicular to the thickness direction of the peripheral circuit and is connected with the bit line contact. The memory further includes a bit line interconnection via extending along the thickness direction of the peripheral circuit. The bit line interconnection via is connected with the first selector and the bit line interconnection line. In this way, the storage array controller can be used to select and independently operate at least one channel structure in the first storage array.

[0017] In a possible implementation of the first aspect, the first storage array further includes a common source structure, a source line contact and a source line interconnection line. The common source structure is located at one side of the stack structure along the thickness direction of the peripheral circuit. The source line contact extends along the thickness direction of the peripheral circuit and is connected with the common source structure. The source line interconnection line extends along a direction perpendicular to the thickness direction of the peripheral circuit and is connected with the source line contact. The memory further includes a source line interconnection via extending along the thickness direction of the peripheral circuit. The source line interconnection via is connected with the first selector and the source line interconnection line. In this way, the storage array controller can be used to select and independently operate the common source structure in the first storage array.

[0018] In a possible implementation of the first aspect, the word line interconnection via, the bit line interconnection via and the source line interconnection via are arranged away from the first storage array. In this way, the word line interconnection via, the bit line interconnection via and the source line interconnection via can be prepared without damaging the storage arrays, thereby improving the yield of the memory.

[0019] In a possible implementation of the first aspect, the memory further includes a second selector connected between the first selector and the plurality of storage arrays. The second selector is configured to select at least one memory page in the selected first storage array and output a driving signal to the selected at least one memory page. That is, by arranging the first selector, the embodiment of the present application can select at least one memory page from the first storage array for operation after the first storage array is selected, without going through all the storage arrays, and without synchronously performing the same operation on all the storage arrays, thereby effectively reducing the time delay of the memory and the storage system to which the memory is applied.

[0020] In a second aspect, an operating method of a memory is provided. The operating method is applied to the memory. The memory includes a peripheral circuit and a plurality of memory arrays. The peripheral circuit includes a memory array controller and a first gate. The memory array controller is connected to the first gate. The plurality of memory arrays are stacked along a thickness direction of the peripheral circuit. The plurality of memory arrays are respectively connected to the first gate. The plurality of memory arrays include a first memory array. The operating method includes: receiving, by the peripheral circuit, a data address; controlling, by the memory array controller, the first gate to select the first memory array according to the data address; and outputting, by the first gate, a driving signal to the selected first memory array.

[0021] In a possible implementation of the second aspect, the memory further includes a second gate connected between the first gate and the plurality of memory arrays. Before the first gate outputs the driving signal to the selected first memory array, the operating method further includes: selecting, by the second gate, at least one memory page in the selected first memory array; receiving, by the second gate, the driving signal; and outputting, by the second gate, the driving signal to the selected at least one memory page.

[0022] In a possible implementation of the second aspect, the number of the first memory arrays is a plurality, and the number of the peripheral circuits is a plurality. The plurality of peripheral circuits include a first peripheral circuit and a second peripheral circuit. The memory array controller controls the first gate to select the first memory array according to the data address, including: a memory array controller of the first peripheral circuit controls the first gate of the first peripheral circuit to select a part of the plurality of first memory arrays; and a memory array controller of the second peripheral circuit controls the first gate of the second peripheral circuit to select another part of the plurality of first memory arrays.

[0023] In a third aspect, a storage system is provided. The storage system includes a plurality of memories and a memory controller. The memory controller is connected to the plurality of memories. The plurality of memories include a first memory. The first memory includes the memory as described in any of the implementations of the first aspect.

[0024] In a possible implementation manner of the third aspect, the plurality of memories further include a second memory, and the second memory includes: a plurality of peripheral circuits and a plurality of memory arrays. The plurality of peripheral circuits are stacked along a thickness direction of the peripheral circuits, and the peripheral circuits include a memory array controller and a first gate. The memory array controller is connected with the first gate. The plurality of peripheral circuits include a first peripheral circuit and a second peripheral circuit adjacent to each other. The plurality of memory arrays are stacked along the thickness direction of the peripheral circuits, and the plurality of memory arrays are located between the first peripheral circuit and the second peripheral circuit. Part of the plurality of memory arrays are respectively connected with the first gate of the first peripheral circuit, and another part of the plurality of memory arrays are respectively connected with the first gate of the second peripheral circuit. The memory array controller of the first peripheral circuit is configured to control the first gate of the first peripheral circuit to select a first memory array from the part of the plurality of memory arrays, so as to output a driving signal to the selected first memory array. The memory array controller of the second peripheral circuit is configured to control the first gate of the second peripheral circuit to select a first memory array from the another part of the plurality of memory arrays, so as to output a driving signal to the selected first memory array.

[0025] In a fourth aspect, an electronic device is provided, and the electronic device includes: a memory system and a circuit board, the memory system being connected with the circuit board. The memory system is the memory system in any of the different implementation manners of the third aspect.

[0026] In a fifth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores computer executable instructions. When the computer executable instructions are executed, the operation method in any of the different implementation manners of the second aspect can be implemented.

[0027] In a sixth aspect, a computer program product is provided, and when the computer program product runs on a computer, the computer is caused to execute the operation method in any of the different implementation manners of the second aspect.

[0028] The technical effects brought by any of the implementation manners of the second aspect to the sixth aspect can refer to the technical effects brought by the different implementation manners of the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is an architecture diagram of an electronic device provided by an embodiment of the present application;

[0030] FIG. 2 is an architecture diagram of another electronic device provided by an embodiment of the present application;

[0031] FIG. 3 is an architecture diagram of a memory system provided by an embodiment of the present application;

[0032] FIG. 4 is an architecture diagram of another memory system provided by an embodiment of the present application;

[0033] Figure 5 is an equivalent circuit diagram of a memory according to an embodiment of the present application;

[0034] Figure 6 is a partial structure diagram of a memory according to an embodiment of the present application;

[0035] Figure 7 is a structure diagram of a memory array according to an embodiment of the present application;

[0036] Figure 8a is a structure diagram of a memory according to an embodiment of the present application;

[0037] Figure 8b is a structure diagram of another memory according to an embodiment of the present application;

[0038] Figure 9 is a structure diagram of yet another memory according to an embodiment of the present application;

[0039] Figure 10 is a structure diagram of yet another memory according to an embodiment of the present application;

[0040] Figure 11 is a structure diagram of yet another memory according to an embodiment of the present application;

[0041] Figure 12a is a structure diagram of yet another memory according to an embodiment of the present application;

[0042] Figure 12b is a structure diagram of yet another memory according to an embodiment of the present application;

[0043] Figure 13 is a flow chart of a method of operating a memory array according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0045] In the description of the present application, "a plurality of" means two or more than two, unless otherwise specified. "At least one" or similar expressions mean any combination of these items, including any combination of single or multiple. For example, at least one of a, b, or c can represent a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple.

[0046] In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms "first", "second", etc. are used to distinguish the same or similar items with basically the same function and role. Those skilled in the art can understand that the terms "first", "second", etc. do not limit the quantity and execution order, and the terms "first", "second", etc. also do not necessarily mean different. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are intended to present the relevant concept in a specific manner, for ease of understanding.

[0047] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" can mean that two or more components have direct physical contact or electrical contact. The term "coupling" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other.

[0048] In the embodiments of the present application, "vertical", "parallel" are described respectively to mean approximately vertical and approximately parallel within a certain error range, which can be a range of less than or equal to 5°, 8° or 10° of deviation angle with respect to absolute vertical and absolute parallel, which is not limited here.

[0049] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in the shape of the drawings relative to the drawings can be contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, etched regions shown as rectangular will typically have curved features. Therefore, the regions shown in the drawings are essentially schematic, and their shape is not intended to show the actual shape of the regions of the device, and is not intended to limit the scope of the exemplary embodiments.

[0050] In addition, the architecture and scenarios described in the embodiments of the present application are to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, as the architecture evolves and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0051] Embodiments of the present application provide an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as: Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0052] The electronic device in embodiments of the present application can be a mobile phone, a pad, a notebook computer, a smart home, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, and the like. The electronic device can also be a handheld device with a wireless communication function, a computing device, or other processing devices connected to a wireless modem, a vehicle-mounted device, an electronic device in a 5G network, or an electronic device in a future evolved public land mobile network (PLMN), and the like, which are not limited in embodiments of the present application.

[0053] FIG. 1 and FIG. 2 are respectively an architecture diagram of an electronic device provided in embodiments of the present application.

[0054] In some examples, as shown in FIG. 1, the electronic device 1000 can include a circuit board 100, a bus 200, and a processor 300. The bus 200 is located on and connected with the circuit board 100. The processor 300 is located on the circuit board 100 and connected with the bus 200. The circuit board 100 is, for example, a printed circuit board (PCB), and the processor 300 is, for example, a central processing unit (CPU) or a system on chip (SoC), which can be used to process data, such as processing data of an application program, processing image data, and buffering temporary data. Optionally, the processor 300 can include an application processor (AP) 310 for processing an application program, a graphics processing unit (GPU) 320 for processing image data, and a first RAM 330 for buffering high-speed data. The first RAM 330 can be a static random access memory (SRAM) or an embedded flash (eFlash), etc. The above-mentioned application processor 300, graphics processing unit 320, and first RAM 330 can be integrated in one die, or can be respectively arranged in multiple dies.

[0055] Continuing to refer to FIG. 1, the electronic device 1000 can further include a second RAM 400, which can be connected with the processor 300 through the bus 200. The second RAM 400 can be a DRAM. The second RAM 400 can be used to save volatile data, such as temporary data generated by the above-mentioned system on chip. The storage capacity of the second RAM 400 can be generally larger than that of the first RAM 330, but the reading speed of the second RAM 400 is generally slower than that of the first RAM 330.

[0056] In addition, the electronic device 1000 can further include a communication chip 500 and a power management chip 600, both of which are connected with the processor 300 through the bus 200. The communication chip 500 can be used for processing of a protocol stack, or for amplification, filtering, etc. of an analog radio frequency signal, or for simultaneously implementing the above-mentioned functions. The power management chip 600 can be used to supply power to other chips. For example, the above-mentioned processor 300 and second RAM 400 can be packaged in the same packaging structure, such as 2.5D (dimension) or 3D (three-dimensional) packaging, etc. to obtain a faster data transmission rate between chips.

[0057] Embodiments of the present application also provide a storage system, which is applied to the electronic device described above. In some embodiments, the storage system can be the first RAM 330 in FIG. 1, or the second RAM 400 in FIG. 1. Embodiments of the present application do not limit the application scenarios of the storage system described above.

[0058] In some examples, as shown in FIG. 2, FIG. 3 and FIG. 4, the storage system 700 described above can include a memory 710 and a memory controller 720, the memory controller 720 is connected with the memory 710 and connected with the processor 300. The memory controller 720 can control the memory 710 and communicate with the processor 300.

[0059] Optionally, the memory controller 720 is configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. Optionally, the memory controller 720 can also be configured to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), wherein the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0060] For example, the memory controller 720 can be configured to control the operation of the memory 710, such as read, erase and program operations. The memory controller 720 can also be configured to manage various functions related to the data stored or to be stored in the memory 710, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In addition, the memory controller 720 can also be configured to process error correction codes (ECC) related to the data read from the memory 710 or written to the memory 710. The memory controller 720 can also perform other suitable functions, such as formatting the memory 710.

[0061] The memory controller 720 described above can communicate with external devices (such as the processor 300) according to a specific communication protocol. For example, the memory controller 720 can communicate with external devices through at least one of various interface protocols. The interface protocol includes but is not limited to USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronic device (IDE) protocol, Firewire protocol, etc.

[0062] The number of the memory 710 can be one, two, three or more. FIG. 2 shows three memories 710, and FIGS. 3 and 4 each show four memories 710. The memory 710 and the memory controller 720 can be integrated in an SSD, and the SSD can further include a connector for connecting the SSD with the processor 300.

[0063] For example, as shown in FIG. 3, the memory 710 and the memory controller 720 in the storage system 700 can be two independent chips, and the memory 710 and the memory controller 720 can be respectively arranged on a carrier board (e.g., a package transistor chain or a re-distribution board) and connected with the carrier board. In this way, the memory 710 and the memory controller 720 can realize signal transmission through metal traces in the carrier board. Therefore, the storage system 700 with the memory 710 can be referred to as a stand-alone storage system.

[0064] Alternatively, for example, the memory 710 and the memory controller 720 in the storage system 700 can be two independent chips, and the memory 710 and the memory controller 720 can be stacked on the carrier board. The memory 710 and the memory controller 720 can be connected through a through silicon via (TSV) or a redistribution layer (RDL), so that the memory 710 and the memory controller 720 can realize signal transmission with the carrier board. Therefore, the storage system 700 with the memory 710 can be referred to as a stand-alone storage system.

[0065] Alternatively, for example, as shown in FIG. 4, the memory 710 is stacked on the memory controller 720, and the memory 710 and the memory controller 720 can be integrated in the same chip, and the integrated chip is connected with the carrier board. Therefore, the storage system 700 with the memory 710 can be referred to as an embedded storage system.

[0066] Optionally, the memory 710 is a three-dimensional memory, for example, in which memory cells are vertically stacked to increase the storage density per unit area and accommodate a higher storage capacity in a smaller space. The memory 710 can be of various types, and can include, but is not limited to, a 3D NAND flash memory, a ferroelectric random access memory (FRAM), and the like. In the following, an embodiment of the present application is illustratively described with the memory 710 including a 3D NAND flash memory.

[0067] FIG. 5 is an equivalent circuit diagram of a memory according to an embodiment of the present application. As shown in FIG. 5, the memory 710 includes a memory array 1 and a peripheral circuit 2, which are connected to each other. The memory array 1 includes a plurality of memory cells MC, each of which can be programmed and store one or more bits of data. At least two memory cells MC are connected in series and vertically stacked to form a memory cell string 112; a plurality of memory cell strings 112 can form a memory block 11; and a plurality of memory blocks 11 can form a memory plane. In the plurality of memory cell strings 112 of the same memory block 11, a plurality of memory cells MC located in the same row can form a memory page 111.

[0068] Referring back to FIG. 5, in each memory cell string 112, a first select transistor Q1 is connected at the source end and a second select transistor Q2 is connected at the drain end. The first and second select transistors Q1 and Q2 can be configured to activate a selected memory cell string 112 during read and program operations. The first select transistors Q1 of the plurality of memory cell strings 112 in the same memory block 11 can be connected to the same source line SL; in other words, the memory block 11 has a common source structure connecting the first select transistors Q1 of the plurality of memory cell strings 112. The second select transistors Q2 of the memory cell strings 112 are respectively connected to corresponding bit lines BL; via the bit lines BL, data can be read or written.

[0069] For example, the memory cell string 112 is further connected to a plurality of word lines WL. Among the plurality of word lines WL, the word line WL connected to each memory page 111 can also be referred to as a control gate line, the word line WL connected to each first select transistor Q1 can also be referred to as a source side select gate (SSG), and the word line WL connected to each second select transistor Q2 can also be referred to as a drain side select gate (DSG).

[0070] Figure 6 is a partial structure diagram of a memory according to an embodiment of the present application. As shown in Figure 6, the channel structure 12 penetrates the stack structure 13 and extends to the source layer 14. The channel structure 12 includes, for example, a channel layer 121 and a storage functional layer 122, which can include a tunneling layer 1221, a charge trapping layer 1222 and a blocking layer 1223 arranged in sequence. The storage functional layer 122 is above the source layer 14, the channel layer 121 extends out of the storage functional layer 122, extends to the source layer 14 and contacts the source layer 14 to form a connection. The material of the source layer 14 includes, but is not limited to, polysilicon, and the source layer 14 can be used as the above-mentioned source line, for example.

[0071] The above-mentioned stack structure 13 can include a plurality of gate layers 131 and a plurality of gate dielectric layers 132 alternately stacked along the thickness direction of the source layer 14. In combination with Figures 5 and 6, each gate layer 131 can be used as a word line WL, and the portion of the gate layer 131 surrounding the channel structure 12 and the portion of the channel structure 12 opposite to the gate layer 131 can constitute a transistor. Specifically, the gate layer 131 closest to the source layer 14 can be used as a source-end selection gate to constitute a first selection transistor Q1; the gate layer 131 farthest from the source layer 14 can be used as a drain-end selection gate to constitute a second selection transistor Q2; and the remaining gate layers 131 can be used as control gate lines to constitute storage transistors (i.e., storage cells MC). In other words, the storage cell string 112 can include the channel structure 12 and the portion of the stack structure 13 surrounding the channel structure 12.

[0072] The above-mentioned peripheral circuit 2 can include any suitable analog, digital and mixed signal circuit for applying voltage signals and / or current signals to or sensing voltage signals and / or current signals from the target storage cell through the bit line BL, the word line WL, the source line SL, etc., to implement the operation of the storage array 1.

[0073] It can be understood that, as the number of gate layers 131 in the stack structure 13 increases, the number of storage cells MC included in the storage cell string 112 also increases, which can increase the storage density by multi-value storage and improve the storage capacity of the memory 710. In the process of manufacturing the above-mentioned storage array 1, the stack structure 13 needs to be etched to form a deep hole, and then the channel structure 12 is formed in the deep hole. However, due to the limitation of the etching capability and the channel current transmission capability, there is an upper limit to the number of gate layers 131 stacked in the above-mentioned stack structure 13, i.e., there is an upper limit to the number of storage cell MCs stacked, which makes it difficult to further increase the storage density and the storage capacity of the memory 710.

[0074] Based on this, some embodiments of the present application provide a memory which can be applied to the above-mentioned storage system 700. Optionally, the memory can be the memory 710 in FIG. 2, FIG. 3 or FIG. 4. The application embodiments do not limit the application scenarios of the above-mentioned memory. FIG. 8a, FIG. 8b, FIG. 9, FIG. 10 and FIG. 11 respectively show a structural diagram of a memory provided by the application embodiments. In addition, FIG. 7 shows a structural diagram of a storage array, and the storage array shown in FIG. 8a, FIG. 8b, FIG. 9, FIG. 10 and FIG. 11 is, for example, a cross-sectional structure of the storage array shown in FIG. 7, and the cross-sectional line of the cross-sectional structure is parallel to the direction X and parallel to the direction Z.

[0075] As shown in FIG. 8a and FIG. 8b, the memory 730 includes a peripheral circuit 3 and a storage array 4, and the peripheral circuit 3 and the storage array 4 are connected.

[0076] In some examples, as shown in FIG. 8a and FIG. 8b, the peripheral circuit 3 includes a storage array controller 31 and a first gate 32, and the storage array controller 31 is connected with the first gate 32. The storage array controller 31 and the first gate 32 can be electrically connected or communicatively coupled (i.e., the storage array controller 31 and the first gate 32 cooperate or interact with each other).

[0077] For example, as shown in FIG. 9, the peripheral circuit 3 further includes a driver 33, and the driver 33 is connected with the storage array controller 31 and connected with the first gate 32. Optionally, the storage array controller 31 and the driver 33 can be electrically connected or communicatively coupled; and the first gate 32 and the driver 33 are electrically connected, for example. The first gate 32 is located in the driver 33, for example, and is connected with part of the circuit structure in the driver 33. The number of the driver 33 is multiple, for example. For example, the number of the driver 33 is two; one of the two drivers 33 includes a row decoder and the like circuit structure, and the other driver 33 includes a column decoder and the like circuit structure, for example.

[0078] Further, the peripheral circuit 3 can further include input / output (I / O) circuit, timing controller and the like circuit structure. Of course, the peripheral circuit 3 can further include more or less circuit structure, which is not limited by the application embodiments.

[0079] In some examples, as shown in FIG. 7, FIG. 8a and FIG. 8b, the above-mentioned storage array 4 includes a stack structure 41, a plurality of channel structures 42 and a common source structure 43.

[0080] The stack structure 41 includes a plurality of gate layers 411 and a plurality of gate dielectric layers 412, which are alternately stacked along the thickness direction of the peripheral circuit 3. The thickness direction of the peripheral circuit 3 is, for example, the direction Z shown in the drawings, which can also be referred to as the vertical (or perpendicular) direction. That is, one gate dielectric layer 412 is arranged between two adjacent gate layers 411, and one gate layer 411 is arranged between two adjacent gate dielectric layers 412. The common source structure 43 is located on one side of the stack structure 41 along the thickness direction of the peripheral circuit 3. The common source structure 43 is, for example, used for grounding. The common source structure 43 is insulated from the gate layers 411. For example, one gate dielectric layer 412 is arranged between the common source structure 43 and the gate layer 411 closest to it. The common source structure 43 can be arranged in various ways, for example, the common source structure 43 includes a substrate, and the stack structure 41 is formed on the substrate; or the common source structure 43 is a polysilicon film layer, in which case the common source structure 43 can also be referred to as a source layer, which is formed by depositing a polysilicon material on the stack structure 41 after removing the substrate. The plurality of channel structures 42 penetrate the stack structure 41, and the channel layer of the channel structure 42 is in contact with the common source structure 43 to form an electrical connection. The relationship between the gate layers 411, the channel structures 42, and the storage units is described above and will not be repeated here.

[0081] For example, the number of the storage arrays 4 is multiple. Optionally, the number of the storage arrays 4 is two, three, four, or even more. Referring to FIGS. 8a and 8b, the plurality of storage arrays 4 are stacked along the thickness direction of the peripheral circuit 3.

[0082] The plurality of storage arrays 4 are insulated from each other and not directly electrically connected. Different storage arrays 4 in the plurality of storage arrays 4 are independent of each other. For example, the plurality of storage arrays 4 are independently prepared on a plurality of wafer substrates. For example, at least two storage arrays 4 are simultaneously prepared on the same wafer substrate and then formed after cutting. Further, different storage arrays 4 are also independent of each other in operation. For example, during the operation of the peripheral circuit 3 on each storage array 4, the data reading or writing of different storage arrays 4 can be independently performed. Optionally, during the data writing of at least one storage array 4 in the plurality of storage arrays 4, other storage arrays 4 can perform data reading or different data writing.

[0083] The plurality of storage arrays 4 can be bonded to each other by a suitable bonding technique or by a suitable intermediate layer (e.g. an adhesive layer) between adjacent two storage arrays 4. Here, the plurality of storage arrays 4 can have various arrangements, which can be selected according to actual needs.

[0084] Optionally, as shown in FIGS. 8a and 8b, the storage array 4 has opposite front surface 4a and back surface 4b along the thickness direction of the peripheral circuit 3. The front surface 4a, for example, refers to the lower surface of the storage array 4 shown in FIGS. 8a and 8b, i.e. the side surface of the stack structure 41 away from the common source structure 43; and the back surface 4b, for example, refers to the upper surface of the storage array 4 shown in FIGS. 8a and 8b, i.e. the side surface of the common source structure 43 away from the stack structure 41. Adjacent two storage arrays 4 are storage array No. 1 and storage array No. 2, and the front surface 4a of the storage array No. 1 is bonded to the back surface 4b of the storage array No. 2. That is, the plurality of storage arrays 4 have a unified orientation. For example, in FIGS. 8a and 8b, the front surfaces 4a of the storage arrays 4 are all downward. For another example, the front surfaces 4a of the storage arrays 4 are all upward.

[0085] In this way, the regularity of the stacking of the storage arrays 4 can be improved, the preparation of the interconnection conductive pillars is facilitated, and the interconnection between the storage arrays 4 and the peripheral circuit 3 is facilitated.

[0086] Optionally, the plurality of storage arrays 4 can also have different orientations. That is, the front surface 4a of at least one storage array 4 is upward, and the front surface 4a of at least one storage array 4 is downward. Here, in the case where there are a plurality of storage arrays 4 with the front surface 4a upward, the plurality of storage arrays 4 with the front surface 4a upward can be arranged adjacent to each other, or can be arranged with at least one storage array 4 with the front surface 4a downward in between, which is not limited in the embodiments of the present application.

[0087] In this way, the embodiments of the present application can greatly increase the number of vertically stacked storage units, greatly increase the storage density and storage capacity of the memory 730, without being limited to the number of stacked gate layers 411 in the stack structure 41, without being limited to the process etching capability and channel current transmission capability. Moreover, this is also conducive to reducing the area occupied by the plurality of storage arrays 4 and reducing the area of the memory 730.

[0088] In some examples, as shown in FIGS. 8a and 8b, the plurality of memory arrays 4 are respectively connected with the first gate 32. That is, each memory array 4 is individually connected with the first gate 32, and the interconnection structure (including the word line interconnection via, the bit line interconnection via, the source line interconnection via, etc. mentioned below) between different memory arrays 4 and the first gate 32 is independent of each other, and the first gate 32 and different memory arrays 4 can transmit signals (such as the driving signal mentioned below) independently of each other.

[0089] In some examples, as shown in FIGS. 8a and 8b, the plurality of memory arrays 4 includes a first memory array 4t. The memory array controller 31 is configured to control the first gate 32 to select the first memory array 4t, so as to output the driving signal to the selected first memory array 4t. For example, the first memory array 4t can also be referred to as a target memory array. The number of the selected first memory array 4t can be one, and correspondingly, the number of the first memory array 4t included in the plurality of memory arrays 4 is one. The number of the selected first memory array 4t can be multiple, and correspondingly, the number of the first memory array 4t included in the plurality of memory arrays 4 is multiple.

[0090] Each memory array 4 in the plurality of memory arrays 4 has a corresponding memory array number. For example, in FIG. 8a, the memory array number of the memory array 4 closest to the peripheral circuit 3 is 1#, and the memory array numbers of the plurality of memory arrays 4 along the thickness direction of the peripheral circuit 3 and sequentially away from the peripheral circuit 3 are 2#, …, (n-1) #, n# respectively.

[0091] For example, the memory array controller 31 can generate a selection signal based on the data address issued to the memory system 700, and the selection signal includes the memory array number of at least one memory array 4 (i.e. the first memory array 4t). For example, the selection signal is a digital signal, the number of memory arrays 4 is eight, and the memory array numbers are 1#, 2#, …, 7#, 8# respectively; if the selection signal is 000, the corresponding memory array 4 with the memory array number 1# (i.e. the memory array number of the first memory array 4t is 1#); if the selection signal is 011, the corresponding memory array 4 with the memory array number 4# (i.e. the memory array number of the first memory array 4t is 4#).

[0092] For example, part of the circuit structure in the peripheral circuit 3 can decode the selection signal and then transmit the decoding result to the first gate 32. At this time, the first gate 32 can selectively transmit the driving signal to the selected first storage array 4t and selectively shut down the path between the peripheral circuit 3 and the remaining storage arrays 4 under the control of the decoding result, so as to independently operate (for example, data writing, reading or erasing) the selected first storage array 4t. Optionally, the first gate 32 includes a plurality of gate transistors. Of course, the first gate 32 can also include other structures.

[0093] Therefore, the memory 730 provided by some embodiments of the present application can remove the limitation of the number of stacked gate layers 411 of the stacked structure 41 in the storage array 4 by stacking a plurality of storage arrays 4 along the thickness direction of the peripheral circuit 3, so that the memory 730 adopts a multi-array wafer stacked architecture, thereby removing the limitation of the etching capability and the channel current transmission capability, greatly increasing the number of vertically stacked storage units, and greatly increasing the storage density and storage capacity of the memory 730.

[0094] Moreover, by adding the storage array controller 31 and the first gate 32 in the peripheral circuit 3 and connecting the plurality of storage arrays 4 to the first gate 32 independently, the storage array controller 31 and the first gate 32 can be used to independently select and operate the plurality of storage arrays 4, to realize the independent control and driving operation of each storage array 4, and to realize the normal operation of the memory 730. In addition, this can shorten the transmission path of the driving signal between the peripheral circuit 3 and the selected first storage array 4t, and reduce the time delay of the memory 730 and the storage system 700 to which the memory 730 is applied.

[0095] In some embodiments, as shown in FIG. 9, the memory 730 further includes a second gate 331, for example, in the driver 33. The second gate 331 is connected between the first gate 32 and the plurality of storage arrays 4. For example, the second gate 331 is used to select at least one storage page in the selected first storage array 4t and output the driving signal to the selected at least one storage page.

[0096] That is, the second strobe 331 can selectively connect the first strobe 32 and at least one selected storage page in the selected first storage array 4t, and selectively shut off the path between the first strobe 32 and the remaining storage pages in the selected first storage array 4t. The drive signal output via the first strobe 32 is first transmitted to the second strobe 331, and then selectively output by the second strobe 331 to the at least one selected storage page in the selected first storage array 4t.

[0097] It can be understood that in the memory 710 shown in FIG. 5, in the case of operating the storage array 1 by the peripheral circuit 2, the format of the data address issued to the storage system 700 is as shown in Table 1:

[0098] Table 1

[0099] Specifically, the memory controller 720 can determine the target storage system according to the storage system number in the data address, determine the target memory in the storage system, and then transmit the data address to the peripheral circuit 2 of the target memory; the peripheral circuit 2 can sequentially determine the target storage surface, the target storage block and the target storage page in the target memory according to the data address; and then the peripheral circuit 2 can operate the target storage page.

[0100] In some embodiments of the present application, in the memory 730 shown in FIGS. 8a and 8b, in the case of operating the storage array 4 by the peripheral circuit 3, the format of the data address issued to the storage system 700 is as shown in Table 2:

[0101] Table 2

[0102] Specifically, the memory controller 720 can determine the target storage system according to the storage system number in the data address, determine the target memory in the storage system, and then transmit the data address to the peripheral circuit 3 of the target memory; the storage array controller 31 in the peripheral circuit 3 can sequentially determine the target storage surface, the target storage block and the target storage page in the target storage array (i.e., the first storage array 4t) in the target memory according to the data address, and the driver 33 in the peripheral circuit 3 can cooperate with the storage array controller 31; and then the circuit structure (including but not limited to the second strobe 331) in the peripheral circuit 3 can operate the target storage page.

[0103] Compared with the memory 710 shown in FIG. 5, the storage array number is newly added in the data address format in the scheme provided by the embodiments of the present application, so that the storage array controller 31 can identify each storage array 4.

[0104] That is, the embodiments of the present application can effectively realize the selection and independent operation of each storage array 4 by stacking a plurality of storage arrays 4 and arranging the first gate 32 and the storage array controller 31. In this way, in the process of operating the target storage page (i.e., at least one selected storage page in the selected first storage array 4t), the drive signal can be directly transmitted to the target storage page without passing through the remaining storage arrays 4, and the remaining storage arrays 4 do not need to be synchronously operated in the same way, which can effectively reduce the latency of the memory 730 and the storage system 700 to which the memory 730 is applied.

[0105] The arrangement of the peripheral circuit 3 described above includes various arrangements, which can be selected and arranged according to actual needs. Different arrangements of the peripheral circuit 3 will be described below in conjunction with the accompanying drawings. Of course, the arrangement of the peripheral circuit 3 is not limited to the several arrangements shown in the accompanying drawings.

[0106] In some possible embodiments, as shown in FIGS. 8a and 8b, the number of peripheral circuits 3 is one. In this case, the peripheral circuit 3 can select a first storage array 4t from a plurality of storage arrays 4 and independently perform data writing or data reading on the first storage array 4t.

[0107] For example, as shown in FIGS. 8a and 8b, the peripheral circuit 3 is located on one side of the plurality of storage arrays 4 along the thickness direction of the peripheral circuit 3. For example, the orthographic projection of the peripheral circuit 3 on a reference plane partially overlaps the orthographic projection of each storage array 4 on the reference plane. Further, the orthographic projection of each storage array 4 on the reference plane is located in the orthographic projection range of the peripheral circuit 3 on the reference plane, for example. The reference plane is perpendicular to the thickness direction of the peripheral circuit 3.

[0108] In other possible embodiments, as shown in FIGS. 10 and 11, the number of peripheral circuits 3 is a plurality, and each peripheral circuit 3 is independently connected to a plurality of storage arrays 4. Alternatively, the number of peripheral circuits 3 can be two, three or even more. FIGS. 10 and 11 both show that the number of peripheral circuits 3 is two. In this case, the storage array controllers 31 of the plurality of peripheral circuits 3 are arranged with a coordination mechanism. At this time, the plurality of peripheral circuits 3 can cooperatively control, manage and drive the plurality of storage arrays 4. For example, each peripheral circuit 3 can control, manage and drive different storage arrays 4, thereby realizing efficient operation of the plurality of storage arrays 4 and improving the performance of the memory 730.

[0109] In some examples, the number of the first storage arrays 4t is plural. Optionally, the number of the first storage arrays 4t can be two, three or even more. In addition, the above-mentioned plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b.

[0110] The storage array controller 31 of the first peripheral circuit 3a is configured to control the first gate 32 of the first peripheral circuit 3a to select a portion of the first storage arrays 4t from the plurality of the first storage arrays 4t, so as to output a driving signal to the selected portion of the first storage arrays 4t. The storage array controller 31 of the second peripheral circuit 3b is configured to control the first gate 32 of the second peripheral circuit 3b to select another portion of the first storage arrays 4t from the plurality of the first storage arrays 4t, so as to output a driving signal to the selected another portion of the first storage arrays 4t. That is, the storage array controller 31 of the first peripheral circuit 3a and the storage array controller 31 of the second peripheral circuit 3b can independently select different first storage arrays 4t, respectively.

[0111] For example, in a case where the memory 730 receives multiple types of commands (e.g. also including a data erase command, etc.) at the same time, such as reading data from the first storage array 4t with the storage array number of 2# and writing data into the first storage array 4t with the storage array number of 3#, the storage array controller 31 in the first peripheral circuit 3a and the storage array controller 31 in the second peripheral circuit 3b can be cooperatively processed, so that one of the first peripheral circuit 3a and the second peripheral circuit 3b (e.g. the first peripheral circuit 3a) performs the reading operation on the data in the first storage array 4t with the storage array number of 2# at the same time when the other of the first peripheral circuit 3a and the second peripheral circuit 3b (e.g. the second peripheral circuit 3b) performs the data writing operation on the first storage array 4t with the storage array number of 3#.

[0112] That is, by setting the plurality of peripheral circuits 3, the memory 730 can support the synchronous execution of multiple types of commands, and improve the performance of the memory 730.

[0113] For example, in the case of a large amount of data writing or data reading in the memory 730, the storage array controllers 31 in the first peripheral circuit 3a and the storage array controllers 31 in the second peripheral circuit 3b can be cooperatively processed, so that one of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the first peripheral circuit 3a) can concentrate on processing data writing or reading operations of a part of the storage arrays 4 (for example, storage arrays numbered 1#, 2#, …, or 1#, 3#, …, (2n-1)#), and the other of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the second peripheral circuit 3b) can concentrate on processing data writing or reading operations of another part of the storage arrays 4 (for example, storage arrays numbered n#, (n-1)#, …, or 2#, 4#, …, 2n#).

[0114] That is, by providing multiple peripheral circuits 3, the memory 730 can preferentially select a better command execution path, thereby improving the performance of the memory 730.

[0115] For example, in the case of a failure of one of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the first peripheral circuit 3a) and the inability to work, the storage array controllers 31 in the first peripheral circuit 3a and the storage array controllers 31 in the second peripheral circuit 3b can be cooperatively processed, so that the other of the first peripheral circuit 3a and the second peripheral circuit 3b (for example, the second peripheral circuit 3b) can manage the operations of the multiple storage arrays 4.

[0116] That is, by providing multiple peripheral circuits 3, the availability of the memory 730 can be ensured, thereby improving the safety and reliability of the memory 730.

[0117] The arrangement mode between the multiple peripheral circuits 3 and the multiple storage arrays 4 can be various, and can be selected according to actual needs.

[0118] In some embodiments, as shown in FIG. 10, along the thickness direction of the peripheral circuit 3, the multiple peripheral circuits 3 are located on the same side of the multiple storage arrays 4. For example, the orthographic projections of the multiple peripheral circuits 3 on the reference plane coincide with each other. Further, the orthographic projections of the storage arrays 4 on the reference plane are located in the range of the orthographic projections of the peripheral circuits 3 on the reference plane, for example.

[0119] In this way, the arrangement regularity of the peripheral circuits 3 and the storage arrays 4 in the memory 730 can be improved, and the internal space of the memory 730 can be reasonably designed.

[0120] Continuing to refer to FIG. 10, the memory 730 further includes a plurality of conductive vias 5, which can be in a number corresponding to the number of the memory arrays 4 and the number of functional structures in the memory arrays 4. The functional structures in the memory arrays 4 can include, for example, the gate layer 411, the channel structure 42, the common source structure 43, and the like. Optionally, the conductive vias 5 include through silicon vias (TSVs).

[0121] As an example, as shown in FIG. 10, the plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b, wherein the first peripheral circuit 3a and the second peripheral circuit 3b are arranged adjacently, and the first peripheral circuit 3a is located between the second peripheral circuit 3b and the plurality of memory arrays 4. The conductive vias 5 pass through the first peripheral circuit 3a and connect the output terminals of the first selectors 32 in the first peripheral circuit 3a and the second peripheral circuit 3b.

[0122] At this time, the driving signal output by the output terminal of the first selector 32 in the second peripheral circuit 3b can be transmitted to the selected first memory array 4t through the output terminal of the first selector 32 in the first peripheral circuit 3a without flowing through the first selector 32 in the first peripheral circuit 3a.

[0123] In this way, the connection between the second peripheral circuit 3b and each memory array 4 can be realized through the conductive vias 5, and the independent connection between each peripheral circuit 3b and the memory array 4 can be realized. Moreover, the second peripheral circuit 3b can share the same set of interconnection structures (including the word line interconnection vias, the bit line interconnection vias, the source line interconnection vias, and the like mentioned below) with the first peripheral circuit 3a, and thus a set of interconnection structures can be shared by the plurality of peripheral circuits 3, which can reduce the arrangement of the interconnection structures, facilitate the simplification of the structure of the memory 730, and reduce the cost of the memory 730.

[0124] In other embodiments, as shown in FIG. 11, the plurality of peripheral circuits 3 are respectively located on opposite sides of the plurality of memory arrays 4 along the thickness direction of the peripheral circuits 3. The number of the peripheral circuits 3 located on the opposite sides of the plurality of memory arrays 4 can be the same or different. For example, the orthographic projections of the plurality of peripheral circuits 3 on the reference plane coincide with each other. Further, the orthographic projections of the memory arrays 4 on the reference plane are located, for example, within the orthographic projection range of the peripheral circuits 3 on the reference plane.

[0125] In this way, the connection between each peripheral circuit 3 and the memory array 4 can be realized, which is conducive to improving the reliability and yield of the memory 730.

[0126] Continuing to refer to FIG. 11, the memory 730 further includes a plurality of interconnect vias 6, which can be in accordance with the number of memory arrays 4 and the number of functional structures in the memory arrays 4. Exemplarily, the interconnect vias 6 include word line interconnect vias, bit line interconnect vias, and source line interconnect vias, which will be described in detail below and thus will not be repeated here. The interconnect vias 6 connect the first memory array 4t and the first gate 32.

[0127] Exemplarily, as shown in FIG. 11, the plurality of peripheral circuits 3 includes a first peripheral circuit 3a and a second peripheral circuit 3b, which are located on opposite sides of the plurality of memory arrays 4. The interconnect vias 6 connecting the first gate 32 of the first peripheral circuit 3a and the first memory array 4t are connected to the interconnect vias 6 connecting the first gate 32 of the second peripheral circuit 3b and the first memory array 4t.

[0128] Alternatively, in FIG. 11, the interconnect vias 6 connecting the first gate 32 of the first peripheral circuit 3a and the first memory array 4t are located below the interconnect vias 6 connecting the first gate 32 of the second peripheral circuit 3b and the first memory array 4t, and the two form a continuous columnar structure as a whole, and the columnar structure extends in the thickness direction of the peripheral circuit 3. Alternatively, the interconnect vias 6 connecting the first gate 32 of the first peripheral circuit 3a and the first memory array 4t and the interconnect vias 6 connecting the first gate 32 of the second peripheral circuit 3b and the first memory array 4t can also be staggered, and then the two can be connected by an interconnection layer. In FIG. 11, in order to show the interconnection structure between the first peripheral circuit 3a, the second peripheral circuit 3b, and the first memory array 4t, the interconnect vias 6 are shown in the same figure.

[0129] Exemplarily, the material of the interconnect vias 6 includes a conductive material, which includes but is not limited to tungsten, aluminum, copper, cobalt, or any combination thereof. In this way, the interconnect vias 6 can achieve electrical connection between the first gate 32 and the first memory array 4t, and the signals in the first peripheral circuit 3a and / or the second peripheral circuit 3b can be transmitted to the corresponding first memory array 4t through the interconnect vias 6.

[0130] In this way, the interconnect vias connecting the first gate of the first peripheral circuit and the first memory array and the interconnect vias connecting the first gate 32 of the second peripheral circuit and the first memory array can share various types of contacts and various types of interconnection lines in the memory array, which is beneficial to simplify the structure of the memory array.

[0131] The type of the interconnection via 6 can be various, depending on the structure of the memory array 4. The type of the interconnection via 6 will be described below with reference to the accompanying drawings, and by way of example with respect to a first memory array 4t of the plurality of memory arrays 4.

[0132] In some embodiments, in combination with FIG. 7 and FIG. 8a, the first memory array 4t comprises a stack structure 41. With respect to the stack structure 41, reference can be made to the relevant description above, which will not be repeated here. Further, the first memory array 4t further comprises a word line contact 44 and a word line interconnection line 45, the word line contact 44 extending along the thickness direction of the peripheral circuit 3, and the word line interconnection line 45 extending along a direction perpendicular to the thickness direction of the peripheral circuit 3, such as the direction X shown in the accompanying drawings. Moreover, the word line contact 44 is connected to the gate layer 411 at one end of the common source structure 43, and the word line contact 44 is connected to one end of the word line interconnection line 45 at an end of the common source structure 43.

[0133] The number of the word line contact 44 and the word line interconnection line 45, for example, is plural. Each of the gate layers 411 in the stack structure 41 is connected to the word line contact 44, and each of the word line contacts 44 is connected to the word line interconnection line 45.

[0134] In this case, the interconnection via 6 comprises a word line interconnection via 61, the word line interconnection via 61 extending along the thickness direction of the peripheral circuit 3, and the word line interconnection via 61 connecting the first gate 32 and the word line interconnection line 45. For example, the number of the word line interconnection via 61 is plural, and the plurality of word line interconnection vias 61 and the plurality of word line interconnection lines 45 can be connected one-to-one. For example, one end of each of the word line interconnection vias 61 is connected to the first gate 32, and the other end of each of the word line interconnection vias 61 is connected to the corresponding word line interconnection line 45.

[0135] Optionally, in the case where the number of the peripheral circuit 3 is one or more, and each of the peripheral circuit 3 is located at one side of the plurality of memory arrays 4, the height (i.e. the dimension in the thickness direction of the peripheral circuit 3) of different word line interconnection vias 61 can be the same or different. In FIG. 10, the height of different word line interconnection vias 61 is different, and the height of each of the word line interconnection vias 61, for example, is equal to the minimum spacing between the word line interconnection line 45 and the peripheral circuit 3 connected by the word line interconnection via 61.

[0136] Optionally, when the number of peripheral circuits 3 is more than one, and the peripheral circuits 3 are respectively located on opposite sides of the plurality of memory arrays 4, as shown in FIG. 11, each word line interconnection via 61 is located between a first peripheral circuit 3a and a second peripheral circuit 3b, and the first peripheral circuit 3a and the second peripheral circuit 3b can be connected to the same word line interconnection line 45 through the word line interconnection via 61. Furthermore, the two word line interconnection vias 61 connected to the same word line interconnection line 45 are connected to each other.

[0137] For example, as shown in FIG. 11, at least one word line interconnection line 45 is connected to two word line interconnection vias 61 in an integrated structure, and at least one word line interconnection line 45 is connected to two word line interconnection vias 61 through an interconnection layer. FIG. 11 is for the purpose of showing the word line interconnection vias 61 connected to each word line interconnection line 45, and thus some word line interconnection lines 45 and word line interconnection vias 61 that are not electrically connected to each other cross each other, but this does not limit the arrangement of the word line interconnection lines 45 and the word line interconnection vias 61.

[0138] By arranging the word line interconnection vias 61 and connecting each word line interconnection via 61 to the corresponding first memory array 4t through the corresponding word line interconnection line 45, the word line contact 44, and the corresponding first memory array 4t, the driving signal can be transmitted to the selected gate layer 411 in the selected first memory array 4t independently, rather than being transmitted to the gate layer 411 with the same serial number in each memory array 4 synchronously. In this way, the selection and independent operation of at least one gate layer 411 in the first memory array 4t can be realized by the memory array controller 31.

[0139] Further, in some embodiments, in combination with FIG. 7 and FIG. 8b, the first memory array 4t further comprises a channel structure 42. For the channel structure 42, please refer to the relevant description above, which will not be repeated here. Further, the first memory array 4t further comprises a bit line contact 46 and a bit line interconnection line 47, the bit line contact 46 extends along the thickness direction of the peripheral circuit 3, and the bit line interconnection line 47 extends along a direction perpendicular to the thickness direction of the peripheral circuit 3, for example, the direction X shown in the drawings. Furthermore, the bit line contact 46 is connected to the channel structure 42 near one end of the common source structure 43, and the bit line contact 46 is connected to one end of the bit line interconnection line 47 away from the other end of the common source structure 43.

[0140] The number of the above-mentioned bit line contacts 46 and bit line interconnection lines 47 is, for example, more than one. Each channel structure 42 is connected to a bit line contact 46, and each bit line contact 46 is connected to a bit line interconnection line 47, for example, in combination with FIG. 7 and FIG. 8b, the bit line contacts 46 connected to at least two channel structures 42 arranged along the direction Y share one bit line interconnection line 47.

[0141] In this case, the interconnection conductive pillars 6 include bit line interconnection conductive pillars 62 extending in the thickness direction of the peripheral circuit 3, and the bit line interconnection conductive pillars 62 connect the first gate 32 and the bit line interconnection lines 47. For example, the number of the bit line interconnection conductive pillars 62 is plural, and the bit line interconnection conductive pillars 62 and the bit line interconnection lines 47 can be connected in one-to-one correspondence. For example, one end of each of the bit line interconnection conductive pillars 62 is connected to the first gate 32, and the other end of each of the bit line interconnection conductive pillars 62 is connected to the corresponding bit line interconnection line 47.

[0142] Here, in the case where the number of the peripheral circuits 3 is one or more, the bit line interconnection conductive pillars 62 and the peripheral circuit 3 and the like can be arranged in the same manner as the word line interconnection conductive pillars 61 and the peripheral circuit 3 and the like described above, and a detailed description thereof will not be repeated here.

[0143] By providing the bit line interconnection conductive pillars 62 and connecting each of the bit line interconnection conductive pillars 62 to the corresponding first memory array 4t via the corresponding bit line interconnection line 47, the bit line contact 46, and the corresponding first memory array 4t, the drive signal can be transmitted to the selected channel structure 42 in the selected first memory array 4t independently, rather than being transmitted to the channel structures 42 having the same serial number in each of the memory arrays 4 simultaneously. Thus, the memory array controller 31 can be used to select and independently operate at least one channel structure 42 in the first memory array 4t.

[0144] Further, in some embodiments, in combination with FIGS. 7 and 8b, the first memory array 4t further includes a common source structure 43. Regarding the common source structure 43, reference can be made to the relevant description above, and a detailed description thereof will not be repeated here. Further, the first memory array 4t further includes a source line contact 48 extending in the thickness direction of the peripheral circuit 3 and a source line interconnection line 49 extending in a direction perpendicular to the thickness direction of the peripheral circuit 3 (for example, the direction X shown in the drawings). One end of the source line contact 48 is connected to the common source structure 43, and the other end of the source line contact 48 away from the common source structure 43 is connected to one end of the source line interconnection line 49.

[0145] The number of the source line contact 48 and the source line interconnection line 49 is, for example, plural or one. In the case where a plurality of memory blocks in the first memory array 4t share the common source structure 43, the number of the source line contact 48 and the source line interconnection line 49 is, for example, one.

[0146] In this case, the interconnection conductive post 6 includes a source line interconnection conductive post 63 extending along the thickness direction of the peripheral circuit 3, and the source line interconnection conductive post 63 is connected to the first selector 32 and the source line interconnection line 49. For example, the number of the source line interconnection conductive post 63 can be one or multiple, which can be determined according to whether the multiple memory blocks in the first memory array 4t share the common source structure 43. For example, one end of each source line interconnection conductive post 63 is connected to the first selector 32, and the other end of each source line interconnection conductive post 63 is connected to the corresponding source line interconnection line 49.

[0147] Here, in the case that the number of the peripheral circuit 3 is one or multiple, the arrangement between the source line interconnection conductive post 63 and the peripheral circuit 3 and other structures can refer to the arrangement between the word line interconnection conductive post 61 and the peripheral circuit 3 and other structures, which will not be described herein.

[0148] By arranging the source line interconnection conductive post 63 and connecting each source line interconnection conductive post 63 to the corresponding first memory array 4t through the corresponding source line interconnection line 49 and source line contact 48, the driving signal can be transmitted to the selected common source structure 43 in the selected first memory array 4t independently, instead of being transmitted to the common source structure 43 with the same serial number in each memory array 4 synchronously. In this way, the selection and independent operation of the common source structure 43 in the first memory array 4t can be realized by the memory array controller 31.

[0149] In combination with FIG. 8a and FIG. 8b, the word line interconnection conductive post 61, the bit line interconnection conductive post 62 and the source line interconnection conductive post 63 are arranged staggered with the first memory array 4t. That is, the orthogonal projection of the word line interconnection conductive post 61, the bit line interconnection conductive post 62 and the source line interconnection conductive post 63 on the reference plane does not overlap with the orthogonal projection of the first memory array 4t on the reference plane.

[0150] In this way, in the process of manufacturing the word line interconnection conductive post 61, the bit line interconnection conductive post 62 and the source line interconnection conductive post 63, the damage to the memory array 4 can be avoided, and the yield of the memory 730 can be improved.

[0151] Some embodiments of the present application also provide a memory which can be applied to the above-mentioned storage system 700. Optionally, the memory can be the memory 710 in FIG. 2, FIG. 3 or FIG. 4. The application scenarios of the above-mentioned memory are not limited by the embodiments of the present application. FIG. 12a and FIG. 12b respectively show the structure of a memory provided by the embodiments of the present application. The memory array shown in FIG. 12a and FIG. 12b is, for example, a cross-sectional structure of the memory array described in FIG. 7, and the cross-sectional line of the cross-sectional structure is parallel to the direction X and parallel to the direction Z.

[0152] As shown in FIG. 12a and FIG. 12b, the memory 740 includes a plurality of peripheral circuits 3 and a plurality of storage arrays 4, and the plurality of peripheral circuits 3 and the plurality of storage arrays 4 are stacked along the thickness direction of the peripheral circuit 3.

[0153] Optionally, in the embodiment, the structure of the peripheral circuit 3 and the structure of the storage array 4 are the same as the structure of the peripheral circuit 3 and the structure of the storage array 4 in the memory 730 mentioned in any one of the above-mentioned embodiments, which will not be described here again.

[0154] In some examples, as shown in FIG. 12a and FIG. 12b, the plurality of peripheral circuits 3 includes adjacent first peripheral circuit 3a and second peripheral circuit 3b, and the plurality of storage arrays 4 is located between the first peripheral circuit 3a and the second peripheral circuit 3b. Among them, part of the plurality of storage arrays 4 is respectively connected with the first gate 32 of the first peripheral circuit 3a, and the other part of the plurality of storage arrays 4 is respectively connected with the first gate 32 of the second peripheral circuit 3b.

[0155] Optionally, the interconnection mode between the first peripheral circuit 3a and part of the plurality of storage arrays 4 and the interconnection mode between the second peripheral circuit 3b and the other part of the plurality of storage arrays 4 are the same. And the interconnection mode and the required interconnection structure are the same as the interconnection mode and the interconnection structure between the peripheral circuit 3 and the storage array 4 in the memory 730 mentioned in any one of the above-mentioned embodiments. Here will not be described again.

[0156] In some examples, the storage array controller 31 of the first peripheral circuit 3a is configured to control the first gate 32 of the first peripheral circuit 3a to select a first storage array 4t from part of the plurality of storage arrays 4 to output a driving signal to the selected first storage array 4t. The storage array controller 31 of the second peripheral circuit 3b is configured to control the first gate 32 of the second peripheral circuit 3b to select a first storage array 4t from the other part of the plurality of storage arrays 4 to output a driving signal to the selected first storage array 4t.

[0157] That is, the first peripheral circuit 3a can select and independently operate part of the plurality of storage arrays 4 connected thereto, and the second peripheral circuit 3b can select and independently operate the other part of the plurality of storage arrays 4 connected thereto.

[0158] In this way, the number of vertically stacked storage units can be greatly increased by using the plurality of storage arrays 4, and the storage density and storage capacity of the memory 740 can be greatly increased while the normal operation of the memory 740 is realized. In addition, the latency of the memory 740 and the storage system 700 to which it is applied can be reduced.

[0159] In the storage system 700 provided by the embodiments of the present application, the plurality of memories includes a first memory. The number of the first memory can be one or more. The first memory can be the memory 730 described in any of the above embodiments. Of course, the first memory can also be the memory 740 described in any of the above embodiments.

[0160] Optionally, in the case where the first memory included in the plurality of memories in the storage system 700 is the memory 730, the plurality of memories can further include a second memory. The number of the second memory can be one or more. The second memory can be, for example, the memory 740 described in any of the above embodiments.

[0161] Some embodiments of the present application further provide an operation method of a memory. The operation method can be applied to the memory 730 described in any of the above embodiments. Of course, the operation method can also be applied to the memory 740 described in any of the above embodiments. The embodiments of the present application take the operation method applied to the memory 730 as an example for illustrative description. For the peripheral circuit 3 and the memory array 4 included in the memory 730 to which the operation method is applied, refer to the related description in the above text, which will not be described herein again.

[0162] The operation method of the memory is schematically described below in combination with FIG. 13. It should be understood that the steps shown in FIG. 13 are not exclusive, and other steps can also be performed before, after or between any of the steps shown in FIG. 13. In addition, some of the steps can be performed simultaneously, or can be performed in an order different from that shown in FIG. 13.

[0163] The operation method of the memory is schematically described below in combination with FIG. 8a-FIG. 11. As shown in FIG. 13, the operation method includes S100-S300.

[0164] S100, the peripheral circuit 3 receives a data address.

[0165] The data address is, for example, a digital signal. The data address includes a memory array number of a first memory array 4t in the plurality of memory arrays 4. Further, the data address can further include, for example, a memory surface number of one or more memory surfaces in the first memory array 4t, and a memory block number of one or more memory blocks in the one or more memory surfaces. Further, the data address can further include a memory page number of one or more memory pages in the one or more memory blocks.

[0166] Exemplarily, in the process that the peripheral circuit 3 receives the data address, the peripheral circuit also receives a command. The type of the command includes multiple types, for example, the command includes at least one of a data read command, a data write command, and a data erase command. Alternatively, the command received by the peripheral circuit 3 can only include a data read command, or can include both a data read command and a data write command.

[0167] S200, the storage array controller 31 controls the first selector 32 to select the first storage array 4t according to the data address.

[0168] Exemplarily, the storage array controller 31 can generate a selection signal based on the data address, the selection signal including a storage array number of at least one storage array 4 (i.e., the first storage array 4t). For example, the selection signal is a digital signal.

[0169] The first selector 32 includes multiple selection transistors. Of course, the first selector 32 can also include other structures. Here, “selection” refers to, for example, the first selector 32 can turn on a path between the selected first storage array 4t and the peripheral circuit 3 (e.g., a driver in the peripheral circuit 3).

[0170] S300, the first selector 32 outputs a driving signal to the selected first storage array 4t.

[0171] Exemplarily, the driving signal corresponds to the command received by the peripheral circuit 3. At this time, the selected first storage array 4t can be independently operated (e.g., data write, read, or erase).

[0172] Therefore, the operation method of the memory provided by the embodiments of the present application can realize independent selection and operation of multiple storage arrays 4 in the memory by adding the storage array number of the storage array 4 in the data address, cooperating with the storage array controller 31, realizing separate control management and driving operation of each storage array 4, and realizing normal operation of the memory. In addition, this can shorten the transmission path between the driving signal and the selected first storage array 4t, reduce the time delay of the memory and the storage system 700 to which the memory is applied.

[0173] In some embodiments, as shown in FIG. 9, the memory 730 includes a second selector 331, and the second selector 331 can be arranged as described above, which will not be described here.

[0174] Before S300, i.e. before the first gate 32 outputs the driving signal to the selected first storage array 4t, the operation method further comprises: the second gate 331 selects at least one storage page in the selected first storage array 4t and receives the driving signal, and outputs the driving signal to the selected at least one storage page.

[0175] For example, the second gate 331 can selectively communicate the first gate 32 and the at least one storage page in the selected first storage array 4t. The driving signal output by the first gate 32 is first transmitted to the second gate 331, and then selectively output by the second gate 331 to the selected at least one storage page in the selected first storage array 4t.

[0176] By selecting the first storage array 4t before the driving signal is output to the selected at least one storage page, the driving signal can be directly transmitted to the selected at least one storage page during the operation of the selected at least one storage page, without passing through the remaining storage arrays 4, and without the need to synchronously perform the same operation on the remaining storage arrays 4, thereby effectively reducing the latency of the memory and the storage system 700 to which it is applied.

[0177] In some embodiments, as shown in FIGS. 10 and 11, the number of first storage arrays 4t is multiple, and the number of peripheral circuits 3 is multiple, and the multiple peripheral circuits 3 include a first peripheral circuit 3a and a second peripheral circuit 3b. For the first peripheral circuit 3a and the second peripheral circuit 3b, please refer to the relevant description above, which will not be repeated here.

[0178] In the above S200, the storage array controller 31 controls the first gate 32 to select the first storage array 4t according to the data address, including: the storage array controller 31 of the first peripheral circuit 3a controls the first gate 32 of the first peripheral circuit 3a to select a part of the first storage arrays 4t from the multiple first storage arrays 4t, and the storage array controller 31 of the second peripheral circuit 3b controls the first gate 32 of the second peripheral circuit 3b to select another part of the first storage arrays 4t from the multiple first storage arrays 4t.

[0179] For example, the storage array controllers 31 of the multiple peripheral circuits 3 are provided with a coordination mechanism. At this time, the multiple peripheral circuits 3 can cooperatively control, manage and drive the above-mentioned multiple storage arrays 4, for example, each peripheral circuit 3 can control, manage and drive different storage arrays 4, thereby realizing efficient operation of the multiple storage arrays 4 and improving the performance of the memory 730.

[0180] For example, the first peripheral circuit 3a and the second peripheral circuit 3b can perform cooperative processing and operate on the selected first storage array 4t, which can be the same or different. Alternatively, the first peripheral circuit 3a and the second peripheral circuit 3b can perform cooperative processing and only one of the first peripheral circuit 3a and the second peripheral circuit 3b operates on the selected first storage array 4t.

[0181] In this way, on the one hand, the multiple types of commands can be supported and executed synchronously in the case that the multiple types of commands are received by the peripheral circuit 3; on the other hand, the better command execution path can be selected preferentially according to actual conditions; and on the other hand, the operation can be performed by the other peripheral circuit 3 in the case that a part of the peripheral circuit 3 fails, so as to guarantee the availability of the memory 730.

[0182] Those skilled in the art should be aware that in the one or more examples described above, the functions described in the embodiments of the present application can be implemented in hardware, software, firmware or any combination thereof. When implemented in software, the functions can be stored in a computer readable medium or transmitted as one or more instructions or codes on a computer readable medium. The computer readable medium includes computer storage medium and communication medium, wherein the communication medium includes any medium that facilitates the transfer of computer programs from one place to another. The storage medium can be any available medium accessible by a general or special purpose computer.

[0183] Based on this, the embodiments of the present application further provide a computer readable storage medium, which stores computer executable instructions, and when the computer executable instructions are executed on a device, the operation method of any one of the above examples can be implemented.

[0184] The embodiments of the present application further provide a computer program product, which, when running on a computer, causes the computer to execute the operation method of any one of the above examples.

[0185] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory, comprising: The memory comprises: a plurality of peripheral circuits, each of which comprises a memory array controller and a first gate; a plurality of memory arrays stacked along a thickness direction of the peripheral circuit; each of the plurality of memory arrays is connected with the first gate; the plurality of memory arrays comprises a first memory array; The memory array controller is configured to control the first gate to select the first memory array, so as to output a driving signal to the selected first memory array.

2. The memory of claim 1, wherein, The number of the peripheral circuits is plural, and the plurality of peripheral circuits are located on the same side of the plurality of memory arrays.

3. The memory of claim 2, wherein, The two adjacent peripheral circuits are a first peripheral circuit and a second peripheral circuit respectively; the first peripheral circuit is located between the second peripheral circuit and the plurality of memory arrays; The memory further comprises a conductive channel, the conductive channel penetrates through the first peripheral circuit, and connects the output end of the first gate in the first peripheral circuit and the second peripheral circuit.

4. The memory of claim 1, wherein, The number of the peripheral circuits is plural, and the plurality of peripheral circuits are located on opposite sides of the plurality of memory arrays.

5. The memory of claim 4, wherein, The plurality of peripheral circuits comprises a first peripheral circuit and a second peripheral circuit located on opposite sides of the plurality of memory arrays respectively; The memory further comprises an interconnection conductive post, the interconnection conductive post connects the first memory array and the first gate; The interconnection conductive post connecting the first gate of the first peripheral circuit and the first memory array is connected with the interconnection conductive post connecting the first gate of the second peripheral circuit and the first memory array.

6. The memory of any one of claims 2-5, wherein, The number of the first memory arrays is plural, and the plurality of peripheral circuits comprises a first peripheral circuit and a second peripheral circuit; The memory array controller of the first peripheral circuit is configured to control the first gate of the first peripheral circuit to select a part of the plurality of first memory arrays, so as to output a driving signal to the selected part of the first memory arrays; The memory array controller of the second peripheral circuit is configured to control the first gate of the second peripheral circuit to select another part of the plurality of first memory arrays, so as to output a driving signal to the selected another part of the first memory arrays.

7. The memory of any one of claims 1-6, wherein, The first memory array comprises: a laminated structure comprising a plurality of gate layers and a plurality of gate dielectric layers alternately stacked along a thickness direction of the peripheral circuit; a word line contact extending along the thickness direction of the peripheral circuit; the word line contact is connected with the gate layer; a word line interconnection line extending along a direction perpendicular to the thickness direction of the peripheral circuit; the word line interconnection line is connected with the word line contact; The memory further comprises a word line interconnection conductive post extending along the thickness direction of the peripheral circuit; the word line interconnection conductive post connects the first gate and the word line interconnection line.

8. The memory of claim 7, wherein, The first memory array further comprises: a channel structure penetrating through the laminated structure; a bit line contact extending along the thickness direction of the peripheral circuit; the bit line contact is connected with the channel structure; Bit line interconnection lines extending in a direction perpendicular to a thickness direction of the peripheral circuit; the bit line interconnection lines are connected with the bit line contacts; The memory further comprises: bit line interconnection vias extending in the thickness direction of the peripheral circuit; the bit line interconnection vias connect the first pass gate and the bit line interconnection lines.

9. The memory of claim 7 or 8, wherein, The first memory array further comprises: A common source structure located on one side of the stack structure in the thickness direction of the peripheral circuit; Source line contacts extending in the thickness direction of the peripheral circuit; the source line contacts are connected with the common source structure; Source line interconnection lines extending in a direction perpendicular to the thickness direction of the peripheral circuit; the source line interconnection lines are connected with the source line contacts; The memory further comprises: source line interconnection vias extending in the thickness direction of the peripheral circuit; the source line interconnection vias connect the first pass gate and the source line interconnection lines.

10. The memory of any one of claims 7-9, wherein, The word line interconnection vias, the bit line interconnection vias and the source line interconnection vias are arranged away from the first memory array.

11. The memory of any one of claims 1-10, wherein, The memory further comprises a second pass gate connected between the first pass gate and the plurality of memory arrays; The second pass gate is configured to select at least one memory page in the selected first memory array and output the driving signal to the selected at least one memory page.

12. A method of operating a memory, comprising: The memory comprises a peripheral circuit and a plurality of memory arrays; the peripheral circuit comprises a memory array controller and a first pass gate; the memory array controller is connected with the first pass gate; the plurality of memory arrays are arranged in a stack structure in a thickness direction of the peripheral circuit; the plurality of memory arrays are respectively connected with the first pass gate; The plurality of memory arrays comprises a first memory array; The operation method comprises: The peripheral circuit receives a data address; The memory array controller controls the first pass gate to select the first memory array according to the data address; The first pass gate outputs a driving signal to the selected first memory array.

13. The method of operation of claim 12, wherein, The memory further comprises a second pass gate connected between the first pass gate and the plurality of memory arrays; Before the first pass gate outputs the driving signal to the selected first memory array, the operation method further comprises: The second pass gate selects at least one memory page in the selected first memory array and receives the driving signal, and outputs the driving signal to the selected at least one memory page.

14. The method of operating according to claim 12 or 13, characterized in that, The number of the first memory arrays is a plurality, and the number of the peripheral circuits is a plurality; the plurality of peripheral circuits comprises a first peripheral circuit and a second peripheral circuit; The memory array controller controls the first pass gate to select the first memory array according to the data address, which comprises: The memory array controller of the first peripheral circuit controls the first pass gate of the first peripheral circuit to select a part of the first memory arrays in the plurality of first memory arrays; The memory array controller of the first peripheral circuit controls the first pass gate of the first peripheral circuit to select a part of the first memory arrays in the plurality of first memory arrays; The memory array controller of the second peripheral circuit controls the first gate of the second peripheral circuit to select another part of the first memory arrays in the plurality of first memory arrays.

15. A storage system, characterized by The memory system comprises: The plurality of memories comprises a first memory; the first memory comprises the memory as claimed in any one of claims 1-11; A memory controller is connected with the plurality of memories.

16. The storage system of claim 15, wherein, The plurality of memories further comprises a second memory; the second memory comprises: The plurality of peripheral circuits are stacked along the thickness direction of the peripheral circuits; the peripheral circuits comprise memory array controllers and first gates; the memory array controllers are connected with the first gates; the plurality of peripheral circuits comprises adjacent first peripheral circuits and second peripheral circuits; The plurality of memory arrays are stacked along the thickness direction of the peripheral circuits; the plurality of memory arrays are located between the first peripheral circuits and the second peripheral circuits; a part of the plurality of memory arrays are respectively connected with the first gates of the first peripheral circuits, and another part of the plurality of memory arrays are respectively connected with the first gates of the second peripheral circuits; The memory array controller of the first peripheral circuit is configured to control the first gate of the first peripheral circuit to select a first memory array in the part of the memory arrays, so as to output a driving signal to the selected first memory array; The memory array controller of the second peripheral circuit is configured to control the first gate of the second peripheral circuit to select a first memory array in the another part of the memory arrays, so as to output a driving signal to the selected first memory array.

17. An electronic device, comprising: The electronic device comprises: The memory system as claimed in claim 15 or 16; A circuit board is connected with the memory system.

18. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions; when the computer executable instructions are executed, the operation method as claimed in any one of claims 12-14 can be implemented.

19. A computer program product, characterised in that, When the computer program product is running on the computer, the computer is caused to execute the operation method as claimed in any one of claims 12-14.

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