Test substrate, display panel, manufacturing method and display apparatus

Abstract

A display panel, comprising a pixel circuit and a test circuit. The pixel circuit comprises a drive transistor, a data writing sub-circuit and a compensation control sub-circuit; the data writing sub-circuit is electrically connected to a data signal line, a first scan signal end and a first node, and is configured to transmit to the first node a data signal from the data signal line under the control of a first scan signal from the first scan signal end; a control electrode of the compensation control sub-circuit is electrically connected to a second scan signal end, the first node and a second node, and is configured to electrically connect the first node to the second node under the control of a second scan signal from the second scan signal end; the pixel circuit is configured to respectively perform threshold voltage compensation and data signal writing on a control electrode of the drive transistor in different periods of time of the same display cycle; the test circuit is electrically connected to a test signal end and is electrically insulated from at least one of the pixel circuit and the data signal line.

Description

Test substrate, display panel and preparation method, and display device

[0001] This application claims priority to Chinese Patent Application No. 202410635872.9, filed on May 21, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular to a test substrate, a display panel and a preparation method, and a display device. BACKGROUND

[0003] With the continuous development of display technology, display panels have been widely applied, and people's requirements for display panels are also getting higher and higher; among them, large size, high pixel density (Pixels Per Inch; PPI) and high refresh rate are important development directions of display panels. When the display panel is working, the threshold voltage compensation time of the driving transistor of the pixel circuit is getting shorter and shorter, and how to improve the threshold voltage compensation time of the driving transistor of the pixel circuit is an important technical problem faced in the development process of the current display panel. SUMMARY

[0004] In one aspect, a test substrate is provided. The test substrate includes a pixel circuit, a first signal line, and a test circuit. The pixel circuit includes a driving transistor, a data writing sub-circuit, and a compensation control sub-circuit. The control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, the second electrode is electrically connected to a third node, one of the second node and the third node is configured to be coupled to a light emitting element, and the other is configured to be coupled to a power voltage signal terminal. The data writing sub-circuit is electrically connected to a data signal line, a first scan signal terminal, and the first node, and is configured to transmit a data signal from the data signal line to the first node under the control of a first scan signal from the first scan signal terminal. The compensation control sub-circuit is electrically connected to a second scan signal terminal, the first node, and the second node, and is configured to electrically connect the first node and the second node under the control of a second scan signal from the second scan signal terminal. The pixel circuit is configured to perform threshold voltage compensation and data signal writing on the control electrode of the driving transistor at different time periods of the same frame period, respectively. The first voltage signal is electrically connected to the pixel circuit. The test circuit is electrically connected to a test signal terminal, the first signal line, and the third node, and the test circuit is configured to electrically connect the first signal line and the third node under the control of a test signal from the test signal terminal.

[0005] In some embodiments, the pixel circuit further comprises a first function sub-circuit. The first function sub-circuit is electrically connected with a first function control signal terminal, a second signal line and the third node, and is configured to electrically connect the second signal line with the third node under the control of a first function control signal from the first function control signal terminal. The test substrate comprises a plurality of the pixel circuits, and the second signal line is configured to be electrically connected with at least one column of the pixel circuits. The test substrate comprises at least one test circuit, the test circuit is electrically connected with the second signal line, and is electrically connected with the third node of the pixel circuit through the second signal line.

[0006] In some embodiments, one of the second signal lines is configured to be electrically connected with one column of the pixel circuits. The test substrate comprises a plurality of the test circuits, and one of the test circuits is electrically connected with one of the second signal lines.

[0007] In some embodiments, the second signal line is configured to be electrically connected with all of the pixel circuits. The test substrate comprises one test circuit, and the test circuit is electrically connected with the second signal line.

[0008] In some embodiments, the pixel circuit further comprises a first function sub-circuit. The first function sub-circuit is electrically connected with a first function control signal terminal, a second signal line and the third node, and is configured to electrically connect the second signal line with the third node under the control of a first function control signal from the first function control signal terminal. The test substrate comprises a plurality of the pixel circuits and a plurality of the test circuits, and one of the test circuits is directly electrically connected with the third node of one of the pixel circuits.

[0009] In some embodiments, the first function sub-circuit comprises a light-emitting control sub-circuit and a first initialization sub-circuit. The light-emitting control sub-circuit is electrically connected with a first light-emitting control signal terminal, a first voltage signal line and the third node, and is configured to electrically connect the first voltage signal line with the third node under the control of a light-emitting control signal from the first light-emitting control signal terminal. The first initialization sub-circuit is electrically connected with a third scan signal terminal, a second voltage signal line and the third node, and the first initialization sub-circuit is configured to electrically connect the second voltage signal line with the third node under the control of a third scan signal from the third scan signal terminal. The second signal line comprises the first voltage signal line and the second voltage signal line.

[0010] In some embodiments, the test circuit comprises a test transistor, a control electrode of the test transistor is electrically connected with the test signal terminal, a first electrode is electrically connected with the first signal line, and a second electrode is electrically connected with the third node.

[0011] In some embodiments, the data writing sub-circuit comprises a second transistor, a third transistor and a first capacitor; a control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode is electrically connected with the data signal line, and a second electrode is electrically connected with a fourth node; one plate of the first capacitor is electrically connected with the first node, and the other plate is electrically connected with the fourth node.

[0012] The pixel circuit further comprises a second initialization sub-circuit, a second light emitting control sub-circuit, a third initialization sub-circuit and a pull-up sub-circuit. The second initialization sub-circuit is electrically connected with a fourth scan signal terminal, a third voltage signal line and the first node, and is configured to transmit a third voltage signal from the third voltage signal line to the first node under the control of a fourth scan signal from the fourth scan signal terminal. The second light emitting control sub-circuit is electrically connected with a second light emitting control signal terminal, the second node and a fifth node, and is configured to electrically connect the second node with the fifth node under the control of a second light emitting control signal from the second light emitting control signal terminal; the fifth node is configured to be electrically connected with a light emitting element. The third initialization sub-circuit is electrically connected with a fifth scan signal terminal, a fourth voltage signal line and the fifth node, and is configured to electrically connect the fifth node with the fourth voltage signal line under the control of a fifth scan signal from the fifth scan signal terminal. The pull-up sub-circuit is electrically connected with a sixth scan signal terminal, a fifth voltage signal line and the fourth node, and is configured to electrically connect the fifth voltage signal line with the fourth node under the control of a sixth scan signal from the sixth scan signal terminal. The first signal line comprises one of the data signal line, the third voltage signal line and the fourth voltage signal line.

[0013] In another aspect, a display panel is provided. The display panel includes a pixel circuit, a first signal line, and a test circuit. The pixel circuit includes a driving transistor, a data writing sub-circuit, and a compensation control sub-circuit. The control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, the second electrode is electrically connected to a third node, one of the second node and the third node is configured to be coupled to a light emitting element, and the other is configured to be coupled to a power voltage signal terminal. The data writing sub-circuit is electrically connected to a data signal line, a first scan signal terminal, and the first node, and is configured to transmit a data signal from the data signal line to the first node under the control of a first scan signal from the first scan signal terminal. The compensation control sub-circuit is electrically connected to a second scan signal terminal, the first node, and the second node, and is configured to electrically connect the first node and the second node under the control of a second scan signal from the second scan signal terminal. The pixel circuit is configured to perform threshold voltage compensation and data signal writing on the control electrode of the driving transistor at different time periods of the same display period, respectively. The first voltage signal is electrically connected to the pixel circuit. The test circuit is electrically connected to a test signal terminal, and the test circuit is electrically insulated from at least one of the pixel circuit and the first signal line.

[0014] In some embodiments, the test circuit is electrically connected to the first signal line and electrically insulated from the pixel circuit.

[0015] In some embodiments, the test circuit includes a test transistor. The test transistor includes a semiconductor pattern, a gate pattern, a first connection pattern, and a second connection pattern. The semiconductor pattern includes a channel region and first and second electrode regions located on both sides of the channel region, respectively. The gate pattern is disposed on one side of the semiconductor pattern, and the gate pattern is electrically connected to the test signal terminal. The first connection pattern is disposed on the side of the gate pattern away from the semiconductor pattern, and the first connection pattern is electrically connected to the data signal line and the first electrode region, respectively. The second connection pattern is the same material and disposed in the same layer as the first connection pattern, and the second connection pattern includes a first sub-pattern and a second sub-pattern separated from each other, the first sub-pattern is electrically connected to the second electrode region, and the second sub-pattern is electrically connected to the pixel circuit.

[0016] In some embodiments, the display panel further comprises a substrate and a first insulating layer. The substrate is located on a side of the semiconductor pattern away from the gate pattern. The first insulating layer is arranged on a side of the first connection pattern and the second connection pattern away from the substrate. The first connection pattern and the second connection pattern have a first gap therebetween, and the first sub-pattern and the second sub-pattern have a second gap therebetween. The first insulating layer fills the first gap, and a projection of the first insulating layer on the substrate does not overlap with a projection of the second gap on the substrate.

[0017] In some embodiments, the display panel further comprises a second insulating layer. The second insulating layer is arranged on a side of the first insulating layer away from the substrate. The second insulating layer is in contact with neither the first connection pattern nor the second connection pattern. The second insulating layer fills the second gap and covers the side walls of the first sub-pattern and the second sub-pattern that are close to each other.

[0018] In some embodiments, the pixel circuit further comprises a first functional sub-circuit electrically connected to a first functional control signal terminal, a second signal line, and the third node. The first functional sub-circuit is configured to electrically connect the second signal line and the third node under the control of a first functional control signal from the first functional control signal terminal. The display panel comprises a plurality of pixel circuits, and the second signal line is electrically connected to at least one column of pixel circuits. The display panel comprises at least one test circuit, the second sub-pattern is electrically connected to the second signal line, and is electrically connected to the third node of the pixel circuit through the second signal line.

[0019] In some embodiments, one of the second signal lines is electrically connected to one column of pixel circuits. The display panel comprises a plurality of test circuits, and the second sub-pattern of one of the test transistors is electrically connected to one of the second signal lines.

[0020] In some embodiments, the second signal line is electrically connected to all the pixel circuits. The display panel comprises one test circuit, and the second sub-pattern is electrically connected to the second signal line.

[0021] In some embodiments, the pixel circuit further comprises a first functional sub-circuit electrically connected to a first functional control signal terminal, a second signal line, and the third node. The first functional sub-circuit is configured to electrically connect the second signal line and the third node under the control of a first functional control signal from the first functional control signal terminal. The display panel comprises a plurality of pixel circuits and a plurality of test circuits, and the second sub-pattern of one of the test transistors is directly electrically connected to the third node of one of the pixel circuits.

[0022] In some embodiments, the first functional sub-circuit includes a light-emitting control sub-circuit and a first initialization sub-circuit. The light-emitting control sub-circuit is electrically connected with a first light-emitting control signal terminal, a first voltage signal line, and the third node, and is configured to electrically connect the first voltage signal line with the third node under the control of a light-emitting control signal from the first light-emitting control signal terminal; the first initialization sub-circuit is electrically connected with a third scan signal terminal, a second voltage signal line, and the third node, and the first initialization sub-circuit is configured to electrically connect the second voltage signal line with the third node under the control of a third scan signal from the third scan signal terminal. The second signal line includes the first voltage signal line and the second voltage signal line.

[0023] In some embodiments, the data writing sub-circuit includes a second transistor, a third transistor, and a first capacitor; the control electrode of the second transistor is electrically connected with the first scan signal terminal, the first electrode is electrically connected with the data signal line, and the second electrode is electrically connected with a fourth node; one plate of the first capacitor is electrically connected with the first node, and the other plate is electrically connected with the fourth node.

[0024] The pixel circuit further includes a second initialization sub-circuit, a second light-emitting control sub-circuit, a third initialization sub-circuit, and a pull-up sub-circuit. The second initialization sub-circuit is electrically connected with a fourth scan signal terminal, a third voltage signal line, and the first node, and is configured to transmit a third voltage signal from the third voltage signal line to the first node under the control of a fourth scan signal from the fourth scan signal terminal. The second light-emitting control sub-circuit is electrically connected with a second light-emitting control signal terminal, the second node, and a fifth node, and is configured to electrically connect the second node with the fifth node under the control of a second light-emitting control signal from the second light-emitting control signal terminal; the fifth node is configured to be electrically connected with a light-emitting element. The third initialization sub-circuit is electrically connected with a fifth scan signal terminal, a fourth voltage signal line, and the fifth node, and is configured to electrically connect the fifth node with the fourth voltage signal line under the control of a fifth scan signal from the fifth scan signal terminal. The pull-up sub-circuit is electrically connected with a sixth scan signal terminal, a fifth voltage signal line, and the fourth node, and is configured to electrically connect the fifth voltage signal line with the fourth node under the control of a sixth scan signal from the sixth scan signal terminal. The first voltage signal line includes one of the data signal line, the third voltage signal line, and the fourth voltage signal line.

[0025] In another aspect, a method for manufacturing a display panel is provided. The method includes manufacturing a test substrate, the test substrate including any of the test substrates described above, the test substrate including a driving transistor. It is determined whether the driving transistor of the test substrate meets a preset condition. If the driving transistor of the test substrate meets the preset condition, a connection between a test circuit of the test substrate and a pixel circuit and / or a data signal line is disconnected, and manufacturing a display panel is continued.

[0026] In some embodiments, the manufacturing the test substrate includes forming a plurality of test transistors on a substrate, and forming a first insulating layer on a side of the plurality of test transistors away from the substrate. The test transistor includes a semiconductor pattern, a gate pattern, a first connection pattern, and an initial second connection pattern. The semiconductor pattern includes a channel region and first and second electrode regions respectively located on two sides of the channel region. The gate pattern is electrically connected to a test signal terminal. The first connection pattern is electrically connected to a data signal line and the first electrode region respectively. The initial second connection pattern is of the same material as the first connection pattern and is disposed in the same layer as the first connection pattern. The initial second connection pattern is electrically connected to the second electrode region and the pixel circuit respectively. A first gap is formed between the first connection pattern and the initial second connection pattern. The first insulating layer fills the first gap, and the first insulating layer exposes a first region of the initial second connection pattern.

[0027] In some embodiments, the disconnecting the connection between the test circuit of the test substrate and the pixel circuit includes, using the first insulating layer as a mask, removing the first region of the initial second connection pattern, forming a second connection pattern, and forming a second gap in the first region. The second connection pattern includes a first sub-pattern and a second sub-pattern separated from each other. The first sub-pattern is electrically connected to the second electrode region, and the second sub-pattern is electrically connected to the pixel circuit.

[0028] In another aspect, a display device is provided. The display device includes the display panel described in any of the embodiments above. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some of the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0030] FIG. 1 is a schematic diagram of a display device according to some embodiments;

[0031] FIG. 2 is a constituent structural diagram of a display device according to some embodiments;

[0032] FIG. 3 is a structural block diagram of a pixel circuit of a test substrate according to some embodiments;

[0033] FIG. 4 is an equivalent circuit diagram of a pixel circuit of a test substrate according to some embodiments;

[0034] FIG. 5 is a structural block diagram of a display panel according to some embodiments;

[0035] FIG. 6 is a structural block diagram of a test substrate according to some embodiments;

[0036] FIG. 7 is another structural block diagram of a test substrate according to some embodiments;

[0037] FIG. 8 is an equivalent circuit diagram of a test substrate according to some embodiments;

[0038] FIG. 9 is a control timing diagram of detecting a test substrate according to some embodiments;

[0039] FIG. 10 is yet another structural block diagram of a test substrate according to some embodiments;

[0040] FIG. 11 is yet another structural block diagram of a test substrate according to some embodiments;

[0041] FIG. 12 is yet another structural block diagram of a test substrate according to some embodiments;

[0042] FIG. 13 is a structural block diagram of a first functional sub-circuit according to some embodiments;

[0043] FIG. 14A is another equivalent circuit diagram of a test substrate according to some embodiments;

[0044] FIG. 14B is yet another equivalent circuit diagram of a test substrate according to some embodiments;

[0045] FIG. 15 is another control timing diagram of detecting a test substrate according to some embodiments;

[0046] FIG. 16 is another structural block diagram of a display panel according to some embodiments;

[0047] FIG. 17 is yet another structural block diagram of a display panel according to some embodiments;

[0048] FIG. 18 is an equivalent circuit diagram of a display panel according to some embodiments;

[0049] FIG. 19 is a cross-sectional structural diagram of a display panel according to some embodiments;

[0050] FIG. 20 is a flow chart of a method for manufacturing a display panel according to some embodiments;

[0051] FIG. 21 is a cross-sectional structure diagram of a display panel according to some embodiments;

[0052] FIGS. 22-24 are flow charts of manufacturing steps of a display panel according to some embodiments. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0054] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, and the like, are used in an open, inclusive sense, i.e., “including, but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to indicate that the particular feature, structure, material, or characteristic following the term is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily indicate a same embodiment or example. In addition, the particular features, structures, materials, or characteristics described can be included in any suitable way in one or more embodiments or examples.

[0055] Hereinafter, the terms “first” and “second” are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of “a plurality of” is two or more, unless otherwise specified.

[0056] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The terms "coupled" and "connected" are not necessarily limited to a direct mechanical or electrical connection, but can include an indirect connection.

[0057] "A, B, and C at least one of" is synonymous with "at least one of A, B, or C," and includes the following combinations: only A, only B, only C, A and B, A and C, B and C, and A and B and C.

[0058] "A and / or B" includes the following three combinations: A alone, B alone, and A and B together.

[0059] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0060] Additionally, the use of "based on" means open and inclusive language that does not exclude additional conditions or values not specifically recited.

[0061] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0062] As used herein, "parallel," "perpendicular," and "equal" include the recited condition and conditions that approximate the recited condition, within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0063] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0064] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have jagged edges. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of an embodiment.

[0065] The transistor employed in the pixel circuit provided by the embodiments of the present disclosure can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics, wherein the transistor in the embodiments of the present disclosure is described by taking a thin film transistor as an example. The thin film transistor can be a P-type transistor or an N-type transistor, wherein the P-type transistor is turned on under a low level and is turned off under a high level, and the N-type transistor is turned on under a high level and is turned off under a low level. In the embodiments of the present disclosure, the thin film transistor included in the pixel circuit is described by taking a P-type transistor as an example. The "effective level" is a level signal capable of turning on the corresponding thin film transistor.

[0066] The control electrode of each thin film transistor employed in the pixel circuit is a gate electrode of the thin film transistor, the first electrode is one of a source electrode and a drain electrode of the thin film transistor, and the second electrode is the other of the source electrode and the drain electrode of the thin film transistor. Since the source electrode and the drain electrode of the thin film transistor can be symmetrical in structure, the source electrode and the drain electrode of the thin film transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be indistinguishable in structure. For example, the first electrode of the thin film transistor is the source electrode, and the second electrode of the thin film transistor is the drain electrode.

[0067] Each circuit node in the pixel circuit, such as a first node, a second node, and the like, is not an actually existing component, but represents a convergence point of relevant electrical connections in a circuit diagram, that is, the nodes are equivalent nodes formed by the convergence point of the relevant electrical connections in the circuit diagram.

[0068] Referring to FIG. 1, embodiments of the disclosure provide a display device 1000, which is a product having an image display function. Exemplarily, the display device 1000 can be any device that displays whether moving (e.g., a video) or fixed (e.g., a still image) and whether text or an image.

[0069] The display device 1000 described above can be applied to various electronic devices. For example, the display device 1000 can be a mobile phone, a wireless device, a personal data assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., a speedometer display, etc.), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a packaging and aesthetic structure (e.g., a display of an image for a piece of jewelry), etc. For example, as shown in FIG. 1, the display device 1000 can be a mobile phone.

[0070] From the light-emitting type of the display device 1000, the display device 1000 described above can be an organic light-emitting diode display device (OLED), a quantum dot light emitting diode display device (QLED), or a micro light emitting diode (MLED) display device, etc. From the form of the display device 1000, the display device 1000 described above can be a flat display device, a curved display device, or a foldable display device, etc. From the shape of the display device 1000, the display device 1000 described above can be rectangular, circular, or other shapes. In the following, some embodiments of the disclosure are schematically described by taking the display device as an organic light-emitting diode display device which is rectangular and flat, but the embodiments of the disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0071] In some embodiments, referring to FIG. 2, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may, for example, include a timing controller (TCON), a power management chip DC / DC, and an adjustable resistance voltage dividing circuit (generating Vcom) and other driving circuits, and the driving circuit board 1200 can also include other circuit structures, which are not listed one by one here. The driving circuit board 1200 is electrically connected to the display panel 1100, used to transmit control signals to the display panel 1100, and then drive the display panel 1100 to realize image display. Of course, the structure of the display device 1000 is not limited to this, and the display device 1000 can also include at least one of a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize multiple different functions such as touch, shooting, video recording, or fingerprint recognition.

[0072] As shown in FIG. 2, the display panel 1100 can include a display area AA and a peripheral area BB disposed on at least one side of the display area AA, and the peripheral area BB can be disposed around the display area AA. The display area AA refers to the area of the display panel 1100 used for displaying images, and the peripheral area BB, also referred to as a non-display area, refers to the area of the display panel 1100 outside the display area AA.

[0073] The display panel 1100 can include a plurality of sub-pixels P disposed in the display area AA, and the sub-pixel P refers to the smallest light-emitting unit in the display panel 1100. The plurality of sub-pixels P can include at least two sub-pixels emitting light of different colors. For example, the plurality of sub-pixels P includes a red light sub-pixel emitting red light, a green light sub-pixel emitting green light, and a blue light sub-pixel emitting blue light, so that the display panel can realize color display.

[0074] The sub-pixel P includes a pixel circuit 100 and a light-emitting element EL, and the pixel circuit 100 is electrically connected to the light-emitting element EL, and the pixel circuit 100 is configured to transmit a driving current to the light-emitting element EL to drive the light-emitting element EL to emit light. The plurality of pixel circuits 100 included in the plurality of sub-pixels P can be arranged in a plurality of rows and a plurality of columns, each row of pixel circuits 100 includes a plurality of pixel circuits 100 arranged along a first direction X, and a plurality of rows of pixel circuits 100 are arranged along a second direction Y; each column of pixel circuits 100 includes a plurality of pixel circuits 100 arranged along the second direction Y, and a plurality of columns of pixel circuits 100 are arranged along the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0075] The display panel 1100 can further include a gate driver on array (GOA) and a source driver IC disposed in the peripheral area BB. The gate driver on array can be connected to the pixel circuits 100 of a row of sub-pixels P through a scan signal line GL, and the source driver IC can be connected to the pixel circuits 100 of a column of sub-pixels P through a data signal line DL and transmit data signals to the pixel circuits 100 of the column of sub-pixels P.

[0076] In some embodiments, in the case of the display device being an OLED display device or a QLED display device, the display panel can include an array substrate, and a light-emitting element and an encapsulation structure (encapsulation layer) stacked on the array substrate. Of course, the structure of the display panel is not limited thereto, for example, the display panel can further include other functional layers disposed on the side of the encapsulation structure away from the array substrate, which can be one or more of a touch functional layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can realize corresponding functions, and the embodiments of the present disclosure do not make specific limitations on the types and numbers of the above-mentioned functional layers. The preparation process of the display panel can include an array process and a back-end process. The array substrate is prepared in the array process, and the light-emitting element and the encapsulation structure are formed on the array substrate in the back-end process. The pixel circuit 100 is disposed in the array substrate.

[0077] In some embodiments, the pixel circuit 100 described above can include a plurality of thin film transistors (TFTs) and at least one capacitor Cst. For example, the pixel circuit 100 can be a “9T2C” circuit, a “7T1C” circuit, or an “8T1C” circuit, and the embodiments of the present disclosure are not limited thereto, and any other pixel circuit can also be considered as long as the same technical idea is applied. Wherein, “T” refers to a TFT, and the number before “T” refers to the number of TFTs; “C” refers to a capacitor Cst, and the number before “C” refers to the number of capacitors Cst.

[0078] The pixel circuit 100 generally includes at least one drive transistor T1, and the pixel circuit 100 generally includes at least a data writing process and a threshold voltage compensation process in one frame period. The threshold voltage compensation process is configured to compensate the threshold voltage Vth of the drive transistor to the control electrode of the drive transistor, so as to eliminate the influence of the threshold voltage Vth of the drive transistor on the drive current generated by the pixel circuit. The data writing process is configured to couple the data signal to the control electrode of the drive transistor, and then control the drive current size of the drive transistor through the data signal, and control the luminance (the size of the displayed gray scale) of the sub-pixel.

[0079] Generally, the pixel circuit is designed to perform the data writing process and the threshold voltage compensation process in the same time period, that is, the threshold voltage of the driving transistor is compensated to the control electrode of the driving transistor in synchronization with the process of writing the data signal to the control electrode of the driving transistor.

[0080] However, as the display panel gradually develops in the direction of large size, high pixel density (Pixels Per Inch; PPI) and high refresh rate, the 1H scanning time of a row of pixel circuits is getting shorter, and the time length of the data writing process is generally 1H, which leads to the time length of the data writing process being shorter and shorter, that is, the time length of the threshold voltage compensation process is getting shorter, which may cause insufficient compensation of the threshold voltage of the driving transistor, poor compensation effect, affect the driving current generated by the driving transistor, and further affect the display quality of the display panel.

[0081] In order to overcome the above technical problems, referring to FIG. 3, the display panel provided by the embodiment of the present disclosure includes a pixel circuit 100, which includes a driving transistor T1, a data writing sub-circuit 10 and a compensation control sub-circuit 20.

[0082] The control electrode of the driving transistor T1 is electrically connected with the first node N1, the first electrode is electrically connected with the second node N2, and the second electrode is electrically connected with the third node N3; one of the second node N2 and the third node N3 is configured to be coupled with the light emitting element EL, and the other is configured to be coupled with the power voltage signal end (such as the first voltage signal line 51).

[0083] The data writing sub-circuit 10 is electrically connected with the data signal line DL, the first scan signal end G1 and the first node N1, and the data writing sub-circuit 10 is configured to transmit the data signal from the data signal line DL to the first node N1 under the control of the first scan signal from the first scan signal end G1.

[0084] The compensation control sub-circuit 20 is electrically connected with the second scan signal end G2, the first node N1 and the second node N2, and the compensation control sub-circuit 20 is configured to electrically connect the first node N1 with the second node N2 under the control of the second scan signal from the second scan signal end G2.

[0085] Based on the pixel circuit 100, in the process of transmitting the data signal to the first node N1 by the data writing sub-circuit 10, the data signal can not pass through the compensation control sub-circuit 20, that is, the pixel circuit 100 is a separate pixel circuit 100, and the data writing sub-circuit 10 and the compensation control sub-circuit 20 of the pixel circuit 100 are independent of each other and can work independently. The pixel circuit 100 is configured to perform threshold voltage compensation and data signal writing on the control electrode (the first node N1) of the driving transistor T1 in different time periods of the same frame period (in one frame time), that is, the data writing process and the threshold voltage compensation process of the pixel circuit 100 can be independent of each other and performed respectively. In this way, the duration of the threshold voltage compensation process can not be limited to 1H, which is beneficial to improve the time length of the threshold voltage compensation process, and thus the threshold voltage Vth of the driving transistor T1 is fully compensated to the control electrode of the driving transistor T1, which is beneficial to improve the accuracy of the driving current generated by the pixel circuit 100, and thus improve the display quality of the display panel.

[0086] In some embodiments, referring to FIG. 4, the compensation control sub-circuit 20 can include a third transistor T3, the control electrode of the third transistor T3 is electrically connected with the second scan signal end G2, the first electrode is electrically connected with the first node N1, and the second electrode is electrically connected with the second node N2. The third transistor T3 is configured to be turned on under the control of the second scan signal from the second scan signal end G2 to electrically connect the first node N1 and the second node N2. For example, in the threshold voltage compensation process, the driving transistor T1 is turned on under the voltage control of the first node N1, and a voltage VN3 is applied to the third node N3, and the third transistor T3 is turned on, so that the voltage VN3 of the third node N3 is transmitted to the first node N1 through the driving transistor T1 and the third transistor T3 in turn, and the voltage of the first node N1 changes to VN3+Vth. In this way, the threshold voltage Vth of the driving transistor T1 can be transmitted to the first node N1.

[0087] Continuing to refer to FIG. 4, the data writing sub-circuit 10 can include a second transistor T2 and a first capacitor C1. The control electrode of the second transistor T2 is electrically connected to the first scan signal terminal G1, the first electrode is electrically connected to the data signal line DL, and the second electrode is electrically connected to the fourth node N4. One plate of the first capacitor C1 is electrically connected to the first node N1, and the other plate is electrically connected to the fourth node N4. The second transistor T2 can be turned on under the control of the first scan signal from the first scan signal terminal G1 to electrically connect the data signal line DL and the fourth node N4, and then transmit the data signal transmitted on the data signal line DL to the fourth node N4. The first capacitor C1 changes the voltage of the first node N1 according to the voltage change of the fourth node N4, and then couples the data signal to the first node N1. The first capacitor C1 can also avoid directly electrically connecting the data signal line DL and the first node N1 during data writing, and then eliminate the threshold voltage Vth written to the first node N1.

[0088] Based on the above pixel circuit 100 (such as the pixel circuit 100 shown in FIGS. 3 and 4), since the data writing sub-circuit 10 and the compensation control sub-circuit 20 are independent of each other, and the threshold voltage Vth of the driving transistor T1 cannot be transmitted to the data signal line DL through the compensation control sub-circuit 20 and the data writing sub-circuit 10. After the array substrate is prepared (after the pixel circuit 100 is formed), the driving transistor T1 cannot be detected (such as whether the threshold voltage Vth of the driving transistor is within a reasonable range) through the structure of the pixel circuit 100 itself, so that the array substrate that does not meet the conditions (defective) cannot be excluded, and the defective array substrate will still be subjected to subsequent back-end processes, which will cause waste of materials and processes used in the back-end processes, and increase the preparation cost of the display panel.

[0089] In order to solve the above problems, referring to FIG. 5, the display panel 1100 provided by the embodiments of the present disclosure further includes a first signal line 200 and a test circuit 300. The first signal line 200 is electrically connected to the pixel circuit 100 and is configured to transmit a voltage signal to the pixel circuit 100. The test circuit 300 is electrically connected to a test signal terminal AT, and the test circuit 300 is electrically insulated from at least one of the pixel circuit 100 and the first signal line 200, so that the test circuit 300 can avoid electrically connecting the pixel circuit 100 and the first signal line 200 during the display process of the display panel 1100, reduce the risk of leakage or short circuit between the pixel circuit 100 and the first signal line 200, and facilitate to improve the reliability of the display panel 1100. For example, the test circuit 300 is electrically connected to the pixel circuit 100 and is electrically insulated from the first signal line 200; or the test circuit 300 is electrically insulated from the pixel circuit 100 and is electrically connected to the first signal line 200; or the test circuit 300 is electrically insulated from the pixel circuit 100 and the first signal line 200, respectively.

[0090] Embodiments of the present disclosure, based on the structure of the display panel 1100 (the display panel shown in FIG. 5), refer to FIG. 6, can be prepared in the preparation process of the display panel, and in the front process (Array process), a test substrate 400 including the pixel circuit 100 and the test circuit 300 is prepared, and in the test substrate 400, the test circuit 300 is electrically connected with the test signal end AT, the first signal line 200 and the third node N3 of the pixel circuit 100, and the test circuit 300 is configured to electrically connect the data signal line DL with the third node N3 under the control of the test signal from the test signal end AT. The driving transistor DT of the pixel circuit 100 can be detected by the test substrate 400 (the detection method is described below), and the test substrate 400 that meets the conditions is further prepared to form the display panel 1100, and the test substrate 400 that does not meet the conditions is processed (including but not limited to repair, recycling or scrapping), to avoid the test substrate 400 that does not meet the conditions entering the back-end process, reduce the material and process waste of the test substrate 400 that does not meet the conditions in the back-end process, and reduce the preparation cost of the display panel 1100.

[0091] Referring to FIG. 6, some embodiments of the present disclosure also provide a test substrate 400, which includes a pixel circuit 100 and a test circuit 300. The pixel circuit 100 includes a driving transistor T1, a data writing sub-circuit 10 and a compensation control sub-circuit 20. The test substrate 400 is configured to detect the driving transistor T1 of the pixel circuit 100, and further prepare the test substrate 400 that meets the conditions to form the above-mentioned display panel 1100, and process the test substrate 400 that does not meet the conditions. Avoid the test substrate 400 that does not meet the conditions entering the back-end process, reduce the material and process waste of the test substrate 400 that does not meet the conditions in the back-end process, and reduce the preparation cost of the display panel.

[0092] Referring to FIG. 6, the control electrode of the driving transistor T1 is electrically connected with the first node N1, the first electrode is electrically connected with the second node N2, and the second electrode is electrically connected with the third node N3; one of the second node N2 and the third node N3 is configured to be coupled with the light emitting element EL, and the other is configured to be coupled with the power voltage signal end (such as VDD). Exemplarily, in embodiments of the present disclosure, the second node N2 is configured to be coupled with the light emitting element EL (refer to FIG. 14A), and the third node N3 is configured to be coupled with the first voltage signal line 51 (refer to FIG. 14A), and the first voltage signal line 51 is configured to transmit the power voltage signal Vdd.

[0093] The data writing sub-circuit 10 is electrically connected with the data signal line DL, the first scan signal terminal G1 and the first node N1, and is configured to transmit a data signal from the data signal line DL to the first node N1 under the control of a first scan signal from the first scan signal terminal G1. The compensation control sub-circuit 20 is electrically connected with the second scan signal terminal G2, the first node N1 and the second node N2, and is configured to electrically connect the first node with the second node N2 under the control of a second scan signal from the second scan signal terminal G2. Wherein, the pixel circuit 100 is configured to perform threshold voltage compensation and data signal writing on the control electrode of the driving transistor T1 in different time periods of the same frame period (in one frame time), that is, the data writing process and the threshold voltage compensation process of the pixel circuit 100 can be independent and performed respectively. In this way, the time length of the threshold voltage compensation process can not be limited to 1H, which is beneficial to improve the time length of the threshold voltage compensation process, and then fully compensate the threshold voltage Vth of the driving transistor T1 to the control electrode of the driving transistor T1, which is beneficial to improve the accuracy of the driving current generated by the pixel circuit 100, and then improve the display quality of the display panel.

[0094] The test circuit 300 is electrically connected with the test signal terminal AT, the data signal line DL and the third node N3 of the pixel circuit 100, and the test circuit 300 is configured to electrically connect the first signal line 200 with the third node N3 under the control of a test signal from the test signal terminal AT.

[0095] When detecting the test substrate 400, on one hand, the test circuit 300 electrically connects the third node N3 with the first signal line 200 under the control of the test signal from the test signal terminal AT. On the other hand, a voltage signal is transmitted to the first node N1 to turn on the driving transistor T1, and a voltage signal is transmitted to the second node N2. At this time, a detection current flowing through the driving transistor T1 is generated, and the detection current flows from the second node N2 to the third node N3, and the size of the detection current is related to the threshold voltage Vth of the driving transistor T1. And the detection current transmitted to the third node N3 can be collected through the first signal line 200. Then, the voltage transmitted to the first node N1 and the voltage transmitted to the second node N2 can be determined, based on which the threshold voltage Vth of the driving transistor T1 can be calculated based on the collected detection current of the third node N3, and then it is judged whether the threshold voltage Vth of the driving transistor T1 meets the use condition of the display panel. If it meets the condition, the test substrate 400 is further prepared to form the display panel 1100. If the driving transistor T1 of at least one pixel circuit 100 does not meet the condition, the test substrate 400 is subjected to other processing. Avoiding the test substrate 400 that does not meet the condition from entering the back-end process, reducing the material and process waste of the test substrate 400 that does not meet the condition in the back-end process, and reducing the preparation cost of the display panel.

[0096] It should be noted that in the above embodiments of the present disclosure, the first signal line 200 is electrically connected with the pixel circuit 100 in the test process of the test substrate 400, that is, the first signal line 200 is also configured to transmit a voltage signal to the pixel circuit, and at the same time the detection current flowing into the third node N3 can be collected through the first signal line 200, that is, the first signal line 200 is a signal line possessed by the display panel itself, which is conducive to reducing the number of signal lines in the display panel, thereby simplifying the structure of the display panel and reducing the preparation difficulty and preparation cost of the display panel. Of course, the structure design and test method of the test substrate 400 are not limited to this, and other signal lines or special collection signal lines can also be considered to collect the voltage of the third node N3.

[0097] In some embodiments, referring to FIG. 7, the first signal line 200 can be the same signal line as the data signal line DL, and at this time, the test circuit 300 is electrically connected with the data line DL and the third node N3 of the pixel circuit 100. In at least some embodiments of the present disclosure, the first signal line 200 and the data signal line DL are taken as the same signal line as an example to describe the embodiments of the present application.

[0098] In some embodiments, referring to FIG. 7, the pixel circuit 100 further comprises a second initialization sub-circuit 30 electrically connected with the fourth scan signal terminal G4, the third voltage signal line Vinit1 and the first node N1, and configured to transmit the third voltage signal V3 from the third voltage signal line Vinit1 to the first node N1 under the control of the fourth scan signal from the fourth scan signal terminal G4. Illustratively, the second initialization sub-circuit 30 can initialize the voltage of the first node N1 after the display panel is prepared from the test substrate 400, and can transmit the third voltage signal V3 to the first node N1 to turn on the driving transistor T1 during the detection of the test substrate 400.

[0099] Illustratively, during the detection of the test substrate 400, the fourth scan signal terminal G4 can transmit an effective level, the second initialization sub-circuit 30 electrically connects the third voltage signal line Vinit1 and the first node N1, and then transmits the third voltage signal V3 from the third voltage signal line Vinit1 to the first node N1. The third voltage signal V3 can turn on the driving transistor T1.

[0100] Illustratively, during the detection of the test substrate 400, the second scan signal terminal G2 can also transmit a second scan signal, and the compensation control sub-circuit 20 electrically connects the first node N1 and the second node N2. In this way, the second initialization sub-circuit 30 can also transmit the third voltage signal V3 to the second node N2. Based on this, the second initialization sub-circuit 30 can transmit voltage signals to the first node N1 and the second node N2 at the same time, which is beneficial to simplify the number of signals required during the detection of the test substrate 400 and simplify the detection control process of the test substrate 400.

[0101] In some embodiments, referring to FIG. 8, the compensation control sub-circuit 20 can comprise a third transistor T3, the control electrode of the third transistor T3 is electrically connected with the second scan signal terminal G2, the first electrode is connected with the first node N1, and the second electrode is electrically connected with the second node N2. The third transistor T3 is configured to be turned on under the control of the second scan signal from the second scan signal terminal G2 to turn on between the first node N1 and the second node N2. Illustratively, during the threshold voltage compensation process, the driving transistor T1 is turned on under the voltage control of the first node N1, and at the same time, a voltage VN3 is applied to the third node N3 and the third transistor T3 is turned on. In this way, the voltage VN3 of the third node N3 is transmitted to the first node N1 through the driving transistor T1 and the third transistor T3 in sequence, and the voltage of the first node N1 changes to VN3+Vth. In this way, the threshold voltage Vth of the driving transistor T1 can be transmitted to the first node N1.

[0102] The data writing sub-circuit 10 can include a second transistor T2 and a first capacitor C1. The control electrode of the second transistor T2 is electrically connected with the first scan signal terminal G1, the first electrode is electrically connected with the data signal line DL, and the second electrode is electrically connected with the fourth node N4. One plate of the first capacitor C1 is electrically connected with the first node N1, and the other plate is electrically connected with the fourth node N4. The second transistor T2 can be turned on under the control of the first scan signal from the first scan signal terminal G1 to electrically connect the data signal line DL and the fourth node N4, and then transmit the data signal transmitted on the data signal line DL to the fourth node N4. The first capacitor C1 changes the voltage of the first node N1 according to the voltage change of the fourth node N4, and then couples the data signal to the first node N1. The first capacitor C1 can also avoid directly electrically connecting the data signal line DL and the first node N1 in the data writing process, and then eliminate the threshold voltage Vth written to the first node N1.

[0103] The second initialization sub-circuit 30 can include a fourth transistor T4, the control electrode of the fourth transistor T4 is electrically connected with the fourth scan signal terminal G4, the first electrode is electrically connected with the third voltage signal line Vinit1, and the second electrode is electrically connected with the first node N1. The fourth transistor T4 is configured to be turned on under the control of the active level from the fourth scan signal terminal G4 to electrically connect the third voltage signal line Vinit1 and the first node N1.

[0104] The test circuit 300 includes a test transistor T10, the control electrode of the test transistor T10 is electrically connected with the test signal terminal AT, the first electrode is electrically connected with the data signal line DL, and the second electrode is electrically connected with the third node N3. The test transistor T10 is configured to electrically connect the third node N3 and the data signal line DL under the control of the active level from the test signal terminal AT.

[0105] Referring to FIGS. 8 and 9, some embodiments of the present disclosure also provide a test method for testing the substrate 400, which includes an initial stage D1 and a detection stage D2.

[0106] In the initial stage D1, the fourth scan signal terminal G4 transmits an active level (low level), the fourth transistor T4 is turned on and electrically connects the third voltage signal line Vinit1 and the first node N1, and the third voltage signal line Vinit1 transmits the third voltage signal V3 to the first node N1. The driving transistor T1 is turned on under the control of the third voltage signal V3.

[0107] In the detection stage D2, the fourth scan signal terminal G4 transmits an invalid level (high level), and the fourth transistor T4 is turned off. The second scan signal terminal G2 transmits the second scan signal (valid level), and the third transistor T3 is turned on and electrically connects the first node N1 and the second node N2. The first node N1 (the third voltage signal V3) transmits the detection current to the first signal line 200 (the data signal line DL) through the third transistor T3, the driving transistor T1 and the test transistor T10 in turn, and then the detection current is collected through the first signal line 200 (the data signal line DL).

[0108] In some embodiments, referring to FIGS. 10, 11 and 12, the pixel circuit 100 further comprises a first function sub-circuit 40, which is electrically connected with the first function control signal terminal G10, the second signal line 500 and the third node N3, and is configured to electrically connect the second signal line 500 and the third node N3 under the control of the first function control signal from the first function control signal terminal G10.

[0109] The second signal line 500 is configured to be electrically connected with at least one column of pixel circuits 100. For example, the test substrate 400 comprises a plurality of second signal lines 500, and one second signal line 500 is electrically connected with one column of pixel circuits 100. Alternatively, the second signal line 500 comprises a plurality of first sub-lines extending in the first direction and a plurality of second sub-lines extending in the second direction, and the plurality of first sub-lines and the plurality of second sub-lines are connected with each other to form a mesh structure. In this case, the second signal line 500 can be understood as the same signal line, or in other words, the test substrate 400 comprises one second signal line 500, and all the sub-pixels P comprised by the test substrate 400 are electrically connected with the second signal line 500.

[0110] The test substrate 400 can comprise at least one test circuit 300, which is electrically connected with the second signal line 500 and the third node N3 of the pixel circuit 100 (indirectly electrically connected) through the second signal line 500. Alternatively, the test substrate 400 comprises a plurality of test circuits 300, and one test circuit 300 is directly electrically connected with the third node N3 of one pixel circuit 100.

[0111] In some embodiments, referring to FIG. 10, the test substrate 400 comprises a plurality of test circuits 300, and one test circuit 300 is directly electrically connected with the third node N3 of one pixel circuit 100. That is, one test circuit 300 is arranged corresponding to each pixel circuit 100, which is beneficial to improve the structural uniformity of the test substrate 400, and the plurality of test circuits 300 can be used to accurately detect whether the driving transistor T1 of each pixel circuit 100 meets the condition.

[0112] Exemplarily, only one pixel circuit 100 and one test circuit 300 are exemplarily shown in FIG. 10. And in the case that one test circuit 300 is directly electrically connected with the third node N3 of one pixel circuit 100, the first signal line 200 can be the same signal line as the data signal line DL. Based on this, in the process of detecting the test substrate 400, the multiple columns of pixel circuits 100 in the test substrate 400 can be detected column by column (one column after another). Meanwhile, since the test substrate 400 is generally line scanning driven, the multiple rows of pixel circuits 100 in the test substrate 400 can be detected row by row (one row after another). In this way, the driving transistor T1 of each pixel circuit 100 can be accurately detected.

[0113] In some embodiments, referring to FIG. 11, one of the second signal lines is configured to be electrically connected with one column of the pixel circuits; the test substrate 400 comprises multiple test circuits 300, one test circuit 300 is respectively electrically connected with one of the first signal lines 200 (the data signal line DL) and one of the second signal lines 500 electrically connected with one column of pixel circuits 100, and the test circuit 300 is electrically connected with the third nodes N3 of one column of pixel circuits 100 through the second signal line 500. In this way, one column of pixel circuits 100 can share one test circuit 300, that is, the driving transistor DT of one column of pixel circuits 100 can be detected through one test circuit 300. At this time, the number of test circuits 300 can be equal to the number of columns of pixel circuits 100, so that the number of test circuits 300 that need to be arranged on the test substrate 400 can be greatly reduced, which is conducive to simplifying the structure of the test substrate 400, and further simplifying the preparation difficulty and preparation cost of the test substrate 400.

[0114] Exemplarily, only one column of pixel circuits 100 is exemplarily shown in FIG. 11. In the case that one test circuit 300 is directly electrically connected with the third nodes N3 of one column of pixel circuits 100 through one second signal line 500, the first signal line 200 can be the same signal line as the data signal line DL. Based on this, in the process of detecting the test substrate 400, the multiple rows and multiple columns of pixel circuits 100 can be detected column by column and row by row, and the driving transistor T1 of each pixel circuit 100 can be accurately detected.

[0115] In some embodiments, referring to FIG. 12, the second signal line 500 is configured to be electrically connected with all the pixel circuits 100 in the test substrate 400, that is, all the pixel circuits 100 share the second signal line 500. The test substrate 400 comprises one test circuit 300, and the test circuit 300 is electrically connected with the second signal line 500. In this way, not only the number of test circuits 300 can be greatly reduced, but also the detection efficiency of the test substrate 400 can be improved.

[0116] It should be noted that the pixel circuit 100 is usually driven in a row scanning manner, so that in the process of testing the test substrate 400, the pixel circuit 100 in a row transmits a test current to the second signal line 500, and whether there is at least one driving transistor T1 that does not meet the condition in the plurality of driving transistors T1 of the pixel circuit 100 can be tested at one time. In the case that there is at least one driving transistor T1 that does not meet the condition, it can be considered that the test substrate 400 does not meet the condition.

[0117] For example, in the case that the driving transistor T1 of at least one pixel circuit 100 in a row of pixel circuits 100 does not meet the preset condition, there will be at least one pixel circuit 100 transmitting a detection current to the second signal line 500 that is not within the preset range, thereby causing the size of the detection current collected by the second signal line 500 to be not within the preset range, and then considering that the test substrate 400 does not meet the condition. Then, other processing is performed on the test substrate 400, which can avoid the test substrate 400 that does not meet the condition from entering the later process, reduce the material waste and process waste of the test substrate 400 that does not meet the condition in the later process, and reduce the preparation cost of the display panel 1100.

[0118] In some embodiments, referring to FIG. 13, the first functional sub-circuit 40 includes a light-emitting control sub-circuit 41 and a first initialization sub-circuit 42. The light-emitting control sub-circuit 41 is electrically connected with the first light-emitting control signal terminal EM1, the first voltage signal line 51 and the third node N3, and is configured to electrically connect the first voltage signal line 51 and the third node N3 under the control of the light-emitting control signal of the first light-emitting control signal terminal EM1. The first initialization sub-circuit 42 is electrically connected with the third scan signal terminal G3, the second voltage signal line 52 and the third node N3, and the first initialization sub-circuit 42 is configured to electrically connect the second voltage signal line 52 and the third node under the control of the third scan signal from the third scan signal terminal G3. The first voltage signal line 51 is configured to transmit a power voltage signal Vdd, and the second voltage signal line 52 is configured to transmit a first reference voltage signal Vref1. The second signal line 500 includes the first voltage signal line 51 and the second voltage signal line 52. In the case that the test circuit 300 is indirectly electrically connected with the third node N3 through the second signal line 500, the test circuit 300 can be electrically connected with the first voltage signal line 51, or the test circuit 300 can be electrically connected with the second voltage signal line 52.

[0119] In the embodiments of the present disclosure, referring to FIGS. 14A and 14B, the embodiments of the present disclosure are exemplarily described by taking the case that the test circuit 300 is electrically connected with the first voltage signal line 51 as an example.

[0120] In some embodiments, referring to FIG. 14A, the light emitting control sub-circuit 41 can include a fifth transistor T5, a control electrode of the fifth transistor T5 being electrically connected with the first light emitting control signal terminal EM1, a first electrode being electrically connected with the first voltage signal line 51, and a second electrode being electrically connected with the third node N3. The light emitting control sub-circuit 41 is configured to be turned on under the control of the first light emitting control signal (active level / low level) from the first light emitting control signal terminal EM1, to electrically connect the third node N3 with the first voltage signal line 51.

[0121] The first initialization sub-circuit 42 includes a sixth transistor T6, a control electrode of the sixth transistor T6 being electrically connected with the third scan signal terminal G3, a first electrode being electrically connected with the second voltage signal line 52, and a second electrode being electrically connected with the third node N3. The sixth transistor T6 is configured to be turned on under the control of the active level from the third scan signal terminal G3, to electrically connect the third node N3 with the second voltage signal line 52.

[0122] Exemplarily, referring to FIG. 15, in the process of detecting the test substrate 400, and in the detection stage D2, the first light emitting control signal terminal EM1 transmits the first light emitting control signal, and the fifth transistor T5 is turned on under the action of the first light emitting control signal, to electrically connect the third node N3 with the first voltage signal line 51. At this time, the detection current is transmitted to the first signal line 200 (data signal line DL) through the third transistor T3, the driving transistor T1, the fifth transistor T5, the first voltage signal line 51 and the test transistor T10 in turn.

[0123] In some embodiments, referring to FIG. 14A and FIG. 14B, the pixel circuit 100 further includes a second light emitting control sub-circuit 50, a third initialization sub-circuit 60 and a pull-up sub-circuit 70.

[0124] The second light emitting control sub-circuit 50 is electrically connected with the second light emitting control signal terminal EM2, the second node N2 and the fifth node N5, and is configured to electrically connect the second node N2 with the fifth node N5 under the control of the second light emitting control signal from the second light emitting control signal terminal EM2. The fifth node N5 is configured to be electrically connected with the anode of the light emitting element EL.

[0125] Exemplarily, the second light emitting control sub-circuit 50 includes a seventh transistor T7, a control electrode of the seventh transistor T7 being electrically connected with the second light emitting control signal terminal EM2, a first electrode being electrically connected with the second node N2, and a second electrode being electrically connected with the fifth node N5. The seventh transistor T7 is configured to be turned on under the control of the second light emitting control signal (active level) from the second light emitting control signal terminal EM2, to electrically connect the second node N2 with the anode of the light emitting element EL.

[0126] The third initialization sub-circuit 60 is electrically connected with the fifth scan signal terminal G5, the fourth voltage signal line Vinit2 and the fifth node N5, and is configured to electrically connect the fifth node N5 with the third voltage signal line Vinit2 under the control of the fifth scan signal from the fifth scan signal terminal G5.

[0127] Exemplarily, the third initialization sub-circuit 60 can include an eighth transistor T8, the control electrode of which is electrically connected with the fifth scan signal terminal G5, the first electrode is electrically connected with the fourth voltage signal line Vinit2, and the second electrode is electrically connected with the fifth node N5. The eighth transistor T8 is configured to electrically connect the fourth voltage signal line Vinit2 with the fifth node N5 under the control of the fifth scan signal (active level) from the fifth scan signal terminal G5, and in turn transmit the fourth voltage signal transmitted by the fourth voltage signal line Vinit2 to the fifth node N5.

[0128] The pull-up sub-circuit 70 is electrically connected with the sixth scan signal terminal G6, the fifth voltage signal line Vref and the fourth node N4, and is configured to electrically connect the fifth voltage signal line Vref with the fourth node N4 under the control of the sixth scan signal from the sixth scan signal terminal G6.

[0129] Exemplarily, the pull-up sub-circuit 70 can include a ninth transistor T9. The control electrode of the ninth transistor T9 is electrically connected with the sixth scan signal terminal G6, the first electrode is electrically connected with the fifth voltage signal line Vref, and the second electrode is electrically connected with the fourth node N4. The ninth transistor T9 is configured to be turned on under the control of the sixth scan signal (active level) from the sixth scan signal terminal G6, so as to electrically connect the fifth voltage signal line Vref with the fourth node N4 and transmit the fifth voltage signal from the fifth voltage signal line Vref to the fourth node N4.

[0130] The pixel circuit 100 further includes one plate of the second capacitor C2 being electrically connected with the fourth node N4, and the other plate being electrically connected with the first voltage signal line 51.

[0131] Referring to FIG. 14B, the first signal line 200 includes one of the data signal line DL, the fourth voltage signal line Vinit2 and the fifth voltage signal line Vref.

[0132] Exemplarily, in a case where the test circuit 300 is directly electrically connected with the third node N3 (as shown in FIG. 10), the first signal line 200 can be the data signal line DL. In a case where the test circuit 300 is indirectly electrically connected with the third node N3 through the second signal line 500, and one second signal line 500 is electrically connected with one column of pixel circuits 100 (as shown in FIG. 11), the first signal line 200 can be the data signal line DL. In a case where the test circuit 300 is indirectly electrically connected with the third node N3 through the second signal line 500, and the second signal line 500 is electrically connected with all the pixel circuits 100 (as shown in FIG. 12 and FIG. 14B), the first signal line 200 can be any one of the fourth voltage signal line Vinit2 and the fifth voltage signal line Vref. It should be noted that embodiments of the present disclosure are not limited thereto, and the test circuit 300 can also be electrically connected with other signal lines, as long as the current for detection in the test phase can be transmitted to the signal line, and there is no other current on the signal line, and embodiments of the present disclosure will not be enumerated one by one.

[0133] The test substrate 400 provided by the embodiments of the present disclosure is subjected to disconnection processing after detection, for the test substrate 400 meeting the conditions, to disconnect the connection between the test transistor T10 (the test circuit 300) and the pixel circuit 100, and / or disconnect the connection between the test transistor T10 (the test circuit 300) and the first signal line 200 (the data signal line DL). In this way, it can be avoided that the test circuit 300 leaks current after the test substrate 400 is prepared to form the display panel, and when the display panel 1100 is working, thereby reducing the influence of the test circuit 300 on the pixel circuit 100, and improving the reliability of the pixel circuit 100.

[0134] The display panel 1100 provided by the embodiments of the present disclosure includes the pixel circuit 100 and the test circuit 300. The test circuit 300 is electrically connected with the test signal end AT, and the test circuit 300 is electrically insulated from at least one of the pixel circuit 100 and the first signal line 200 (the data signal line DL). In this way, it can be avoided that the test circuit 300 electrically connects the pixel circuit 100 and the first signal line 200 (the data signal line DL) during the display process of the display panel 1100, and the risk of leakage or short circuit between the pixel circuit 100 and the first signal line 200 (the data signal line DL) is reduced, which is beneficial to improve the reliability of the display panel 1100.

[0135] Exemplarily, the test circuit 300 is electrically connected with the pixel circuit 100 and electrically insulated from the data signal line DL; or the test circuit 300 is electrically insulated from the pixel circuit 100 and electrically connected with the first signal line 200; or the test circuit 300 is electrically insulated from both the pixel circuit 100 and the first signal line 200. In the following embodiments of the present disclosure, referring to FIG. 16, the test circuit 300 is electrically connected with the first signal line 200 and electrically insulated from the pixel circuit 100 as an example, and the embodiments of the present disclosure are exemplarily described.

[0136] In some embodiments, referring to FIG. 16, the test circuit 300 (test transistor T10) is electrically connected with the first signal line 200 and electrically insulated from the pixel circuit 100. The influence of the test circuit 300 on the pixel circuit 100 can be greatly reduced, and the difficulty of the disconnection process of the test substrate 400 is reduced.

[0137] In some embodiments, referring to FIGS. 17 and 18, the pixel circuit 100 includes the driving transistor T1, the data writing sub-circuit 10, the compensation control sub-circuit 20, the second initialization sub-circuit 30 and the first function sub-circuit 40. The pixel circuit 100 can further include the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the second capacitor C2.

[0138] The structure and connection relationship of the driving transistor T1, the data writing sub-circuit 10, the compensation control sub-circuit 20, the second initialization sub-circuit 30, the first function sub-circuit 40, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the second capacitor C2 are the same as the structure and connection relationship of the corresponding part in the test substrate 400 described above, and the embodiments of the present disclosure will not be described again.

[0139] In some embodiments, referring to FIG. 19, the display panel 1100 can include a substrate 21, and a semiconductor layer 22, a gate insulating layer 23, a gate conductive layer 24, an interlayer dielectric layer 25, a first source-drain conductive layer 26, a first insulating layer 27 (which can also be referred to as a first planarization layer), a second source-drain conductive layer 28, a second planarization layer 29, an anode layer 31 and a second insulating layer (which can also be referred to as a pixel defining layer) 32 arranged in sequence away from the substrate 21. Of course, the structure of the display panel 1100 is not limited to this, and can include other any suitable film layers, for example, the display panel 1100 can further include a light-emitting functional layer, a cathode layer and an encapsulation functional layer (not shown in the figure) arranged away from the substrate 21 side of the second insulating layer 32.

[0140] In some embodiments, referring to FIG. 19, the test circuit 300 includes a test transistor T10, which includes a semiconductor pattern 11, a gate pattern 12, a first connection pattern 13, and a second connection pattern 14. The semiconductor pattern 11 is located in the semiconductor layer 22, and the semiconductor pattern 11 can include a channel region 111 and a first electrode region 112 and a second electrode region 113 located on both sides of the channel region 111, respectively. The gate pattern 12 is disposed on one side of the semiconductor pattern 11, for example, the gate pattern 12 is located in the gate conductive layer 24, and the gate pattern 12 is configured to be electrically connected to the test signal terminal AT. The second connection pattern 14 is the same material as the first connection pattern 13 and is disposed in the same layer, for example, the second connection pattern 14 and the first connection pattern 13 are both located in the first source-drain conductive layer 26. The first connection pattern 13 is disposed on the side of the gate pattern 12 away from the semiconductor pattern 11, and the first connection pattern 13 is electrically connected to the first signal line 200 and the first electrode region 112, respectively. The second connection pattern 14 includes a first sub-pattern 141 and a second sub-pattern 142 separated from each other, the first sub-pattern 141 is electrically connected to the second electrode region 113, and the second sub-pattern 142 is electrically connected to the pixel circuit 100. The first connection pattern 13 and the second connection pattern 14 have a first gap N1 therebetween, and the first sub-pattern 141 and the second sub-pattern 142 have a second gap N2 therebetween.

[0141] Exemplarily, in the preparation process of the display panel, and in the preparation of the formed test substrate, the second connection pattern 14 can include the first sub-pattern 141, the second sub-pattern 142, and a connection part located between the first sub-pattern 141 and the second sub-pattern 142 and connected to the first sub-pattern 141 and the second sub-pattern 142, respectively. In this way, the test transistor T10 can be electrically connected to the pixel circuit 100, and the driving transistor T1 of the pixel circuit 100 can be detected. Then, after detecting the test substrate, the connection part between the first sub-pattern 141 and the second sub-pattern 142 is removed by etching process, so as to form the first sub-pattern 141 and the second sub-pattern 142 separated from each other, and the connection between the test transistor T10 and the pixel circuit 100 is disconnected.

[0142] In some embodiments, referring to FIG. 19, the display panel 1100 further includes a substrate 21 and a first insulating layer 27. The substrate 21 is disposed on a side of the semiconductor pattern 11 away from the gate pattern 12, or in other words, the test transistor T10 is disposed on the substrate 21. The first insulating layer 27 is disposed on a side of the first connection pattern 13 and the second connection pattern 14 away from the substrate 21. Exemplarily, the first insulating layer 27 can be an insulating layer directly in contact with the first connection pattern 13 and the second connection pattern 14. The first insulating layer 27 fills the first gap N1, and a footprint of the first insulating layer 27 on the substrate 21 does not overlap with a footprint of the second gap N2 on the substrate 21, or in other words, the first insulating layer 27 does not cover and fill the second gap N2.

[0143] In some embodiments, referring to FIG. 19, the display panel 1100 further includes a second insulating layer 32. The second insulating layer 32 is disposed on a side of the first insulating layer 27 away from the substrate 21. The second insulating layer 32 is not in contact with the first connection pattern 13, and the second insulating layer 32 fills the second gap N2 and covers the side walls of the first sub-pattern 141 and the second sub-pattern 142 close to each other. The second insulating layer 32 can electrically insulate the first sub-pattern 141 and the second sub-pattern 142, and reduce the risk of short circuit between the first sub-pattern 141 and the second sub-pattern 142.

[0144] Some embodiments of the present disclosure further provide a preparation method of the display panel 1100. Referring to FIG. 20, the preparation method includes S100-S300.

[0145] S100, referring to FIG. 21 or FIG. 22, a test substrate 400 is prepared.

[0146] The test substrate 400 can be the test substrate 400 described in any of the preceding embodiments. Embodiments of the present disclosure do not list them one by one. Among them, the test substrate 400 includes a substrate 21 and a test transistor T10 disposed on the substrate 21. In some embodiments, S100 of preparing the test substrate 400 includes S110 and S120.

[0147] S110, a plurality of test transistors T10 are formed on the substrate 21.

[0148] The test transistor T10 includes a semiconductor pattern 11 in a semiconductor layer 22, a gate pattern 12 in a gate conductive layer 24, and a first connection pattern 13 and an initial second connection pattern 14' in a first source-drain conductive layer 26. The first connection pattern 13 and the initial second connection pattern 14' have a first gap N1 therebetween.

[0149] The semiconductor pattern 11 can include a channel region 111 and a first electrode region 112 and a second electrode region 113 located on two sides of the channel region 111 respectively. The gate pattern 12 is electrically connected with the test signal terminal AT. The first connection pattern 13 is electrically connected with the data signal line DL and the first electrode region 112 respectively. The initial second connection pattern 14' is electrically connected with the second electrode region 113 and the pixel circuit 100 respectively.

[0150] S120, forming a first insulating layer 27 on a side of the plurality of test transistors T10 away from the substrate 21.

[0151] The test substrate 400 further includes the first insulating layer 27 disposed on a side of the test transistor T10 away from the substrate 21. The first insulating layer 27 directly contacts the first connection pattern 13 and the initial second connection pattern 14', the first insulating layer 27 covers the first connection pattern 13, the first insulating layer 27 exposes the first region 143 of the initial second connection pattern 14', and the first insulating layer 27 covers the second region 144 and the third region 145 of the initial second connection pattern 14', and the first region 143 is located between the second region 144 and the third region 145. The first insulating layer 27 also fills the first gap N1.

[0152] In some embodiments, after the step S120 described above, the method further includes preparing a second source-drain conductive layer 28 and a second planarization layer 29 on a side of the first insulating layer 27 away from the substrate 21. That is, the test substrate 400 further includes the second source-drain conductive layer 28 and the second planarization layer 29 on a side of the first insulating layer 27 away from the substrate 21. Exemplarily, the second source-drain conductive layer 28 includes the data signal line DL and a first voltage signal line 51. The data signal line DL is electrically connected with the first connection pattern 13 through a via, and the first voltage signal line 51 is electrically connected with the third region 145 of the initial second connection pattern 14' through a via. The second planarization layer 29 has a projection on the substrate 21 that does not overlap with a projection of the first region 143 on the substrate 21.

[0153] In some embodiments, in the case that the etching selectivity of the anode layer and the first source-drain conductive layer 26 is equal or approximately equal (or in the case that the anode layer and the first source-drain conductive layer 26 can be etched at the same time), the structure of the test substrate 400 is as shown in FIG. 20, and the preparation of the test substrate 400 is completed after the preparation of the second planarization layer 29.

[0154] In some embodiments, in the case that the etching selectivity ratio of the anode layer and the first source-drain conductive layer 26 is not equal (or in the case that the anode layer and the first source-drain conductive layer 26 cannot be etched at the same time), the structure of the test substrate 400 is as shown in FIG. 20, or the test substrate 400 can further include the anode layer 31. As shown in FIG. 21, in the case that the test substrate 400 includes the anode layer 31, a continuous whole layer of the anode layer can be first prepared, and then the whole layer of the anode layer is patterned to obtain the anode layer 31. In the process of patterning the whole layer of the anode layer, the first region 143 of the initial second connection pattern 14' is not damaged.

[0155] S200, detecting whether the driving transistor of the test substrate 400 meets a preset condition.

[0156] Exemplarily, the preset condition can be a voltage range of the threshold voltage of the driving transistor, so that the threshold voltage of the driving transistor can be detected, and it is determined whether the threshold voltage of the driving transistor is within the preset range. If the threshold voltage of the driving transistor is within the preset range, it is considered that the driving transistor meets the preset condition, i.e., meets the use condition. If the threshold voltage of at least one driving transistor is not within the preset range, it is considered that the at least one driving transistor does not meet the preset condition, i.e., does not meet the use condition.

[0157] S300, referring to FIGS. 23 and 24, if the driving transistor of the test substrate 400 meets the preset condition, the connection between the test circuit 300 of the test substrate 400 and the pixel circuit 100 is disconnected, and / or the connection between the test circuit 300 and the data signal line is disconnected, and the preparation of the display panel is continued.

[0158] In some embodiments, referring to FIGS. 23 and 24, the embodiments of the present disclosure are exemplarily described by taking the disconnection of the connection between the test circuit 300 of the test substrate 400 and the pixel circuit 100 as an example. The step S300 of disconnecting the connection between the test circuit 300 of the test substrate 400 and the pixel circuit 100 includes S310.

[0159] In the case that the test substrate 400 is as shown in FIG. 21, S310 can include:

[0160] Referring to FIG. 23, a continuous whole layer of the anode layer 31' is first formed on the test substrate 400.

[0161] Referring to FIG. 24, then the whole anode layer 31' is patterned to form the anode layer 31, and the first region 143 of the initial second connection pattern 14' is removed synchronously to form the second connection pattern 14. Wherein, the first region 143 of the initial second connection pattern 14' forms the second gap N2, the second region 144 forms the first sub-pattern 141, and the third region 145 forms the second sub-pattern 142.

[0162] In the case where the test substrate 400 is a structure as shown in FIG. 21, S310 can include:

[0163] The first insulating layer 27 is used as a mask to remove the first region 143 of the initial second connection pattern 14' to form the second connection pattern 14, and the second gap N2 is formed in the first region. The structure of the display panel 1100 formed thereby is the same as that of the display panel shown in FIG. 24.

[0164] Wherein, the first region 143 of the initial second connection pattern 14' forms the second gap N2, the second region 144 forms the first sub-pattern 141, and the third region 145 forms the second sub-pattern 142.

[0165] The above is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical scope disclosed by the present disclosure, which shall be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A test substrate, comprising: a pixel circuit comprising a driving transistor, a data writing sub-circuit and a compensation control sub-circuit; wherein a control electrode of the driving transistor is electrically connected with a first node, a first electrode is electrically connected with a second node, a second electrode is electrically connected with a third node, one of the second node and the third node is configured to be coupled to a light emitting element, and the other is configured to be coupled to a power voltage signal terminal; the data writing sub-circuit is electrically connected with a data signal line, a first scan signal terminal and the first node, and is configured to transmit a data signal from the data signal line to the first node under control of a first scan signal from the first scan signal terminal; the compensation control sub-circuit is electrically connected with a second scan signal terminal, the first node and the second node, and is configured to electrically connect the first node with the second node under control of a second scan signal from the second scan signal terminal; the pixel circuit is configured to perform threshold voltage compensation and data signal writing on the control electrode of the driving transistor at different time periods of a same display period, respectively; a first signal line electrically connected with the pixel circuit; and a test circuit electrically connected with a test signal terminal, the first signal line and the third node, and configured to electrically connect the first signal line with the third node under control of a test signal from the test signal terminal.

2. The test substrate according to claim 1, wherein: the pixel circuit further comprises a first function sub-circuit electrically connected with a first function control signal terminal, a second signal line and the third node, and configured to electrically connect the second signal line with the third node under control of a first function control signal from the first function control signal terminal; and the test substrate comprises a plurality of columns of the pixel circuit, and the second signal line is configured to be electrically connected with at least one column of the pixel circuit.

3. The test substrate according to claim 2, wherein: one of the second signal lines is configured to be electrically connected with one column of the pixel circuit; and the test substrate comprises a plurality of the test circuits, and one of the test circuits is electrically connected with one of the second signal lines.

4. The test substrate according to claim 2, wherein: the second signal line is configured to be electrically connected with all of the pixel circuits; and the test substrate comprises one of the test circuits, and the test circuit is electrically connected with the second signal line.

5. The test substrate according to claim 1, wherein: the pixel circuit further comprises a first function sub-circuit electrically connected with a first function control signal terminal, a second signal line and the third node, and configured to electrically connect the second signal line with the third node under control of a first function control signal from the first function control signal terminal. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The test substrate includes a plurality of the pixel circuits and a plurality of the test circuits, one of the test circuits being directly electrically connected with a third node of one of the pixel circuits.

6. The test substrate according to any one of claims 2 to 5, wherein The first functional sub-circuit includes a light-emitting control sub-circuit and a first initialization sub-circuit; the light-emitting control sub-circuit is electrically connected with a first light-emitting control signal terminal, a first voltage signal line and the third node, and is configured to electrically connect the first voltage signal line with the third node under control of a light-emitting control signal from the first light-emitting control signal terminal; the first initialization sub-circuit is electrically connected with a third scan signal terminal, a second voltage signal line and the third node, and is configured to electrically connect the second voltage signal line with the third node under control of a third scan signal from the third scan signal terminal; The second signal line includes the first voltage signal line and the second voltage signal line.

7. The test substrate according to any one of claims 1 to 6, wherein The test circuit includes a test transistor, a control electrode of the test transistor being electrically connected with the test signal terminal, a first electrode being electrically connected with the first signal line, and a second electrode being electrically connected with the third node.

8. The test substrate according to claim 1, wherein The data writing sub-circuit includes a second transistor, a third transistor and a first capacitor; a control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode is electrically connected with the data signal line, and a second electrode is electrically connected with a fourth node; one plate of the first capacitor is electrically connected with the first node, and the other plate is electrically connected with the fourth node; The pixel circuit further includes: a second initialization sub-circuit, electrically connected with a fourth scan signal terminal, a third voltage signal line and the first node, and configured to transmit a third voltage signal from the third voltage signal line to the first node under control of a fourth scan signal from the fourth scan signal terminal; a second light-emitting control sub-circuit, electrically connected with a second light-emitting control signal terminal, the second node and a fifth node, and configured to electrically connect the second node with the fifth node under control of a second light-emitting control signal from the second light-emitting control signal terminal; the fifth node is configured to be electrically connected with a light-emitting element; a third initialization sub-circuit, electrically connected with a fifth scan signal terminal, a fourth voltage signal line and the fifth node, and configured to electrically connect the fifth node with the fourth voltage signal line under control of a fifth scan signal from the fifth scan signal terminal; a pull-up sub-circuit, electrically connected with a sixth scan signal terminal, a fifth voltage signal line and the fourth node, and configured to electrically connect the fifth voltage signal line with the fourth node under control of a sixth scan signal from the sixth scan signal terminal; The first signal line includes one of the data signal line, the fourth voltage signal line and the fifth voltage signal line.

9. A display panel, comprising: A pixel circuit comprises a driving transistor, a data writing sub-circuit and a compensation control sub-circuit; wherein a control electrode of the driving transistor is electrically connected with a first node, a first electrode is electrically connected with a second node, a second electrode is electrically connected with a third node, one of the second node and the third node is configured to be coupled to a light emitting element, and the other is configured to be coupled to a power voltage signal terminal; the data writing sub-circuit is electrically connected with a data signal line, a first scan signal terminal and the first node, and is configured to transmit a data signal from the data signal line to the first node under the control of a first scan signal from the first scan signal terminal; the compensation control sub-circuit is electrically connected with a second scan signal terminal, the first node and the second node, and is configured to electrically connect the first node with the second node under the control of a second scan signal from the second scan signal terminal; the pixel circuit is configured to perform threshold voltage compensation and data signal writing on the control electrode of the driving transistor in different time periods of a same display period, respectively. A first signal is electrically connected with the pixel circuit. A test circuit is electrically connected with a test signal terminal, and the test circuit is electrically insulated from at least one of the pixel circuit and the first signal line.

10. The display panel of claim 9, wherein The test circuit is electrically connected with the first signal line and is electrically insulated from the pixel circuit.

11. The display panel of claim 10, wherein, The test circuit comprises a test transistor, and the test transistor comprises: A semiconductor pattern comprising a channel region and a first electrode region and a second electrode region located on both sides of the channel region, respectively; A gate pattern disposed on one side of the semiconductor pattern, and the gate pattern is electrically connected with the test signal terminal; A first connection pattern disposed on a side of the gate pattern away from the semiconductor pattern, and the first connection pattern is electrically connected with the first signal line and the first electrode region, respectively; A second connection pattern, which is made of the same material as the first connection pattern and is disposed in the same layer, comprises a first sub-pattern and a second sub-pattern separated from each other, the first sub-pattern is electrically connected with the second electrode region, and the second sub-pattern is electrically connected with the pixel circuit.

12. The display panel of claim 11, further comprising: A substrate located on a side of the semiconductor pattern away from the gate pattern; A first insulating layer disposed on a side of the first connection pattern and the second connection pattern away from the substrate; Wherein, a first gap is formed between the first connection pattern and the second connection pattern, a second gap is formed between the first sub-pattern and the second sub-pattern; the first insulating layer fills the first gap, and a projection of the first insulating layer on the substrate does not overlap with a projection of the second gap on the substrate.

13. The display panel of claim 12, further comprising: A second insulating layer is disposed on a side of the first insulating layer away from the substrate, the second insulating layer is free of contact with the first connection pattern, the second insulating layer fills the second gap, and covers the sidewalls of the first sub-pattern and the second sub-pattern that are close to each other.

14. The display panel of any one of claims 11-13, wherein, The pixel circuit further comprises a first function sub-circuit electrically connected with a first function control signal terminal, a second signal line and the third node, and configured to electrically connect the second signal line with the third node under control of a first function control signal from the first function control signal terminal; wherein the display panel comprises a plurality of columns of the pixel circuit, and the second signal line is configured to be electrically connected with at least one column of the pixel circuit; The display panel comprises at least one test circuit, the second sub-pattern is electrically connected with the second signal line, and the second sub-pattern is electrically connected with the third node of the pixel circuit through the second signal line.

15. The display panel of claim 14, wherein, The second signal line is configured to be electrically connected with all the pixel circuits; The display panel comprises one test circuit, and the second sub-pattern is electrically connected with the second signal line.

16. The display panel of claim 14, wherein, The pixel circuit further comprises a first function sub-circuit electrically connected with a first function control signal terminal, a second signal line and the third node, and configured to electrically connect the second signal line with the third node under control of a first function control signal from the first function control signal terminal; The display panel comprises a plurality of the pixel circuits and a plurality of the test circuits, and the second sub-pattern of one test transistor is directly electrically connected with the third node of one pixel circuit.

17. The display panel of claim 16, wherein, The first function sub-circuit comprises a light emission control sub-circuit and a first initialization sub-circuit; the light emission control sub-circuit is electrically connected with a first light emission control signal terminal, a first voltage signal line and the third node, and configured to electrically connect the first voltage signal line with the third node under control of a light emission control signal from the first light emission control signal terminal; the first initialization sub-circuit is electrically connected with a third scan signal terminal, a second voltage signal line and the third node, and the first initialization sub-circuit is configured to electrically connect the second voltage signal line with the third node under control of a third scan signal from the third scan signal terminal; The second signal line comprises the first voltage signal line and the second voltage signal line.

18. The display panel of claim 17, wherein, The data writing sub-circuit comprises a second transistor, a third transistor and a first capacitor; a control electrode of the second transistor is electrically connected with the first scan signal terminal, a first electrode is electrically connected with the data signal line, and a second electrode is electrically connected with a fourth node; One plate of the first capacitor is electrically connected to the first node, and the other plate is electrically connected to the fourth node. The pixel circuit further comprises: A second initialization sub-circuit is electrically connected to a fourth scan signal terminal, a third voltage signal line and the first node, and is configured to transmit a first voltage signal from the third voltage signal line to the first node under the control of a fourth scan signal from the fourth scan signal terminal; A second light-emitting control sub-circuit is electrically connected to a second light-emitting control signal terminal, the second node and a fifth node, and is configured to electrically connect the second node and the fifth node under the control of a second light-emitting control signal from the second light-emitting control signal terminal; the fifth node is configured to be electrically connected to a light-emitting element; A third initialization sub-circuit is electrically connected to a fifth scan signal terminal, a third voltage signal line and the fifth node, and is configured to electrically connect the fifth node and the third voltage signal line under the control of a fifth scan signal from the fifth scan signal terminal; A pull-up sub-circuit is electrically connected to a sixth scan signal terminal, a fourth voltage signal line and the fourth node, and is configured to electrically connect the fourth voltage signal line and the fourth node under the control of a sixth scan signal from the sixth scan signal terminal; The first signal line comprises one of the data signal line, the third voltage signal line and the fourth voltage signal line.

19. A preparation method of a display panel, comprising: Preparation of a test substrate; The test substrate comprises the test substrate according to any one of claims 1-9, and the test substrate comprises a driving transistor; Detecting whether the driving transistor of the test substrate meets a preset condition; If the driving transistor of the test substrate meets the preset condition, disconnecting the connection between the test circuit of the test substrate and the pixel circuit and / or the data signal line, and continuing to prepare to form the display panel according to any one of claims 10-18.

20. A display device, comprising: The display panel according to any one of claims 9-18; A driving circuit board electrically connected to the display panel and configured to transmit a control signal to the display panel.

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