Data transmission method based on cloud service system, and cloud service system

Abstract

Disclosed in the present application are a data transmission method based on a cloud service system, and a cloud service system, which method and system can increase the data transmission speed, thus improving the efficiency for processing tasks associated with data. The method of the present application comprises: when a first processor of a first computing node needs to send data to a second processor of a second computing node, the first processor of the first computing node directly writing the data into a first memory area of a first host machine that is allocated to the first processor, and writing a first instruction into a second memory area of the first host machine; the first host machine polling the second memory area, and then determining on the basis of a second instruction obtained by means of polling that the data is stored in the first memory area; and then, the first host machine notifying a first SDI card of the first computing node to read the data from the first memory area, so as to send the data to the second processor of the second computing node.

Description

A data transmission method based on a cloud service system and the cloud service system

[0001] The present application claims priority to the Chinese Patent Application No. 202410650705.1, filed on May 21, 2024, and entitled "A computing cluster and a model training method", and to the Chinese Patent Application No. 202410799293.8, filed on June 19, 2024, and entitled "A data transmission method based on a cloud service system and the cloud service system", the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of cloud technology, and in particular to a data transmission method based on a cloud service system and the cloud service system. BACKGROUND

[0003] With the rapid development of cloud technology, cloud vendors have launched hypernode products in order to provide better cloud services to tenants. A hypernode usually includes multiple computing nodes, each of which can include a host and multiple processors connected to the host. The processors of different computing nodes are connected through a high-speed bus for communication. Therefore, the hypernode can have high computing and network communication capabilities, and can perform complex computing tasks.

[0004] In the related art cloud service system, a source computing node can include a source host, a source processor and a source network card, and a destination computing node can include a target host, a target processor and a target network card. When the source processor needs to send data to the destination processor, the source processor can first write the data to the memory of the source host. Then, the central processing unit (CPU) of the source host writes the data to the communication buffer of the source host. Then, the source network card reads the data from the communication buffer and sends the data to the destination network card, and then to the destination processor, so that the destination processor processes the data to complete the task.

[0005] In the above data transmission process, since multiple data writing is involved, and the CPU of the source host is also involved, CPU resources are occupied, which can affect the speed of data transmission, and thus the efficiency of task processing is low. SUMMARY

[0006] Embodiments of the present application provide a data transmission method based on a cloud service system and the cloud service system, which can improve the speed of data transmission, and thus improve the processing efficiency of tasks associated with data.

[0007] A first aspect of the embodiments of the present application provides a data transmission method based on a cloud service system, the cloud service system comprising infrastructures providing cloud services, the infrastructures comprising a first computing node and a second computing node, the first computing node comprising a first host, a first processor and a first software define infrastructure (SDI) card. The method comprises:

[0008] In the first computing node, when the first processor has data to be transmitted, the first processor can directly write the data into a first memory region of the first host allocated to the first processor, and directly write a first instruction into a second memory region of the first host.

[0009] Since the first host will poll the second memory region, the first host can determine the role played by the first instruction in the second memory region after polling is completed, so as to determine that the first memory region stores the data based on the role.

[0010] After determining that the first memory region stores the data, the first host can notify the first SDI card to read the data from the first memory region. Then, the first SDI card can send the data to the second computing node. Thus, the data transmission is completed.

[0011] As can be seen from the above method, when the first processor of the first computing node needs to send data to the second processor of the second computing node, the first processor of the first computing node can directly write the data into a first memory region of the first host allocated to the first processor, and write a first instruction into a second memory region of the first host. Since the first host will poll the second memory region, it can determine that the first memory region stores the data based on the second instruction obtained by polling. Then, the first host can notify the first SDI card of the first computing node to read the data from the first memory region to send the data to the second processor of the second computing node. As can be seen, in the process of data transmission, after the first processor writes the data into the first host, the first host does not need to participate in any write operation, and the first host only needs to perceive the arrival of the data and notify the first SDI card to directly read the data from the first host, and then complete the data transmission. This can reduce the occupation of too many resources of the first host, improve the speed of data transmission, and further improve the processing efficiency of tasks associated with the data.

[0012] In a possible implementation, the first processor writing the data to be transmitted into the first memory region of the first host computer comprises: the first processor generating the data to be transmitted and storing the data in a third memory region of the first processor; and the first processor copying the data from the third memory region to the first memory region based on an address of the third memory region and an address of the first memory region of the first host computer. In the foregoing implementation, after the first processor generates the data to be transmitted, the first processor can first store the data in the third memory region of the first processor. Since the first processor has determined the address of the first memory region, the first processor can copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host computer. Thus, the first processor can copy the data directly to the first memory region of the first host computer without the participation of the CPU of the first host computer and without occupying the CPU resources in the first host computer.

[0013] In a possible implementation, the second computing node includes a second host, a second processor, and a second SDI card, the first host informs the first SDI card to read data from the first memory area, and the first SDI card sends the data to the second computing node includes that the first host obtains, from the first mapping table, addresses of the third memory area bound to each other, the first memory area, the first SDI card, the second SDI card, and a fourth memory area of the second host, the fourth memory area being a memory area of the second processor allocated to the second host by the second host; the first host provides, based on the address of the first SDI card, the first host to the first SDI card with the address of the first memory area, the address of the second SDI card, and the address of the fourth memory area; the first SDI card reads the data from the first memory area based on the address of the first memory area; and the first SDI card sends, based on the address of the second SDI card, the data and the address of the fourth memory area to the second SDI card, the address of the fourth memory area being used by the second SDI card to write the data into the fourth memory area. In the foregoing implementation, after determining that the first memory area stores the data, the first host can first obtain, from the first mapping table of the first host, addresses of the third memory area bound to each other, the first memory area, the first SDI card, the second SDI card, and the fourth memory area of the second host. Then, based on the addresses bound to each other, the first host can determine that the first SDI card is an SDI card bound to the first memory area, and therefore the first host can provide, based on the address of the first SDI card, the first host to the first SDI card with the address of the first memory area, the address of the second SDI card, and the address of the fourth memory area, so that the first SDI card reads the data from the first memory area based on the address of the first memory area, and sends, based on the address of the second SDI card, the data and the address of the fourth memory area of the first task to the second SDI card. As can be seen, the first host only needs to query the first mapping table to determine from which processor the data comes and to which processor the data is sent, so that the first host does not need to query multiple tables, and resource consumption of the first host can be reduced.

[0014] In a possible implementation, the first host machine provides, to the first SDI card based on the address of the first SDI card, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region, including: the first host machine writes, to a first register of the first SDI card based on the address of the first SDI card, a second instruction; and the first SDI polls the first register to obtain, based on the polled second instruction, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region provided by the first host machine. In the foregoing implementation, the first host machine can write, to the first register of the first SDI card based on the address of the first SDI card, the second instruction. Since the first SDI polls the first register, the first SDI card can obtain, based on the polled second instruction, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region provided by the first host machine. Thus, the first host machine can trigger the first SDI card to perform the data transmission task quickly by directly writing the first register of the first SDI card.

[0015] In a possible implementation, the first instruction and the second instruction are store instructions.

[0016] In a possible implementation, the method further includes: the second SDI card writes data from the first SDI card to a fourth memory region of the second host machine, and causes the second host machine to determine that the data reaches the fourth memory region; the second host machine writes the data from the fourth memory region to a second processor; and the second processor processes the data to obtain a processing result of the data. In the foregoing implementation, after receiving the data from the first SDI card, the second SDI card can write the data to the fourth memory region of the second host machine, and cause the second host machine to perceive that the data reaches the fourth memory region. After the second host machine perceives that the data reaches the fourth memory region, since the fourth memory region is a memory region allocated to the second processor of the second computing node, the second host machine can write the data from the fourth memory region to the second processor directly, so that the second processor processes the data to obtain a processing result of the data, thereby meeting the data processing requirement of the tenant.

[0017] In a possible implementation, the second SDI card writes the data from the first SDI card to the fourth memory region, and causes the second host to determine that the data is stored in the fourth memory region, including: the second SDI card writes the data to the fourth memory region based on the address of the fourth memory region, and provides the address of the fourth memory region, the address of the first SDI card and the address of the second SDI card to the second host, so that the second host determines that the data reaches the fourth memory region of the second host. In the foregoing implementation, after receiving the data from the first SDI card and the address of the fourth memory region of the second host, the second SDI card can write the data to the fourth memory region based on the address of the fourth memory region. Then, the second SDI card can provide the address of the fourth memory region, the address of the first SDI card and the address of the second SDI card to the second host, so that the second host determines that the data is stored in the fourth memory region based on the information.

[0018] In a possible implementation, the second host writes the data from the fourth memory region to the second processor, including: the second host obtains, from the second mapping table, the address of the fifth memory region of the second processor that is bound with the address of the fourth memory region, the address of the first SDI card and the address of the second SDI card; and the second host copies the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region. In the foregoing implementation, the second host determines that the data reaches the fourth memory region, and therefore obtains, from the second mapping table, the address of the fifth memory region of the second processor that is bound with the address of the fourth memory region, the address of the first SDI card and the address of the second SDI card. Then, the second host can copy the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region. In this way, the second host only needs to query the second mapping table to determine from which processor the data comes and to which processor the data is sent, and therefore, the second host does not need to query multiple tables, and the resource consumption of the second host can be reduced.

[0019] In a possible implementation, the second processor processes the data, and obtaining the processing result of the data comprises: the second processor polls a second register of the second processor to determine that the data is stored in the fifth memory region based on a third instruction obtained through the polling, the third instruction being written into the second register by the second host; and the second processor obtains the data from the fifth memory region based on the address of the fifth memory region and processes the data to obtain the processing result of the data. In the foregoing implementation, after the second host writes the data into the fifth memory region, the second host can also write the third instruction into the second register of the second processor. Since the second processor polls the second register, the second processor can determine that the data is stored in the fifth memory region based on the third instruction obtained through the polling. Then, the second processor can obtain the data from the fifth memory region based on the address of the fifth memory region and process the data, thereby obtaining the processing result of the data. It can be seen that the second host or the second SDI card can quickly notify the second processor that the data has arrived by directly writing the second register of the second processor, without kernel mode switching overhead and in-out queue overhead.

[0020] A second aspect of the embodiment of the application provides a cloud service system, the cloud service system comprising an infrastructure providing a cloud service, the infrastructure comprising a first computing node and a second computing node, the first computing node comprising a first host, a first processor, and a first SDI card; the first processor is configured to write data to be transmitted into a first memory region of the first host and write a first instruction into a second memory region of the first host, the first memory region being a memory region allocated to the first processor by the first host; the first host is configured to poll the second memory region to determine that the first memory region stores the data based on the first instruction obtained through the polling; the first host is further configured to notify the first SDI card to read the data from the first memory region; and the first SDI card is configured to send the data to the second computing node.

[0021] In a possible implementation, the first processor is configured to: generate data to be transmitted and store the data in a third memory region of the first processor; and copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host.

[0022] In a possible implementation, the second computing node comprises a second host, a second processor, and a second SDI card; the first host is configured to: obtain, from the first mapping table, an address of the third memory region, an address of the first memory region, an address of the first SDI card, an address of the second SDI card, and an address of a fourth memory region of the second host, the fourth memory region being a memory region of the second host allocated to the second processor; provide, based on the address of the first SDI card, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region to the first SDI card; and the first SDI card is configured to: read data from the first memory region based on the address of the first memory region; and send, based on the address of the second SDI card, the data and the address of the fourth memory region to the second SDI card, the address of the fourth memory region being used by the second SDI card to write the data into the fourth memory region.

[0023] In a possible implementation, the first host is configured to write, based on the address of the first SDI card, the second instruction into a first register of the first SDI card; and the first SDI card is configured to poll the first register to obtain, based on the second instruction polled, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region provided by the first host.

[0024] In a possible implementation, the first instruction and the second instruction are store instructions.

[0025] In a possible implementation, the second SDI card is configured to write, based on the address of the fourth memory region, the data into the fourth memory region of the second host, and cause the second host to determine that the data reaches the fourth memory region; the second host is configured to write the data from the fourth memory region to the second processor; and the second processor is configured to process the data to obtain a processing result of the data.

[0026] In a possible implementation, the second SDI card is configured to write, based on the address of the fourth memory region, the data into the fourth memory region, and provide, to the second host, the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card, so that the second host determines that the data reaches the fourth memory region of the second host.

[0027] In a possible implementation, the second host is configured to: obtain, from the second mapping table, an address of a fifth memory region of the second processor bound with the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card; and copy, based on the address of the fourth memory region and the address of the fifth memory region, the data from the fourth memory region to the fifth memory region.

[0028] In a possible implementation, the second processor is configured to: poll a second register of the second processor to determine, based on a third instruction obtained through the polling, that the data is stored in the fifth memory region, the third instruction being written into the second register by the second host; and obtain the data from the fifth memory region based on an address of the fifth memory region, and process the data to obtain a processing result of the data.

[0029] A third aspect of the embodiments of the present application provides a computing device cluster, the computing device cluster comprising at least one computing device, each computing device comprising a processor and a memory: the memory is configured to store instructions; and the processor is configured to execute the method according to the first aspect or any possible implementation manner of the first aspect according to the instructions.

[0030] A fourth aspect of the embodiments of the present application provides a computer storage medium, the computer storage medium storing one or more instructions, the instructions causing one or more computers to implement the method according to the first aspect or any possible implementation manner of the first aspect when executed by the one or more computers.

[0031] A fifth aspect of the embodiments of the present application provides a computer program product, the computer program product storing instructions, the instructions causing a computer to implement the method according to the first aspect or any possible implementation manner of the first aspect when executed by the computer.

[0032] In the embodiments of the present application, when the first processor of the first computing node needs to send data to the second processor of the second computing node, the first processor of the first computing node can write the data into a first memory region of the first host allocated to the first processor, and write a first instruction into a second memory region of the first host. Since the first host will poll the second memory region, the first host can determine, based on a second instruction obtained through the polling, that the first memory region stores the data. Then, the first host can notify the first SDI card of the first computing node to read the data from the first memory region allocated to the first memory region, so as to send the data to the second processor of the second computing node. As can be seen, in the process of data transmission, after the first processor writes the data into the first host, the first host does not need to participate in any write operation, and the first host only needs to perceive the arrival of the data and notify the first SDI card to read the data directly from the first host, and then complete the data transmission, which can reduce the occupation of too many resources of the first host, improve the speed of data transmission, and further improve the processing efficiency of the task associated with the data. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 is a structural schematic diagram of a cloud service system provided by the embodiments of the present application;

[0034] Fig. 2a is a structural schematic diagram of a super cluster according to an embodiment of the present application;

[0035] Fig. 2b is a structural schematic diagram of a computing node according to an embodiment of the present application;

[0036] Fig. 3 is a schematic diagram of a mapping table according to an embodiment of the present application;

[0037] Fig. 4 is a flow schematic diagram of a data transmission method based on a cloud service system according to an embodiment of the present application;

[0038] Fig. 5a is a schematic diagram of data transmission according to an embodiment of the present application;

[0039] Fig. 5b is another schematic diagram of data transmission according to an embodiment of the present application;

[0040] Fig. 6 is another schematic diagram of data transmission according to an embodiment of the present application;

[0041] Fig. 7 is another structural schematic diagram of a cloud service system according to an embodiment of the present application;

[0042] Fig. 8 is a structural schematic diagram of a computing device according to an embodiment of the present application;

[0043] Fig. 9 is a structural schematic diagram of a computing device cluster according to an embodiment of the present application;

[0044] Fig. 10 is a schematic diagram of a network connection of computing devices in a computer cluster according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application provide a data transmission method based on a cloud service system and a cloud service system, which can improve the speed of data transmission and further improve the processing efficiency of tasks associated with data.

[0046] The terms "first", "second", and the like in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, which is only a distinguishing way used in the description of the embodiments of the present application to describe the objects with the same properties. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or devices containing a series of units do not have to be limited to those units, but can include other units not clearly listed or inherent to these processes, methods, products or devices.

[0047] With the rapid development of cloud technology, cloud vendors have launched supernode products in order to provide tenants with better cloud services. A supernode usually contains multiple computing nodes, each computing node contains a host and multiple processors (such as graphics processing units (GPUs) or neural network processing units (NPUs), etc.) connected to the host, and the processors of different computing nodes are connected through high-speed bus communication. Therefore, the supernode can have high-performance computing and network communication capabilities, and can perform complex computing tasks (such as model training tasks in the field of artificial intelligence (AI), etc.).

[0048] In a related art cloud service system, a source computing node can include a source host, a source processor, and a source network card, and a destination computing node can include a target host, a target processor, and a target network card. When the source processor needs to send data to the destination processor, the source processor can first write the data to the memory of the source host. Then, the CPU of the source host writes the data to the communication buffer of the source host. Then, the source network card reads the data from the communication buffer and sends the data to the destination network card, so that the destination network card sends the data to the destination processor through the destination host, and then the destination processor processes the data to complete the task.

[0049] In the above data transmission process, since multiple data writes are involved, and the CPU of the source host is also involved, it will occupy a certain CPU resource, which can easily affect the speed of data transmission, and thus cause the efficiency of task processing to be low.

[0050] To solve the above problems, an embodiment of the present application provides a data transmission method based on a cloud service system. The method can be implemented through a cloud service system (such as a public cloud system, etc.). FIG. 1 is a structural schematic diagram of a cloud service system according to an embodiment of the present application. As shown in FIG. 1, the cloud service system includes infrastructure that can provide cloud services and a cloud management platform that manages these infrastructures. The cloud management platform and the infrastructure will be introduced respectively as follows:

[0051] The cloud management platform can manage the infrastructure in the whole cloud service system (for example, in the infrastructure, according to the instructions of a tenant, create a hypercluster serving the tenant for the tenant, the hypercluster can include multiple supernodes, the multiple supernodes can be communicatively connected, and thus jointly process the tasks of the tenant, for example, model training tasks in the AI field). The cloud management platform can also be open to tenants outside the cloud service system and respond to their requests. For example, the cloud management platform can provide various interfaces such as a login interface and a task processing interface for the client of the tenant (for example, a terminal device used by the tenant or a browser on the terminal device, etc.) to access. Among them, the cloud management platform can authenticate the client of the tenant through the login interface, and allow the client of the tenant to log in to the cloud management platform after successful authentication. For another example, the cloud management platform can also allow the client of the tenant to send the task to be processed of the tenant to the cloud management platform through the task processing interface, and the cloud management platform can call the hypercluster serving to process the task of the tenant to return the processing result of the task to the tenant.

[0052] The infrastructure includes a hypercluster serving the tenant, as shown in FIG. 2a (FIG. 2a is a structural schematic diagram of a hypercluster provided by an embodiment of the present application), the hypercluster includes multiple supernodes, each supernode can include multiple computing nodes (nodes), which are introduced below from two aspects of hardware and software respectively:

[0053] From the hardware aspect, for any one of the plurality of computing nodes, the computing node comprises a host, a plurality of processors connected to the host, and a plurality of software define infrastructure (SDI) cards. The host of the computing node can be connected to the plurality of processors of the computing node and the plurality of SDI cards of the computing node through a peripheral component interconnect express (PCIe) interface, and the host of the computing node, the plurality of processors of the computing node, and the plurality of SDI cards of the computing node each have an independent CPU and memory. The host of the computing node, the plurality of processors of the computing node, and the plurality of SDI cards of the computing node can work cooperatively, the plurality of processors of the computing node read and write the memory on the host of the computing node without the participation of the CPU of the host of the computing node, and after the host of the computing node submits a data transmission task, the subsequent interface and sending of data do not need the participation of the host of the computing node. The SDI card of the computing node comprises a CPU, a memory, and a door bell (DB) register, the DB register triggers the SDI card of the computing node to execute a data transmission task, and it can be directly written by a forwarding module of the host of the computing node in a user state without kernel state switching overhead. The processor of the computing node mainly comprises a computing processor (for example, when the processor is an NPU, the computing processor of the NPU can be an AI CORE, etc.), a high bandwidth memory (HBM), and a Notify register and the like, and the Notify register can also be directly written by a forwarding module of the host of the computing node or a TA module of the SDI card of the computing node in a user state without kernel state switching and in-out queue overhead.

[0054] As shown in FIG. 2b (which is a structural diagram of a computing node provided by an embodiment of the present application), from the software aspect, for any one of the computing nodes, the host of the computing node, the processors of the computing node, and the SDI cards of the computing node all have independent operating systems (running on the CPUs of the host of the computing node, the processors of the computing node, and the SDI cards of the computing node). The operating system of the host of the computing node contains a forwarding module, which can manage the receiving and sending of data between the processors of the computing node, the host of the computing node, and the SDI cards of the computing node. The operating system of the processors of the computing node contains a scheduler, which can manage the receiving and sending of data between the processors of the computing node and the host of the computing node. The operating system of the SDI cards of the computing node contains a transaction (TA) module, which can manage the receiving and sending of data between the computing node and the rest of the computing nodes. It should be noted that the related introduction of the receiving and sending of data will not be expanded here.

[0055] It is worth noting that for any one of the computing nodes, the memory of the processors of the computing node can contain a special memory area, which can be referred to as Segment 1, and Segment 1 is used to store the data required to be sent or interfaced by the processors of the computing node. The memory of the host of the computing node can contain four special memory areas, which are Segment 2, Trigger, a mapping table, and a communication queue, which will be introduced respectively as follows:

[0056] (1) Segment 2 can also be referred to as a communication buffer, and the processors of the computing node and the SDI cards of the computing node can all directly read and write Segment 2. It is worth noting that since the host of the computing node is connected with multiple processors, the host of the computing node will allocate a corresponding piece of Segment 2 to each processor connected thereto, that is, for the multiple processors of the computing node, each processor has a dedicated Segment 2 in the host of the computing node.

[0057] (2) Trigger is used for the processors of the computing node to notify the forwarding module of the host of the computing node whether the data to be transmitted is ready, and Trigger can also be directly written by the processors of the computing node in the user state, and the arrival of data can be quickly perceived in the user state.

[0058] (3) The mapping table is used to store information related to the transmission channel. The forwarding module of the host of the computing node can query the mapping table to determine which processor of the computing node or which processor of the remaining computing node the data is sent to. As shown in FIG. 3 (which is a schematic diagram of the mapping table provided in an embodiment of the present application), when a processor of the computing node needs to establish a transmission channel with a processor of another computing node, the forwarding module of the host of the computing node can add a tag in the mapping table. The tag records the mutually bound dChannel and nChannel. The dChannel is a channel between a processor of the computing node and the host of the computing node, and the nChannel is a channel between the host of the computing node and the host of another computing node. Then, the dChannel and the nChannel can be combined to form a transmission channel established between the processor of the computing node and the processor of another computing node. The information contained in the dChannel and the nChannel is different according to different transmission protocols based on which the dChannel and the nChannel are established. For example, when the dChannel and the nChannel adopt the remote direct memory access (RDMA) protocol, the dChannel includes the (memory) address of Segment 1 of the processor of the computing node and the (memory) address of Segment 2 of the host of the computing node (the Segment 2 is the Segment 2 allocated to the processor), and the nChannel includes the (network) address of an SDI card of the computing node and the (network) address of an SDI card of another computing node, and even can include the address of Segment 2 of the host of another computing node (the Segment 2 is the Segment 2 allocated to the processor of another computing node). As can be seen, the mutually bound pair of dChannel and nChannel recorded in the mapping table of the computing node describes a transmission channel established between the processor of the computing node and the processor of another computing node.

[0059] To further understand the mapping table, a specific application example is introduced below. As shown in FIG. 3, assume that a certain supernode of a tenant contains a computing node 1, a computing node 2,..., and a computing node n. For the computing node 1, a plurality of NPUs and a plurality of SDI cards are connected to a host 1. The host 1 maintains a mapping table containing a plurality of table entries. A table entry 1 records a mutual binding of a dChannel 1 and an nChannel 2. The dChannel 1 contains an address of a Segment 1 of an NPU 1 and an address of a Segment 2-1 of the host 1, and the Segment 2-1 is a Segment 2 allocated by the host 1 to the NPU 1. The nChannel 2 contains an address of an SDI card 1, an address of an SDI card 3 of the computing node 2, and an address of a Segment 2-9 of a host 2 of the computing node 2, and the Segment 2-9 is a Segment 2 allocated by the host 2 to an NPU 9 of the computing node 2.

[0060] As can be seen, the dChannel 1 (between the Segment 1 of the NPU 1 and the Segment 2-1 of the host 1) and the nChannel 2 (between the Segment 2-1 of the host 1 and the Segment 2-9 of the host 2) form a transmission channel constructed between the NPU 1 and the NPU 9, and the transmission channel indicates that the host 1 binds the Segment 1 of the NPU 1, the Segment 2-1 of the host 1, the SDI card 1, the SDI card 3, the Segment 2-9 of the host 2, and the NPU 9, and data can be transmitted from the Segment 1 of the NPU 1 to the Segment 1 of the NPU 9 along the transmission channel. As for the remaining dChannels and nChannels in the mapping table, they are similar, and thus are not described herein.

[0061] (4) The communication queue includes a work queue (WQ) and a completion queue (CQ), the WQ is used to submit a data transmission task, and the CQ is used to submit a task completion notification, wherein description information of the data transmission task can be saved in a work queue element (WQE). When the forwarding module of the host of the computing node determines that data arrives, the forwarding module can generate a WQE and submit the WQE to the WQ, so that the SDI card of the computing node takes out the WQE from the WQ, reads data in the host of the computing node based on the WQE, and sends the data to the SDI card of another computing node, so as to complete data transmission. The completion information of the data transmission task is saved in a completion queue element (CQE), and the SDI card of another computing node can generate a CQE and submit the CQE to the CQ after receiving data, to notify the forwarding module of the host of another computing node that data transmission is completed.

[0062] Further, in the embodiments of the present application, any two computing nodes in communication can be located in the same super node or in different super nodes, which is not limited here.

[0063] Further, in the embodiments of the present application, for the computing nodes in the super node, the computing nodes can be cloud instances in the infrastructure, and the cloud instances can be presented in various ways, for example, the cloud instances can be physical servers selected by a cloud management platform, for example, the cloud instances can be bare metal servers selected by a cloud management platform, and the like.

[0064] Further, in the embodiments of the present application, for the multiple super nodes of the tenant, the multiple super nodes can be deployed in the same site or different sites, and the site can be presented in various forms, for example, the site can be a region in the infrastructure, for example, the site can be an availability zone in the infrastructure, for example, the site can be a data center (DC) in the infrastructure, for example, the site can be a room in the infrastructure, for example, the site can be a rack in the infrastructure, and the like.

[0065] Based on the cloud service system, in the plurality of computing nodes serving the tenants, when a source processor (a processor of a plurality of processors of a source computing node) of a source computing node (a computing node in a certain supernode) needs to send data to a destination processor (a processor of a plurality of processors of a destination computing node) of a destination computing node (another computing node of the supernode or a computing node of another supernode), the source processor of the source computing node can directly write the data into a memory region of the source host machine allocated to the source processor, and write a certain instruction into another memory region of the source host machine. Since the source host machine will poll the other memory region, it can determine that the memory region allocated to the source processor stores the data based on the instruction obtained by polling. Then, the source host machine can notify the source SDI card (a SDI card of a plurality of SDI cards of the source computing node) of the source computing node to read the data from the memory region allocated to the source processor to send the data to the destination processor of the destination computing node. As can be seen, in the process of data transmission, after the source processor writes the data into the source host machine, the source host machine does not need to participate in any write operation, and the source host machine only needs to perceive the arrival of the data and notify the source SDI card to directly read the data from the source host machine, and then complete the data transmission, which can reduce the occupation of the resources of the source host machine and improve the speed of data transmission, thereby improving the processing efficiency of the task associated with the data. In order to further understand the workflow of the foregoing cloud service system, the following will further introduce the workflow in combination with FIG. 4, which is a flowchart of a data transmission method based on a cloud service system provided by an embodiment of the present application. The method can be implemented by the cloud service system shown in FIG. 1, which includes an infrastructure providing cloud services, and the infrastructure includes a first computing node (also referred to as a source computing node) and a second computing node (also referred to as a destination computing node). The first computing node includes a first host machine (also referred to as a source host machine), a first processor (also referred to as a source processor), and a first SDI card (also referred to as a source SDI card). The second computing node includes a second host machine (also referred to as a destination host machine), a second processor (also referred to as a destination processor), and a second SDI card (also referred to as a destination SDI card). The method includes:

[0066] 401. The first processor writes the data to be transmitted into a first memory region of the first host machine, and writes a first instruction into a second memory region of the first host machine. The first memory region is a memory region of the first host machine allocated to the first processor.

[0067] In this embodiment, when the first processor of the first computing node has data to be transmitted, the first processor can directly write the data to the first memory region of the first host of the first computing node, and directly write the first instruction to the second memory region of the first host. It should be noted that the first memory region is a memory region allocated by the first host to the first processor, and the second instruction is used to make the first host perceive that the first memory region stores the data.

[0068] Specifically, the first processor can write the data to the first memory region in the following manner:

[0069] After the first processor generates the data to be transmitted, the first processor can first store the data in the third memory region of the first processor. Since the first processor has obtained the address of the first memory region allocated by the first host to the first processor in advance, the first processor can directly copy the data from the third memory region to the first memory region based on the address of the third memory region and the address of the first memory region of the first host (the two addresses constitute the dChannel between the first processor and the first host).

[0070] For example, as shown in FIGS. 5a and 5b (FIG. 5a is a schematic diagram of data transmission provided by an embodiment of the present application, and FIG. 5b is another schematic diagram of data transmission provided by an embodiment of the present application), for the convenience of description, the examples shown in FIGS. 5a and 5b are divided into multiple steps and introduced respectively.

[0071] Step 1: When the AI core of the NPU1 of the computing node 1 generates data to be transmitted, the AI core of the NPU1 can first write the data to the segment1 (i.e., the third memory region described above) of the NPU1, and make the scheduler of the NPU1 perceive that the segment1 of the NPU1 stores the data, and can start data copying.

[0072] Step 2: Since the scheduler of the NPU1 has determined the dChannel (the dChannel contains the address of the segment1 of the NPU1 and the address of the segment2-1 of the host1) between the segment2-1 (i.e., the second memory region described above) of the host1 of the computing node 1 and the segment1 of the NPU1, and the dChannel is dChannel1, the scheduler of the NPU1 can copy the data from the segment1 of the NPU1 to the segment2-1 of the host1 through the dChannel1.

[0073] Step 3: When the data copying is completed, the scheduler of NPU1 can write the store instruction (i.e., the first instruction mentioned above) into the Trigger (i.e., the second memory area mentioned above), and the store instruction can set the flag associated with segment2-1 in the Trigger. Therefore, the forwarding module of host1 can find that the flag has been set when polling the Trigger, and thus can determine that segment2-1 stores the data.

[0074] 402. The first host machine polls the second memory area to determine that the first memory area stores the data based on the first instruction obtained by polling.

[0075] Since the first host machine polls the second memory area, the first host machine can determine that the first memory area stores the data based on the first instruction obtained by polling (i.e., find the role played by the first instruction in the second memory area).

[0076] Still as in the above example, step 4: The forwarding module of host1 finds that the flag associated with segment2-1 in the Trigger has been set by polling the Trigger, and thus can determine that segment2-1 stores the data.

[0077] 403. The first host machine instructs the first SDI card to read the data from the first memory area, and the first SDI card sends the data to the second SDI card.

[0078] After determining that the first memory area stores the data, the first host machine can instruct the first SDI card of the first computing node to read the data from the first memory area, and thus the first SDI card can send the data to the second SDI card of the second computing node. It should be noted that the first SDI card is an SDI card bound with the first host machine, and the second SDI card is an SDI card bound with the first SDI card.

[0079] Specifically, the first host machine can make the first SDI card obtain and send the data in the following ways:

[0080] After determining that the first memory region stores the data, the first host can first acquire, from the first mapping table of the first host, a dchannel between the third memory region of the first processor and the first memory region of the first host (the dchannel includes the address of the third memory region and the address of the first memory region), since the dchannel is bound with an nchannel, the nchannel is an nchannel between the first memory region of the first host and the fourth memory region of the second host (the nchannel includes the address of the first SDI card, the address of the second SDI card and the address of the fourth memory region of the second host), and the fourth memory region is a memory region allocated by the second host to the second processor.

[0081] Then, based on the dchannel and the nchannel bound with each other, the first host can determine that the first SDI card is the SDI card bound with the first memory region, and thus the first host can take the address of the first memory region in the dchannel, the address of the second SDI card in the nchannel and the address of the fourth memory region as a first task, and submit the first task to the first task queue.

[0082] Then, based on the address of the first SDI card in the nchannel, the first host can instruct the first SDI to acquire the first task from the first task queue. After obtaining the first task, the first SDI card can read the data from the first memory region based on the address of the first memory region in the first task. Subsequently, the first SDI card can send the data and the address of the fourth memory region in the first task to the second SDI card based on the address of the second SDI card in the first task.

[0083] More specifically, the first host can instruct the first SDI card by the following way:

[0084] The first host can write a second instruction to a first register of the first SDI card based on the address of the first SDI card in the nchannel. Since the first SDI card will poll the first register, the first SDI card can determine that there is a first task to be processed in the first task queue based on the second instruction obtained by polling (i.e. the role played by the second instruction in the first register is found), and thus the first SDI card can acquire the first task from the first task queue, which is equivalent to acquiring the address of the first memory region, the address of the second SDI card and the address of the fourth memory region.

[0085] Still as the above example, step 5: the forwarding module of host 1 can find dChannell between Segmentl of NPU 1 and Segment2-1 of host 1 from the mapping table (i.e. the first mapping table mentioned above), then the forwarding module of host 1 can further find nChannel2 bound with dChannell from the mapping table, nChannel2 is the nChannel between Segment2-1 of host 1 and Segment2-9 of host 2.

[0086] Step 6: the forwarding module of host 1 can generate a WQE (i.e. the first task mentioned above) with the address of Segment2-1 of host 1 in dChannell, the address of SDI card 2 in nChannel and the address of Segment2-9 of host 2, and submit the WQE to a WQ (i.e. the first task queue mentioned above).

[0087] Step 7: the forwarding module of host 1 writes a store instruction (i.e. the second instruction mentioned above) into the DB register (i.e. the first register mentioned above) of SDI card 1 based on the address of SDI card 1 in nChannel, to set the DB register.

[0088] Step 8: since the TA module of SDI card 1 polls the DB register, the TA module of SDI card 1 can sense that the DB register is set, and determine that there is a WQE to be processed in the WQ.

[0089] Step 9: the TA module of SDI card 1 gets the WQE from the WQ.

[0090] Step 10: the TA module of SDI card 1 can extract the address of Segment2-1 of host 1, the address of SDI card 2 and the address of Segment2-9 of host 2 from the WQE, read the data from Segment2-1 of host 1 based on the address of Segment2-1 of host 1, and send the data and the address of Segment2-9 of host 2 to SDI card 2 based on the address of SDI card 2.

[0091] 404、the second SDI card writes the data into the fourth memory area of the second host computer and causes the second host computer to determine that the data reaches the fourth memory area.

[0092] After receiving the data from the first SDI card, the second SDI card of the second computing node can write the data into the fourth memory area of the second host computer of the second computing node, and cause the second host computer to sense that the data reaches the fourth memory area.

[0093] In particular, the first SDI card can make the second host perceive that the data has arrived by the following way:

[0094] After receiving the data from the first SDI card and the address of the fourth memory region of the second host, the second SDI card can write the data into the fourth memory region based on the address of the fourth memory region. Then, the second SDI card can use the address of the fourth memory region, the address of the first SDI card and the address of the second SDI card as a second task, and submit the second task to a second task queue of the second host. Since the second host will poll the second task queue, the second host can obtain the second task from the second task queue to determine that the data has been stored in the fourth memory region based on the second task.

[0095] Still as the above example, steps 11-12: Since the communication connection between the SDI card 1 and the SDI card 2 is realized through a virtual private cloud (VPC), the TA module of the SDI card 1 can send the data and the address of Segment2-9 of host2 to the TA module of the SDI card 2 through the VPC.

[0096] Step 13: The TA module of the SDI card 2 can write the data into Segment2-9 of host2 (i.e. the fourth memory region mentioned above) based on the address of Segment2-9 of host2.

[0097] Step 14: The TA module of the SDI card 2 can use the address of Segment2-9 of host2, the address of the SDI card 1 and the address of the SDI card 2 as a CQE (i.e. the second task mentioned above), that is, use nChannel2 as the CQE and add it to the CQ of host2 (i.e. the second task queue mentioned above).

[0098] Step 15: The forwarding module of host2 will poll the CQ, and can obtain the CQE from the CQ and determine that the data has reached Segment2-9 of host2 based on the CQE.

[0099] 405、The second host writes the data from the fourth memory region to the second processor.

[0100] 406、The second processor processes the data to obtain a processing result of the data.

[0101] The second host machine is aware of the data reaching the fourth memory area. Since the fourth memory area is a memory area allocated to the second processor of the second computing node, the second host machine can directly write the data from the fourth memory area to the second processor, so that the second processor processes the data to obtain a processing result of the data. At this point, the data transmission and data processing are completed, and the task processing requirement of the tenant associated with the data is met.

[0102] Specifically, the second host machine can write the data to the second processor in the following manner:

[0103] The second host machine has obtained the second task, and the second task includes the address of the fourth memory area, the address of the first SDI card, and the address of the second SDI card, that is, the second task includes nchannel between the first memory area of the first host machine and the fourth memory area of the second host machine. Therefore, the second host machine obtains dchannel bound to the nchannel from the second mapping table, and the dchannel is dchannel between the fifth memory area of the second processor and the fourth memory area of the second host machine, that is, the dchannel includes the address of the fourth memory area of the second host machine and the address of the fifth memory area of the second processor. Then, the second host machine can directly copy the data from the fourth memory area to the fifth memory area based on the address of the fourth memory area and the address of the fifth memory area.

[0104] Still as in the above example, step 16: Since the CQE includes nChannel2, the forwarding module of host2 can obtain dchannel21 bound to nChannel2 from the mapping table of host2 (i.e., the second mapping table mentioned above), and dchannel21 includes the address of Segment2-9 of host2 and the address of Segment1 of NPU9.

[0105] Step 17: Since dchannel21 includes the address of Segment2-9 of host2 and the address of Segment1 of NPU9, the forwarding module of host2 can directly copy the data from Segment2-9 of host2 to Segment1 of NPU9 (i.e., the fifth memory area mentioned above) based on these two addresses, that is, based on dchannel21.

[0106] More specifically, the second processor can process the data in the following manner:

[0107] After the second host computer writes the data into the fifth memory region, the second host computer can also write a third instruction into the second register of the second processor. Since the second processor polls the second register, the second processor can determine that the data is stored in the fifth memory region based on the third instruction obtained by polling (i.e., the role played by the third instruction in the second register). Then, the second processor can obtain the data from the fifth memory region based on the address of the fifth memory region, and process the data to obtain a processing result of the data.

[0108] Still as in the above example, after the copying of the data is completed, the forwarding module of host2 can use a store instruction (i.e., the third instruction described above) to directly write the Notify register (i.e., the second register described above) of NPU9 to set the Notify register.

[0109] After the copying of the data is completed, the forwarding module of host2 can use a store instruction (i.e., the third instruction described above) to directly write the Notify register (i.e., the second register described above) of NPU9 to set the Notify register.

[0110] It should be understood that in the embodiments of the present application, the first SDI card can also only send the data to the second SDI card, without sending the address of the fourth memory region, and even the first mapping table does not contain the address of any memory region of the destination (e.g., the address of the fourth memory region). In this case, after receiving the data, the second SDI card will randomly write the data into any memory region in the second host computer, and inform the second host computer that the data is stored in the memory region, so that the second host computer can subsequently write the data from the memory region to the second processor. The writing process is the same as the process of writing the data from the fourth memory region to the second processor, which will not be described again here. It should be noted that the memory region is no longer the memory region allocated by the second host computer to the second processor.

[0111] It should also be understood that, in the embodiments of the present application, after the second SDI card receives the data and writes the data into the fourth memory area of the second host, since the second SDI card has determined the address of the fourth memory area, the address of the first SDI card and the address of the second SDI card, i.e. nchannel between the first memory area of the first host and the fourth memory area of the second host, the second SDI card can also directly query the second mapping table of the second host to obtain the dchannel bound with the nchannel. Since the dchannel contains the address of the fourth memory area of the second host and the address of the fifth memory area of the second processor, the second SDI card can copy the data from the fourth memory area to the fifth memory area, and the second SDI card informs the second processor to read and process the data from the fifth memory area.

[0112] For example, as shown in FIG. 6 (FIG. 6 is another schematic diagram of data transmission provided by the embodiments of the present application), steps 1-2: after the TA module of the SDI card 2 receives the data and the address of Segment 2-9 of host 2, the TA module of the SDI card 2 can write the data into Segment 2-9 of host 2 based on the address of Segment 2-9 of host 2.

[0113] Step 3: since the TA module of the SDI card 2 has determined nChannel2, the TA module of the SDI card 2 can obtain dchannel21 bound with nChannel2 from the mapping table of host 2, and dchannel21 contains the address of Segment 2-9 of host 2 and the address of Segment 1 of NPU 9.

[0114] Step 4: the TA module of the SDI card 2 can directly copy the data from Segment 2-9 of host 2 to Segment 1 of NPU 9 based on dchannel21.

[0115] Steps 5-6: after the copying of the data is completed, the TA module of the SDI card 2 can use the store instruction to directly write the Notify register of NPU 9 to set the Notify register. The scheduler of NPU 9 will poll the Notify register, and after finding that the Notify register is set, the scheduler of NPU 9 determines that Segment 1 of NPU 9 stores the data, so the scheduler of NPU 9 informs the AI core of NPU 9 to read the data from Segment 1 of NPU 9 and process the data.

[0116] In the embodiment of the present application, when the first processor of the first computing node needs to send data to the second processor of the second computing node, the first processor of the first computing node can directly write the data into the first memory region of the first host machine allocated to the first processor, and write the first instruction into the second memory region of the first host machine. Since the first host machine will poll the second memory region, it can determine that the first memory region stores the data based on the second instruction obtained by polling. Then, the first host machine can notify the first SDI card of the first computing node to read the data from the first memory region allocated to the first memory region, so as to send the data to the second processor of the second computing node. As can be seen, in the process of data transmission, after the first processor writes the data into the first host machine, the first host machine does not need to participate in any write operation, and the first host machine only needs to perceive the arrival of the data and notify the first SDI card to directly read the data from the first host machine, and then complete the data transmission, which can reduce the occupation of too many resources of the first host machine, improve the speed of data transmission, and further improve the processing efficiency of the task associated with the data.

[0117] Further, in the embodiment of the present application, the first processor can directly copy the data to the first memory region of the first host machine through the synchronous direct memory access (SDMA) technology (of course, the embodiment of the present application is not limited to this technology, and the first processor can also copy data through other technologies, which is not limited here), without occupying the CPU resources in the first host machine. Moreover, the first processor can complete data copying in the user state, without kernel state switching overhead. Moreover, the first processor can directly write the second memory region, so as to make the first host machine perceive that the data has arrived at the first memory region, and this process has no interruption overhead.

[0118] Further, in the embodiment of the present application, the first host machine and the second host machine can respectively quickly query the first mapping table and the second mapping table, since the first mapping table and the second mapping table both contain the dChannel and the nChannel bound to each other, the first host machine and the second host machine can quickly determine which processor the data comes from and which processor the data is sent to, and for the first host machine and the second host machine, only one mapping table of itself needs to be queried, without the need to query multiple tables, which is beneficial to improve the efficiency of data transmission.

[0119] Further, in the embodiment of the present application, the first host computer can directly write the first register of the first SDI card to quickly trigger the first SDI card to perform the data transmission task. Moreover, the first host computer submits the first task in the user mode, and the first SDI card can read the first task in the user mode without kernel mode switching overhead. Moreover, the data is transmitted between the first host computer, the first processor and the first SDI card by using the RDMA protocol without using the kernel protocol stack.

[0120] Further, in the embodiment of the present application, the second host computer or the second SDI card directly writes the second register of the second processor to quickly notify the second processor that the data has arrived, without kernel mode switching overhead and the overhead of entering and exiting the queue.

[0121] The above is a detailed description of the data transmission method based on the cloud service system provided by the embodiment of the present application. The cloud service system provided by the embodiment of the present application will be introduced below. FIG. 7 is another structure schematic diagram of the cloud service system provided by the embodiment of the present application. As shown in FIG. 7, the cloud service system includes an infrastructure for providing cloud services. The infrastructure includes a first computing node and a second computing node. The first computing node includes a first host computer 701, a first processor 702 and a first SDI card 703. The second computing node includes a second host computer 704, a second processor 705 and a second SDI card 706. It is worth noting that the first host computer 701 includes a first forwarding module, the first processor 702 includes a first scheduler, the first SDI card 703 includes a first TA module, the second host computer 704 includes a second forwarding module, the second processor 705 includes a second scheduler, and the second SDI card 706 includes a second TA module.

[0122] The first processor 702 is configured to write the data to be transmitted into a first memory area of the first host computer 701 and write a first instruction into a second memory area of the first host computer 701. The first memory area is a memory area allocated to the first processor 702 by the first host computer 701. For example, the first processor 702 is configured to perform the step 401 in the embodiment shown in FIG. 4.

[0123] The first host computer 701 is configured to poll the second memory area to determine that the first memory area stores the data based on the first instruction obtained by polling. For example, the first host computer 701 is configured to perform the step 402 in the embodiment shown in FIG. 4.

[0124] The first host computer 701 is further configured to notify the first SDI card 703 to read the data from the first memory area. For example, the first host computer 701 is configured to perform the step 403 in the embodiment shown in FIG. 4.

[0125] The first SDI card 703 is configured to send data to the second computing node. For example, the first SDI card 703 is configured to perform step 403 in the embodiment shown in FIG. 4.

[0126] In a possible implementation, the first processor 702 is configured to: generate data to be transmitted, and store the data in a third memory region of the first processor 702; and copy the data from the third memory region to a first memory region of the first host 701 based on an address of the third memory region and an address of the first memory region.

[0127] In a possible implementation, the first host 701 is configured to: obtain, from the first mapping table, an address of a third memory region, an address of a first memory region, an address of the first SDI card 703, an address of the second SDI card 706, and an address of a fourth memory region of a second host 704, the fourth memory region being a memory region of the second host 704 allocated to the second processor 705; provide, based on the address of the first SDI card 703, the address of the first memory region, the address of the second SDI card 706, and the address of the fourth memory region to the first SDI card 703; and the first SDI card 703 is configured to: read data from the first memory region based on the address of the first memory region; and send, based on the address of the second SDI card 706, the data and the address of the fourth memory region to the second SDI card 706, the address of the fourth memory region being used by the second SDI card 706 to write the data to the fourth memory region.

[0128] In a possible implementation, the first host 701 is configured to write, based on the address of the first SDI card 703, a second instruction to a first register of the first SDI card 703; and the first SDI card is configured to poll the first register to obtain, based on the second instruction polled, the address of the first memory region, the address of the second SDI card 706, and the address of the fourth memory region provided by the first host 701.

[0129] In a possible implementation, the first instruction and the second instruction are store instructions.

[0130] In a possible implementation, the second SDI card 706 is configured to write, to a fourth memory region of the second host 704, the data from the first SDI card 703, and cause the second host 704 to determine that the data reaches the fourth memory region; the second host 704 is configured to write, from the fourth memory region, the data to the second processor 705; and the second processor 705 is configured to process the data to obtain a processing result of the data.

[0131] In a possible implementation, the second SDI card 706 is configured to write data into the fourth memory region based on the address of the fourth memory region, and provide the address of the fourth memory region, the address of the first SDI card 703, and the address of the second SDI card 706 to the second host 704, so that the second host 704 determines that the data reaches the fourth memory region of the second host 704.

[0132] In a possible implementation, the second host 704 is configured to: obtain, from the second mapping table, an address of a fifth memory region of the second processor 705 that is bound with the address of the fourth memory region, the address of the first SDI card 703, and the address of the second SDI card 706; and copy the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region.

[0133] In a possible implementation, the second processor 705 is configured to: poll a second register of the second processor 705 to determine, based on a third instruction obtained through the polling, that the data is stored in the fifth memory region, the third instruction being written into the second register by the second host 704; and obtain the data from the fifth memory region based on the address of the fifth memory region, and process the data to obtain a processing result of the data.

[0134] It should be noted that the information interaction and implementation process between the modules / units of the apparatus are based on the same consideration as the method embodiments of the present application, and the technical effects brought by the same are the same as those of the method embodiments of the present application. For details, refer to the foregoing description of the method embodiments of the present application, which will not be repeated here.

[0135] Referring to FIG. 8, FIG. 8 is a structural schematic diagram of a computing device provided by an embodiment of the present application. As shown in FIG. 8, the computing device 800 (which can be used to present the foregoing first computing node or second computing node, for ease of description, the following is illustratively described by taking the computing device 800 used to present the foregoing first computing node) includes a processor 801, a memory 802, a communication interface 803, and a bus 804, the processor 801, the memory 802, and the communication interface 803 are coupled through a bus (not shown in the figure). The memory 802 stores instructions, when the instructions in the memory 802 are executed, the computing device 800 executes the method performed by the first computing node or the second computing node in the foregoing method embodiments.

[0136] The computing device 800 can be one or more integrated circuits (ICs) configured to implement one or more of the above methods, e.g., one or more application specific integrated circuits (ASICs), or, one or more digital signal processors (DSPs), or, one or more field programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when units of the apparatus can be implemented by way of a processing element scheduler, the processing element can be a general purpose processor, e.g., a central processing unit (CPU) or other processor that can invoke a program. As another example, these units can be integrated together in a system-on-a-chip (SOC) form.

[0137] The processor 801 can be a central processing unit (CPU), and can also be other general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general purpose processor can be a microprocessor or any conventional processor.

[0138] The memory 802 can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Among them, the nonvolatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0139] The executable program code stored in the memory 802 is executed by the processor 801 to respectively implement the functions of the aforementioned first forwarding module, first scheduler, and first TA module, and the like, thereby implementing the aforementioned data transmission method based on the cloud service system. That is, the memory 802 has instructions for executing the aforementioned data transmission method based on the cloud service system.

[0140] The communication interface 803 uses a transceiving module such as, but not limited to, a network interface card, a transceiver, and the like, to implement communication between the computing device 800 and other devices or communication networks.

[0141] The bus 804 can include, in addition to a data bus, a power bus, a control bus, and a state signal bus, etc. The bus can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0142] Referring to FIG. 9, FIG. 9 is a structural schematic diagram of a computing device cluster provided by an embodiment of the present application. As shown in FIG. 9, the computing device cluster 900 includes at least one computing device 800.

[0143] As shown in FIG. 9, the computing device cluster 900 includes at least one computing device 800. The memory 802 in one or more computing devices 800 in the computing device cluster 900 can store the same instructions for executing the cloud service system-based data transmission method described above.

[0144] In some possible implementation manners, the memory 802 in one or more computing devices 800 in the computing device cluster 900 can also respectively store partial instructions for executing the cloud service system-based data transmission method described above. In other words, the combination of one or more computing devices 800 can collectively execute the instructions for executing the cloud service system-based data transmission method described above.

[0145] It should be noted that the memory 802 in different computing devices 800 in the computing device cluster 900 can store different instructions, respectively, for executing partial functions of the cloud management platform described above. That is, the instructions stored in the memory 802 in different computing devices 800 can implement the functions of one or more of the first forwarding module, the first scheduler, and the first TA module, etc.

[0146] In some possible implementation manners, one or more computing devices 800 in the computing device cluster 900 can be connected through a network. The network can be a wide area network or a local area network, etc.

[0147] Referring to FIG. 10, FIG. 10 is a schematic diagram of the connection of the computer devices in the computer cluster provided by the embodiment of the present application through a network. As shown in FIG. 10, the two computer devices 800A and 800B are connected through a network. Specifically, the communication interface in each computer device is connected to the network.

[0148] In a possible implementation, the memory in the computer device 800A stores instructions for performing the functions of the first forwarding module and other modules. Meanwhile, the memory in the computer device 800B stores instructions for performing the functions of the first scheduler, the first TA module and other modules.

[0149] It should be understood that the functions of the computer device 800A shown in FIG. 10 can also be completed by multiple computer devices. Similarly, the functions of the computer device 800B can also be completed by multiple computer devices.

[0150] The embodiment of the present application also relates to a computer storage medium, which stores a program for performing signal processing, and when the program is run on a computer, the computer executes the steps performed by the first computing node or the second computing node in the embodiment shown in FIG. 4.

[0151] The embodiment of the present application also relates to a computer program product, which stores instructions, and the instructions make the computer execute the steps performed by the first computing node or the second computing node in the embodiment shown in FIG. 4 when the instructions are executed by the computer.

[0152] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0153] In the several embodiments of the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the units is only a logical function division. There can be another division manner for actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0154] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0155] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0156] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical scheme of the present application essentially or the part that contributes to the prior art or the whole or part of the technical scheme can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a magnetic disk or an optical disk, and various program code storage media.

Claims

A data transmission method based on a cloud service system, characterized in that, The cloud service system comprises an infrastructure providing cloud services, the infrastructure comprising a first computing node and a second computing node, the first computing node comprising a first host, a first processor and a first software-defined infrastructure (SDI) card, and the method comprises: The first processor writes data to be transmitted into a first memory region of the first host, and writes a first instruction into a second memory region of the first host, the first memory region being a memory region allocated to the first processor by the first host; The first host polls the second memory region to determine, based on the first instruction polled, that the first memory region stores the data; The first host notifies the first SDI card to read the data from the first memory region; The first SDI card sends the data to the second computing node. The method of claim 1, wherein The first processor writes data to be transmitted into a first memory region of the first host comprises: The first processor generates data to be transmitted, and stores the data in a third memory region of the first processor; The first processor copies the data from the third memory region to the first memory region based on an address of the third memory region and an address of the first memory region of the first host. The method according to claim 1 or 2, characterized in that The second computing node comprises a second host, a second processor and a second SDI card, the first host notifying the first SDI card to read the data from the first memory region, and the first SDI card sending the data to the second computing node comprises: The first host obtains, from a first mapping table, addresses of a third memory region, the first memory region, the first SDI card, the second SDI card and a fourth memory region of the second host, the fourth memory region being a memory region allocated to the second processor by the second host; The first host provides, based on the address of the first SDI card, the first host to the first SDI card with the address of the first memory region, the address of the second SDI card and the address of the fourth memory region; The first SDI card reads the data from the first memory region based on the address of the first memory region; The first SDI card sends, based on the address of the second SDI card, the data and the address of the fourth memory region to the second SDI card, the address of the fourth memory region being used by the second SDI card to write the data into the fourth memory region. The method according to claim 3, characterized in that The first host provides, based on the address of the first SDI card, the first host to the first SDI card with the address of the first memory region, the address of the second SDI card and the address of the fourth memory region comprises: The first host writes a second instruction into a first register of the first SDI card based on the address of the first SDI card; The first SDI polls the first register to obtain, based on the second instruction obtained through polling, an address of the first memory region provided by the first host, an address of the second SDI card, and an address of the fourth memory region. The method according to claim 4, characterized in that The first instruction and the second instruction are store instructions. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The second SDI card writes the data from the first SDI card into a fourth memory region of a second host, and causes the second host to determine that the data reaches the fourth memory region; The second host writes the data from the fourth memory region to a second processor; The second processor processes the data to obtain a processing result of the data. The method according to claim 6, characterized in that The second SDI card writes the data from the first SDI card into a fourth memory region, and causes the second host to determine that the data is stored in the fourth memory region, comprising: The second SDI card writes the data into the fourth memory region based on the address of the fourth memory region, and provides the second host with the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card, so that the second host determines that the data reaches the fourth memory region of the second host. The method of claim 7, wherein The second host writes the data from the fourth memory region to a second processor, comprising: The second host obtains, from a second mapping table, an address of a fifth memory region of the second processor that is bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card; The second host copies the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region. The method of claim 8, wherein The second processor processes the data to obtain a processing result of the data, comprising: The second processor polls a second register of the second processor to determine, based on a third instruction obtained through polling, that the data is stored in the fifth memory region, the third instruction being written into the second register by the second host; The second processor obtains the data from the fifth memory region based on the address of the fifth memory region, and processes the data to obtain a processing result of the data. A cloud service system characterized by comprising: The cloud service system comprises an infrastructure that provides cloud services, and the infrastructure comprises a first computing node and a second computing node, the first computing node comprising a first host, a first processor, and a first SDI card; The first processor is configured to write data to be transmitted into a first memory region of the first host, and write a first instruction into a second memory region of the first host, the first memory region being a memory region allocated to the first processor by the first host; The first host is configured to poll the second memory region to determine, based on the first instruction obtained through polling, that the first memory region stores the data; The first host is further configured to notify the first SDI card to read the data from the first memory region; The first host is further configured to notify the first SDI card to read the data from the first memory region; The first SDI card is configured to send the data to the second computing node. The cloud service system of claim 10, wherein The first processor is configured to: generate data to be transmitted, and store the data in a third memory region of the first processor; copy the data from the third memory region to a first memory region of the first host based on an address of the third memory region and an address of the first memory region. The cloud service system according to claim 10 or 11, characterized in that The second computing node comprises a second host, a second processor, and a second SDI card. The first host is configured to: obtain, from a first mapping table, an address of a third memory region, an address of the first memory region, an address of the first SDI card, an address of the second SDI card, and an address of a fourth memory region of the second host, the fourth memory region being a memory region allocated by the second host to the second processor; provide, to the first SDI card based on the address of the first SDI card, the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region; The first SDI card is configured to: read the data from the first memory region based on the address of the first memory region; send the data and the address of the fourth memory region to the second SDI card based on the address of the second SDI card, the address of the fourth memory region being used by the second SDI card to write the data into the fourth memory region. The cloud service system of claim 12, wherein The first host is configured to write a second instruction into a first register of the first SDI card based on the address of the first SDI card. The first SDI is configured to poll the first register to obtain the address of the first memory region, the address of the second SDI card, and the address of the fourth memory region provided by the first host based on the second instruction obtained by polling. The cloud service system of claim 13, wherein The first instruction and the second instruction are store instructions. The cloud service system according to any one of claims 10 to 14, characterized in that The second SDI card is configured to write the data from the first SDI card into a fourth memory region of the second host, and cause the second host to determine that the data reaches the fourth memory region. The second host is configured to write the data from the fourth memory region to the second processor. The second processor is configured to process the data to obtain a processing result of the data. The cloud service system of claim 15, wherein The second SDI card is configured to write the data into the fourth memory region based on the address of the fourth memory region, and provide the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card to the second host, so as to cause the second host to determine that the data reaches the fourth memory region of the second host. The cloud service system of claim 16, wherein The second host is configured to: obtain, from a second mapping table, an address of a fifth memory region of the second processor that is bound to the address of the fourth memory region, the address of the first SDI card, and the address of the second SDI card; copy the data from the fourth memory region to the fifth memory region based on the address of the fourth memory region and the address of the fifth memory region. The cloud service system of claim 17, wherein The second processor is configured to: poll a second register of the second processor to determine that the data is stored in the fifth memory region based on a third instruction obtained by polling, the third instruction being written into the second register by the second host; obtain the data from the fifth memory region based on an address of the fifth memory region, and process the data to obtain a processing result of the data. A cluster of computing devices, characterized in that, The computing device cluster comprises at least one computing device, and each computing device comprises a processor and a memory: The memory is configured to store instructions; The processor is configured to execute the instructions to cause the computing device cluster to perform the method in any one of claims 1 to 9. A computer storage medium, characterized by The computer storage medium stores one or more instructions, which, when executed by one or more computers, cause the one or more computers to implement the method in any one of claims 1 to 9. A computer program product, characterized in that The computer program product stores instructions, which, when executed by a computer, cause the computer to implement the method in any one of claims 1 to 9.

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