Metal oxide layer and transistor

Abstract

Provided is a metal oxide layer in which oxygen easily diffuses within crystal grains. This metal oxide layer has a crystal lattice containing indium and oxygen. The indium and oxygen are in an In-O-O-In state within the crystal lattice, and the diffusion barrier of oxygen within the crystal lattice is 1.25 eV or less. The inside of the metal oxide layer has a region in which the concentration of aluminum is 3.0 × 1015 atoms / cm3 or less, and the concentration of gallium is 4.0 × 1015 atoms / cm3 or less.

Description

Metal oxide layer and transistor

[0001] 1. Field of the Invention One embodiment of the present invention relates to a metal oxide layer, a transistor, a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a metal oxide layer and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0005] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power central processing unit (CPU) that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0006] In addition, examples of oxide semiconductors that can be used for the semiconductor layer of a transistor (a semiconductor layer having a channel formation region) include indium oxide (indium oxide, InO Ｘ ) is an example. Alternatively, for example, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO) is an example. Non-Patent Document 1 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization as a semiconductor layer.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Research and Development Agency, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> W. Fischer, E. Koch, “14.2 Symbols and properties of lattice complexes”, International tables for crystallography Volume A, Fifth edition (ISBN: 0-7923-6590-9), Springer, (2005), pp. 848-872.

[0009] An object of one embodiment of the present invention is to provide a metal oxide layer in which oxygen easily diffuses inside crystal grains.An object of one embodiment of the present invention is to provide a metal oxide layer having high carrier mobility.An object of one embodiment of the present invention is to provide a novel metal oxide layer.An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, a memory device, or a display device to which a metal oxide layer is applied.

[0010] Another object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance. Another object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device. Another object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operating speed. Another object of one embodiment of the present invention is to provide a manufacturing method of the transistor, the semiconductor device, the memory device, or the display device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a metal oxide layer having a crystal lattice containing indium and oxygen, wherein the indium and oxygen have an In-O-O-In state within the crystal lattice, and the diffusion barrier of oxygen within the crystal lattice is 1.25 eV or less.

[0013] Another embodiment of the present invention is a metal oxide layer having a crystal lattice containing indium and oxygen, wherein the concentration of aluminum in the metal oxide layer is 3.0×10 １５ atoms / cm ３ and the concentration of gallium is 4.0 × 10 １５ atoms / cm ３ A metal oxide layer having a region that is:

[0014] Another embodiment of the present invention is a metal oxide layer having a crystal lattice containing indium and oxygen, wherein the indium and oxygen have an In—O—O—In state in the crystal lattice, the oxygen diffusion barrier in the crystal lattice is 1.25 eV or less, and the aluminum concentration in the metal oxide layer is 3.0×10 １５ atoms / cm ３ and the gallium concentration is 4.0 × 10 １５ atoms / cm ３ A metal oxide layer having a region that is:

[0015] In the above, the diffusion coefficient of oxygen is 1.00 nm at temperatures of 300°C or higher. ２ / s or more is preferable.

[0016] In the above, the metal oxide layer preferably has a bixbyite-type crystal structure.

[0017] Another embodiment of the present invention is a transistor including the above-described metal oxide layer, an insulating layer, and a conductive layer. The metal oxide layer has a region overlapping with the conductive layer with the insulating layer interposed therebetween. The metal oxide layer functions as a channel formation region of the transistor. The insulating layer functions as a gate insulating layer of the transistor. The conductive layer functions as a gate electrode of the transistor.

[0018] According to one embodiment of the present invention, a metal oxide layer in which oxygen easily diffuses inside crystal grains can be provided. Alternatively, according to one embodiment of the present invention, a metal oxide layer having high carrier mobility can be provided. Alternatively, according to one embodiment of the present invention, a novel metal oxide layer can be provided. Alternatively, according to one embodiment of the present invention, a transistor, a semiconductor device, a memory device, or a display device to which the metal oxide layer is applied can be provided.

[0019] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with high on-state current can be provided. According to one embodiment of the present invention, a transistor with low parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the transistor, the semiconductor device, the memory device, or the display device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0021] FIGS. 1A and 1B are diagrams illustrating the crystal structure of indium oxide. FIG. 2A is a diagram illustrating the crystal structure of indium oxide. FIG. 2B is a diagram illustrating possible states of oxygen in an indium oxide film. FIGS. 3A, 3B, and 3C are diagrams illustrating oxygen diffusion in an indium oxide film. FIGS. 4A, 4B, and 4C are diagrams illustrating oxygen diffusion in an indium oxide film. FIG. 5 is a diagram illustrating an oxygen diffusion barrier in an indium oxide film. FIGS. 6A and 6B are perspective schematic diagrams illustrating an example of a semiconductor device. FIG. 7A is a plan view illustrating an example of a semiconductor device. FIGS. 7B, 7C, and 7D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views illustrating an example of a semiconductor device. FIG. 9A is a plan view illustrating an example of a semiconductor device. FIGS. 9B and 9C are cross-sectional views illustrating an example of a semiconductor device. FIG. 10A is a plan view illustrating an example of a semiconductor device. FIGS. 10B, 10C, and 10D are cross-sectional views illustrating an example of a semiconductor device. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIG. 12A is a plan view showing an example of a semiconductor device. FIGS. 12B, 12C, and 12D are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a plan view showing an example of a semiconductor device. FIGS. 13B, 13C, and 13D are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a plan view showing an example of a semiconductor device. FIGS. 14B, 14C, and 14D are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. FIGS. 15B and 15C are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIGS. 16B, 16C, and 16D are cross-sectional views showing an example of a semiconductor device. FIGS. 17A and 17B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 17C is a cross-sectional view illustrating an indium oxide film. FIGS. 18A and 18B are diagrams illustrating an example of an electronic component. Fig. 19A, Fig. 19B, and Fig. 19C are diagrams showing an example of a mainframe computer. Fig. 19D is a diagram showing an example of space equipment. Fig. 19E is a diagram showing an example of a storage system applicable to a data center. Figs. 20A, 20B, 20C, 20D, 20E, and 20F are diagrams showing examples of electronic equipment.21A, 21B, 21C, 21D, 21E, 21F, and 21G are diagrams showing an example of an electronic device. 22A, 22B, 22C, 22D, 22E, and 22F are diagrams showing an example of an electronic device. 23A and 23B are depth profiles obtained by SIMS analysis of an indium oxide film according to an example. 24A, 24B, and 24C are depth profiles obtained by SIMS analysis of an indium oxide film according to an example.

[0022] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0024] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0025] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0026] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0027] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0028] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0029] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0030] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A ＺIn addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0031] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0033] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0034] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0035] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0036] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0037] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0038] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0039] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0040] Embodiment 1 One embodiment of the present invention is a crystalline metal oxide (indium oxide) layer containing indium (In) and oxygen (O). ２ O ３ In the case of the metal oxide layer, the crystal structure is a cubic structure (bixbyite type) and has spaces within the crystal lattice. Therefore, for example, oxygen (also referred to as excess oxygen) supplied from the outside (such as an oxide insulating film in contact with the metal oxide layer) can diffuse into the crystal grains through the spaces.

[0041] Furthermore, the metal oxide layer of one embodiment of the present invention can be stabilized (In-O-O-In state) by filling the metal oxide layer with excess oxygen. Furthermore, by subjecting the metal oxide layer to heat treatment or the like, oxygen (O) is released from In-O-O-In and diffuses through the metal oxide layer, thereby forming new In-O-O-In. Because oxygen easily diffuses through the metal oxide layer of one embodiment of the present invention, oxygen vacancies in the metal oxide layer can be efficiently filled.

[0042] For example, when a metal oxide layer is used as a semiconductor layer of a transistor, oxygen vacancies in the metal oxide layer can adversely affect the electrical characteristics and reliability of the transistor. Therefore, by filling the oxygen vacancies in the metal oxide layer with excess oxygen diffusing through the metal oxide layer, a transistor with good electrical characteristics and reliability can be realized. For example, a metal oxide layer with reduced oxygen vacancies can achieve high carrier mobility. Therefore, a transistor using the metal oxide layer as a semiconductor layer can achieve high field-effect mobility and a large on-state current.

[0043] Furthermore, for example, if a metal oxide layer contains an impurity element such as aluminum or gallium, the impurity element may trap oxygen diffusing through the metal oxide layer. As a result, the amount of oxygen required to compensate for oxygen vacancies in the metal oxide layer may decrease. Therefore, by using a metal oxide layer with reduced impurity elements such as aluminum or gallium as the semiconductor layer of a transistor, higher field-effect mobility and larger on-current can be achieved.

[0044] Hereinafter, the crystal structure of a metal oxide layer according to one embodiment of the present invention, the diffusion behavior of oxygen in the metal oxide layer, and the like will be described with reference to FIGS. 1A to 5 .

[0045] <Crystalline Structure of Metal Oxide Layer> FIG. 1A shows a metal oxide layer (here, single-crystal indium oxide (In ２ O ３ 1A is a diagram illustrating the crystal structure of single-crystal indium oxide (InO). Single-crystal indium oxide has a cubic bixbyite-type crystal structure. In FIG. 1A, indium atoms and oxygen atoms are shown with sizes equivalent to the atomic radius. As shown in FIG. 1A, when a bixbyite-type indium oxide crystal is viewed from the a-axis direction, it has a structure in which indium (In) layers and oxygen (O) layers are alternately stacked in the c-axis direction. In FIG. 1A, two types of indium (In) sites (24d site and 8b site in Wyckoff positions (Non-Patent Document 3) of space group Ia-3 (space group number 206)) are distinguished.

[0046] FIG. 1B is a view of the oxygen layer surrounded by a thick solid line in the crystal structure shown in FIG. 1A, as viewed from the c-axis direction. Note that in FIG. 1B, oxygen atoms are displayed with a size equivalent to the ionic radius. As shown in FIG. 1B, it can be seen that spaces exist in bixbyite-type indium oxide crystals when viewed from the c-axis direction. Furthermore, it can be seen that spaces exist not only when viewed from the c-axis direction, but also when an oxygen layer is extracted and the extracted layer is viewed from a direction perpendicular to the c-axis (for example, the a-axis direction or the b-axis direction). In other words, it can be said that bixbyite-type indium oxide crystals have a structure in which spaces can be confirmed when the crystal lattice is viewed from any direction. For example, when oxygen contained in an oxide insulating film or the like in contact with the indium oxide layer is supplied into the indium oxide layer by heat treatment or the like from an oxide insulating film or the like in contact with the indium oxide layer, the oxygen can diffuse to any region in the indium oxide layer using the above-mentioned spaces as a migration path.

[0047] <Oxygen Diffusion Behavior in Metal Oxide Layer> FIG. 2A shows the diffusion behavior of oxygen in a single crystal of indium oxide (here, In ２ O ３) crystal structure. FIG. 2B shows an example of a state that oxygen can take in an indium oxide crystal when oxygen is supplied to the indium oxide crystal. Specifically, FIG. 2B shows the state in which oxygen becomes stable as the crystal structure of indium oxide when oxygen diffuses into the crystal lattice of single-crystal indium oxide. As shown in the area surrounded by the dashed line in FIG. 2B, oxygen diffused into the space within the crystal lattice of single-crystal indium oxide tends to exist in the state of In-O-O-In, and this state can be said to be a stable state for the crystal structure of indium oxide. The In-O-O-In state is a state in which two oxygen atoms exist at the oxygen site. In this state, one oxygen atom is bonded to the other oxygen atom and one In atom, and the other oxygen atom is bonded to one oxygen atom and another In atom. The state of oxygen in the indium oxide crystal (such as the state of In-O-O-In) can be confirmed by using a technique such as X-ray photoelectron spectroscopy (XPS).

[0048] In addition, first-principles calculations were performed on the diffusion behavior of oxygen when oxygen was supplied to the indium oxide crystal (FIG. 3A) in which oxygen exists in the above-mentioned In-O-O-In state. The calculations were performed for three cases: one in which oxygen exists in the In-O-O-In state (unsubstituted), and one in which one In atom (In at the 8b site) of In-O-O-In was replaced with aluminum (Al), assuming a case in which an impurity element is contained in the indium oxide layer. Furthermore, aluminum (Al) and gallium (Ga) were more stable when substituted with indium (In) at the 8b site than when substituted with indium (In) at the 24d site. Details of the calculation conditions are shown in Table 1.

[0049]

[0050] 3A to 3C show the initial structures of the calculation models for the above three cases: Fig. 3A is the calculation model without substitution, Fig. 3B is the calculation model with Al substitution at the 8b site, and Fig. 3C is the calculation model with Ga substitution at the 8b site.

[0051] 4A to 4C show the oxygen diffusion path obtained by the first-principles calculation when oxygen exists in the state of In-O-O-In (unsubstituted). In the calculation, it was assumed that oxygen, which was stable in the state of In-O-O-In (FIG. 4A), first diffuses around the 8b site (FIG. 4B), and then diffuses around the 24d site (FIG. 4C). In other words, when oxygen permeates the indium oxide layer, it can diffuse around both the 8b site and the 24d site. This is also true when one In atom in In-O-O-In (In at the 8b site) is replaced with aluminum (Al) or when one In atom in In-O-O-In (In at the 8b site) is replaced with gallium (Ga).

[0052] A graph showing the oxygen diffusion barrier (also called migration barrier) obtained by calculation is shown in Figure 5. Table 2 summarizes the oxygen diffusion barrier in the above three cases.

[0053]

[0054] In the graph shown in Figure 5, the horizontal axis represents the number of images in the CI-NEB (climbing-image nudged elastic band) method used to calculate the oxygen diffusion barrier, and the vertical axis represents energy. Figure 5 shows calculation results for both the case where oxygen diffuses around the 8b site and the case where oxygen diffuses around the 24d site. The energy corresponding to the peak in the graph shown in Figure 5 corresponds to the oxygen diffusion barrier in each case. Table 2 summarizes the oxygen diffusion barriers for the above three cases extracted from the graph in Figure 5.

[0055] It can be seen from Table 2 that in all three cases, the diffusion barrier of oxygen is larger when diffusing around the 24d site than when diffusing around the 8b site. Furthermore, focusing on the diffusion around the 24d site, which has a larger diffusion barrier, the diffusion barrier is smallest (1.18 eV) when oxygen is present in the In-O-O-In state (unsubstituted), and the diffusion barrier becomes larger when one indium (In) in In-O-O-In is replaced with aluminum (Al) or gallium (Ga).

[0056] The presence of an impurity element such as aluminum or gallium in an indium oxide layer increases the oxygen diffusion barrier (i.e., oxygen is less likely to diffuse) compared to the absence of the impurity element. This is thought to be because the impurity element such as aluminum or gallium traps oxygen diffusing in the indium oxide layer. In this case, the presence of an impurity element such as aluminum or gallium in the indium oxide layer reduces the amount of oxygen diffusing in the indium oxide layer, which may make it impossible to fully compensate for oxygen vacancies in the indium oxide layer.

[0057] Therefore, it is preferable that the impurity elements such as aluminum and gallium are reduced as much as possible in the indium oxide layer. A transistor using an indium oxide layer with reduced impurity elements such as aluminum and gallium for its semiconductor layer can more easily compensate for oxygen vacancies in the semiconductor layer with oxygen diffusing in the semiconductor layer than a transistor using an indium oxide layer containing a large amount of impurity elements such as aluminum and gallium for its semiconductor layer. Therefore, a transistor using an indium oxide layer with reduced impurity elements such as aluminum and gallium for its semiconductor layer can achieve high field-effect mobility and large on-state current.

[0058] For example, when a crystalline indium oxide layer is used as a semiconductor layer of a transistor, oxygen supplied to the indium oxide layer can be diffused relatively easily by heat treatment or the like during the transistor manufacturing process (in Example 1, oxygen (１８ Analysis results obtained by secondary ion mass spectrometry (SIMS) suggest that oxygen (In—O) can diffuse.) Therefore, if the magnitude of the oxygen diffusion barrier shown in Table 2 is correlated with the energy of heat treatment, the diffusion barrier of 1.18 eV (the diffusion barrier when oxygen is present in the state of In—O—O—In (unsubstituted)) can be said to be a small energy that allows oxygen to diffuse relatively easily in indium oxide crystals.

[0059] As described above, a transistor using an indium oxide layer for a semiconductor layer can very efficiently compensate for oxygen vacancies in the indium oxide layer, and can be expected to have good electrical characteristics and reliability. For example, as described in Embodiment 3, indium oxide has a property that the higher the purity and intrinsic nature of indium oxide, as a result of the compensation of oxygen vacancies, the higher the hole mobility, unlike IGZO, which is also an oxide semiconductor. Therefore, a transistor using an indium oxide layer for a semiconductor layer can achieve higher field-effect mobility and a larger on-state current than a transistor using IGZO for a semiconductor layer.

[0060] <Oxygen Diffusion Coefficient> The oxygen diffusion barrier can be calculated using the following formulas (1) and (2), where formula (1) is the frequency v of atom movement per second, and formula (2) is the diffusion coefficient D.

[0061]

[0062]

[0063] In formula (1), ν is the frequency at which atoms move per second, and ν ０ is the trial frequency, E ａ is the activation energy (here, it corresponds to the oxygen diffusion barrier), k Ｂ is the Boltzmann constant (8.62 x 10 −５ eV / K), and T is the absolute temperature. In equation (2), D is the diffusion coefficient, α is a number factor, and d is the jump distance.

[0064] The frequency of attempts to overcome the diffusion barrier when atoms are thermally vibrating, ν ０ of atomic vibration frequency by 10 １３ s −１ Assuming that, the barrier to oxygen diffusion at the 24d site center (activation energy E ａ ) of 1.18 eV, the number factor α of 1 / 3 due to the three diffusion paths, and the jump distance d of 0.195 nm are taken into consideration, and the diffusion coefficient D of oxygen is approximately 186 nm at 400 °C. ２ At 300°C, it is estimated to be approximately 5.34 nm ２ It is estimated to be / s.

[0065] Furthermore, if the value between the value (1.18 eV) in the case of In (unsubstituted) and the value (1.30 eV) in the case of Ga substitution is taken as the boundary value between the cases where the indium oxide layer contains an impurity element and the case where it does not, based on the diffusion barrier at the time of diffusion at the 24d site center shown in Table 2, then it can be said that the boundary value can take a value between 1.18 eV and 1.30 eV. For example, if the oxygen diffusion barrier is taken as the aforementioned 1.25 eV, the oxygen diffusion coefficient at 400°C is approximately 55.5 nm ２ At 300°C, it is estimated to be approximately 1.29 nm ２ It is estimated to be / s.

[0066] Therefore, when the diffusion barrier of oxygen in an indium oxide layer that does not contain impurity elements such as aluminum and gallium is 1.25 eV or less, the diffusion coefficient of the oxygen is 1.00 nm or less at a temperature of 300° C. or more. ２ / s or more. At temperatures of 400°C or more, ２ It is estimated to be more than / s.

[0067] For example, consider a case where an indium oxide layer having an oxygen diffusion barrier of 1.25 eV or less is applied to a semiconductor layer having a channel formation region of a transistor. For example, by performing heat treatment at 400° C. or more after forming the semiconductor layer (here, the indium oxide layer) of the transistor, oxygen in the semiconductor layer is diffused to a depth of 50.0 nm in 1 second. ２Therefore, for example, when the area of ​​the channel formation region of the transistor (corresponding to the channel length×channel width) is 50.0 nm 2 or more, ２ In this case, oxygen can be diffused over the entire channel formation region of the transistor in one second by heat treatment at 400° C. or higher.

[0068] Furthermore, for example, an indium oxide layer that does not contain impurity elements such as aluminum or gallium (for example, it can be said that the concentration of aluminum, gallium, etc. is equal to or lower than the background level in SIMS analysis) is formed in a channel formation region (area of ​​50.0 nm ) of a transistor. ２ For example, if the oxygen diffusion barrier in the indium oxide layer is 1.25 eV or less, oxygen can be diffused throughout the entire channel formation region of the transistor in one second by heat treatment at 400° C. or higher. This means that when heat treatment is performed at 300° C. or higher, oxygen can be diffused over 1.00 nm in one second. ２ This corresponds to the fact that oxygen can be diffused over the above area.

[0069] Note that for the structure of a transistor to which the metal oxide layer of one embodiment of the present invention can be applied, specific values ​​of the channel length and the channel width of the transistor, and the like, Embodiment 2 can be referred to.

[0070] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0071] Embodiment 2 In this embodiment, a semiconductor device to which the metal oxide layer of one embodiment of the present invention can be applied will be described. The semiconductor device of one embodiment of the present invention includes a transistor. For example, the metal oxide layer of one embodiment of the present invention can be applied to a semiconductor layer having a channel formation region of a transistor.

[0072] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 6A to 15C.

[0073] 6A and 6B are schematic perspective views of a semiconductor device having a transistor 200A. Fig. 6B is a perspective view in which a part of Fig. 6A is cut away. In Fig. 6A and 6B, only the outlines of some components (such as interlayer insulating layers) are indicated by dashed lines.

[0074] 6A and 6B, the X, Y, and Z directions are indicated by arrows. Note that although the same X, Y, and Z symbols are used in both Fig. 6A and Fig. 6B, the directions do not necessarily have to match.

[0075] Fig. 7A is a plan view of a semiconductor device having a transistor 200A. Fig. 7B is a cross-sectional view taken along dashed dotted lines A1-A2 in Fig. 7A. Fig. 7C is a cross-sectional view taken along dashed dotted lines A3-A4 in Fig. 7A. Fig. 7D is a cross-sectional view taken along dashed dotted lines A5-A6 in Figs. 7B and 7C. Note that some elements are omitted in the plan view of Fig. 7A for clarity. Some elements may also be omitted in the subsequent plan views.

[0076] Fig. 8A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 7A. Fig. 8B is a cross-sectional view taken along dashed lines A5-A6 in Fig. 7B and Fig. 7C. Fig. 8A and Fig. 8B correspond to examples of enlarged views of Fig. 7B and Fig. 7D, respectively.

[0077] The semiconductor device shown in FIGS. 7A to 7D includes an insulating layer 210 on a substrate (not shown), a transistor 200A on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0078] [Transistor 200A] The transistor 200A includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The insulating layer 280 is located on the conductive layer 220.

[0079] 7B and 7C show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 on the conductive layer 240_1, and the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1.

[0080] The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200A, and the conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor 200A. The conductive layer 260 has a region that functions as a gate electrode of the transistor 200A.

[0081] As shown in FIGS. 7B and 7C, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0082] The openings 290 include an opening in the insulating layer 280 and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the top surface shape of the openings 290 is circular, the top surfaces of the openings in each layer may or may not be concentric.

[0083] Each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is arranged so that at least a portion thereof is located within the opening 290. Furthermore, the portions of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are arranged within the opening 290 are provided so as to reflect the shape of the opening 290.

[0084] The semiconductor layer 230 is provided so as to cover the upper surface and side surfaces of the conductive layer 220 in the region overlapping with the opening 290, the side surfaces of the insulating layer 280 within the opening 290, and the side surfaces of the conductive layer 240 within the opening 290. The semiconductor layer 230 also has a recess that reflects the shape of the opening 290. The semiconductor layer 230 has a portion that contacts the upper surface of the conductive layer 240 and a portion that contacts the upper surface of the conductive layer 220 within the opening 290.

[0085] The insulating layer 250 is provided so as to cover the semiconductor layer 230. The insulating layer 250 is also provided so as to cover the top surface and side surfaces of the semiconductor layer 230, the side surfaces of the conductive layer 240, and the top surface of the insulating layer 280. The insulating layer 250 has a recess that reflects the shape of the recess that the semiconductor layer 230 has.

[0086] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the opening 290 that overlaps with the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0087] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200A. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0088] The semiconductor layer 230 is provided to have a region located inside the opening 290. The transistor 200A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below the substrate surface and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above the substrate surface, allowing current to flow vertically. That is, a channel is formed along the side surface of the opening 290. This allows the transistor 200A to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. The transistor 200A can be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like because the channel length direction has a component in the height direction (vertical direction).

[0089] As shown in FIG. 8A , the conductive layer 220 has a recessed portion overlapping with the opening 290. Specifically, the recessed portion is provided in the conductive layer 220_2 at a position overlapping with the opening 290. When the conductive layer 220_2 has the recessed portion, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the region overlapping with the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 in contact with the insulating layer 280, as compared to when the conductive layer 220_2 does not have the recessed portion. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0090] The semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220_2. The recessed portion of the conductive layer 220_2 can increase the area where the semiconductor layer 230 and the conductive layer 220_2 are in contact with each other. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0091] 7C shows a structure in which the end of the conductive layer 240 and the end of the semiconductor layer 230 are aligned or substantially aligned outside the opening 290. The conductive layer 240 and the semiconductor layer 230 can be fabricated by processing using the same mask. This is preferable because it reduces the number of masks required to fabricate a semiconductor device. Note that the present invention is not limited to this. For example, a structure may be adopted in which any one of the end of the semiconductor layer 230, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0092] 7A , the transistor 200A is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 7A , the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200A can be said to have a structure that allows for high integration and miniaturization.

[0093] As shown in FIG. 8B , by forming the opening 290 so that it has a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each arranged concentrically. Therefore, the side surface of the conductive layer 260 located at the center of the opening 290 faces the side surface of the semiconductor layer 230 via the insulating layer 250. In other words, in a plan view, the entire inner periphery of the semiconductor layer 230 becomes a channel formation region. In this case, the channel width of the transistor 200A is determined, for example, by the length of the inner periphery of the semiconductor layer 230. In other words, the channel width of the transistor 200A can be determined by the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view) and the film thickness of the semiconductor layer 230. In FIGS. 8A and 8B , the width D of the opening 290 is shown, and in FIG. 8B , the channel width W of the transistor 200A is shown.

[0094] Furthermore, by arranging the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 concentrically, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, and therefore a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0095] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200A, allowing for higher integration of the semiconductor device.

[0096] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening at the highest position in the conductive layer 240, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 is determined using the width of the opening in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening side may be used as the width D. Alternatively, the width of the opening at the highest position in the insulating layer 280, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D of the opening 290.

[0097] The width D of the opening 290 is set by the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290.

[0098] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By using a circular shape, the processing accuracy when forming the opening can be improved, and openings of finer sizes can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0099] The channel length of the transistor 200A is the distance between the source region and the drain region. In other words, the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of the transistor 200A does not affect the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a planar view. In FIG. 8A , the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. Note that the channel length L can be considered as the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0100] The channel length of the transistor 200A can be, for example, 0.1 nm to 500 nm, 1 nm to 300 nm, 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm. Typically, the channel length can be 1 nm to 300 nm, preferably 5 nm to 100 nm. This can improve productivity and yield in the formation of the insulating layer 280, the formation of the opening 290 in the insulating layer 280, and the like. Furthermore, the on-state current of the transistor 200A can be increased, thereby improving frequency characteristics.

[0101] The channel length L of the transistor 200A is preferably at least shorter than the channel width W of the transistor 200A. The channel length L of the transistor 200A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200A. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0102] 8A shows an example in which the semiconductor layer 230 has a single-layer structure. Note that the semiconductor layer 230 can have a stacked structure of two or more layers.

[0103] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0104] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200A to the semiconductor layer 230 can be suppressed.

[0105] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has the function of capturing or fixing hydrogen, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 210 through the conductive layer 220 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0106] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced. This can suppress diffusion of impurities such as hydrogen or water from the insulating layer 210 to the channel formation region of the semiconductor layer 230.

[0107] 8A shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0108] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0109] As described above, by using silicon oxide, which has a small thermal expansion coefficient, for the insulating layer 280 provided before the formation of the semiconductor layer 230, when indium oxide is used for the semiconductor layer 230, crystal growth of the indium oxide can be promoted inside the opening of the insulating layer 280.

[0110] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can suppress diffusion of impurities such as hydrogen or water from the insulating layer 280 to the channel formation region of the semiconductor layer 230.

[0111] FIG. 8A shows an example in which the insulating layer 250 has a single-layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0112] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value) can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0113] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200A can be improved.

[0114] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0115] 8A shows an example in which the insulating layer 280 has a single-layer structure. Note that the insulating layer 280 can have a stacked structure of two or more layers.

[0116] The conductive layer 220 and the conductive layer 240 are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, because they are in contact with the semiconductor layer 230. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of each of the conductive layer 220 and the conductive layer 240.

[0117] By using a conductive material containing oxygen for each of the conductive layer 220 and the conductive layer 240, the conductive layer 220 and the conductive layer 240 can maintain their conductivity even if they absorb oxygen. Furthermore, even when an insulator containing oxygen such as hafnium oxide is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, In—Zn oxide, or the like.

[0118] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, the contact resistance between the conductive layer 220 and the semiconductor layer 230 and between the conductive layer 240 and the semiconductor layer 230 can be reduced by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230.

[0119] The conductive layer 240 shown in FIG. 8A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0120] Note that a conductive material containing oxygen can be used for the conductive layer 240_1, and a material having higher conductivity than that of the conductive layer 240_1 can be used for the conductive layer 240_2. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200A can be increased.

[0121] 8A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0122] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0123] 8A , both the conductive layer 260_1 and the conductive layer 260_2 are located in the opening 290. Depending on the width of the opening 290 and the thicknesses of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, the conductive layer 260_1 may be provided to have a region located inside the opening 290, and the conductive layer 260_2 may be provided outside the opening 290.

[0124] It is preferable that the side surface of the conductive layer 240 and the side surface of the insulating layer 280 coincide or substantially coincide within the opening 290. With this configuration, the opening 290 can be formed simultaneously in the conductive layer 240 and the insulating layer 280. Furthermore, the film thickness distribution of the semiconductor layer 230 and the like provided within the opening 290 can be made uniform. Furthermore, it is possible to prevent the semiconductor layer 230 and the like from being divided by steps formed by the respective side surfaces of the conductive layer 240 and the insulating layer 280.

[0125] It should be noted that the present invention is not limited to the above configuration. For example, within the opening 290, the side surface of the conductive layer 240 and the side surface of the insulating layer 280 may be discontinuous. Furthermore, within the opening 290, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0126] By tapering the sidewalls of the opening 290, the coverage of the semiconductor layer 230, the insulating layer 250, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the opening 290 are tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 in the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of the semiconductor device. Alternatively, an angle of 45 degrees or more and less than 80 degrees, or 50 degrees or more and less than 75 degrees is preferable, as this improves the coverage of the film formed in the opening 290.

[0127] Also, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, the coverage of the semiconductor layer 230 and the like on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a laminated structure, the inclination of the side surface of each layer in the opening 290 may be different. Similarly, when the conductive layer 240 has a laminated structure, the inclination of the side surface of each layer in the opening 290 may be different.

[0128] 9A to 15C, examples of transistor configurations that are partially different from the transistor 200A will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0129] [Transistor 200B] Fig. 9A is a plan view of a semiconductor device including transistor 200B. Fig. 9B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 9A. Fig. 9C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 9A. Note that Fig. 7D can be referred to for a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 9B and 9C.

[0130] The semiconductor device shown in FIGS. 9A to 9C differs from the semiconductor device shown in FIGS. 7A to 7D in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0131] In the transistor 200B, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the transistor 200A described above, and therefore detailed description thereof will be omitted.

[0132] 9B and 9C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with opening 270 that reaches insulating layer 250 at a position overlapping opening 290.

[0133] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 is provided on the insulating layer 250 and contacts the insulating layer 250 within the opening 270. The conductive layer 260 has a portion that faces the semiconductor layer 230 with the insulating layer 250 interposed therebetween within the opening 290, and a portion that is located within the opening 270.

[0134] 9B and 9C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that when the width of the opening 290 and the width of the opening 270 are small, only the conductive layer 260_1 may be provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 may be provided in the opening 270. Alternatively, only the conductive layer 260_1 may be provided in the opening 270.

[0135] The conductive layer 265 is provided over the conductive layer 260 and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other. The conductive layer 265 may be considered a component of the transistor 200B. The height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same.

[0136] The conductive layer 265 functions as a gate electrode. The conductive layer 265 can be formed using a material that can be used for the conductive layer 260. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 265. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0137] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0138] The transistor 200B has a structure in which parasitic capacitance generated between the gate electrode and the other of the source electrode and the drain electrode is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0139] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0140] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0141] The insulating layer 284 preferably has a function of capturing or fixing hydrogen. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230 can be suppressed, and further, hydrogen contained in the semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced. The insulating layer 284 can be made of aluminum oxide, hafnium oxide, hafnium zirconium oxide, hafnium silicate, or the like.

[0142] The insulating layer 284 can also serve as a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen from above the insulating layer 284 to the semiconductor layer 230. Silicon nitride and silicon nitride oxide are each unlikely to transmit oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0143] When the insulating layer 284 includes a silicon nitride film, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0144] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may have a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0145] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0146] Note that a structure similar to that of the transistor 200A can also be applied to the transistor 200B.

[0147] [Transistor 200C] Fig. 10A is a plan view of a semiconductor device including transistor 200C. Fig. 10B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 10A. Fig. 10C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 10A. Fig. 10D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 10B and 10C.

[0148] 11A shows an enlarged view of FIG. 10B, and FIG. 11B shows an enlarged view of FIG. 10D.

[0149] The transistor 200C shown in FIGS. 10A to 10D differs from the transistor 200A shown in FIGS. 7A to 7D in that an insulating layer 225 is provided between the insulating layer 280 and the semiconductor layer 230.

[0150] Since the insulating layer 225 is a layer provided in the opening 290, it is preferably formed by a chemical vapor deposition (CVD) method or an ALD method, and more preferably by an ALD method, thereby enabling the insulating layer 225 to be provided with good coverage.

[0151] As shown in FIG. 10B and other figures, the conductive layer 220_2 has a first recess and a second recess whose end is located further outward than the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. Furthermore, the side surface of the second recess coincides or nearly coincides with the side surface of the insulating layer 280 in the opening 290, and the side surface of the first recess coincides or nearly coincides with the surface of the insulating layer 225 facing the semiconductor layer 230. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0152] 10B and other drawings, the insulating layer 225 is in contact with the bottom surface and side surfaces of the second recessed portion of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280 and the conductive layer 240 within the opening 290. The semiconductor layer 230 is in contact with the bottom surface and side surfaces of the first recessed portion of the conductive layer 220, the surface of the insulating layer 225 facing the semiconductor layer 230, and the top surface of the conductive layer 240_2. The insulating layer 250 is located inside the semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0153] 11A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area where the side surface of the conductive layer 220_2 is in contact with the semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200C due to the contact resistance between the conductive layer 220_2 and the semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening 290.

[0154] 11A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably greater than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200C. Furthermore, the gate electric field is also easier to apply to the region of the semiconductor layer 230 in contact with the conductive layer 220_2, thereby increasing the on-state current of the transistor 200C. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200C can be improved. The shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 in the opening 290.

[0155] Here, as shown in FIG. 11A, the width (film thickness) of the insulating layer 225 is set to width T ＳＷ11B shows the channel width W of the transistor 200C. ＳＷ By reducing the width T ＳＷ By increasing the width T ＳＷ is, for example, preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less.

[0156] The channel length of the transistor 200C can be regarded as the distance between the source region and the drain region, and can be referred to as the length L shown in FIG.

[0157] 11A illustrates a configuration in which the conductive layer 220_2 has a first recess and a second recess, but the present invention is not limited to this. For example, the transistor 200C may have a configuration in which only the first recess is provided in the conductive layer 220_2. In this case, the insulating layer 225 contacts the side surface of the insulating layer 280, the side surface of the conductive layer 240, and the top surface of the conductive layer 220_2 within the opening 290. Furthermore, the semiconductor layer 230 contacts the bottom surface and side surface of the first recess of the conductive layer 220_2, the surface of the insulating layer 225 facing the semiconductor layer 230, and the top surface of the conductive layer 240_2.

[0158] A recess may be formed in the conductive layer 220_2 in one or both of the steps of forming the opening 290 and forming the insulating layer 225.

[0159] The transistor 200C may have a structure in which the insulating layer 225 does not cover at least a part of the side surface of the conductive layer 240_2. In this case, the side surface of the conductive layer 240_2 that is not covered with the insulating layer 225 is in contact with the semiconductor layer 230. Therefore, contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. Furthermore, by having a structure in which the insulating layer 225 does not cover at least a part of the side surface of the conductive layer 240_1, the contact resistance can be further reduced.

[0160] 11A shows an example in which the insulating layer 225 has a single-layer structure. Note that the insulating layer 225 can have a stacked structure of two or more layers.

[0161] Note that the same structure as at least one of the transistor 200A and the transistor 200B can also be applied to the transistor 200C.

[0162] [Transistor 200D] Fig. 12A is a plan view of a semiconductor device including transistor 200D. Fig. 12B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 12A. Fig. 12C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 12A. Fig. 12D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 12B and 12C.

[0163] 12A to 12D differs from the semiconductor device shown in Figures 7A to 7D mainly in that it includes an insulating layer 225, a conductive layer 255, and an insulating layer 281. Furthermore, the transistor 200D shown in Figures 12A to 12D differs from the transistor 200C shown in Figures 10A to 10D mainly in that it includes the conductive layer 255 and the insulating layer 281.

[0164] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240_1 is located over the insulating layer 281.

[0165] As shown in FIG. 12B, an opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0166] The semiconductor layer 230 has a region that faces the conductive layer 255 with the insulating layer 225 interposed therebetween and faces the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200D.

[0167] In the transistor 200D, the conductive layer 260 serves as a first gate electrode, the insulating layer 250 serves as a first gate insulating layer, the conductive layer 255 serves as a second gate electrode, and the insulating layer 225 serves as a second gate insulating layer.

[0168] In the transistor 200D, one of the conductive layer 255 and the conductive layer 260 can be used as a gate electrode, and the other can be used as a back gate electrode. The transistor 200D may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. By using the conductive layer 260, which has a wider region facing the semiconductor layer 230 than the conductive layer 255, as the gate electrode, a gate electric field can be applied to the semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. Note that when the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer, and the insulating layer 225 functions as a back gate insulating layer.

[0169] Since the transistor 200D includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200D can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0170] The conductive layer 255 can be formed using a conductive material that can be used for the conductive layer 260 .

[0171] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0172] Note that the same structure as at least one of the transistors 200A to 200C can also be applied to the transistor 200D.

[0173] Although the transistors 200A to 200D each have a configuration in which at least some of the components of the transistor are provided in the opening 290 that is circular in plan view, the present invention is not limited to this. At least some of the components of the transistor can be provided in a groove that extends through the insulating layer 280 or the like.

[0174] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0175] [Transistor 200E] Fig. 13A is a plan view of a semiconductor device including transistor 200E. Fig. 13B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 13A. Fig. 13C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 13A. Fig. 13D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 13B and 13C.

[0176] 13A to 13D differ from the semiconductor device shown in Figures 7A to 7D in that the semiconductor device includes a conductive layer 243a, a conductive layer 243b, and a conductive layer 246. A transistor 200E shown in Figures 13A to 13D differs from the transistor 200A shown in Figures 7A to 7D in that some of the components are provided in a groove 291 instead of an opening 290. The transistor 200E also differs from the transistor 200A shown in Figures 7A to 7D in that the conductive layer 240 is separated into a conductive layer 240a and a conductive layer 240b by the groove 291.

[0177] 13A to 13D includes an insulating layer 283 over a transistor 200E. The insulating layer 285 is provided over the insulating layer 283.

[0178] 13A to 13D , the insulating layer 280 has a groove 291 that reaches the conductive layer 220. The groove 291 extends in the X direction. The semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each disposed such that at least a portion thereof is located within the groove 291.

[0179] The semiconductor layer 230 is provided in an island shape. The semiconductor layer 230 is provided so as to follow part of the bottom and part of the sidewall of the groove 291. The semiconductor layer 230 has a portion in contact with the top surface of the conductive layer 240, a portion in contact with the side surface of the conductive layer 240 on the groove 291 side, a portion in contact with the side surface of the insulating layer 280 on the groove 291 side, and a portion in contact with the bottom surface and side surface of the recess of the conductive layer 220 in the groove 291.

[0180] The insulating layer 250 is provided to cover the semiconductor layer 230. The insulating layer 250 is also provided on the insulating layer 280 to cover the top and side surfaces of the semiconductor layer 230 and the side surfaces of the conductive layer 240.

[0181] The conductive layer 260 is provided so as to fill at least a part of the groove 291. Therefore, the conductive layer 260 is provided so as to extend in the direction in which the groove 291 extends.

[0182] The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200E, and the conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode of the transistor 200E. A channel is also formed along the sidewall of the groove 291 in the transistor 200E.

[0183] Openings reaching the conductive layer 240a are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 243a is provided in the openings. Openings reaching the conductive layer 240b are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, and a conductive layer 243b is provided in the openings. The conductive layer 243a is in contact with the conductive layer 240a, and the conductive layer 243b is in contact with the conductive layer 240b.

[0184] The conductive layer 246 is provided on the insulating layer 285. The conductive layer 246 is connected to the conductive layer 240a through the conductive layer 243a and to the conductive layer 240b through the conductive layer 243b. The conductive layer 246 functions as the other of the source electrode and the drain electrode. The conductive layer 246 extends in the Y direction. That is, the direction in which the conductive layer 246 extends intersects with the direction in which the groove 291 extends.

[0185] In the transistors 200A to 200D, the width of the conductive layer 240 in the X direction (short side) needs to be larger than the width D of the opening 290 in order to provide the conductive layer 240 in an extended state. On the other hand, in the transistor 200E, the conductive layers 240a and 240b functioning as the other of the source electrode and the drain electrode are connected through the conductive layer 246. Therefore, the widths of the conductive layers 240a and 240b in the X direction can be smaller than those of the transistors 200A to 200D, thereby enabling miniaturization of the semiconductor device. For example, the widths of the conductive layers 240a and 240b in the X direction can be smaller than the width D1 of the groove 291 (see FIG. 13D ).

[0186] On the other hand, in the transistors 200A to 200D, it is not necessary to process the semiconductor layer 230 in the opening 290, which makes it easier to process the semiconductor layer 230 and improves the productivity of the semiconductor device.

[0187] In a plan view, the side surface of the conductive layer 260 provided in the groove 291 has a portion facing the side surface of the semiconductor layer 230 with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200E is determined by the width D2 of the semiconductor layer 230 (see FIG. 13D ). The channel width of the transistor 200E can be calculated as "2×D2."

[0188] 13D , in a plan view of the transistor 200E, the portion of the semiconductor layer 230 located in the groove 291 does not have a curved surface. Therefore, distortion is less likely to occur in the region of the semiconductor layer 230 near the insulating layer 250, and deterioration of the crystallinity of the region can be suppressed. Note that the region includes a channel formation region.

[0189] On the other hand, in a plan view of the transistors 200A to 200D, a portion of the semiconductor layer 230 located at the opening 290 has a curved surface. However, the curvature of the curved surface can be reduced (the radius of curvature of the curved surface can be increased) by increasing the width of the opening 290 or by reducing the film thickness of the semiconductor layer 230. Therefore, distortion occurring in a region of the semiconductor layer 230 near the insulating layer 250 can be reduced, and deterioration of the crystallinity of the region can be suppressed.

[0190] Furthermore, when the semiconductor layer 230 is formed in the groove portion 291, by using silicon oxide having a small thermal expansion coefficient for the insulating layer 280 provided before the formation of the semiconductor layer 230, when indium oxide is used for the semiconductor layer 230, the crystal growth of the indium oxide can be promoted inside the groove portion 291 of the insulating layer 280.

[0191] 13A to 13D , the height of the top surface of the conductive layer 260 is higher than the height of the top surface of the insulating layer 250. Note that the present invention is not limited to this. The height of the top surface of the conductive layer 260 may be the same as or approximately the same as the height of the top surface of the insulating layer 250, or may be lower than the height of the top surface of the insulating layer 250.

[0192] 13A to 13D, the cross-sectional area of ​​the conductive layer 260 functioning as a gate electrode can be increased, leading to reduced wiring resistance. Thus, the power consumption of the semiconductor device can be reduced.

[0193] 13A to 13D illustrate a configuration in which the extension direction of the groove 291 coincides with the extension direction of the conductive layer 260 functioning as the gate electrode, but the present invention is not limited to this. For example, the extension direction of the groove 291 may intersect with the extension direction of the gate electrode.

[0194] [Transistor 200F] Fig. 14A is a plan view of a semiconductor device including transistor 200F. Fig. 14B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 14A. Fig. 14C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 14A. Fig. 14D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 14B and 14C.

[0195] 14A to 14D differ from the semiconductor device shown in Figures 13A to 13D mainly in that it has a conductive layer 265 and does not have an insulating layer 283, a conductive layer 243a, a conductive layer 243b, or a conductive layer 246. It also differs from the semiconductor device shown in Figures 13A to 13D mainly in that the conductive layer 260 is provided in an island shape and that the conductive layers 240a and 240b are provided in an extended manner.

[0196] The conductive layer 265 is provided on the insulating layer 285 and is in contact with the conductive layer 260. The conductive layer 265 is provided to extend in the Y direction. The conductive layers 240a and 240b are provided to extend in the X direction.

[0197] The conductive layer 260 is provided in an island shape. In a plan view, the outer periphery of the conductive layer 260 is located inside the outer periphery of the semiconductor layer 230. Note that in a plan view, the outer periphery of the conductive layer 260 may overlap with a part of the outer periphery of the semiconductor layer 230, or may be located outside the part of the outer periphery of the semiconductor layer 230.

[0198] In the YZ plane including the semiconductor layer 230, the end of the semiconductor layer 230 outside the groove portion 291 is located more inward than the end of the conductive layer 240 outside the groove portion 291 (see FIG. 14B ). Note that in the YZ plane including the semiconductor layer 230, the end of the semiconductor layer 230 outside the groove portion 291 may coincide or approximately coincide with the end of the conductive layer 240 outside the groove portion 291, or may be located more outward than the end of the conductive layer 240 outside the groove portion 291.

[0199] The insulating layer 285 is provided on the insulating layer 250. The insulating layer 285 is also provided so as to fill in the portion of the groove 291 where the conductive layer 260 is not located.

[0200] 14A to 14D , the physical distance between the conductive layer 260 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or 240b can be reduced. Furthermore, the physical distance between the conductive layer 265 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a or 240b can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0201] 14A to 14D illustrate a configuration in which the conductive layer 260 has a region facing the side surface of the conductive layer 240a across the semiconductor layer 230 and a region facing the side surface of the conductive layer 240b across the semiconductor layer 230, but the present invention is not limited to this. For example, a first conductive layer facing the side surface of the conductive layer 240a across the semiconductor layer 230 and a second conductive layer facing the side surface of the conductive layer 240b across the semiconductor layer 230 may be provided.

[0202] [Transistor 200Ga and Transistor 200Gb] Fig. 15A is a plan view of a semiconductor device including transistor 200Ga and transistor 200Gb. Fig. 15B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 15A. Fig. 15C is a cross-sectional view taken along dashed dotted line A5-A6 in Fig. 15B.

[0203] The semiconductor device shown in Figures 15A to 15C differs from the semiconductor device shown in Figures 14A to 14C in that the conductive layer 220, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each separated in and near the groove portion 291.

[0204] The transistor 200Ga has a conductive layer 220a, a conductive layer 240a on the insulating layer 280, a semiconductor layer 230a, an insulating layer 250a on the semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. The transistor 200Gb has a conductive layer 220b, a conductive layer 240b on the insulating layer 280, a semiconductor layer 230b, an insulating layer 250b on the semiconductor layer 230b, and a conductive layer 260b on the insulating layer 250b.

[0205] In the transistor 200Ga, the semiconductor layer 230a functions as a semiconductor layer, the conductive layer 260a functions as a gate electrode, the insulating layer 250a functions as a gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source electrode and the drain electrode. In the transistor 200Gb, the semiconductor layer 230b functions as a semiconductor layer, the conductive layer 260b functions as a gate electrode, the insulating layer 250b functions as a gate insulating layer, the conductive layer 220b functions as one of a source electrode and a drain electrode, and the conductive layer 240b functions as the other of the source electrode and the drain electrode.

[0206] By providing the transistor 200Ga in contact with one sidewall of the groove 291 and the transistor 200Gb in contact with the other sidewall of the groove 291, miniaturization and high integration of semiconductor devices can be promoted.

[0207] Although FIGS. 15A to 15C illustrate a configuration in which the insulating layer 250 is separated into insulating layers 250a and 250b, the present invention is not limited to this.

[0208] Note that a structure similar to that of at least one of the transistors 200A to 200D can also be applied to each of the transistors 200E, 200F, 200Ga, and 200Gb.

[0209] <Structural Example 2 of Semiconductor Device> Another structural example of a semiconductor device of one embodiment of the present invention will be described with reference to Figures 16A to 16D. Figure 16A is a plan view of a semiconductor device including a transistor 200H. Figure 16B is a cross-sectional view taken along dash-dotted line A1-A2 in Figure 16A and is also a cross-sectional view of the transistor 200H in the channel length direction. Figure 16C is a cross-sectional view taken along dash-dotted line A3-A4 in Figure 16A and is also a cross-sectional view of the transistor 200H in the channel width direction. Figure 16D is a cross-sectional view taken along dash-dotted line A5-A6 in Figure 16A.

[0210] The transistor 200H has a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 271a on the conductive layer 242a, an insulating layer 271b on the conductive layer 242b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0211] In the transistor 200H, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0212] An insulating layer 275 is provided on the insulating layer 271a and the insulating layer 271b, and an insulating layer 280 is provided on the insulating layer 275. An opening 289 is formed in the insulating layer 280 and the insulating layer 275, reaching the insulating layer 222 and the semiconductor layer 230, and the opening 289 overlaps the region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surfaces of the insulating layer 280 in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a and the conductive layer 242b. The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the upper end of the insulating layer 250, and the top surface of the conductive layer 260, respectively. An insulating layer 283 is provided on the insulating layer 282, and an insulating layer 285 is provided on the insulating layer 283. Further, an insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0213] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, 275, and 271a, and conductive layers 243a and 241a are provided in the openings. An insulating layer 241a is provided in contact with the sidewall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, 275, and 271b, and conductive layers 243b and 241b are provided in the openings. An insulating layer 241b is provided in contact with the sidewall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as plugs that connect a wiring or the like provided over the transistor 200H to the source or drain of the transistor 200H.

[0214] The semiconductor layer 230 includes a channel formation region and a source region and a drain region sandwiching the channel formation region, as in the transistor 200H. That is, the semiconductor layer 230 includes a channel formation region, a source region, and a drain region. At least a portion of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0215] The semiconductor layer 230 is physically separated between the transistors 200H adjacent in the channel length direction. This configuration can prevent the Row Hammer effect and the Passing Gate effect when the transistor 200H is used in a memory cell. The Row Hammer effect refers to a phenomenon in which, in a configuration in which the word lines (conductive layers 260) of two transistors are adjacent and the channel formation regions of the two transistors are connected, accumulated charge leaks to the adjacent word line, causing malfunction. The Passing Gate effect refers to a phenomenon in which charge moves to a floating gate or gate insulating layer, resulting in the formation of an unintended current path or a change in characteristics such as a threshold voltage fluctuation.

[0216] An insulating layer containing excess oxygen is provided near an oxide semiconductor layer, and heat treatment is performed to supply oxygen from the insulating layer to the oxide semiconductor layer, thereby filling oxygen vacancies in the oxide semiconductor layer and defects in which hydrogen has entered the oxygen vacancies (hereinafter referred to as V Ｏ H). However, if an excessive amount of oxygen is supplied to the source region or drain region, the on-state current or field-effect mobility of the transistor 200H may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if the amount of oxygen supplied from the insulating layer to the oxide semiconductor layer becomes excessively large, the electrical characteristics and reliability of the transistor may be adversely affected. Furthermore, oxygen may diffuse into conductive layers such as a gate electrode, a source electrode, and a drain electrode, causing the conductive layers to be oxidized and losing their conductivity.

[0217] First, at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen is formed near the semiconductor layer 230, and V in the channel formation region of the semiconductor layer 230 and its vicinity is formed. Ｏ It is preferable to reduce H.

[0218] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0219] It is preferable that the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 each have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may each be made of silicon nitride, which has a high hydrogen barrier property.

[0220] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating layer.

[0221] 16B , by providing an insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200H, it is possible to suppress diffusion of hydrogen from layers below the transistor 200H. Furthermore, by providing an insulating layer 214 having a function of capturing or fixing hydrogen, it is possible to capture or fix hydrogen contained in the insulating layer 216 or the like in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0222] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0223] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0224] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200H, it is possible to suppress diffusion of hydrogen from above the transistor 200H. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0225] In this way, by using a structure in which the transistor 200H is surrounded by barrier insulating layers against hydrogen from above and below, diffusion of hydrogen into the oxide semiconductor is suppressed, and the V Ｏ H can be reduced. This can improve the electrical characteristics and reliability of the transistor 200H.

[0226] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0227] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0228] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 via the insulating layer 250. Because the insulating layers 282 and 283 having a barrier property against oxygen are formed on the insulating layer 280, the oxygen contained in the insulating layer 280 can be prevented from being released from the insulating layer 280 to above the transistor 200H during the heat treatment. Furthermore, because the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, the oxygen contained in the insulating layer 280 can be prevented from being excessively supplied from the insulating layer 280 to the semiconductor layer 230. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be outward diffused, and the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 can be adjusted.

[0229] 16B shows an example in which the semiconductor layer 230 has a single-layer structure. Note that the semiconductor layer 230 can have a stacked structure of two or more layers.

[0230] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layers 242a, 242b, and 260 from being oxidized.

[0231] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0232] The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. The conductive material described in the below-described [Conductive Layer] can be used for the conductive layer 205. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. Furthermore, as shown in FIGS. 16A and 16C , the conductive layer 205 is preferably provided so as to extend in the channel width direction. With such a structure, when a plurality of transistors are provided, the conductive layer 205 functions as a wiring.

[0233] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200H can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. For example, when the transistor 200H is an n-channel transistor, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200H and reduce its off-state current. Therefore, when the transistor 200H is an n-channel transistor, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V compared to when a negative potential is not applied.

[0234] The insulating layer 224 functions as a second gate insulating layer together with the insulating layers 221 and 222 .

[0235] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0236] Furthermore, the insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. As a result, when a plurality of transistors 200H are provided, each transistor 200H has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200H becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200H within the substrate surface can be suppressed.

[0237] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 16C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230.

[0238] The conductive layers 242a and 242b can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a and 242b. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0239] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen.

[0240] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. For example, when each of the conductive layers 242a and 242b has a two-layer stacked structure, the first layer of each of the conductive layers 242a and 242b may be made of the above-mentioned conductive material, and the second layer of each of the conductive layers 242a and 242b may be made of a conductive material having higher conductivity than the first layer. For example, tantalum nitride may be used for the first layer, and tungsten may be used for the second layer.

[0241] The insulating layers 271a and 271b are inorganic insulating layers that function as etching stoppers and protect the conductive layers 242a and 242b when processing the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, respectively, they are preferably inorganic insulators that are resistant to oxidation of the conductive layers 242a and 242b. Therefore, it is preferable that the insulating layers 271a and 271b each have a two-layer structure. Here, it is preferable to use, for example, silicon nitride for the first layer of each of the insulating layers 271a and 271b to prevent oxidation of the conductive layers 242a and 242b. It is also preferable to use, for example, silicon oxide for the second layer of each of the insulating layers 271a and 271b to function as an etching stopper.

[0242] The insulating layers that are the basis for the insulating layers 271a and 271b function as masks for the conductive layers that are the basis for the conductive layers 242a and 242b, so that the conductive layers 242a and 242b do not have curved surfaces between their side surfaces and top surfaces, as shown in FIG. 16D . As a result, the conductive layers 242a and 242b have angular ends where their side surfaces and top surfaces intersect. The angular ends where their side surfaces and top surfaces intersect increase the cross-sectional areas of the conductive layers 242a and 242b compared to when the ends have curved surfaces. As a result, the resistance of the conductive layers 242a and 242b is reduced, thereby increasing the on-state current of the transistors.

[0243] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side surface and upper surface of the semiconductor layer 230, via the insulating layer 250. The height of the upper surface of the conductive layer 260 is the same as or approximately the same as the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0244] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 can be improved, and defects such as voids can be reduced.

[0245] 16A and 16C, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0246] 16C , in a cross-sectional view of the transistor 200H in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0247] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0248] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, as described in the "Insulating Layer" section below. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0249] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0250] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0251] The conductive layer 243a and the conductive layer 243b can each be formed using a conductive material described in the "Conductive Layer" section below. The conductive layer 243a and the conductive layer 243b are each preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 243a and the conductive layer 243b may each have a stacked structure.

[0252] 16B , the height of the upper surface of each of conductive layer 243a and conductive layer 243b is the same or approximately the same as the height of the upper surface of insulating layer 285. In addition, conductive layer 243a may be formed so that its lower portion is embedded in conductive layer 242a. Similarly, conductive layer 243b may be formed so that its lower portion is embedded in conductive layer 242b.

[0253] The insulating layer 241a and the insulating layer 241b may each be a barrier insulating layer applicable to the insulating layer 275 or the like. For example, silicon nitride may each be used for the insulating layer 241a and the insulating layer 241b. The insulating layer 241a and the insulating layer 241b are provided in contact with the insulating layer 285, the insulating layer 283, the insulating layer 282, the insulating layer 280, the insulating layer 275, the insulating layer 271a, or the insulating layer 271b, respectively. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from diffusing into the semiconductor layer 230 through the conductive layer 243a and the conductive layer 243b. Silicon nitride is particularly suitable because of its high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layer 243a and the conductive layer 243b.

[0254] The insulating layer 241 a and the insulating layer 241 b may each have a stacked structure. In this case, a first insulating layer in contact with a sidewall of an opening such as the insulating layer 280 and a second insulating layer therein are preferably formed by combining a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0255] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0256] [Metal Oxide Layer] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in the semiconductor layer 230 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer (or a metal oxide layer).

[0257] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics may be easily changed and reliability may be reduced. Ｏ H may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0258] Furthermore, when an excessive amount of oxygen is supplied to the semiconductor layer 230, electron traps due to the excess oxygen are formed in the insulating layer 250. This makes the OS transistor more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0259] Therefore, in the semiconductor device of one embodiment of the present invention, the hydrogen concentration in the semiconductor layer 230 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the semiconductor layer 230. Furthermore, it is preferable to reduce the amount of excess oxygen in the semiconductor layer 230.

[0260] The semiconductor layer 230 preferably includes indium oxide. In this case, the semiconductor layer 230 includes indium and oxygen. For example, the semiconductor layer 230 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor can have a large on-state current and high frequency characteristics.

[0261] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of the film having crystal grains include a single crystal film, a polycrystalline film, and an amorphous film containing crystal grains.

[0262] The indium oxide film is preferably a single-crystal film. A single-crystal film does not have grain boundaries, so that carrier scattering at the grain boundaries can be suppressed, thereby realizing a transistor with high field-effect mobility and high reliability.

[0263] The indium oxide film may be a polycrystalline film or an amorphous film containing crystal grains. In this case, it is preferable that no crystal grain boundaries are observed in the channel formation region or that the grain boundary components are small. For example, by locating one crystal grain in the channel formation region, a structure in which no crystal grain boundaries are observed in the channel formation region can be achieved. Even in such a structure, the same effects as in a structure in which the indium oxide film is a single crystal film can be achieved.

[0264] Furthermore, two or more crystal grains may be located in the channel formation region. For example, when first and second crystal grains are located in the channel formation region, it is preferable that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide. When the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, a crystal grain boundary may not be observed at the boundary between the first crystal grain and the second crystal grain. By ensuring that the crystal orientation of the first crystal grain and the crystal orientation of the second crystal grain coincide or substantially coincide, the formation of a crystal grain boundary between the first crystal grain and the second crystal grain can be suppressed. Therefore, even in this configuration, the same effects as in the configuration in which the indium oxide film is a single crystal film can be achieved. The fact that the crystal orientation of the first crystal grains and the crystal orientation of the second crystal grains are aligned or substantially aligned can sometimes be confirmed, for example, by a high-resolution transmission electron microscope (TEM) image. Specifically, this can be confirmed by the fact that the lattice fringes of the first crystal grains and the lattice fringes of the second crystal grains are continuously connected at the boundary between the first crystal grains and the second crystal grains in the high-resolution TEM image.

[0265] In this specification, the term "grain boundary" refers to, for example, a grain boundary formed at the boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a grain boundary formed at the boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary between two crystal grains is observed in a high-resolution TEM image, if the crystal orientations of the two crystal grains are the same or nearly the same, the boundary may not be called a grain boundary.

[0266] In a crystalline film, for example, crystal grains can be confirmed in a high-resolution TEM image. In addition, in a crystalline film, for example, crystal grain boundaries can sometimes be confirmed in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0267] The degree of polycrystallinity of an indium oxide film can be evaluated by the grain size of the crystal grains. The grain size can be calculated, for example, by calculating the area of ​​the crystal grain and assuming a perfect circle corresponding to the calculated area as the diameter. The diameter in this case is sometimes called the area-equivalent circle diameter.

[0268] The degree of polycrystallinity of an indium oxide film can also be evaluated by the extension length of the grain boundaries. The extension length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification at which the grain boundaries can be observed, and calculating the total length of the grain boundaries observed in that field of view. An indium oxide film with a grain boundary extension length of 0 nm can be considered a single-crystal film. Furthermore, the longer the extension length of the grain boundaries, the more grain boundary components there are.

[0269] The extension length of the grain boundary in the indium oxide film is preferably 0 nm to 1500 nm, more preferably 0 nm to 1000 nm, and even more preferably 0 nm to 800 nm. By including an indium oxide film having an extension length of the grain boundary in the above range in the semiconductor layer 230, a configuration in which no crystal grain boundary is observed or only a small amount of grain boundary components can be realized in the channel formation region. Unless otherwise specified in this specification, the area of ​​the field of view used to calculate the extension length of the grain boundary is 90 nm square.

[0270] The thickness of the semiconductor layer 230 is more preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, even more preferably 2.5 nm to 20 nm, even more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. It is sufficient that at least a portion of the semiconductor layer 230 has a region with the above-described thickness. For example, it is sufficient that the channel formation region of the semiconductor layer 230 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved. By improving the crystallinity of the semiconductor layer 230, the semiconductor layer 230 can have crystal grains.

[0271] When a metal oxide contains indium and zinc, the metal oxide may have a high crystallinity, for example, a CAAC (C-Axis Aligned Crystal) structure. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)) and IGZO.

[0272] In an oxide semiconductor layer with high crystallinity, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film with high permeability to one or both of hydrogen and oxygen compared to, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film with low barrier properties against one or both of hydrogen and oxygen compared to, for example, an IGZO film.

[0273] The indium oxide film is formed by heat treatment at a heating temperature of 400° C. for 8 hours, and the oxygen concentration is 1×10 ２０ atoms / cm ３ 2x10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ Furthermore, the indium oxide film is preferably permeable to, for example, 1×10 ２０ atoms / cm ３ 2x10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ It is preferable that the following oxygen has the property of diffusing within the crystal grains.

[0274] Oxygen in the indium oxide film diffuses through the crystal grains and grain boundaries, and V present in the crystal grains or grain boundaries is removed. Ｏ and V Ｏ H can be reduced, and thus the transistor can be prevented from becoming normally on.

[0275] The crystallinity of the semiconductor layer 230 can be analyzed by, for example, X-ray diffractometry (XRD), TEM, or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0276] The content of the first element in the semiconductor layer 230 is preferably low. Furthermore, the concentration of the first element in the semiconductor layer 230 is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer 230, the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is preferably low, the concentrations of two selected from boron, carbon, aluminum, silicon, zinc, and gallium are more preferably low, and the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium are even more preferably low. The concentration of the first element in the semiconductor layer 230 is, for example, preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Note that the preferable concentration of the first element in the semiconductor layer 230 can also be said to be the preferable concentration of the first element in the channel formation region.

[0277] Furthermore, as will be described later, by using a precursor that has been distilled one or more times, it is possible to set the concentration of the first element in the semiconductor layer 230 to 0.01 atomic % (100 ppm) or less, 0.0001% (1 ppm) or less, 0.00001% (0.1 ppm or 100 ppb) or less, or 0.0000001% (0.001 ppm or 1 ppb) or less. That is, the content (purity) of indium excluding oxygen in the semiconductor layer 230 can be set to 99.99 atomic % or more (4N), 99.9999 atomic % or more (6N), 99.99999 atomic % or more (7N), or 99.9999999 atomic % or more (9N), and it is possible to form a semiconductor layer 230 having a purity comparable to the purity (10N) of silicon used in the semiconductor layer.

[0278] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer 230, the crystallinity of the semiconductor layer 230 can be improved.

[0279] When the semiconductor layer 230 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor having a semiconductor layer 230 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer 230, the variation in threshold voltage in the PBTS test can be reduced. This makes it possible to realize a transistor with high reliability against positive bias application. Note that the same phenomenon as when the semiconductor layer 230 contains zinc atoms may occur.

[0280] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0281] Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible reduces the number of crystal nuclei, which can promote the growth of large crystal grains, as described below.

[0282] Furthermore, by reducing the impurities in the indium oxide film, impurity scattering can be suppressed. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer 230 in the above preferred range, the field-effect mobility of the transistor can be increased to 100 cm ２ / (V·s) or more, preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0283] The concentration of the first element can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), or inductively coupled plasma atomic emission spectroscopy (ICP-AES). The evaluation can be performed using a microscope (spectroscopy) or the like.

[0284] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide with a wide band gap for the semiconductor layer 230, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0285] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide with a small effective mass of electrons for the semiconductor layer of a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0286] Here, the effective mass of the electron in the semiconductor material (m ＊ ｅ ), the effective mass of the hole (m ＊ ｈ ), and band gap (E ｇ ) are shown in Table 3. The semiconductor materials shown in Table 3 are indium oxide (In ２ O ３ ), In-Ga-Zn oxide (IGZO), and silicon (Si). ＊ ｅ and m ＊ ｈ is a value calculated by first-principles electronic structure calculation, and Eg shown in Table 3 is a value calculated by actual measurement. Note that Eg of silicon in Table 3 shows a representative actual measurement value.

[0287]

[0288] As shown in Table 3, the effective mass of electrons in indium oxide is small. Therefore, by using indium oxide, which has a small effective mass of electrons, for the semiconductor layer 230, a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also referred to as f characteristics) can be realized. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, from the viewpoint of the effective mass of electrons, the f characteristics of a transistor using indium oxide in a channel formation region are higher than the f characteristics of a Si transistor.

[0289] As shown in Table 3, the effective mass of holes in indium oxide is large. Therefore, by using indium oxide, which has a large effective mass of holes, for the semiconductor layer 230, a transistor with extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, in terms of the effective mass of holes, the off-state current of a transistor using indium oxide for a channel formation region is sufficiently smaller than the off-state current of a Si transistor.

[0290] In a transistor using indium oxide for the semiconductor layer 230, the off-state current per 1 μm of channel width at room temperature is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ It is possible to make it less than A / μm.

[0291] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be increased. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

[0292] The indium oxide film may contain one or more metal elements having a large period number in the periodic table, provided that the film has crystallinity. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction. Therefore, by including a metal element having a large period number in the periodic table, the field-effect mobility of the transistor may be improved. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium).

[0293] The semiconductor layer 230 is preferably formed by ALD. For example, a precursor and an oxidizing agent can be used to form the semiconductor layer 230. The precursor preferably contains indium. In this case, an indium oxide film is formed as the semiconductor layer 230. Note that when the precursor contains indium, a thermal ALD method can be used as the ALD method.

[0294] Examples of precursors that can be used that contain indium include triethylindium, eldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0295] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C or higher and 700°C or lower. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C or higher and 600°C or lower, for example, at 500°C.

[0296] It is preferable to use a precursor with a low impurity concentration, i.e., a high purity, in the method for forming the semiconductor layer 230. For example, by using a precursor with a purity of 3N (99.9%) or higher, preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher, it is possible to reduce the impurities in the semiconductor layer 230.

[0297] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor layer 230 can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor layer 230 can be reduced, thereby improving the crystallinity of the semiconductor layer 230.

[0298] Furthermore, it is preferable to use a precursor purified by two or more rounds of distillation (also referred to as rectification or precision distillation). Using such a precursor facilitates the formation of a metal oxide film with fewer impurities, which is preferable. By performing distillation multiple times, it is possible to further suppress the impurities originating from the starting materials used in the production of the precursor from remaining in the precursor, which is preferable. The present invention is not limited to the above, and a precursor purified by one round of distillation, i.e., simple distillation, may also be used. Simple distillation is preferable because it reduces production costs. By performing distillation one or more times, the aluminum content of the indium-containing precursor can be reduced to 100 ppm or less, 1 ppm or less, or 1 ppb (0.001 ppm) or less.

[0299] As an oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ The oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the oxidizing agent, the amount of hydrogen that diffuses into the underlayer can be reduced.

[0300] The semiconductor layer 230 can also be formed by a sputtering method. As described above, it is preferable to use a high-purity material in the method for forming the semiconductor layer 230. For example, the purity of an indium oxide sputtering target is preferably 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher. By using a high-purity material, impurities in the semiconductor layer 230 can be reduced.

[0301] As the sputtering gas, a noble gas (typically argon) or oxygen alone, or a mixture of a noble gas and oxygen, can be used. The proportion of the noble gas (typically argon) in the entire sputtering gas is, for example, 50% to 100%, preferably 70% to 100%, and more preferably 90% to 100%. By increasing the proportion of the noble gas (typically argon) in the entire sputtering gas, a semiconductor layer 230 with low crystallinity at the time of film formation can be formed. Furthermore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0302] The sputtering gas is hydrogen (H ２ ) can also be included. By introducing hydrogen when forming the semiconductor layer 230 by a sputtering method, the semiconductor layer 230 can be formed with low crystallinity. Furthermore, when forming the semiconductor layer 230, generation of crystal nuclei can be suppressed or disappearance of crystal nuclei can be promoted.

[0303] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 225, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 281, insulating layer 282, insulating layer 283, insulating layer 284, insulating layer 285, etc.) included in the semiconductor device. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of nitride oxide insulating films include silicon nitride oxide films and aluminum nitride oxide films. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0304] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0305] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0306] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0307] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0308] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0309] Furthermore, examples of materials that may have ferroelectricity include metal nitrides containing nitrogen and at least one of element M1 and element M2. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0310] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0311] Although metal oxides and metal nitrides have been described above as examples, the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0312] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0313] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0314] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0315] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has a function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor including the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0316] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a metal nitride such as aluminum nitride or silicon nitride; or a metal nitride oxide such as silicon nitride oxide.

[0317] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Other examples include metal nitride oxides such as silicon nitride oxide. Other examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0318] An insulating layer such as a gate insulating layer that is in contact with or near an oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0319] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0320] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0321] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0322] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0323] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0324] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule or OH − . Furthermore, unless otherwise specified, impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0325] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0326] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0327] [Conductive Layer] For each of the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 255, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0328] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0329] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0330] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0331] [Substrate] The substrate on which a transistor is formed can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia (YSZ) substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, any of these substrates may be used on which elements are provided. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0332] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0333] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0334] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0335] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0336] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0337] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 17A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 17B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0338] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 17B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 17A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 17A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 17A.

[0339] 17A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0340] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0341] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0342] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0343] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 17A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0344] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0345] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also referred to as microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0346] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0347] The crystallinity of indium oxide can be analyzed by, for example, XRD, TEM, or ED. Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0348] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0349] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0350] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0351] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0352] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0353] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 17C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0354] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0355] Furthermore, as shown in FIG. 17C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0356] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0357] Table 4 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 4, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 4, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0358]

[0359] A seed layer is preferably provided so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals that has a small difference in lattice constant with indium oxide (also referred to as lattice mismatch). This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0360] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0361] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0362] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0363] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0364] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0365] Embodiment 4 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 18A to 22F.

[0366] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance of the electronic components, mainframes, space equipment, data centers, and various electronic devices can be achieved.

[0367] Furthermore, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0368] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0369] In particular, the display device of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display portion. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as virtual reality (VR) devices, glasses-type augmented reality (AR) devices, and mixed reality (MR) devices.

[0370] The display device of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having such high resolution and / or high resolution, it is possible to further enhance the sense of realism and depth. The display device of one embodiment of the present invention is not particularly limited in terms of the screen ratio (aspect ratio). For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0371] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0372] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0373] [Electronic Component] FIG. 18A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 18A has a semiconductor device 981 inside a mold 984. FIG. 18A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are connected to electrode pads 986, and the electrode pads 986 are connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and connected on the printed circuit board 988 to complete the mounting substrate 989.

[0374] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0375] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0376] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0377] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0378] 18B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0379] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0380] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0381] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0382] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0383] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0384] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0385] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0386] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 18B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0387] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0388] 19A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 19A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0389] The computer 5620 can have the configuration shown in the perspective view in Fig. 19B, for example. In Fig. 19B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0390] A PC card 5621 shown in Figure 19C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 19C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.

[0391] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0392] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0393] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0394] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0395] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0396] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, learning and inference in artificial intelligence.

[0397] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0398] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0399] Fig. 19D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 19D illustrates a planet 6804 in space.

[0400] 19D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0401] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0402] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0403] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0404] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0405] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0406] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0407] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0408] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for storing the data, or to ensure cooling equipment required for storing the data.

[0409] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0410] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0411] Fig. 19E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 19E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0412] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0413] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0414] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0415] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0416] 20A to 20F , an example of a wearable device that can be worn on the head will be described. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display Substitutional Reality (SR) content, and a function to display MR content. By having an electronic device with the function to display at least one of AR, VR, SR, MR, or other content, it is possible to enhance the user's sense of immersion.

[0417] The electronic device 800 shown in Figure 20A has a pair of display panels 810, a pair of housings 811, a communication unit (not shown), a pair of mounting units 813, a control unit 814, an imaging unit (not shown), a pair of optical members 816, a frame 817, and a pair of nose pads 818.

[0418] The display device of one embodiment of the present invention can be applied to the display panel 810. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. Furthermore, the semiconductor device of one embodiment of the present invention can be applied to the control unit 814. This can reduce the power consumption of the electronic device.

[0419] The electronic device 800 can project an image displayed on the display panel 810 onto a display area 819 of the optical member 816. Because the optical member 816 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 816. Therefore, the electronic device 800 is an electronic device capable of AR display.

[0420] The electronic device 800 may be provided with a camera capable of capturing an image in front of it as an imaging unit. The electronic device 800 may also be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in the display area 819.

[0421] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0422] The electronic device 800 is also provided with a battery, which can be charged wirelessly and / or wired.

[0423] The housing 811 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 811. The touch sensor module can detect a tap operation or a slide operation by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 811 can widen the range of operations.

[0424] The electronic device 830A shown in Figure 20B and the electronic device 830B shown in Figure 20C each have a pair of display units 840, a housing 841, a communication unit 842, a pair of mounting units 843, a control unit 844, a pair of imaging units 845, and a pair of lenses 846.

[0425] The display device of one embodiment of the present invention can be applied to the display portion 840. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. This allows a user to feel a high sense of immersion. Furthermore, the semiconductor device of one embodiment of the present invention can be applied to the control portion 844. This allows the power consumption of the electronic device to be reduced.

[0426] The display unit 840 is provided inside the housing 841 at a position where it can be viewed through the lens 846. Also, by displaying different images on the pair of display units 840, it is possible to perform three-dimensional display using parallax.

[0427] The electronic device 830A and the electronic device 830B can be said to be electronic devices for VR. A user wearing the electronic device 830A or the electronic device 830B can view an image displayed on the display unit 840 through the lens 846.

[0428] It is preferable that the electronic devices 830A and 830B each have a mechanism for adjusting the left-right positions of the lens 846 and the display unit 840 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic devices 830A and 830B each have a mechanism for adjusting the focus by changing the distance between the lens 846 and the display unit 840.

[0429] The mounting unit 843 allows the user to mount the electronic device 830A or the electronic device 830B on the head. Note that, in Fig. 20B and other figures, the mounting unit 843 is shaped like the temples of glasses, but is not limited to this. The mounting unit 843 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0430] The imaging unit 845 has a function of acquiring external information. Data acquired by the imaging unit 845 can be output to the display unit 840. An image sensor can be used for the imaging unit 845. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.

[0431] Although an example including the imaging unit 845 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 845 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0432] The electronic device 830A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 840, the housing 841, and the wearing unit 843. This allows a user to enjoy video and audio simply by wearing the electronic device 830A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0433] The electronic device 830A and the electronic device 830B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0434] The electronic device of one embodiment of the present invention may have a function of wirelessly communicating with earphones 820. The earphones 820 include a communication unit (not shown) and have a wireless communication function. The earphones 820 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 800 shown in FIG. 20A has a function of transmitting information to the earphones 820 through the wireless communication function.

[0435] The electronic device may also have an earphone unit. The electronic device 830B shown in Fig. 20C has an earphone unit 847. For example, the earphone unit 847 and the control unit 844 may be configured to be connected to each other by wire. A portion of the wiring connecting the earphone unit 847 and the control unit 844 may be disposed inside the housing 841 or the attachment unit 843. The earphone unit 847 and the attachment unit 843 may also have a magnet. This allows the earphone unit 847 to be fixed to the attachment unit 843 by magnetic force, which is preferable as it makes storage easier.

[0436] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0437] 20D and 20E are perspective views of a goggle-type electronic device 860A for VR. Each of FIGS. 20D and 20E shows an example in which a pair of curved display devices 870 (display device 870_R and display device 870_L) is housed within a housing 875. Electronic device 860A also includes a motion detection unit 871, a gaze detection unit 872, a calculation unit 873, a communication unit 874, a lens 876, operation buttons 877, a mounting device 878, a sensor 879, a dial 880, and the like.

[0438] By having two display devices 870, the user can view one display device per eye. This allows for high-resolution images to be displayed even when performing 3D display using parallax. Furthermore, the display device 870 is curved in an arc shape roughly centered on the user's eye. This allows the distance from the user's eye to the display surface of the display device 870 to be constant, allowing the user to view more natural images. Even if the display device 870 exhibits viewing angle dependency, in which the brightness or chromaticity of light changes depending on the viewing angle, the user's eye can be positioned in the normal direction to the display surface of the display device 870. This effectively eliminates the effect, particularly in the horizontal direction, and allows for the display of more realistic images.

[0439] As shown in Fig. 20E, lens 876 is positioned between display device 870 and the user's eyes. Fig. 20E shows an example in which dial 880 is provided to change the position of the lens for diopter adjustment. Note that if electronic device 860A has an autofocus function, dial 880 for diopter adjustment may not be provided.

[0440] 20F shows a goggle-type electronic device 860B having one display device 870. With such a configuration, the number of parts can be reduced.

[0441] The display device 870 can display two images, one for the right eye and one for the left eye, side by side in two left and right areas. This makes it possible to display a stereoscopic image using binocular parallax. Note that the display device 870 may display two different images side by side using parallax, or may display two identical images side by side without using parallax.

[0442] Alternatively, a single image visible to both eyes may be displayed across the entire area of ​​the display device 870. This allows a panoramic image to be displayed across both ends of the field of view, enhancing the sense of realism.

[0443] The display device of one embodiment of the present invention can be applied to the display device 870. The display device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using the lens 876, pixels are not visible to a user, and a more realistic image can be displayed.

[0444] The electronic device 6500 shown in FIG. 21A is a portable information terminal that can be used as a smartphone.

[0445] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.

[0446] The electronic device 6520 shown in FIG. 21B is a portable information terminal that can be used as a tablet terminal.

[0447] The electronic device 6520 includes a housing 6501, a display portion 6502, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a control device 6509, a connection terminal 6519, and the like.

[0448] In each of the electronic devices 6500 and 6520, the display portion 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 6502 and the control device 6509.

[0449] FIG. 21C is a schematic cross-sectional view including the end portion of the housing 6501 of the electronic device 6500 or the electronic device 6520 on the microphone 6506 side.

[0450] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0451] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0452] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0453] The display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0454] 21D shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0455] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0456] 21D can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0457] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0458] 21E shows an example of a laptop computer. The laptop computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7215, and the like. A display portion 7000 is incorporated in the housing 7211. The control device 7215 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 7000 and the control device 7215.

[0459] 21F and 21G show an example of digital signage.

[0460] 21F includes a housing 7301, a display portion 7000, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0461] 21G shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0462] 21F and 21G, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0463] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0464] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0465] 21F and 21G , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0466] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0467] Furthermore, the semiconductor device and the display device according to one embodiment of the present invention can be applied to the area around the driver's seat of an automobile, which is a moving object.

[0468] Fig. 22A is a diagram illustrating the area around the windshield in the interior of a vehicle, showing display panels 9001a, 9001b, and 9001c attached to the dashboard, and a display panel 9001d attached to a pillar.

[0469] The display panels 9001a to 9001c can provide various information by displaying navigation information, a speedometer, a tachometer, mileage, a fuel gauge, gear status, air conditioning settings, etc. Furthermore, the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 9001a to 9001c can also be used as lighting devices.

[0470] The display panel 9001d can display an image from an imaging device installed on the vehicle body to complement the view blocked by the pillar (blind spot). In other words, by displaying an image from an imaging device installed on the outside of the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 9001d can also be used as a lighting device.

[0471] FIG. 22B is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0472] The mobile information terminal 9200 shown in Figure 22B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0473] 22C is a perspective view of a foldable portable information terminal 9201. The portable information terminal 9201 includes a housing 9000a, a housing 9000b, a display portion 9001, and an operation button 9056.

[0474] The housing 9000a and the housing 9000b are joined by a hinge 9055, and the hinge 9055 allows the device to be folded in half.

[0475] A display portion 9001 included in the portable information terminal 9201 is supported by two housings (a housing 9000 a and a housing 9000 b ) connected by a hinge 9055 .

[0476] 22D to 22F are perspective views showing a foldable portable information terminal 9202. Fig. 22D is a perspective view of the portable information terminal 9202 in an unfolded state, Fig. 22F is a perspective view of the portable information terminal 9202 in a folded state, and Fig. 22E is a perspective view of the portable information terminal 9202 in a state in which it is changing from one of Fig. 22D and Fig. 22F to the other. In this way, the portable information terminal 9202 can be folded into three.

[0477] A display portion 9001 of the portable information terminal 9202 is supported by three housings 9000 connected by hinges 9055 .

[0478] 22C to 22F, the display device of one embodiment of the present invention can be applied to the display portion 9001. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm to 150 mm.

[0479] The portable information terminals 9201 and 9202 are each highly portable when folded, and have a seamless, wide display area when unfolded, allowing for excellent display visibility.

[0480] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0481] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0482] In this example, the oxygen in the indium oxide film ( １８ Specifically, six samples (Sample 1A, Sample 1B, Sample 1C, Sample 1D, Sample 1E, and Sample 1F) containing indium oxide films were prepared and subjected to SIMS analysis.

[0483] Methods for manufacturing Samples 1A to 1F will be described.

[0484] For each of Samples 1A, 1B, and 1C, a silicon substrate was first prepared, and then a silicon oxide (SiOx) film with a thickness of 100 nm was formed on the silicon substrate by thermal oxidation. For each of Samples 1D, 1E, and 1F, a yttria-stabilized zirconia (YSZ) substrate was prepared.

[0485] Hereinafter, the same manufacturing method was used for Samples 1A to 1F.

[0486] Subsequently, indium oxide (InO Ｘ ) film was formed.

[0487] The indium oxide film was formed by ALD. Triethylindium (TEI) was used as a precursor. Ozone (O ３ ) and oxygen (O ２ The time for introducing the oxidizing agent during one cycle was set to 9 seconds. The target thickness of the indium oxide film was 20 nm.

[0488] Subsequently, a silicon oxynitride (SiON) film having a thickness of 50 nm was formed on the indium oxide film by plasma enhanced chemical vapor deposition (PECVD: Plasma Enhanced CVD, also referred to as plasma CVD).

[0489] Subsequently, a silicon oxide (SiOx) film having a thickness of 50 nm was formed on the silicon oxynitride film by sputtering. １８ O ２ Gas was used.

[0490] Subsequently, a silicon nitride (SiN) film having a thickness of 20 nm was formed on the silicon oxide film by sputtering.

[0491] Subsequently, Sample 1B and Sample 1E were each subjected to a heat treatment in a nitrogen atmosphere at 400° C. for 1 hour. Sample 1C and Sample 1F were each subjected to a heat treatment in a nitrogen atmosphere at 400° C. for 8 hours. Sample 1A and Sample 1D were not subjected to a heat treatment.

[0492] In this manner, Samples 1A to 1F were fabricated.

[0493] SIMS analysis was performed on each of Samples 1A to 1F. The analysis direction of the SIMS analysis was from the surface side of the sample toward the substrate. １８The SIMS analysis was performed using a quadrupole secondary ion mass spectrometer (PHI-ADEPT1010) manufactured by ULVAC-PHI, Inc., and the primary ion species was Cs. ＋ Hereafter, the depth profile of oxygen concentration is calculated as follows: １８ This is sometimes referred to as the O profile.

[0494] FIG. 23A shows the results of the measurements of Samples 1A to 1C. １８ The results of the O profile are shown in FIG. 23B. １８ 23A and 23B, the horizontal axis indicates the depth [nm] from the sample surface, and the position at the left end, 0 nm in depth, corresponds to the sample surface (surface of the SiN film). １８ O concentration [atoms / cm ３ In each of Figures 23A and 23B, the solid lines indicate the values ​​of the samples without heat treatment (Sample 1A and Sample 1D). １８ The broken line indicates the O profile of the samples (samples 1B and 1E) that were heat-treated at 400°C for 1 hour in a nitrogen atmosphere. １８ The dotted line indicates the O profile of the samples (samples 1C and 1F) that were heat-treated at 400°C for 8 hours in a nitrogen atmosphere. １８ This is the O profile.

[0495] 23A and 23B, regardless of the difference in the underlayer film (SiOx film or YSZ substrate) on which the indium oxide film is formed, the oxygen ( １８ It was found that oxygen (O) diffuses in the indium oxide film. Note that since the lattice mismatch between YSZ crystals and indium oxide crystals is small, the indium oxide film on the YSZ substrate can grow epitaxially and become a single crystal film. On the other hand, since the SiOx film has an amorphous structure, the indium oxide film formed on the SiOx film can become a film with lower crystallinity than a single crystal (e.g., a polycrystalline film). From FIGS. 23A and 23B, it can be seen that both the indium oxide film formed on the SiOx film (corresponding to Samples 1A to 1C) and the indium oxide film formed on the YSZ substrate (corresponding to Samples 1D to 1F) can be annealed at 400° C. to remove oxygen ( １８It was found that SiO diffuses in the indium oxide film.

[0496] Oxygen in the indium oxide film ( １８ The oxygen (O) concentration in the indium oxide film after the heat treatment tended to be higher in the region closer to the interface with the upper SiON film, and there were also regions where the concentration changed by more than 10 times before and after the heat treatment. １８ It was found that the O) concentration increased slightly after 8 hours of heat treatment (corresponding to Samples 1C and 1F) compared to after 1 hour of heat treatment (corresponding to Samples 1B and 1E).

[0497] From the above, the indium oxide film can absorb oxygen ( １８ The results suggest that oxygen (O) has a tendency to easily diffuse. This result supports the content explained in the first embodiment. It was also found that oxygen present in the indium oxide film can be diffused relatively easily by performing a heat treatment at 400°C. This is because the heat treatment at 400°C increases the energy of the oxygen ( １８ O).

[0498] In this example, the impurity concentrations in the indium oxide films were evaluated. Specifically, three samples (Sample 2A, Sample 2B, and Sample 2C) including indium oxide films were prepared and subjected to SIMS analysis.

[0499] Methods for manufacturing Samples 2A, 2B, and 2C will be described.

[0500] For all samples, a silicon substrate was first prepared, and then a silicon oxide (SiOx) film with a thickness of 100 nm was formed on the silicon substrate by thermal oxidation.

[0501] Subsequently, indium oxide (InO Ｘ ) film was formed.

[0502] For Sample 2A, an indium oxide film was formed by sputtering. ２ O ３ Using a target, 5% hydrogen (H ２ The deposition was carried out under an argon atmosphere (Ar) containing HCl, aiming for a film thickness of 50 nm.

[0503] For both Sample 2B and Sample 2C, the indium oxide films were formed by ALD, but the precursor conditions used for forming the indium oxide films were different between Sample 2B and Sample 2C.

[0504] In this film formation, triethylindium (TEI) was used as a precursor. For sample 2B, a precursor that was not subjected to precision distillation was used, and for sample 2C, a precursor that was subjected to precision distillation twice was used. In addition, in this film formation, ozone (O ３ ) and oxygen (O ２ ) was used, and the time for introducing the oxidant in one cycle was set to 30 seconds.

[0505] In addition, for Sample 2B, an indium oxide film was formed to a target thickness of 40 nm, and for Sample 2C, an indium oxide film was formed to a target thickness of 20 nm.

[0506] In this manner, Samples 2A, 2B, and 2C were prepared.

[0507] SIMS analysis was performed on each of Sample 2A, Sample 2B, and Sample 2C. The analysis direction of the SIMS analysis was from the surface side of the sample toward the substrate. The SIMS analysis obtained depth profiles of aluminum (Al), gallium (Ga), and zinc (Zn) concentrations. The SIMS analysis was performed using a magnetic field secondary ion mass spectrometer (IMS-7f-Auto) manufactured by CAMECA, and the primary ion species was O. ２ ＋ Hereinafter, the depth profile of Al concentration may be referred to as an Al profile. The depth profile of Ga concentration may be referred to as a Ga profile. The depth profile of Zn concentration may be referred to as a Zn profile.

[0508] FIG. 24A shows the results of the Al profile, Ga profile, and Zn profile for sample 2A. FIG. 24B shows the results of the Al profile, Ga profile, and Zn profile for sample 2B. FIG. 24C shows the results of the Al profile, Ga profile, and Zn profile for sample 2C. In FIGS. 24A to 24C, the horizontal axis indicates the depth [nm] from the sample surface, and the position at a depth of 0 nm on the left edge corresponds to the sample surface (the surface of the indium oxide film). The vertical axis indicates the concentration [atoms / cm] of Al, Ga, or Zn, respectively. ３ The background level of Al in the SIMS analysis is 3.0 × 10 １５ atoms / cm ３ and the background level of Ga is 4.0 × 10 １５ atoms / cm ３ and the background level of Zn is 1.5×10 １７ atoms / cm ３ 24A to 24C, the solid line is the Al profile, the dashed line is the Ga profile, and the dotted line is the Zn profile.

[0509] 24B, it was confirmed that the concentrations of Al, Ga, and Zn in the indium oxide film of Sample 2B were all higher than their respective background levels. On the other hand, FIG. 24C confirmed that the concentrations of Al, Ga, and Zn in the indium oxide film of Sample 2C were all suppressed to below their respective background levels. From this, it was found that when the ALD method is used to form an indium oxide film, the concentrations of Al, Ga, and Zn in the indium oxide film can be significantly reduced when the film is formed using a precursor that has been subjected to precision distillation (corresponding to Sample 2C) compared to when the film is formed using a precursor that has not been subjected to precision distillation (corresponding to Sample 2B). Note that the Al concentration (3.0 × 10) in the indium oxide film of Sample 2C was 1.0 × 10. １５ atoms / cm ３ or less), and Ga concentration (4.0 × 10 １５ atoms / cm ３(below) correspond to a purity of 7N.

[0510] Furthermore, it was confirmed from FIG. 24A that the concentrations of Al, Ga, and Zn in the indium oxide film of Sample 2A were all lower than those of Sample 2B, although not as high as those of Sample 2C.

[0511] From the above, it was found that when ALD is used to form an indium oxide film, the impurity concentration in the indium oxide film can be reduced and the purity can be increased by using a precursor that has been subjected to precision distillation. It was also suggested that increasing the number of precision distillations may enable the formation of indium oxide with a purity of 7N or higher.

[0512] Furthermore, it was found that even when a sputtering method is used to form an indium oxide film, the impurity concentration in the indium oxide film can be reduced compared to when the film is formed by an ALD method using a precursor that has not been subjected to precision distillation.

[0513] As shown in Table 2 (diffusion barrier during diffusion at the 24d site center), when a crystalline indium oxide film contains impurity elements such as Al or Ga, the oxygen diffusion barrier in the indium oxide film increases, increasing the possibility that oxygen vacancies in the indium oxide film cannot be fully compensated for. Furthermore, as described in the third embodiment, Al, Ga, and Zn in the indium oxide film are all impurity elements that can serve as carrier scattering sources and can cause a decrease in the field-effect mobility of a transistor using an indium oxide film as a semiconductor layer. Therefore, it is preferable that the concentrations of these impurity elements in the indium oxide film be reduced as much as possible. In this example, it was found that the impurity elements in the indium oxide film can be reduced by adjusting the film formation conditions, and that, depending on the film formation conditions, the Al concentration and Ga concentration can be reduced to below the background level in SIMS analysis.

[0514] The configurations, structures, or methods described in this embodiment can be used in appropriate combination with the configurations, structures, or methods described in other embodiment modes.

[0515] 200A: transistor, 200B: transistor, 200C: transistor, 200D: transistor, 200E: transistor, 200F: transistor, 200Ga: transistor, 200Gb: transistor, 200H: transistor, 205: conductive layer, 210: insulating layer, 212: insulating layer, 214: insulating layer, 216: insulating layer, 220: conductive layer, 220_1: conductive layer, 220_2: conductive layer, 220a: conductive layer, 220b: conductive layer, 221: insulating layer, 222: insulating layer, 224: insulating layer, 225: insulating layer, insulating layer, 230: semiconductor layer, 230a: semiconductor layer, 230b: semiconductor layer, 240: conductive layer, 240_1: conductive layer, 240_2: conductive layer, 240a: conductive layer, 240b: conductive layer, 241a: insulating layer, 241b: insulating layer, 242a: conductive layer, 242b: conductive layer, 243a: conductive layer, 243b: conductive layer, 246: conductive layer, 250: insulating layer, 250a: insulating layer, 250b: insulating layer, 255: conductive layer, 260: conductive layer, 260_1: conductive layer, 260_2: conductive layer, 260a: conductive layer, 260b: conductive layer, 265: conductive layer, 270: opening, 271a: insulating layer, 271b: insulating layer, 275: insulating layer, 280: insulating layer, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 285: insulating layer, 289: opening, 290: opening, 291: groove, 800: electronic device, 810: display panel, 811: housing, 813: wearing portion, 814: control portion, 816: optical member, 817: frame, 818: nose pad, 819: display area, 820: earphone, 830A: electronic device, 830B: electronic device, 840: display portion, 841: housing, 842: communication portion, 843: wearing portion, 844: control portion, 845: imaging portion, 846: lens, 847: earphone portion, 860A: electronic device, 86 0B: electronic device, 870: display device, 870_L: display device, 870_R: display device, 871: motion detection unit, 872: gaze detection unit, 873: calculation unit, 874: communication unit, 875: housing, 876: lens, 877: operation button, 878: attachment, 879: sensor, 880: dial, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board,993: Electrode, 994: Semiconductor device, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Motherboard 6507: camera, 6508: light source, 6509: control device, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 6519: connection terminal, 6520: electronic device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: display unit, 7001: host, 700 1sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system, 7100: television device, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7215: control device, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal , 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Housing, 9000a: Housing, 9000b: Housing, 9001: Display unit, 9001a: Display panel, 9001b: Display panel, 9001c: Display panel, 9001d: Display panel, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9055: Hinge, 9056: Operation button, 9200: Portable information terminal, 9201: Portable information terminal, 9202: Portable information terminal,

Claims

having a crystal lattice containing indium and oxygen; the indium and the oxygen have an In—O—O—In state in the crystal lattice; the diffusion barrier of the oxygen within the crystal lattice is 1.25 eV or less; Metal oxide layer. 　 A metal oxide layer having a crystal lattice comprising indium and oxygen, In the metal oxide layer, the concentration of aluminum is 3.0×10 １５ atoms / cm ３ and the concentration of gallium is 4.0 × 10 １５ atoms / cm ３ having a region that is: Metal oxide layer. 　 A metal oxide layer having a crystal lattice comprising indium and oxygen, the indium and the oxygen have an In—O—O—In state in the crystal lattice; the diffusion barrier of the oxygen in the crystal lattice is 1.25 eV or less; In the metal oxide layer, the concentration of aluminum is 3.0×10 １５ atoms / cm ３ and the gallium concentration is 4.0 × 10 １５ atoms / cm ３ having a region that is: Metal oxide layer. 　 In any one of claims 1 to 3, The diffusion coefficient of oxygen is 1.00 nm at temperatures above 300°C. ２ / s or more, Metal oxide layer. 　 In any one of claims 1 to 3, The metal oxide layer has a bixbyite-type crystal structure. Metal oxide layer. 　 A transistor comprising the metal oxide layer according to any one of claims 1 to 3, an insulating layer, and a conductive layer, the metal oxide layer has a region overlapping with the conductive layer via the insulating layer, the metal oxide layer functions as a channel formation region of the transistor, the insulating layer functions as a gate insulating layer of the transistor, the conductive layer functions as a gate electrode of the transistor. Transistor.

Images