Solid-state imaging device, and imaging device

Abstract

[Problem] To provide a solid-state imaging device and an imaging device with which, when performing a global shutter by an FD accumulation method, it is possible to suppress a decrease in conversion efficiency from accumulated charges to a voltage and reduce kTC noise. [Solution] A solid-state imaging device according to the present disclosure includes a pixel array unit. Each pixel includes: a photoelectric conversion unit that stores charge; a discharge transistor that resets the charge before the photoelectric conversion; a transfer transistor that transfers the charge stored in the photoelectric conversion unit; and a first floating diffusion that stores the transferred charge. The plurality of pixels share a second floating diffusion that stores the charge transferred from the first floating diffusion, a first reset transistor that resets the charge stored in the first and second floating diffusions, a first capacitor that is an additional capacitor that reduces the kTC noise, and a second reset transistor that connects the second floating diffusion and the first capacitor.

Description

Solid-state imaging device and imaging device

[0001] FIELD Embodiments of the present invention relate to a solid-state imaging device and an imaging apparatus.

[0002] One global shutter technique used in image capture devices is the floating diffusion (FD) accumulation method, which adds a shutter transistor to each pixel circuit, making it possible to use a rolling shutter in addition to the global shutter.

[0003] On the other hand, in the FD accumulation method, when the imaging device performs a global shutter, the charge is read out by DDS (Double Data Sampling) rather than CDS (Correlated Double Sampling), and therefore kTC noise at the time of reset cannot be canceled.

[0004] Japanese Patent Application Laid-Open No. 2022-116063

[0005] One way to reduce kTC noise is to increase the FD capacitance of the pixel. In the above-mentioned technology, in the global shutter system, multiple pixels are shared to make the FD wiring redundant, thereby increasing the FD capacitance and reducing kTC noise.

[0006] However, this structure does not sufficiently reduce kTC noise. Also, increasing the capacitance in the circuit reduces the efficiency of converting stored charge to voltage, so there is a trade-off between capacitance and conversion efficiency.

[0007] In view of these problems, the present disclosure provides a solid-state imaging device and an imaging apparatus that can suppress a decrease in the efficiency of conversion from accumulated charge to voltage and reduce kTC noise when performing a global shutter using the FD accumulation method.

[0008] A solid-state imaging device according to a first aspect of the present disclosure includes a pixel array unit in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including a photoelectric conversion unit that accumulates charge through photoelectric conversion, a drain transistor that resets the charge in the photoelectric conversion unit before the photoelectric conversion, a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit through the photoelectric conversion, and a first floating diffusion that accumulates the charge transferred by the transfer transistor, wherein a plurality of the pixels share a second floating diffusion that accumulates the charge transferred from the first floating diffusion, a first reset transistor that resets the charge accumulated in the first and second floating diffusions, a first capacitor that is an additional capacitor that reduces kTC noise, and a second reset transistor that connects the second floating diffusion and the first capacitor. As a result, for example, in the solid-state imaging device, the capacitance of the circuit increases when the second floating diffusion is reset, thereby reducing kTC noise.

[0009] In this first aspect, the second reset transistor connects the second floating diffusion and the first capacitance when resetting the charges stored in the first and second floating diffusions, thereby increasing the capacitance of the circuit when resetting the second floating diffusion, and reducing kTC noise, for example.

[0010] In this first aspect, each of the pixels further includes a first connection transistor that connects the first floating diffusion and the second floating diffusion, thereby increasing the circuit capacitance when the second floating diffusion is reset, and reducing kTC noise, for example.

[0011] In this first aspect, the plurality of pixels further include FD wiring connecting the plurality of first connection transistors and the second floating diffusion. This results in, for example, a longer wiring length for the FD wiring compared to the FD wiring of a single pixel. This increases the wiring capacitance and the capacitance of the entire circuit.

[0012] In this first aspect, the first capacitor is an MIM connected to the drain side of the second reset transistor, thereby enabling the first capacitor to have the largest capacitance for reducing kTC noise, thereby achieving a large noise reduction effect.

[0013] In this first aspect, the first capacitance is a wiring capacitance connected to a drain side of the second reset transistor or a MOS capacitance, thereby enabling, for example, the solid-state imaging device to reduce kTC noise and also reduce manufacturing steps and manufacturing costs.

[0014] In this first aspect, the drain of each of the drain transistors is connected to a power supply, which increases the circuit capacitance when the second floating diffusion is reset, thereby reducing kTC noise, for example.

[0015] In this first aspect, the second reset transistor is disposed in any empty space among the plurality of pixels that is created by sharing the first reset transistor, thereby making it possible to prevent the circuit size of the pixel from increasing, for example.

[0016] In this first aspect, each of the pixels further includes a second capacitor that stores charge overflowing from the photoelectric conversion unit, and the drain of each of the drain transistors is connected to the second capacitor. This allows the solid-state imaging device to use the first capacitor and the plurality of second capacitors in a global shutter operation, thereby further reducing kTC noise.

[0017] In the first aspect, the second capacitor is an MIM capacitor, which allows the second capacitor to have the largest capacitance for reducing kTC noise, thereby achieving a large noise reduction effect.

[0018] In this first aspect, each of the pixels further includes a second connection transistor connecting the second capacitor and the second floating diffusion, which allows the solid-state imaging device to use the first capacitor and the plurality of second capacitors as horizontal overflow storage capacitors in a rolling shutter operation, thereby achieving a high dynamic range.

[0019] In addition, in this first aspect, the drain transistor connects the second capacitor and the photoelectric conversion unit when the charges of the first and second floating diffusions are reset during global shutter operation. This allows the solid-state imaging device to use the first capacitor and the plurality of second capacitors during global shutter operation, thereby further reducing kTC noise.

[0020] In addition, in this first aspect, the second connection transistor connects the second capacitor and the second floating diffusion during a read operation in a rolling shutter operation. This allows the solid-state imaging device to use the first capacitor and the plurality of second capacitors as horizontal overflow storage capacitors during the rolling shutter operation, for example, and achieve a high dynamic range.

[0021] An imaging device according to a second aspect of the present disclosure is an imaging device including a solid-state imaging device, the solid-state imaging device including a pixel array unit in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including a photoelectric conversion unit that accumulates charge through photoelectric conversion, a drain transistor that resets the charge in the photoelectric conversion unit before the photoelectric conversion, a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit through the photoelectric conversion, and a first floating diffusion that accumulates the charge transferred by the transfer transistor, wherein a plurality of the pixels share a second floating diffusion that accumulates the charge transferred from the first floating diffusion, a first reset transistor that resets the charge accumulated in the first and second floating diffusions, a first capacitor that is an additional capacitor that reduces kTC noise, and a second reset transistor that connects the second floating diffusion and the first capacitor. As a result, for example, the imaging device can increase the capacitance of its circuit when the second floating diffusion is reset, thereby reducing kTC noise.

[0022] In this second aspect, the second reset transistor connects the second floating diffusion to the first capacitance when resetting the charge stored in the second floating diffusion, thereby increasing the capacitance of the circuit when resetting the second floating diffusion, and reducing kTC noise, for example.

[0023] In this second aspect, the first capacitor is an MIM connected to the drain side of the second reset transistor, thereby enabling the first capacitor to have the largest capacitance for reducing kTC noise, thereby achieving a large noise reduction effect.

[0024] In the second aspect, the first capacitance is a wiring capacitance connected to a drain side of the second reset transistor or a MOS capacitance, thereby enabling, for example, the imaging device to reduce kTC noise and also reduce manufacturing steps and manufacturing costs.

[0025] In this second aspect, each of the pixels further includes a second capacitor that stores charge overflowing from the photoelectric conversion unit, and the drain of each of the drain transistors is connected to the second capacitor. This allows the imaging device to use the first capacitor and the plurality of second capacitors in a global shutter operation, for example, thereby further reducing kTC noise.

[0026] In the second aspect, the second capacitor is an MIM capacitor, which allows the second capacitor to have the largest capacitance for reducing kTC noise, thereby achieving a large noise reduction effect.

[0027] In this second aspect, each of the pixels further includes a second connection transistor connecting the second capacitor and the second floating diffusion, which allows the imaging device to use the first capacitor and the plurality of second capacitors as lateral overflow storage capacitors in a rolling shutter operation, thereby achieving a high dynamic range.

[0028] FIG. 1 is a block diagram showing an example of the configuration of an imaging device in a first embodiment; FIG. 2 is a block diagram showing a schematic configuration of a solid-state imaging device in a first embodiment; FIG. 3 is an example of a circuit diagram of a pixel in a first embodiment; FIG. 4 is a diagram showing the layout of each pixel in a first embodiment; FIG. 5 is a circuit diagram of a pixel in a comparative example; FIG. 6 is an example of a timing chart of a solid-state imaging device in a first embodiment; FIG. 7 is another example of a timing chart of a solid-state imaging device in a comparative example; FIG. 8 is a diagram showing the layout of each pixel in a second embodiment; FIG. 9 is an example of a circuit diagram of a pixel in a third embodiment; FIG. 10 is a diagram showing the layout of each pixel in a third embodiment.

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and their description will be omitted as appropriate. The drawings are simplified, and components necessary for implementation other than those shown in the drawings are also included as appropriate. Furthermore, when terms such as "first" and "second" are used in this specification or claims, unless otherwise specified, they do not represent any order or importance, but are used to distinguish one configuration from another.

[0030] Additionally, in this disclosure, the terms "equal to or greater than" and "equal to or less than" can be read as "greater than" and "less than," respectively.

[0031] The X-axis, Y-axis, and Z-axis shown in the following drawings are axes that are perpendicular to one another. The X-axis and Y-axis correspond to the lateral direction (horizontal direction), and the Z-axis corresponds to the longitudinal direction (vertical direction). The +Z-axis corresponds to the upward direction, and the -Z-axis corresponds to the downward direction. Note that the -Z-axis may or may not strictly coincide with the direction of gravity.

[0032] First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device 1 according to a first embodiment.

[0033] The imaging device 1 is a device that captures an image of an object, and includes an imaging lens 210, a solid-state imaging device 10, a recording unit 211, and an imaging control unit 230. Examples of the imaging device 1 include a digital camera such as an IoT camera, or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0034] The solid-state imaging device 10 captures an image under the control of the imaging control unit 230. The solid-state imaging device 10 supplies the image to a recording unit 211 via a signal line 209.

[0035] The imaging lens 210 collects light and guides it to the solid-state imaging device 10. The imaging control unit 230 controls the solid-state imaging device 10 to capture an image. The imaging control unit 230 supplies an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging device 10 via, for example, a signal line 139. The recording unit 211 records the image.

[0036] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a fixed frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0037] In this embodiment, the imaging device 1 records the captured image in the recording unit 211, but the image may also be transmitted to the outside of the imaging device 1. In this case, an external interface for transmitting the image to the imaging device 1 is further provided. The imaging device 1 may also display the captured image. In this case, the imaging device 1 is further provided with a display unit.

[0038] FIG. 2 is a block diagram showing a schematic configuration of the solid-state imaging device 10 according to the first embodiment.

[0039] 2 includes a pixel array section 20 in which a plurality of pixels are arranged in a matrix, and a peripheral circuit section therearound, which includes a vertical drive section 12, an AD conversion section 13, a horizontal drive section 14, a control section 15, a signal processing section 16, a data storage section 17, an input / output section 18, and the like.

[0040] Each pixel arranged in a two-dimensional array in the pixel array unit 20 is composed of a photoelectric conversion unit and a plurality of pixel transistors, etc. The plurality of pixel transistors are, for example, MOS transistors such as transfer transistors, amplification transistors, selection transistors, and reset transistors. Each pixel in the pixel array unit 20 has, for example, red (R), green (G), or blue (B) color filters arranged in a Bayer array, and each pixel outputs a pixel signal of either R, G, or B (hereinafter simply referred to as a signal).

[0041] The vertical drive unit 12 is configured by, for example, a shift register, and drives the pixels row by row by supplying drive pulses to each pixel of the pixel array unit 20 via pixel drive wiring (not shown). That is, the vertical drive unit 12 selects and scans each pixel of the pixel array unit 20 row by row in the vertical direction, and outputs pixel signals based on signal charges generated in the photoelectric conversion unit of each pixel according to the amount of incident light to the signal processing unit 16 via vertical signal lines provided in common for each column.

[0042] The AD conversion unit (ADC) 13 performs DDS processing on the signal output from the pixel array unit 20 when performing a global shutter, and performs CDS processing when performing a rolling shutter, and also performs AD conversion of the signal according to these processes.

[0043] The horizontal drive unit 14 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially output the (digital) pixel signals after AD conversion of each pixel in a specified row held in the AD conversion unit 13 to the signal processing unit 16.

[0044] The control unit 15 receives a clock signal input from the outside and data instructing the operation mode, etc., and controls the overall operation of the solid-state imaging device 10. For example, the control unit 15 generates a vertical synchronization signal, a horizontal synchronization signal, etc. based on the input clock signal, and supplies them to the vertical drive unit 12, the AD conversion unit 13, the horizontal drive unit 14, etc.

[0045] The signal processing unit 16 performs various digital signal processing such as black level adjustment, column variation correction, and demosaic processing on the pixel signals supplied from the AD conversion unit 13 as needed, and supplies the resulting signals to the input / output unit 18. Depending on the operation mode, the signal processing unit 16 may only buffer the pixel signals and output them. The data storage unit 17 stores data such as parameters required for the signal processing performed by the signal processing unit 16. The data storage unit 17 also includes a frame memory for storing image signals in processes such as demosaic processing. The signal processing unit 16 can store parameters and the like input from an external image processing device via the input / output unit 18 in the data storage unit 17, and can appropriately select and execute signal processing based on instructions from the external image processing device.

[0046] The input / output unit 18 outputs the image signals sequentially input from the signal processing unit 16 to an external image processing device, for example, an ISP (Image Signal Processor) at a subsequent stage, etc. The input / output unit 18 also supplies signals and parameters input from the external image processing device to the signal processing unit 16 and the control unit 15.

[0047] The solid-state imaging device 10 is configured as described above and is, for example, a CMOS image sensor of a column AD type.

[0048] FIG. 3 is an example of a circuit diagram of the pixel 200 according to the first embodiment.

[0049] In this embodiment, the solid-state imaging device 10 has a configuration in which two vertically adjacent pixels 200 in the pixel array section 20 share a floating diffusion FD2, a reset transistor RST, a reset transistor RST2, and a capacitance Cap. For ease of explanation, the upper pixel 200 of the vertically adjacent pixels 200 will be referred to as pixel 200a, and the lower pixel 200 will be referred to as pixel 200b. The shared configuration of pixels 200a and 200b will also be referred to as a shared pixel 201.

[0050] For ease of explanation, the pixel 200 will also refer to the photoelectric conversion unit SP as a photoelectric conversion unit SPa or SPb, and the discharge transistor OFG as a discharge transistor OFGa or OFGb. The transfer transistor TGL will also refer to the transfer transistor TGLa or TGLb, and the selection transistor SEL as a selection transistor SELa or SELb. The amplification transistor AMP will also refer to the amplification transistor AMPa or AMPb, and the connection transistor FDG as a connection transistor FDGa or FDGb. The floating diffusion FD1 will also refer to the floating diffusion FD1a or FD1b.

[0051] The pixel 200a includes a photoelectric conversion unit SPa, a discharge transistor OFGa, a transfer transistor TGLa, a selection transistor SELa, an amplification transistor AMPa, a connection transistor FDGa, and a floating diffusion FD1a.

[0052] The pixel 200b includes a photoelectric conversion unit SPb, a discharge transistor OFGb, a transfer transistor TGLb, a selection transistor SELb, an amplification transistor AMPb, a connection transistor FDGb, and a floating diffusion FD1b.

[0053] As described above, the pixel 200a and the pixel 200b share the reset transistor RST, which creates free space in the circuit compared to when each pixel has a reset transistor RST. In this embodiment, the pixel 200a and the pixel 200b each have a reset transistor RST2 and a capacitance Cap in the free space in one of the circuits, and the reset transistor RST2 is turned on only when the floating diffusion FD2 is reset. When three or more pixels 200 are used as the shared pixel 201, the reset transistor RST2 and the capacitance Cap may be provided in any of the pixels 200.

[0054] Furthermore, the pixels 200a and 200b share elements via FD wiring 220, which is wiring connected to the floating diffusion FD2, and the wiring length of the FD wiring 220 is longer than that of the FD wiring of a single pixel 200. This increases the wiring capacitance, and therefore the capacitance of the entire circuit. More specifically, the connection transistor FDGa of the pixel 200a and the connection transistor FDGb of the pixel 200b are connected to the floating diffusion FD2 via the FD wiring 220.

[0055] In this example, two pixels 200 in the vertical direction share the floating diffusion FD2, the reset transistor RST, the reset transistor RST2, and the capacitance Cap. The shared pixel 201 is not limited to this configuration, and may be configured, for example, so that two pixels 200 in the horizontal direction share the reset transistor RST, the reset transistor RST2, and the capacitance Cap, or so that pixels 200 having an arbitrary n×m (n and m are natural numbers) row arrangement share the reset transistor RST, the reset transistor RST2, and the capacitance Cap. The following description will focus on the configuration in FIG. 3.

[0056] The photoelectric conversion unit SP receives incident light, performs photoelectric conversion, and accumulates the resulting electric charge. When a drive signal TGL supplied to the gate of the transfer transistor TGL goes high and the transfer transistor TGL is turned on, the electric charge accumulated in the photoelectric conversion unit SP is transferred to the floating diffusion FD1 via the transfer transistor TGL. The cathode of the photoelectric conversion unit SP is connected to the drain of the transfer transistor TGL and the drain of the discharge transistor OFG.

[0057] The discharge transistor OFG discharges electric charge from the photoelectric conversion unit SP via the overflow gate in accordance with a reset signal OFG applied to the gate. In this embodiment, the source of the discharge transistor is connected to the photoelectric conversion unit SP, and the drain is connected to the power supply VDD. This discharge of electric charge resets the amount of electric charge in the photoelectric conversion unit SP. During global shutter operation, the solid-state imaging device 10 simultaneously turns on all of the discharge transistors OFG in the pixel array unit 20 to reset the electric charge in the photoelectric conversion unit SP and start exposure. The source of the discharge transistor OFG is connected to the power supply VDD, and the gate is connected to the vertical drive unit 12 via a pixel drive line.

[0058] The floating diffusion FD1 temporarily holds the charge transferred from the photoelectric conversion unit SP by the transfer transistor TGL. The floating diffusion FD1 is formed at the connection point between the source of the transfer transistor TGL and the gate of the amplification transistor AMP. The floating diffusion FD1 is an example of a first floating diffusion.

[0059] The amplification transistor AMP outputs a pixel signal corresponding to the potentials of the floating diffusions FD1 and FD2. That is, the amplification transistor AMP forms a source follower circuit together with a load MOS (not shown) serving as a constant current source, and a pixel signal indicating a level corresponding to the charges held in the floating diffusions FD1 and FD2 is output from the amplification transistor AMP to the AD conversion unit 13 via the selection transistor SEL. The source of the amplification transistor AMP is connected to the drain of the selection transistor SEL, and the drain is connected to the power supply VDD.

[0060] The selection transistor SEL is turned on when the pixel 100 is selected by the selection signal SEL, and outputs a pixel signal of the pixel 100 to the AD conversion unit 13 via a vertical signal line. The selection transistor SEL has a drain connected to the source of the amplification transistor AMP, a source connected to the AD conversion unit 13 via a vertical signal line, and a gate connected to the vertical drive unit 12 via a pixel drive line.

[0061] The connection transistor FDG connects the floating diffusion FD1 and the floating diffusion FD2. When the connection transistor FDG is turned on by the control signal FDG, the floating diffusion FD2 stores the charge transferred from the floating diffusion FD1. By connecting the floating diffusion FD2 to the circuit, when a large signal charge flows in from the photoelectric conversion unit SP, the charge can be stored not only in the floating diffusion FD1 but also in this capacitance, so the dynamic range is not limited. The floating diffusion FD2 is an example of a second floating diffusion. One of the drain or source of the connection transistor FDG is connected to the floating diffusion FD1, the other of the drain or source is connected to the floating diffusion FD2, and the gate is connected to the vertical drive unit 12 via a pixel drive line. The connection transistor FDG is an example of a first connection transistor.

[0062] When the reset transistor RST is turned on by a reset signal RST, the charges held in the floating diffusions FD1 and FD2 are discharged to the power supply VDD, thereby resetting the charges in the floating diffusions FD1 and FD2. The reset transistor RST is an example of a first reset transistor, and the reset signal RST is an example of a first reset signal. The reset transistor RST has a drain connected to the power supply VDD, a source connected to the floating diffusion FD2, and a source connected to the vertical drive unit 12 via a pixel drive line.

[0063] When the reset transistor RST2 is turned on by the reset signal RST2, it connects the capacitance Cap to the floating diffusions FD1 and FD2. More specifically, before and after the reset transistor RST is turned on, the reset transistor RST2 is also turned on, thereby connecting the capacitance Cap to the floating diffusion FD2. At this time, the connection transistor FDG is turned on, so the floating diffusion FD1 is connected to the floating diffusion FD2. The drain of the reset transistor RST2 is connected to the power supply VDD or VSS via the capacitance Cap, and the source is connected to the floating diffusion FD2, and the source is connected to the vertical drive unit 12 via a pixel drive line. The reset transistor RST2 is an example of a second reset transistor, and the reset signal RST2 is an example of a second reset signal.

[0064] The capacitance Cap functions as an additional capacitance for reducing kTC noise that occurs when the floating diffusions FDFD1 and 2 are reset. The capacitance Cap can be a metal-insulator-metal (MIM) or wiring capacitance. The capacitance Cap is an example of a first capacitance.

[0065] FIG. 4 is a diagram showing the layout of each pixel 200 in the first embodiment.

[0066] 4 is a view of pixels 200a and 200b viewed from the +Z direction, showing the two pixels 200 viewed from the same metal layer. Similarly to the example in FIG. 3, pixels 200a and 200b are shown as pixels 200 adjacent to each other in the vertical direction. In this figure, pixels 200a and 200b are connected by FD wiring 220. For the sake of explanation, the FD wiring 220 is shown on the same metal layer, but the FD wiring 220 may be routed through a layer different from the layer shown in the figure.

[0067] In this diagram, pixel 200a and pixel 200b share the reset transistor RST, and this transistor is provided on the pixel 200a side. Furthermore, a similar location in pixel 200b is empty space, so a reset transistor RST2 is provided instead. The capacitance Cap is provided in a different layer, and is connected via a contact provided near the reset transistor RST2 of pixel 200b.

[0068] As shown in the figure, the shared pixel 201 is provided with an FD wiring 220 that connects the pixel 200a and the pixel 200b, so the wiring length is longer than when an FD wiring is provided in each pixel 200, and the FD capacitance is larger.

[0069] FIG. 5 is a circuit diagram of a pixel 200 in the comparative example.

[0070] In the comparative example, the pixel 200 includes a photoelectric conversion unit SP, a discharge transistor OFG, a transfer transistor TGL, a selection transistor SEL, an amplification transistor AMP, a connection transistor FDG, a floating diffusion FD1, a floating diffusion FD2, and a reset transistor RST.

[0071] In the comparative example, the pixel 200 does not share the FD wiring 220 with an adjacent pixel 200. The FD wiring 220 is configured as a wiring that connects the connection transistor FDG and the reset transistor RST. Therefore, the FD wiring 220 has a shorter wiring length than the shared pixel 201 in this embodiment, and the kTC noise is not sufficiently suppressed.

[0072] FIG. 6 is an example of a timing chart of the solid-state imaging device 10 according to the first embodiment.

[0073] This timing chart is a timing chart for a solid-state imaging device 10 including the pixel 200 shown in Figure 3. This timing chart shows the states of the power supply FCVDD, reset transistor RST, reset transistor RST2, connection transistor FDG, transfer transistor TGL, drain transistor OFG, and selection transistor SEL during global shutter operation. The voltage value of the power supply FCVDD is shown, and the on / off states of the other elements are shown. In this example, the power supply VDD is connected to a power supply FCVDD that lowers the power supply voltage to suppress the effects of dark current generated in the circuit while charge is being stored in the floating diffusions FD1 and FD2.

[0074] At times T1 to T3, rolling reset driving is performed on each pixel 200. Rolling reset driving refers to driving in which the photoelectric conversion units SP of a target row (in this example, two pixels 200 in the vertical direction are shared, so the target row is two rows of pixels 200) are reset and the process of starting exposure of the photoelectric conversion units SP is performed sequentially while changing the target row.

[0075] At time T1, the connection transistor FDG and the discharge transistor OFG are turned on in the pixels 200 in the target row. This resets the charge accumulated in the photoelectric conversion unit SP, and the charge accumulated in the floating diffusion FD1 is transferred to the floating diffusion FD2. From time T2 to T3, when the reset transistor RST is turned on, the charge accumulated in the floating diffusion FD2 is reset. This example shows an example in which the floating diffusion FD2 included in the pixels 200 in the target row is reset, but the other rows are also reset sequentially by the reset transistor RST being turned on from time T2 to T3.

[0076] Between times T3 and T4, exposure of each pixel 200 is performed. At time T3, the discharge transistor OFG is turned off. As a result, exposure is performed with the reset of the photoelectric conversion unit SP completed. Also at time T3, the transfer transistor TGL is turned on. As a result, the charge accumulated in the photoelectric conversion unit SP is transferred to the floating diffusion FD1. In the global shutter operation, exposure in the pixel array unit 20 is performed simultaneously for all pixels 200. At time T4, the transfer transistor TGL is turned off, and the discharge transistor OFG is turned off, completing the exposure. Also, in the FD accumulation method, the connection transistor FDG may be turned off during exposure.

[0077] Between times T4 and T6, a readout operation is performed for each pixel 200. In this configuration, readout is performed by the DDS process as described above. In the DDS process, two readout operations are performed. In the first of the two readout operations, the signal charges accumulated in the floating diffusions FD1a, FD1b, and FD2 are read out as a signal level. In the second readout operation, the floating diffusions FD1a, FD1b, and FD2 are reset to the potential of the power supply VDD, and this potential is read out as a reset level. Due to kTC noise generated when the potential is reset, different reset levels (corresponding to the potentials at times T1 and T4, respectively) are obtained when the potential is reset the first time. In the two readout operations, the difference between the first readout and the second readout is at a different reset level, and kTC noise remains.

[0078] Furthermore, where k is the Boltzmann constant, T is temperature, and C is capacitance in the circuit, kTC noise N is expressed as N=kT / C, and therefore, increasing the capacitance connected to pixel 200 reduces kTC noise. On the other hand, increasing the capacitance of pixel 200 reduces the efficiency of conversion from stored charge to voltage, and therefore, there is a trade-off between the capacitance value and conversion efficiency in the circuit.

[0079] Between times T4 and T5, the discharge transistor OFG is turned on, and the charge remaining in the photoelectric conversion unit SP is reset. Between times T5 and T6, the selection transistor SEL is turned on twice. During the first on-state, the signal charge accumulated in the floating diffusions FD1 and FD2 is read out as a signal level and output to the AD conversion unit 13. Between times T5 and T6, after the signal level is read out, the selection transistor SEL is turned off, and the first readout is completed. After the first readout is completed, the reset transistor RST is turned on, and the charge held in the floating diffusion FD2 is reset. Also, before and after the reset transistor RST is turned on, the reset transistor RST2 is turned on, and the capacitance Cap is connected to the pixel 200, thereby reducing kTC noise.

[0080] The timing at which the reset transistor RST2 turns on is not limited to the example of this timing chart, and it may be turned on at the timing at which the reset transistor RST turns on, that is, at the timing at which the floating diffusion FD2 is reset.

[0081] Between times T5 and T6, the floating diffusion FD2 is reset, and then the reset transistor RST is turned off. At this time, the reset transistor RST2 is also turned off. After the reset transistor RST is turned off, the selection transistor SEL is turned on. In the second on state, the reset level is read out from the pixel 200 with reduced kTC noise and output to the AD conversion unit 13. This completes the DDS process. By reducing the kTC noise, the S / N ratio of the pixel signal output from the solid-state imaging device 10 can be improved.

[0082] FIG. 7 is another example of a timing chart of the solid-state imaging device 10 according to the first embodiment.

[0083] This timing chart is for the solid-state imaging device 10 including the pixel 200 shown in Fig. 3. This timing chart shows the states of the power supply FCVDD, reset transistor RST, reset transistor RST2, connection transistor FDG, transfer transistor TGL, drain transistor OFG, and selection transistor SEL during rolling shutter operation.

[0084] Between times T21 and T23, the pixels 200 in the target row (in this example, two pixels 200 in the vertical direction are shared, so the target row is two rows of pixels 200) are reset. In this timing chart, between times T21 and T22, the reset transistor RST, connection transistor FDG, and transfer transistor TGL are turned on, and the pixels 200 are reset. After the reset is complete, the above-mentioned transistors are turned off. Thereafter, between times T21 and T23, the pixels 200 are reset sequentially while the target row changes.

[0085] Between times T23 and T24, the target row is changed and the pixels 200 are sequentially exposed.

[0086] Between times T24 and T25, a P-phase readout is performed, followed by a D-phase readout. In this example, in the P-phase readout, a first readout is performed in a state of low conversion efficiency in which the pixel 200 is connected to the floating diffusion FD2, and a second readout is performed in a state of high conversion efficiency in which the pixel 200 is not connected to the floating diffusion FD2. In addition, in the D-phase readout, a first readout is performed in a state of high conversion efficiency in which the pixel 200 is not connected to the floating diffusion FD2, and a second readout is performed in a state of low conversion efficiency in which the pixel 200 is connected to the floating diffusion FD2. This type of method is also called a DCG (Dual Conversion Gain) method.

[0087] In this example, the reset transistor RST2 is always in an off state during the rolling shutter operation.

[0088] FIG. 8 is an example of a timing chart of the solid-state imaging device 10 in the comparative example.

[0089] This timing chart is a timing chart for the solid-state imaging device 10 including the pixel 200 shown in Fig. 5. It shows the states of the power supply FCVDD, reset transistor RST, connection transistor FDG, transfer transistor TGL, drain transistor OFG, and selection transistor SEL during global shutter operation.

[0090] 6, the operation from times T1' to T5' is the same as the operation from times T1 to T5, and the operation from times T5' to T6' is different from the operation from times T5 to T6. Specifically, the solid-state imaging device 10 including the pixel 200 of the comparative example does not include the reset transistor RST2 and the capacitance Cap, and therefore cannot reduce the kTC noise that occurs when the floating diffusion FD2 is reset.

[0091] According to this embodiment, the solid-state imaging device 10 includes a capacitance Cap that is connected via the reset transistor RST2 when resetting the floating diffusion FD2 to each pixel 200. This increases the circuit capacitance of the solid-state imaging device 10 when resetting the floating diffusion FD2, thereby enabling kTC noise to be reduced.

[0092] Furthermore, according to this embodiment, the pixel 200 of the solid-state imaging device 10 turns on the reset transistor RST2 to connect to the capacitance Cap only when resetting the floating diffusion FD2. This prevents the solid-state imaging device 10 from connecting the capacitance Cap to the pixel 200 at unnecessary times, and can suppress a decrease in conversion efficiency.

[0093] Furthermore, according to the present embodiment, in the solid-state imaging device 10, the reset transistor RST is shared by multiple pixels 200, and the reset transistor RST2 and the capacitor Cap are arranged in the empty space of the pixel 200. This makes it possible to prevent the circuit size of the pixel 200 from becoming large.

[0094] Furthermore, according to this embodiment, the capacitance Cap connected to the pixel 200 can be an MIM or capacitance wiring. When the capacitance Cap is an MIM, the capacitance for reducing kTC noise can be maximized, resulting in a large noise reduction effect. When the capacitance Cap is a capacitance wiring, the number of manufacturing steps and manufacturing costs for the pixel 200 can be reduced compared to when the capacitance Cap is an MIM. Furthermore, using an MIM or capacitance wiring for the capacitance Cap also enables miniaturization of the circuit.

[0095] Second Embodiment FIG. 9 is a diagram showing the layout of each pixel 200 in a second embodiment.

[0096] 9 is a view of pixels 200a and 200b viewed from the +Z direction, showing the two pixels 200 viewed from the same metal layer. Similarly to the first embodiment, pixels 200a and 200b are shown as pixels 200 adjacent to each other in the vertical direction. In this figure, pixels 200a and 200b are connected by FD wiring 220. For the sake of explanation, the FD wiring 220 is shown on the same metal layer, but the FD wiring 220 may be routed through a layer different from the layer shown in the figure.

[0097] In this embodiment, two pixels 200 in the vertical direction share the floating diffusion FD2, the reset transistor RST, the reset transistor RST2, and the FC. Descriptions of the same configuration as in the first embodiment, such as the circuit diagram and timing chart of the pixel 200, will be omitted.

[0098] The floating capacitor (FC) is a MOS capacitor (gate electrode) connected to the drain of the reset transistor RST2. When the reset transistor RST2 is turned on, the pixel 200 is connected to the FC and the capacitance increases.

[0099] In this example, two pixels 200 in the vertical direction are configured to share the floating diffusion FD2, the reset transistor RST, the reset transistor RST2, and the capacitance Cap, but the shared pixel 201 is not limited to this configuration, and may be configured, for example, so that two pixels 200 in the horizontal direction share the reset transistor RST, the reset transistor RST2, and the FC, or so that pixels 200 having an arbitrary n×m (n and m are natural numbers) row arrangement share the reset transistor RST, the reset transistor RST2, and the capacitance Cap.

[0100] According to this embodiment, the capacitance Cap connected to the pixel 200 can be FC, which not only reduces kTC noise but also reduces the manufacturing process and manufacturing costs.

[0101] Third Embodiment FIG. 10 is an example of a circuit diagram of a pixel 200 according to a third embodiment.

[0102] In this embodiment, two pixels 200 adjacent in the vertical direction share the floating diffusion FD2, the reset transistor RST, the reset transistor RST2, and the capacitance MIM3.

[0103] For ease of explanation, the pixel 200 will also refer to the photoelectric conversion unit SP as a photoelectric conversion unit SPa or SPb, and the discharge transistor OFG as a discharge transistor OFGa or OFGb. The transfer transistor TGL will also refer to the transfer transistor TGLa or TGLb, and the selection transistor SEL as a selection transistor SELa or SELb. The amplification transistor AMP will also refer to the amplification transistor AMPa or AMPb, and the connection transistor FDG will also refer to the connection transistor FDGa or FDGb. The floating diffusion FD will also refer to the floating diffusion FD1a or FD1b, and the connection transistor FCG will also refer to the connection transistor FCGa or connection transistor FCGb.

[0104] The pixel 200a includes a photoelectric conversion unit SPa, a discharge transistor OFGa, a transfer transistor TGLa, a selection transistor SELa, an amplification transistor AMPa, a connection transistor FDGa, a floating diffusion FD1a, a capacitance MIM1, and a connection transistor FCGa.

[0105] The pixel 200b includes a photoelectric conversion unit SPb, a discharge transistor OFGb, a transfer transistor TGLb, a selection transistor SELb, an amplification transistor AMPb, a connection transistor FDGb, a floating diffusion FD1b, a capacitance MIM2, and a connection transistor FCGb.

[0106] In the pixel 200a, the capacitor MIM1 holds charge that overflows from the photoelectric conversion unit SPa. In the pixel 200b, the capacitor MIM2 holds charge that overflows from the photoelectric conversion unit SPb. The capacitor MIM1 is connected via a contact provided between the drain of the connection transistor FCGa and the drain of the discharge transistor OFGa in the pixel 200a. In addition, the capacitors MIM1 and MIM2 are connected to the power supply FCVDD to suppress the influence of dark current while charge is being stored in the floating diffusion FD2.

[0107] The connection transistor FCGa connects the capacitance MIM1 and the floating diffusion FD2 during rolling shutter operation. When the connection transistor FCGa is turned on by the control signal FCG, the drain is connected to the capacitance MIM1, the other source is connected to the floating diffusion FD2, and the gate is connected to the vertical drive unit 12 via a pixel drive line. The capacitance MIM2 is connected via a contact provided between the drain of the connection transistor FCGb and the drain of the discharge transistor OFGb of the pixel 200b.

[0108] The connection transistor FCGb connects the capacitor MIM2 and the floating diffusion FD2 during the rolling shutter operation. The connection transistor FCGb has a drain connected to the capacitor MIM2, the other source connected to the floating diffusion FD2, and a gate connected to the vertical drive unit 12 via a pixel drive line.

[0109] 7, the connection transistors FCGa and FCGb connect the capacitors MIM1, MIM2, and the floating diffusion FD2 during the rolling shutter operation, for example, during the read operation. The connection transistors FCGa and FCGb may also connect the capacitors MIM1, MIM2, and the floating diffusion FD2 during high conversion efficiency read.

[0110] Furthermore, the capacitors MIM1 and MIM2 are connected to the drains of the discharge transistors OFGa and OFGb, respectively, and are connected to the photoelectric conversion unit SP when the discharge transistor OFG is turned on during global shutter operation. For example, similar to the timing chart of FIG. 6, the capacitors MIM1 and MIM2 are connected to the photoelectric conversion unit when the charges of the floating diffusions FD1 and FD2 are reset.

[0111] As described above, the pixel 200a and the pixel 200b share the reset transistor RST, which creates free space in the circuit compared to when each pixel has a reset transistor RST. In this embodiment, the reset transistor RST2 and the capacitor MIM3 are provided in this free space in the circuit. The capacitor MIM3 is connected via a contact provided near the reset transistor RST2 of the pixel 200b.

[0112] In the rolling shutter operation, the capacitors MIM1, MIM2, and MIM3 can be used as lateral overflow integration capacitors (LOFICs). During charge accumulation in the photoelectric conversion unit SP and the floating diffusions FD1 and FD2, overflowed charge can be held in the capacitors MIM1, MIM2, and MIM3. As the capacitance value of the conversion capacitance in the pixel 200 increases, the charge-to-voltage conversion efficiency decreases. Furthermore, as the capacitance value of the conversion efficiency decreases, the charge-to-voltage conversion efficiency increases. A high dynamic range can be achieved by outputting pixel signals with various charge-to-voltage conversion efficiencies from each pixel and combining these pixel signals using the signal processing unit 16. The conversion efficiency of a given pixel 200 can be, for example, of the following four types: The capacitor MIM3 shared by each pixel 200 is an example of a first capacitor, and the capacitors MIM provided in each pixel, i.e., the capacitors MIM1 and MIM2, are examples of second capacitors.

[0113] The first conversion efficiency, which is the highest conversion efficiency, can be achieved by turning off the connection transistor FDG, the connection transistor FCG, the reset transistor RST, and the reset transistor RST2.

[0114] The second highest conversion efficiency can be achieved by turning on the connection transistor FDG and turning off the connection transistor FCG, the reset transistor RST, and the reset transistor RST2.

[0115] The third highest conversion efficiency can be achieved by turning on the connection transistor FDG and the connection transistor FCG and turning off the reset transistor RST and the reset transistor RST2.

[0116] The fourth conversion efficiency, which is the lowest conversion efficiency, can be achieved by turning on the connection transistor FDG, the connection transistor FCG, and the reset transistor RST2, and turning off the reset transistor RST.

[0117] In global shutter operation, the capacitors MIM1, MIM2, and MIM3 can be used as capacitors to reduce kTC noise. The reset transistor RST2 is turned on only when the floating diffusion FD2 is reset. Furthermore, the discharge transistor OFG is turned on, and when the photoelectric conversion unit SP is reset, the capacitors MIM1 and MIM2 are connected to the photoelectric conversion unit SP.

[0118] Furthermore, in the FD accumulation method, during exposure, the connection transistor FDG is in an on or off state, and the connection transistor FCG is in an off state.

[0119] FIG. 11 is a diagram showing the layout of each pixel 200 in the third embodiment.

[0120] 11 is a view of pixels 200a and 200b viewed from the +Z direction, showing the two pixels 200 viewed from the same metal layer. Similarly to FIG. 10, pixels 200a and 200b are shown as pixels 200 adjacent to each other in the vertical direction. In this figure, pixels 200a and 200b are connected by FD wiring 220. For the sake of explanation, the FD wiring 220 is shown on the same metal layer, but the FD wiring 220 may be routed through a layer different from the layer shown in the figure.

[0121] 11, the FD wiring 220 connects the reset transistor RST and the reset transistor RST2. The FD wiring 220 is also connected to the connection transistor FCGa, the connection transistor FDGa, the connection transistor FCGb, and the connection transistor FDGb.

[0122] According to this embodiment, each pixel 200 includes a capacitor MIM1 or MIM2 for charge storage, and furthermore, these pixels 200 share the reset transistor RST, the reset transistor RST2, and the capacitor MIM3. This allows the solid-state imaging device 10 to use three capacitors MIM1, MIM2, and MIM3 in global shutter operation, thereby further reducing kTC noise.

[0123] Furthermore, according to this embodiment, the solid-state imaging device 10 can use the three capacitors MIM1, MIM2, and MIM3 as horizontal overflow storage capacitors in rolling shutter operation, thereby achieving a high dynamic range.

[0124] The present disclosure has been described above by giving embodiments and their modifications, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0125] Furthermore, for example, the present disclosure can be configured as follows.

[0126] (1) A solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates charge by photoelectric conversion; a drain transistor that resets the charge in the photoelectric conversion section before the photoelectric conversion; a transfer transistor that transfers the charge accumulated in the photoelectric conversion section by the photoelectric conversion; and a first floating diffusion that accumulates the charge transferred by the transfer transistor, wherein a plurality of the pixels share: a second floating diffusion that accumulates the charge transferred from the first floating diffusion; a first reset transistor that resets the charge accumulated in the first and second floating diffusions; a first capacitance that is an additional capacitance that reduces kTC noise; and a second reset transistor that connects the second floating diffusion and the first capacitance.

[0127] (2) The solid-state imaging device according to (1), wherein the second reset transistor connects the second floating diffusion and the first capacitor when resetting the charges stored in the first and second floating diffusions.

[0128] (3) The solid-state imaging device according to (1), wherein each of the pixels further includes a first connection transistor that connects the first floating diffusion and the second floating diffusion.

[0129] (4) The solid-state imaging device according to (3), wherein the plurality of pixels further include FD wiring that connects the plurality of first connection transistors and the second floating diffusion.

[0130] (5) The solid-state imaging device according to (1), wherein the first capacitor is a metal-insulator-metal (MIM) capacitor connected to a drain side of the second reset transistor.

[0131] (6) The solid-state imaging device according to (1), wherein the first capacitance is a wiring capacitance connected to a drain side of the second reset transistor or a MOS capacitance.

[0132] (7) The solid-state imaging device according to (1), wherein the drain of each of the drain transistors is connected to a power supply.

[0133] (8) The solid-state imaging device according to (1), wherein the second reset transistor is disposed in any empty space among a plurality of pixels that is created by sharing the first reset transistor.

[0134] (9) The solid-state imaging device according to (5), wherein each of the pixels further includes a second capacitance that stores charge overflowing from the photoelectric conversion unit, and a drain of each of the drain transistors is connected to the second capacitance.

[0135] (10) The solid-state imaging device according to (9), wherein the second capacitor is a metal-insulator-metal (MIM) capacitor.

[0136] (11) The solid-state imaging device according to (10), wherein each of the pixels further includes a second connection transistor that connects the second capacitance and the second floating diffusion.

[0137] (12) The solid-state imaging device according to (10), wherein the drain transistor connects the second capacitance and the photoelectric conversion unit when the charges of the first and second floating diffusions are reset during a global shutter operation.

[0138] (13) The solid-state imaging device according to (11), wherein the second connection transistor connects the second capacitance and the second floating diffusion during a read operation in a rolling shutter operation.

[0139] (14) An imaging device including a solid-state imaging device, wherein the solid-state imaging device includes a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates charge by photoelectric conversion; a drain transistor that resets the charge of the photoelectric conversion section before the photoelectric conversion; a transfer transistor that transfers the charge accumulated in the photoelectric conversion section by the photoelectric conversion; and a first floating diffusion that accumulates the charge transferred by the transfer transistor, wherein a plurality of the pixels share: a second floating diffusion that accumulates the charge transferred from the first floating diffusion; a first reset transistor that resets the charge accumulated in the first and second floating diffusions; a first capacitance that is an additional capacitance that reduces kTC noise; and a second reset transistor that connects the second floating diffusion and the first capacitance.

[0140] (15) The imaging device according to (14), wherein the second reset transistor connects the second floating diffusion and the first capacitor when resetting the charge stored in the second floating diffusion.

[0141] (16) The imaging device according to (14), wherein the first capacitor is a metal-insulator-metal (MIM) connected to a drain side of the second reset transistor.

[0142] (17) The imaging device according to (14), wherein the first capacitance is a wiring capacitance connected to a drain side of the second reset transistor or a MOS capacitance.

[0143] (18) The imaging device according to (16), wherein each of the pixels further includes a second capacitance that stores charge overflowing from the photoelectric conversion unit, and a drain of each of the drain transistors is connected to the second capacitance.

[0144] (19) The imaging device according to (18), wherein the second capacitor is a metal-insulator-metal (MIM) capacitor.

[0145] (20) The imaging device according to (19), wherein each of the pixels further includes a second connection transistor that connects the second capacitance and the second floating diffusion.

[0146] 1: imaging device, 10: solid-state imaging device, 12: vertical drive unit, 13: AD conversion unit, 14: horizontal drive unit, 15: control unit, 16: signal processing unit, 17: data storage unit, 18: input / output unit, 20: pixel array unit, 200: pixel, 200a: pixel, 200b: pixel, 201: shared pixel, 139: signal line, 209: signal line, 210: imaging lens, 211: recording unit, 220: FD wiring, 230: imaging control unit

Claims

1. A solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates charge through photoelectric conversion; a drain transistor that resets the charge in the photoelectric conversion section before the photoelectric conversion; a transfer transistor that transfers the charge accumulated in the photoelectric conversion section through the photoelectric conversion; and a first floating diffusion that accumulates the charge transferred by the transfer transistor, wherein a plurality of the pixels share: a second floating diffusion that accumulates the charge transferred from the first floating diffusion; a first reset transistor that resets the charge accumulated in the first and second floating diffusions; a first capacitance that is an additional capacitance that reduces kTC noise; and a second reset transistor that connects the second floating diffusion and the first capacitance.

2. The solid-state imaging device according to claim 1, wherein the second reset transistor connects the second floating diffusion and the first capacitance when resetting the charges stored in the first and second floating diffusions.

3. The solid-state imaging device according to claim 1, wherein each of the pixels further includes a first connection transistor connecting the first floating diffusion and the second floating diffusion.

4. The solid-state imaging device according to claim 3, wherein the plurality of pixels further include FD wiring that connects the plurality of first connection transistors and the second floating diffusion.

5. The solid-state imaging device according to claim 1, wherein the first capacitor is a metal-insulator-metal (MIM) capacitor connected to the drain side of the second reset transistor.

6. The solid-state imaging device according to claim 1, wherein the first capacitance is a wiring capacitance connected to the drain side of the second reset transistor or a MOS capacitance.

7. The solid-state imaging device according to claim 1, wherein the drain of each of said drain transistors is connected to a power supply.

8. The solid-state imaging device according to claim 1, wherein the second reset transistor is disposed in any empty space created by sharing the first reset transistor among a plurality of pixels.

9. A solid-state imaging device according to claim 5, wherein each of the pixels further comprises a second capacitance for storing charge overflowing from the photoelectric conversion section, and the drain of each of the discharge transistors is connected to the second capacitance.

10. The solid-state imaging device according to claim 9, wherein the second capacitor is an MIM.

11. The solid-state imaging device according to claim 10, wherein each of the pixels further includes a second connection transistor connecting the second capacitance and the second floating diffusion.

12. The solid-state imaging device according to claim 10, wherein the drain transistor connects the second capacitance and the photoelectric conversion unit when the charges in the first and second floating diffusions are reset during global shutter operation.

13. The solid-state imaging device according to claim 11, wherein the second connection transistor connects the second capacitance and the second floating diffusion during a read operation in a rolling shutter operation.

14. An imaging device comprising a solid-state imaging device, the solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates charge through photoelectric conversion; a drain transistor that resets the charge in the photoelectric conversion section before the photoelectric conversion; a transfer transistor that transfers the charge accumulated in the photoelectric conversion section through the photoelectric conversion; and a first floating diffusion that accumulates the charge transferred by the transfer transistor, wherein a plurality of the pixels share: a second floating diffusion that accumulates the charge transferred from the first floating diffusion; a first reset transistor that resets the charge accumulated in the first and second floating diffusions; a first capacitance that is an additional capacitance that reduces kTC noise; and a second reset transistor that connects the second floating diffusion and the first capacitance.

15. The imaging device according to claim 14, wherein the second reset transistor connects the second floating diffusion and the first capacitor when resetting the charge stored in the second floating diffusion.

16. The imaging device according to claim 14, wherein the first capacitor is an MIM connected to the drain side of the second reset transistor.

17. The imaging device according to claim 14, wherein the first capacitance is a wiring capacitance connected to the drain side of the second reset transistor or a MOS capacitance.

18. The imaging device according to claim 16, wherein each of the pixels further comprises a second capacitance for storing charge overflowing from the photoelectric conversion section, and the drain of each of the discharge transistors is connected to the second capacitance.

19. The imaging device according to claim 18, wherein the second capacitor is an MIM.

20. The imaging device according to claim 19, wherein each of the pixels further includes a second connection transistor connecting the second capacitance and the second floating diffusion.

Images