Circuit board and semiconductor package

Abstract

This circuit board comprises: a build-up layer including an upper surface and a lower surface; a protective layer disposed on the build-up layer; and a bump part disposed on the protective layer, wherein the protective layer includes a recess part that is concave from the upper surface of the protective layer toward the lower surface of the protective layer, the recess part of the protective layer includes a first recess part and a second recess part having different widths in the horizontal direction, and the bump part includes a first bump part at least partially disposed inside the first recess part and a plurality of second bump parts disposed inside the second recess part.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Electronic components employed in electronic devices include various active and passive circuit elements, and these circuit elements may be integrated into semiconductor chips or dies. Furthermore, the semiconductor chips or dies may be provided in the form of electronic packages mounted on a substrate including circuit wiring, such as a printed circuit board (PCB).

[0004] Meanwhile, flip-chip connection structures, which utilize connection structures to mount and electrically connect semiconductor chips on printed circuit boards, are widely used in electronic packages. For example, flip-chip connection structures utilizing bumps are advantageous for implementing stacked structures of various semiconductor chips. Furthermore, flip-chip connection structures facilitate the use of multiple connection structures to secure a large number of input / output (I / O) terminals.

[0005] Among the methods for forming such connection structures, there is the Solder-On-Pad (SOP) method. The SOP method manufactures connection structures by printing metallic paste or mounting ball-shaped solder on the connection pads on the upper surface of a printed circuit board exposed by a solder mask pattern, and then reflowing to form a spherical solder portion through the surface tension effect. However, as the integration level of semiconductor chips increases and their size decreases, there is a problem that the SOP method has limitations in implementing connection members with fine pitches.

[0006] Recently, a method has been proposed that introduces post-shaped bumps as connecting elements. This method, compared to the conventional SOP method, can facilitate the implementation of fine pitches.

[0007]

[0008] The present embodiment provides a circuit board and semiconductor package that are easy to implement in a fine pitch in a heterogeneous bump portion arrangement structure with different electrical connections.

[0009]

[0010] A circuit board according to the present embodiment comprises a build-up layer including an upper surface and a lower surface; a protective layer disposed on the build-up layer; and a bump portion disposed on the protective layer, wherein the protective layer includes a recess portion concave from an upper surface of the protective layer toward a lower surface of the protective layer, the recess portion of the protective layer includes a first recess portion and a second recess portion having different widths in a horizontal direction, and the bump portion includes a first bump portion at least partially disposed inside the first recess portion, and a plurality of second bump portions disposed inside the second recess portion.

[0011] The horizontal width of the second recessed portion may be greater than the horizontal width of the first recessed portion.

[0012] The above build-up layer may include a plurality of insulating layers stacked in a vertical direction and a pad portion disposed on an upper surface of the build-up layer.

[0013] The first bump portion and the second bump portion can be connected to the pad portion.

[0014] The horizontal width of the first bump portion may be greater than the horizontal width of at least one of the plurality of second bump portions.

[0015] The first bump portion may include a penetration portion disposed on the inside of the first recess portion and penetrating the protective layer, and a protrusion portion disposed on the penetration portion.

[0016] The penetration portion of the first bump portion may include a stepped portion whose width becomes narrower as it approaches the build-up layer.

[0017] Based on the horizontal direction, the widths of the penetration portion and the protrusion portion may be the same.

[0018] The above protrusion may be arranged on the upper surface of the protective layer.

[0019] A semiconductor package according to the present embodiment includes a circuit board; and an upper circuit board disposed on the circuit board, the circuit board including a build-up layer including an upper surface and a lower surface; a protective layer disposed on the build-up layer; and a bump portion disposed on the protective layer, wherein the protective layer includes a recess portion concave from an upper surface of the protective layer toward a lower surface of the protective layer, the recess portion of the protective layer includes a first recess portion and a second recess portion having different widths in a horizontal direction, and the bump portion includes a first bump portion at least partially disposed inside the first recess portion, and a plurality of second bump portions disposed inside the second recess portion.

[0020]

[0021] Through this embodiment, an electronic component and an upper circuit board can be compactly combined by arranging a plurality of bump portions on the circuit board.

[0022] Specifically, by adjusting the vertical length of the first bump portion and the second bump portion, a sufficient placement area for the first electronic component can be secured between the first bump portion and the upper circuit board. In addition, the thickness of the solder portion for electrical connection with the upper circuit board can be reduced, and the electrical connection can also be more stable.

[0023] In addition, since the vertical thickness of the first electronic element can be increased by the vertical length of the first bump portion, there is an advantage in that the heat dissipation performance of the first electronic element can be improved.

[0024] In addition, there is an advantage in that a fine pitch of each of the plurality of bump parts can be implemented according to the division of the bonding area according to the height difference of the plurality of bump parts.

[0025]

[0026] Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0027] Figure 2 is an enlarged view of A in Figure 1.

[0028] Fig. 3 is an enlarged drawing showing the bonding structure of the first bump portion and the protective layer in Fig. 1.

[0029] FIG. 4 is a drawing showing a modified example of the bonding structure between the first bump portion and the upper protective layer according to the first embodiment of the present invention.

[0030] Figure 5 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0031] Figure 6 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0032] Figure 7 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0033] Figure 8 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0034] Figure 9 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

[0035]

[0036] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0037] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0038] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0039] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0040] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0041] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0042] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0043] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0044] Additionally, when a C component is described as being positioned between an A component and a B component, the C component includes the meaning that at least a portion overlaps with the A component or the B component. Here, the meaning of overlapping may include the meaning of overlapping in the vertical and / or horizontal direction.

[0045] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIG. 2 is an enlarged view of A in FIG. 1, and FIG. 3 is an enlarged view of the bonding structure of the first bump portion and the protective layer in FIG. 1.

[0046] Referring to FIGS. 1 to 3, a circuit board (10) according to an embodiment of the present invention may include a build-up layer (100), a protective layer (180, 190), and a bump portion (160, 170).

[0047] The build-up layer (100) may include an upper surface and a lower surface. Protective layers (180, 190) may be arranged on the upper surface and the lower surface of the build-up layer (100), respectively. The build-up layer (100) may include a plurality of insulating layers laminated in the vertical direction.

[0048] The plurality of insulating layers may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). The first to third insulating layers (111, 112, 113) may be stacked along a vertical direction. The second insulating layer (112) may be arranged on the first insulating layer (111). The third insulating layer (113) may be arranged on the second insulating layer (112). The number of insulating layers illustrated is exemplary, and the build-up layer (100) may have a greater number of insulating layers or a smaller number of insulating layers stacked in the vertical direction.

[0049] The first to third insulating layers (111, 112, 113) may each be any insulator, such as photocurable and / or thermosetting. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a prepreg (PPG) including glass fibers in a resin may be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be provided with a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material provided with glass fibers or aramid fibers may be included. When the first to third insulating layers (111, 112, 113) are photocurable insulators, the first to third insulating layers (111, 112, 113) may each be a PID (Photo Imageable Dielectric).

[0050] The materials of the first to third insulating layers (111, 112, 113) described above are exemplary, and some of the plurality of insulating layers may be implemented with materials different from other parts. In addition, although not illustrated, the circuit board (10) may include a core layer, and in this case, the plurality of insulating layers of the build-up layer (100) may be arranged on one side and the other side of the core layer with the same number of insulating layers based on the core layer. The core layer may be a prepreg (PPG) including glass fiber in a resin.

[0051] The build-up layer (100) may include a circuit pattern. A plurality of wiring portions and a plurality of via portions may be arranged in the build-up layer (100).

[0052] A plurality of wiring sections may be respectively arranged on the surfaces of a plurality of insulating layers. Here, "arranged on the surface" may also mean that at least a portion of the plurality of wiring sections are respectively embedded within the plurality of insulating layers and exposed to the outside from the surface.

[0053] In detail, the plurality of wiring portions may include a first wiring portion (121) disposed on the upper surface of the first insulating layer (111), a second wiring portion (122) disposed on the upper surface of the second insulating layer (112), and a third wiring portion (123, 124) disposed on the upper surface of the third insulating layer (113). Each of the first to third wiring portions (121, 122, 123, 124) may have a predetermined length in the horizontal direction. The first to third wiring portions (121, 122, 123, 124) may have different lengths in the horizontal direction. For example, the horizontal length of the first wiring portion (121) may be shorter than the horizontal length of the second wiring portion (122). The horizontal length of the third wiring section (123, 124) may be shorter than the horizontal length of the second wiring section (122).

[0054] The third wiring portion (123, 124) may be connected to the bump portion (160, 170). Since it is connected to the bump portion (160, 170), the third wiring portion (123, 124) may be called a pad portion. In this case, the third wiring portion (123, 124) may include a second pad portion (124) connected to the second bump portion (160) to be described later, and a first pad portion (123) connected to the first bump portion (170). The second pad portion (124) and the first pad portion (123) may be arranged to overlap in the horizontal direction. The horizontal length of the first pad portion (123) may be longer than the horizontal length of the second pad portion (124). The second pad portion (124) may be positioned at the center of the upper surface of the build-up layer (100), and the first pad portion (123) may be positioned on the outer side of the second pad portion (124) on the upper surface of the build-up layer (100). Accordingly, a bonding area with the upper circuit board (2000, see FIG. 5) to be described later may be uniformly formed along the edge of the upper surface of the build-up layer (100).

[0055] A third pad portion (125) may be arranged on the lower surface of the build-up layer (100). At least a portion of the third pad portion (125) may be exposed downward through a hole (192) of the lower protective layer (190) to be described later.

[0056] A via may be a metal material placed in a hole formed within a plurality of insulating layers to connect a plurality of pads facing each other in a vertical direction. Here, the hole may have a shape that penetrates each of the plurality of insulating layers.

[0057] The via portion may include a first via portion (126) penetrating the first insulating layer (111), a second via portion (127) penetrating the second insulating layer (112), and a third via portion (128) penetrating the third insulating layer (113). The first via portion (126) may electrically connect the third pad portion (125) and the first wiring portion (121). The second via portion (127) may electrically connect the first wiring portion (121) and the second wiring portion (122). The third via portion (128) may electrically connect the second wiring portion (122) and the third wiring portions (123, 124). The first to third via portions (126, 127, 128) may each have a shape in which a horizontal width increases as it goes downward. The first to third via portions (126, 127, 128) may each have a smaller horizontal width than the adjacent wiring portions. The first to third insulating layers (111, 112, 113) each include via holes in which the first to third via portions (126, 127, 128) are arranged, and the via holes may have a shape that penetrates from one surface of the insulating layer to the other surface.

[0058] A protective layer (180, 190) may be disposed on the surface of the build-up layer (100). The protective layer (180, 190) may include an upper protective layer (180) disposed on the upper surface of the build-up layer (100) and a lower protective layer (190) disposed on the lower surface of the build-up layer (100). The upper protective layer (180) and the lower protective layer (190) may each perform a function of preventing short circuits between solders due to low wettability with solder when a semiconductor element is disposed on the surface of a circuit board (10) using a material such as solder. A photocurable insulating material may be used for the upper protective layer (180) and the lower protective layer (190). For example, a solder resist or a PID (Photo Imageable Dielectric) may be used for the upper protective layer (180) and the lower protective layer (190).

[0059] The upper protective layer (180) and the lower protective layer (190) are distinguished based on the area where they are combined based on the build-up layer (100), and both the upper protective layer (180) and the lower protective layer (190) can be called protective layers.

[0060] The lower protective layer (190) includes a hole (192), and a portion of the lower surface of the third pad portion (125) can be exposed downward through the hole (192). Accordingly, when an electronic component (not shown) is bonded to the lower surface of the circuit board (10), the electronic component can be bonded to the lower surface of the third pad portion (125) exposed through the hole (192) through a bonding member such as a solder portion.

[0061] The upper protective layer (180) may include a recessed portion (182, 184) having a concave shape from the upper surface of the upper protective layer (180) toward the lower surface of the upper protective layer (180). When viewed from the upper side of the circuit board (10), the recessed portion (182, 184) may have a groove shape.

[0062] The recessed portions (182, 184) may include a first recessed portion (184) and a second recessed portion (182). The first recessed portion (184) and the second recessed portion (182) may be arranged to overlap in a horizontal direction.

[0063] A second bump portion (160) may be arranged in the second recess portion (182). The second recess portion (182) may be arranged to vertically overlap with a first electronic element (1000, see FIG. 5) to be described later. The horizontal width of the second recess portion (182) may be larger than the horizontal width of the first electronic element (1000). The cross-sectional area of ​​the second recess portion (182) may be larger than the cross-sectional area of ​​the first electronic element (1000). The bonding area of ​​the first electronic element (1000) may be guided on the upper surface of the circuit board (10) through the second recess portion (182).

[0064] As illustrated in FIG. 2, the bottom surface of the second recessed portion (182) may include a curved surface (181). Here, the bottom surface of the second recessed portion (182) may be the upper surface of the upper protective layer (180) on which the second bump portion (160) is disposed. The curved surface (181) may be disposed on the upper surface of the second region (187). The curved surface (181) may have a shape that connects a plurality of adjacent second bump portions (160). The curved surface (181) may have a concave shape such that the central portion faces the build-up layer (100).

[0065] The upper protective layer (180) forming the second recessed portion (182) by the curved surface (181) may include regions having different vertical thicknesses. Specifically, the upper surface of the second region (187) may have an increased thickness as it gets closer to the second bump portion (160) in the horizontal direction. The upper surface of the second region (187) may have a decreased thickness as it gets farther away from the second bump portion (160) in the horizontal direction.

[0066] Accordingly, the upper protective layer (180) can secure a wide bonding area with the second bump portion (160) by concentrating on the arrangement area of ​​the second bump portion (160). In addition, the thickness of the upper protective layer (180) can be minimized by the curved surface (181) in areas other than the arrangement area of ​​the second bump portion (160).

[0067] A first bump portion (170) can be placed in the first recess portion (184).

[0068] The first recessed portion (184) and the second recessed portion (182) may have different horizontal widths. The horizontal width of the second recessed portion (182) may be greater than the horizontal width of the first recessed portion (184). Accordingly, a relatively wide electrical connection area with the first electronic element (1000) on the circuit board (10) may be formed.

[0069] The second recessed portion (182) may be arranged in the center of the upper surface of the upper protective layer (180), and the first recessed portion (184) may be arranged on the outer side of the second recessed portion (182) on the upper surface of the upper protective layer (180). The second recessed portion (182) may be arranged to vertically overlap with the second pad portion (124). The first recessed portion (184) may be arranged to vertically overlap with at least a portion of the first pad portion (123). The first recessed portions (184) may be provided in plurality and may be arranged to be spaced apart from each other in the horizontal direction on the upper surface of the upper protective layer (180).

[0070] The vertical thickness of the upper protective layer (180) may be 5 um or more and 30 um or less. If the thickness of the upper protective layer (180) is less than 5 um, not only may its function as a protective layer be insufficient, but also the contact area with the bump portions (160, 170) described later on the upper protective layer (180) may become small. If the thickness of the upper protective layer (180) exceeds 30 um, there is a problem in that the thickness of the circuit board (10) excessively increases.

[0071] The bump portions (160, 170) may be disposed on the protective layer. The bump portions (160, 170) may be disposed on the upper protective layer (180). The bump portions (160, 170) may be disposed to penetrate the upper protective layer (180). The bump portions (160, 170) may include a first bump portion (170) and a second bump portion (160). At least a portion of the first bump portion (170) may be disposed on the inner side of the first recess portion (184). At least a portion of the second bump portion (160) may be disposed on the inner side of the second recess portion (182).

[0072] The bump portions (160, 170) can be connected to the pad portions (123, 124). The first bump portion (170) can be connected to the first pad portion (123). The second bump portion (160) can be connected to the second pad portion (124). The first bump portion (170) can be connected to an upper circuit board (2000, see FIG. 5) to be described later. The lower surface of the upper circuit board (2000) can be supported through the first bump portion (170). The second bump portion (160) can be coupled to the first electronic element (1000). The first electronic element (1000) can be electrically connected to the second bump portion (160). The first bump portion (170) and the second bump portion (160) are each provided in multiple numbers and can be arranged to be spaced apart from each other in the horizontal direction. The horizontal width of the first bump portion (170) can be larger than the horizontal width of at least one second bump portion (160) among the multiple second bump portions (160). Accordingly, the bonding with the upper circuit board (2000) having a relatively large area compared to the first electronic element (1000) can be more stably achieved.

[0073] The first bump portion (170) may include a penetration portion (174) disposed on the inside of the first recess portion (184) and a protrusion portion (176) disposed on the penetration portion (174). The penetration portion (174) may be disposed to penetrate the upper protective layer (180). The penetration portion (174) may be disposed on the inside of the first recess portion (184) and may be disposed to overlap the upper protective layer (180) in a horizontal direction.

[0074] The penetration portion (174) may include a stepped portion (172) whose width becomes narrower toward the build-up layer (100). The upper protective layer (180) may include a first hole (185) for the first bump portion (170) to pass through, and the stepped portion (172) may be arranged within the first hole (185). The first pad portion (123) and the first bump portion (170) may be connected through the stepped portion (172). The horizontal width of the first hole (185) may be the same as the horizontal width of the stepped portion (172). The horizontal width of the first hole (185) may be smaller than the horizontal width of the first recess portion (184).

[0075] The protrusion (176) may be arranged on the upper surface of the upper protective layer (180). The protrusion (176) may be arranged on the outer side of the first recessed portion (184). As illustrated in FIG. 3, the protrusion (176) may include an overlapping portion (177) that overlaps the upper protective layer (180) along the vertical direction. The horizontal width (W1) of the overlapping portion (177) may be 1 um or more and 100 um or less. The first bump portion (170) may be stably supported on the upper protective layer (180) through the overlapping portion (177), but if the width (W1) of the overlapping portion (177) exceeds 100 um, a sufficient space for arranging components on the circuit board (10) may not be secured.

[0076] In the horizontal direction, the widths of the penetration portion (174) and the protrusion portion (176) may be the same. Here, the same width may mean that the difference between the width of the penetration portion (174) and the width of the protrusion portion (176) in the horizontal direction is less than 10% of the width of the penetration portion (174) or the protrusion portion (176). Accordingly, the width of the first bump portion (170) can be formed relatively large in the connection area with the first pad portion (123), so that the durability of the first bump portion (170) can be improved.

[0077] Alternatively, the width of the protrusion (176) may be greater than the width of the penetration (174). In this case, the contact area of ​​the protrusion (176) with the upper circuit board (2000) described later may be increased.

[0078] As illustrated in FIG. 3, the length (T1) of the protrusion (176) may be 20 um or more and 90 um or less in the vertical direction. Here, the length (T1) of the protrusion (176) may be the vertical length from the upper surface of the upper protective layer (180) to the upper surface of the first bump portion (170). If the length (T1) of the protrusion (176) is less than 20 um, the vertical distance between the first electronic element (1000) and the upper circuit board (20000, see FIG. 5) may not be sufficiently secured. If the length (T1) of the protrusion (176) exceeds 90 um, the volume of the package including the circuit board (10) may excessively increase, and there is a concern that warpage of the circuit board (10) may occur due to the increase in the thickness of the first bump portion (170) relative to the thickness of the build-up layer (100).

[0079] Referring to FIG. 3, the upper protective layer (180) may include a plurality of regions with different thicknesses due to the formation of a first recessed portion (184) and a second recessed portion (182). The upper protective layer (180) may include a first region (188) having a first thickness and a second region (187) having a second thickness thinner than the first thickness. The first region (188) may be a region where the first recessed portion (184) and the second recessed portion (182) are not formed. The upper surface of the first region (188) may support the lower surface of the protrusion (176). The second region (187) may be a region where the first recessed portion (184) and the second recessed portion (182) are formed. The upper surface of the second region (187) can form the bottom surface of the first recessed portion (184) or the second recessed portion (182).

[0080] The overlapping portion (177) of the protrusion (176) can be arranged to overlap the first region (188) in a vertical direction on the first region (188). Accordingly, there is an advantage in that the first bump portion (170) can be firmly supported through the upper protective layer (180).

[0081] FIG. 4 is a drawing showing a modified example of the bonding structure between the first bump portion and the upper protective layer according to the first embodiment of the present invention.

[0082] Referring to FIG. 4, the first region (188) within the upper protective layer (180) may be omitted. In this case, the upper protective layer (180) may be formed entirely by the second region (187) having the second thickness, and the first bump portion (170) may be composed only of the protrusion (176) and the step portion (172) coupled to the first hole (185), or the protrusion (176) and the penetration portion (174) may be formed to have the same width in the horizontal direction and may be arranged in the vertical direction. In this case, a part of the penetration portion (174) may be arranged on the upper protective layer (180), and the step portion (172) may be coupled within the first hole (185) of the upper protective layer (180). Accordingly, the upper protective layer (180) may be formed to have a constant horizontal width in a wider range of regions. The horizontal width of the protrusion (176) may be greater than the horizontal width of the first pad portion (123).

[0083] Referring back to FIG. 1, the second bump portion (160) may be connected to the second pad portion (124). The second bump portions (160) may be provided in multiple numbers corresponding to the number of second pad portions (124) and may be arranged to be spaced apart from each other in the horizontal direction. The upper protective layer (180) may include a second hole (183) through which the second bump portion (160) passes, and the horizontal width of the second hole (183) may be the same as the horizontal width of the second bump portion (160). The upper surface of the second bump portion (160) may be arranged lower than the upper surface of the upper protective layer (180). The upper surface of the second bump portion (160) may be arranged to overlap the inner surface of the second recess portion (182) in the horizontal direction. Here, the inner surface of the second recess (182) may be a surface connecting the upper surface of the first region (188) and the upper surface of the second region (187).

[0084] The second bump portion (160) can be coupled with the first electronic element (1000, see FIG. 5). The second bump portion (160) can be electrically and physically connected to the first electronic element (1000) through a solder portion (198).

[0085] The plurality of second bump portions (160) may have different horizontal widths. For example, the second bump portion (160) may include a second-first bump portion (162) having a first width in the horizontal direction, and a second-second bump portion (164) having a second width smaller than the first width. Here, the first width and the second width may each be smaller than the width of the protrusion (176) of the first bump portion (170).

[0086] The vertical length (T2) of the second bump portion (160) may be shorter than the vertical length (T3) of the first bump portion (170). The vertical length (T2) of the second bump portion (160) may be 5 um or more and 30 um or less. If the vertical length (T2) of the second bump portion (160) is less than 5 um, it may be difficult to secure a sufficient thickness of the upper protective layer (180). If the vertical length (T2) of the second bump portion (160) exceeds 30 um, there is a problem in that it is difficult to secure a sufficient space for arranging the first electronic element (1000) between the upper circuit board (2000, see FIG. 5).

[0087] Accordingly, the circuit board (10) can be electrically connected to the first electronic element (1000) through a plurality of second bump portions (160).

[0088] Figure 5 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.

[0089] Referring to FIG. 5, the semiconductor package may include an upper circuit board (2000) arranged on a circuit board (10). A pad portion (2010) may be arranged on a lower surface of the upper circuit board (2000). Accordingly, the circuit board (10) and the upper circuit board (2000) may be electrically connected by a solder portion (199) connecting the pad portion (2010) and the first bump portion (170).

[0090] The vertical length (T0) from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182) may be 180 um or more and 240 um or less. If the vertical length from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182) is less than 180 um, there is a problem that it is difficult to secure sufficient space for arranging the first electronic element (1000), and the size of the first electronic element (1000) must also be reduced. If the vertical length from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182) exceeds 240 um, there is a problem that production efficiency is reduced because the size of the solder portion (199) for electrical connection between the first bump portion (170) and the upper circuit board (2000) increases unnecessarily.

[0091] Meanwhile, as described above, the bottom surface of the second recessed portion (182) may include a curved surface (181), in which case, the vertical length (T0) may be the maximum vertical distance from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182), or the minimum vertical distance. Here, the maximum vertical distance may be defined as the vertical distance from the lower surface of the upper circuit board (2000) to a concave surface of a concave shape toward the build-up layer (100) among the curved surfaces (181). The minimum vertical distance may be defined as the vertical distance from the lower surface of the upper circuit board (2000) to a surface connected to the second bump portion (160) arranged on the outer side of the concave surface among the curved surfaces (181).

[0092] The ratio of the vertical length (T1) of the protrusion (176) protruding onto the upper protective layer (180) to the vertical length (T0) from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182) may be 1:0.08 to 1:0.5. A first electronic element (1000) may be arranged on the second bump portion (160). A pad portion (1010) may be arranged on the lower surface of the first electronic element (1000). Accordingly, the second bump portion (160) and the pad portion (1010) of the first electronic element (1000) may be electrically connected by the solder portion (198). The first electronic element (1000) may be arranged so that at least a portion overlaps the first bump portion (170) in the horizontal direction. The upper surface of the first bump portion (170) may be positioned below an imaginary line (l) that divides the vertical length of the first electronic element (1000) into 1 / 2. The upper surface of the first electronic element (1000) may be vertically spaced apart from the lower surface of the upper circuit board (2000). The vertical distance between the upper surface of the first electronic element (1000) and the lower surface of the upper circuit board (2000) may be shorter than the vertical distance between the upper surface of the first bump portion (170) and the lower surface of the upper circuit board (2000). Accordingly, the thickness of the solder portion (199) for connecting the first bump portion (170) and the upper circuit board (2000) may be sufficiently secured.

[0093] A second electronic element (2100) may be placed on the upper surface of the upper circuit board (2000). The second electronic element (2100) may be soldered onto the upper circuit board (2000).

[0094] According to the above structure, the electronic component and the upper circuit board can be compactly combined by arranging a plurality of bump portions on the circuit board (10).

[0095] Specifically, by adjusting the vertical length of the first bump portion and the second bump portion, a sufficient placement area for the first electronic component can be secured between the first bump portion and the upper circuit board. In addition, the thickness of the solder portion for electrical connection with the upper circuit board can be reduced, and the electrical connection can also be more stable.

[0096] In addition, since the vertical thickness of the first electronic element can be increased by the vertical length of the first bump portion, there is an advantage in that the heat dissipation performance of the first electronic element can be improved.

[0097] In addition, there is an advantage in that a fine pitch of each of the plurality of bump parts can be implemented according to the division of the bonding area according to the height difference of the plurality of bump parts.

[0098] FIG. 6 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 7 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention.

[0099] This embodiment is identical to the first embodiment in other respects, with the only difference being that the vertical length of the protrusion is increased. Therefore, only the characteristic aspects of this embodiment will be described below, and the description of the first embodiment will be used for the remaining portions.

[0100] Referring to FIGS. 6 and 7, the circuit board (20) according to the present embodiment may include a first bump portion (270). The first bump portion (270) may include a through portion (274) disposed on the inside of the first recess portion (184) and a protrusion (276) disposed on the through portion (274). The through portion (274) may include a step portion (272) coupled within the first hole (185) of the upper protective layer (180).

[0101] The vertical length (T4) of the protrusion (276) according to the present embodiment may be longer than the vertical length of the protrusion (176) according to the first embodiment. The vertical length (T4) of the protrusion (276) may be 20 um or more and 300 um or less. When the vertical length (T4) of the protrusion (276) is 300 um, the vertical length (T0) from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182) may be longer than the length described in the first embodiment.

[0102] The upper surface of the protrusion (276) may be positioned above an imaginary line (l) that divides the vertical length of the first electronic element (1000) into 1 / 2. The vertical thickness of the protrusion (276) may be greater than the vertical thickness of the upper protective layer (180). Accordingly, not only can the thickness of the solder portion (199) for bonding with the upper circuit board (2000) be further reduced, but there is also an advantage in that the vertical length of the first electronic element (1000) can be increased by expanding the space for arranging the first electronic element (1000) between the upper circuit boards (2000).

[0103] The ratio of the vertical length (T4) of the protrusion (276) protruding onto the upper protective layer (180) to the vertical length (T0) from the lower surface of the upper circuit board (2000) to the bottom surface of the second recessed portion (182) may be 1:0.08 to 1:0.8.

[0104] FIG. 8 is a cross-sectional view of a circuit board according to a third embodiment of the present invention, and FIG. 9 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention.

[0105] In this embodiment, other aspects are identical to those of the first embodiment, with the only difference being the shape of the first bump portion. Therefore, only the characteristic aspects of this embodiment will be described below, and the description of the first embodiment will be used for the remaining aspects.

[0106] Referring to FIGS. 8 and 9, the circuit board (30) according to the present embodiment may include a first bump portion (370). The first bump portion (370) may be disposed in a first recess portion (384) of an upper protective layer (380). The first bump portion (370) may be disposed to penetrate a first hole (385) of the upper protective layer (380). The upper surface of the first bump portion (370) may be disposed lower than the upper surface of the upper protective layer (380).

[0107] Specifically, the upper protective layer (380) may include a first region (388) having a first thickness and a second region (381) having a second thickness smaller than the first thickness. A first recessed portion (384) may be arranged in the first region (388), and a second recessed portion (382) may be arranged in the second region (388). The first bump portion (370) may be arranged to penetrate the upper protective layer (380) and may be arranged on the inner side of the first recessed portion (384). The upper surface of the first bump portion (370) may be arranged lower than the upper surface of the first region (388). The upper surface of the first bump portion (370) may be arranged to overlap the inner surface of the first recessed portion (384) in a horizontal direction.

[0108] The vertical length of the first bump portion (370) may be the same as the vertical length of the second bump portion (160). Specifically, the vertical length of the first bump portion (370) may be 5 um or more and 40 um or less.

[0109] The ratio of the vertical length (T2) of the first bump portion (370) to the vertical length (T0) from the lower surface of the upper circuit board (2000) to the bottom surface of the second recess portion (182) may be 1:0.02 to 1:0.2.

[0110] According to this embodiment, the vertical length of the solder portion (199) for bonding with the upper circuit board (2000) can be increased compared to the first embodiment, but since the solder portion (199) can be guided in the placement area on the upper protective layer (380) by the first recess portion (384), there is an advantage in that the bonding process with the upper circuit board (2000) can be performed more easily.

[0111] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0112] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

[0113] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0114] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Build-up layer including the upper and lower surfaces; a protective layer disposed on the above build-up layer; and Including a bump portion disposed on the above protective layer, The protective layer includes a concave recessed portion from the upper surface of the protective layer toward the lower surface of the protective layer, The recessed portion of the above protective layer includes a first recessed portion and a second recessed portion having different widths in the horizontal direction, A circuit board including a first bump portion at least partially disposed on the inside of the first recess portion, and a plurality of second bump portions disposed on the inside of the second recess portion.

2. In paragraph 1, A circuit board in which the horizontal width of the second recessed portion is greater than the horizontal width of the first recessed portion.

3. In paragraph 1, The above build-up layer is formed by stacking multiple insulating layers along the vertical direction, A circuit board including a pad portion arranged on the upper surface of the above build-up layer.

4. In paragraph 3, A circuit board in which the first bump portion and the second bump portion are connected to the pad portion.

5. In paragraph 1, A circuit board in which the horizontal width of the first bump portion is greater than the horizontal width of at least one of the plurality of second bump portions.

6. In paragraph 1, A circuit board including a first bump portion, a penetration portion disposed on the inside of the first recess portion and penetrating the protective layer, and a protrusion portion disposed on the penetration portion.

7. In paragraph 6, A circuit board including a stepped portion in which the penetration portion of the first bump portion becomes narrower toward the build-up layer.

8. In paragraph 6, A circuit board in which the width of the penetration portion and the protrusion portion are the same in the horizontal direction.

9. In paragraph 6, A circuit board in which the protrusion is placed on the upper surface of the protective layer.

10. Circuit board; and Including an upper circuit board arranged on the circuit board, The above circuit board, A build-up layer including the upper and lower surfaces; a protective layer disposed on the above build-up layer; and Including a bump portion disposed on the above protective layer, The protective layer includes a concave recessed portion from the upper surface of the protective layer toward the lower surface of the protective layer, The recessed portion of the above protective layer includes a first recessed portion and a second recessed portion having different widths in the horizontal direction, A semiconductor package including a first bump portion at least partially disposed on the inside of the first recess portion, and a plurality of second bump portions disposed on the inside of the second recess portion.

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