High-brightness optoelectronic device and manufacturing method therefor

Abstract

The present invention relates to a high-brightness optoelectronic device and a manufacturing method therefor. The optoelectronic device comprises a driver wafer and pixel units. The pixel units are located between an N-type semiconductor layer and the driver wafer. Each pixel unit comprises a pixel body; the pixel body comprises a P-type semiconductor layer and an active layer; the P-type semiconductor layer is electrically connected to a corresponding anode contact on the driver wafer; and the N-type semiconductor layer is electrically connected to a cathode metal member, and the cathode metal member is located on a side surface of the pixel unit. Also disclosed in the present invention is a manufacturing method for an optoelectronic device. The present invention prevents a cathode connecting structure from shielding a light-emitting area of the N-type semiconductor layer, improves the light-emitting brightness of the pixel units, and effectively ensures the use reliability of the optoelectronic device.

Description

A high-brightness optoelectronic device and its fabrication method

[0001] Priority information: This application claims priority to Chinese Patent Application No. 2024107890402, filed on June 19, 2024, and Chinese Patent Application No. 2024106990085, filed on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a high-brightness optoelectronic device and its fabrication method. Background Technology

[0003] The structure of existing LED optoelectronic devices is shown in Figure 1. The pixel unit 30 of existing LED optoelectronic devices generally includes a P-type semiconductor layer 3011 and an N-type semiconductor layer 40. An active layer 3012 for emitting light is generally disposed between the P-type semiconductor layer 3011 and the N-type semiconductor layer 40, as shown in Figure 1. The P-type semiconductor layer 3011 needs to be electrically connected to the corresponding anode contact 201 on the driving wafer 20. A common cathode 10 is separately disposed on the outside of all N-type semiconductor layers 40 to achieve cathode connection of the N-type semiconductor layers of each pixel unit through the common cathode. In this way, the common cathode is covered on the N-type semiconductor layer, which will block the light emitted from the N-type semiconductor layer, thereby affecting the light emission efficiency. Even if the common cathode is a transparent conductive film, a certain amount of light loss will still occur, thereby reducing the light emission brightness.

[0004] Therefore, the existing LED optoelectronic devices have low brightness, which affects their reliability. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the defect of low brightness in existing LED optoelectronic devices, so as to improve the reliability of LED optoelectronic devices.

[0006] To address the aforementioned technical problems, this invention provides a high-brightness optoelectronic device, comprising:

[0007] A driving wafer, wherein the driving wafer includes an anode contact;

[0008] A pixel unit, wherein the pixel unit is disposed on the driving wafer and corresponds to the anode contact;

[0009] The pixel unit is located between the N-type semiconductor layer and the driving wafer. The pixel unit includes a pixel body, which includes a P-type semiconductor layer and an active layer. The active layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The P-type semiconductor layer is electrically connected to the corresponding anode contact on the driving wafer.

[0010] The N-type semiconductor layer is electrically connected to the cathode metal element, which is located on the side of the pixel unit to expose the light-emitting area of ​​the N-type semiconductor layer.

[0011] In one embodiment of the present invention, the pixel unit further includes an outer edge wall, the outer edge wall being disposed on the side wall of the pixel body, the outer edge wall including a first wall layer, the first wall layer being an insulator, the first wall layer being attached to the side wall of the pixel body, and the P-type semiconductor layer and N-type semiconductor layer of each pixel unit being insulated from each other through the first wall layer.

[0012] In one embodiment of the present invention, each pixel unit is covered with a first insulating dielectric layer, and an anode metal element is disposed on the first insulating dielectric layer. The P-type semiconductor layer of the pixel unit is electrically connected to the corresponding anode contact on the driving wafer through the anode metal element.

[0013] In one embodiment of the present invention, the driving wafer is further provided with a cathode contact corresponding to the cathode metal element. The cathode contact and the anode contact are insulated from each other by a second insulating dielectric layer. One end of the cathode metal element is connected to the N-type semiconductor layer, and the other end is connected to the corresponding cathode contact.

[0014] In one embodiment of the present invention, a metal reinforcement is provided between the cathode metal element and the N-type semiconductor layer.

[0015] In one embodiment of the present invention, each pixel unit is provided with metal reinforcements on both sides, and there is a gap between the outer edge wall of the pixel unit and the adjacent metal reinforcement, or the outer edge wall of the pixel unit is in contact with the adjacent metal reinforcement.

[0016] In one embodiment of the present invention, the N-type semiconductor layer has a first surface and a second surface arranged opposite to each other, the light-emitting area of ​​the N-type semiconductor layer is located on the first surface, the pixel unit is located between the second surface and the driving wafer, the contact surface between the cathode metal element and the N-type semiconductor layer is located on the second surface, or the contact surface between the cathode metal element and the N-type semiconductor layer covers part of the first surface and exposes the light-emitting area of ​​the N-type semiconductor layer.

[0017] In one embodiment of the present invention, there is a gap between the outer edge wall of the pixel unit and the adjacent cathode metal element, or the outer edge wall of the pixel unit is in contact with the adjacent cathode metal element.

[0018] In one embodiment of the present invention, the outer wall further includes a second wall layer, the second wall layer being attached to the outer wall of the first wall layer.

[0019] In one embodiment of the present invention, the second wall layer is either a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

[0020] In one embodiment of the present invention, the light-emitting region of the N-type semiconductor layer is formed with a plurality of protrusions.

[0021] This invention also discloses a method for fabricating a high-brightness optoelectronic device, comprising,

[0022] Fabricate a driver wafer such that the driver wafer includes anode contacts;

[0023] The invention also includes the preparation of a compound semiconductor comprising a substrate and an N-type semiconductor layer, an active layer and a P-type semiconductor layer sequentially formed along a direction away from the substrate.

[0024] A pixel unit corresponding to the anode contact is obtained by processing a compound semiconductor. The pixel unit includes a pixel body, which includes a P-type semiconductor layer and an active layer. The active layer is located between the P-type semiconductor layer and the N-type semiconductor layer, and the N-type semiconductor layer is exposed to the outside of the pixel unit.

[0025] A compound semiconductor having pixel units is connected to a driving wafer, such that the pixel units are located between an N-type semiconductor layer and the driving wafer, and that the P-type semiconductor layer of each pixel unit is electrically connected to a corresponding anode contact on the driving wafer.

[0026] Remove the substrate from the compound semiconductor;

[0027] The N-type semiconductor layer is electrically connected to the cathode metal element, such that the cathode metal element is located on the side of the pixel unit to expose the light-emitting area of ​​the N-type semiconductor layer.

[0028] In one embodiment of the present invention, the obtained pixel unit further includes an outer edge wall, the outer edge wall being disposed on the side wall of the pixel body, the outer edge wall including a first wall layer, the first wall layer being an insulator, the first wall layer being attached to the side wall of the pixel body, and the P-type semiconductor layer and N-type semiconductor layer of each pixel unit being insulated from each other through the first wall layer.

[0029] In one embodiment of the present invention, before connecting the compound semiconductor having pixel units to the driving wafer, a first insulating dielectric layer is coated on the outside of each pixel unit, and an anode metal element is disposed on the first insulating dielectric layer. Then, the P-type semiconductor layer of the pixel unit is electrically connected to the corresponding anode contact on the driving wafer through the anode metal element.

[0030] In one embodiment of the present invention, a method for processing a compound semiconductor to obtain a pixel unit corresponding to the anode contact includes,

[0031] Step S1) The compound semiconductor is etched by the first etching method, and the etching is stopped at the N-type semiconductor layer or the etching continues after the N-type semiconductor layer is etched and is stopped at a maximum of 50% of the thickness of the N-type semiconductor layer, thereby obtaining the pixel body corresponding to the anode contact.

[0032] Step S2) Deposit a first wall layer on the outside of the pixel body and etch the first wall layer using a dry etching method. After etching, only the first wall layer located on the sidewall of the pixel body is retained.

[0033] In one embodiment of the present invention, in step S2), after depositing the first wall layer on the outside of the pixel body, a second wall layer is also deposited. After all the deposition is completed, the overall structure composed of the first wall layer and the second wall layer is etched using a dry etching method. After etching, only the first wall layer and the second wall layer located on the side wall of the pixel body are retained.

[0034] Alternatively, after depositing a first wall layer on the outside of the pixel body, the first wall layer is first etched using a dry etching method, and only the first wall layer located on the sidewall of the pixel body is retained after etching. Then, a second wall layer is deposited on the outside of the first wall layer. After the deposition is completed, the second wall layer is etched using a dry etching method, and only the second wall layer located on the sidewall of the pixel body is retained after etching.

[0035] In one embodiment of the present invention, in the above preparation method, a cathode contact corresponding to the cathode metal element is provided on the driving wafer, and the cathode contact and the anode contact are insulated from each other by a second insulating dielectric layer. When the N-type semiconductor layer is electrically connected to the cathode metal element, one end of the cathode metal element is connected to the N-type semiconductor layer, and the other end is connected to the corresponding cathode contact.

[0036] In one embodiment of the present invention, in the above preparation method, a metal reinforcement is deposited on the N-type semiconductor layer, so that the N-type semiconductor layer is electrically connected to the cathode metal through the metal reinforcement.

[0037] In one embodiment of the present invention, the light-emitting region of the N-type semiconductor layer needs to undergo surface roughening treatment to form multiple protrusions.

[0038] The technical solution of the present invention has the following advantages over the prior art:

[0039] The high-brightness optoelectronic device and its fabrication method described in this invention directly connect a cathode metal component to the side of the N-type semiconductor layer to achieve cathode communication, thereby avoiding the obstruction of the light-emitting area of ​​the N-type semiconductor layer by the cathode connection structure and greatly improving the light-emitting brightness and light-emitting efficiency of the pixel unit. Attached Figure Description

[0040] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0041] Figure 1 is a schematic diagram of the structure of existing LED optoelectronic devices;

[0042] Figure 2 is a schematic diagram of the structure of the first embodiment of the high-brightness optoelectronic device of the present invention;

[0043] Figure 3 is a schematic diagram of the structure of a second embodiment of the high-brightness optoelectronic device of the present invention;

[0044] Figure 4 is a schematic diagram of the third embodiment of the high-brightness optoelectronic device of the present invention;

[0045] Figure 5 is a schematic diagram of the fourth embodiment of the high-brightness optoelectronic device of the present invention;

[0046] Figure 6 is a structural schematic diagram of the fifth embodiment of the high-brightness optoelectronic device of the present invention;

[0047] Figure 7 is a flowchart of the fabrication process of the optoelectronic device of the present invention;

[0048] Figure 8 is a flowchart illustrating the fabrication process of one embodiment of the outer wall of the optoelectronic device of the present invention;

[0049] Figure 9 is a schematic diagram of one arrangement of the metal reinforcement of the present invention;

[0050] Figure 10 is a schematic diagram of another arrangement of the metal reinforcement of the present invention;

[0051] Figure 11 is a schematic diagram of one arrangement of the cathode metal component of the present invention;

[0052] Figure 12 is a schematic diagram of another arrangement of the cathode metal component of the present invention;

[0053] Figure 13 is a top view of a single pixel region on the driving wafer;

[0054] Figure 14 is a schematic diagram of the sixth embodiment of the high-brightness optoelectronic device of the present invention;

[0055] Explanation of reference numerals in the accompanying drawings: 10, common cathode; 20, driving wafer; 201, anode contact; 30, pixel unit; 301, pixel body; 3011, P-type semiconductor layer; 3012, active layer; 302, outer edge wall; 3021, first wall layer; 30211, step portion; 3022, second wall layer; 40, N-type semiconductor layer; 401, first surface; 4011, protrusion; 402, second surface; 50, cathode metal element; 60, first insulating dielectric layer; 70, anode metal element; 80, cathode contact; 90, second insulating dielectric layer; 100, metal reinforcement; 110, compound semiconductor; 1101, substrate; 120, hard mask; 130, cathode wiring area; 140, color transfer layer. Detailed Implementation

[0056] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present disclosure or its application or use.

[0057] In the description of this invention, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0058] This embodiment provides a high-brightness optoelectronic device and its fabrication method, which can effectively improve the brightness of LED optoelectronic devices and avoid the phenomenon of pixel unit leakage failure, thereby effectively improving the reliability of LED optoelectronic devices.

[0059] The structure of this embodiment will be further described below with reference to Figures 2-12.

[0060] Example 1

[0061] Referring to Figure 2, this embodiment discloses a high-brightness optoelectronic device, including a driving wafer 20 and a pixel unit 30;

[0062] The driving wafer 20 includes an anode contact 201;

[0063] Pixel unit 30 is disposed on driving wafer 20 and corresponds to anode contact 201. Pixel unit 30 includes pixel body 301 and outer edge wall 302. The outer edge wall 302 is disposed on the side wall of pixel body 301. The outer edge wall 302 includes a first wall layer 3021. The first wall layer 3021 is an insulator. The first wall layer 3021 is attached to the side wall of pixel body 301.

[0064] Pixel unit 30 is located between N-type semiconductor layer 40 and driving wafer 20. Pixel body 301 includes P-type semiconductor layer 3011 and active layer 3012. Active layer 3012 is used to emit light. The light emitted through active layer 3012 will eventually pass through N-type semiconductor layer 40 and be emitted through N-type semiconductor layer. Active layer 3012 is located between N-type semiconductor layer 40 and P-type semiconductor layer 3011. P-type semiconductor layer 3011 is electrically connected to the corresponding anode contact 201 on driving wafer 20 to realize anode connection.

[0065] The P-type semiconductor layer 3011 and the N-type semiconductor layer 40 of each pixel unit 30 are insulated from each other by a first wall layer 3021;

[0066] The N-type semiconductor layer 40 is electrically connected to the cathode metal element 50 to achieve cathode communication. The cathode metal element 50 is located on the side of the pixel unit 30 so that the light-emitting area of ​​the N-type semiconductor layer is exposed and not blocked.

[0067] Understandably, the "light-emitting area of ​​the N-type semiconductor layer" here refers to the area where light emitted from the active layer 3012 inside the pixel unit 30 is emitted through the N-type semiconductor layer 40.

[0068] The above structure eliminates the need for a separate common cathode outside the N-type semiconductor layer 40. Instead, a cathode metal component 50 is directly provided on the side of the N-type semiconductor layer 40 for connection to achieve cathode communication, thus exposing the N-type semiconductor layer 40. This avoids the cathode metal component 50 from blocking the light-emitting area of ​​the N-type semiconductor layer 40, greatly improving the light-emitting brightness of the pixel unit 30, achieving optimal light-emitting efficiency, and enhancing reliability. It also allows for full utilization of the N-type semiconductor layer, reducing material waste and saving costs. Furthermore, by providing an outer edge wall 302 on the side wall of the pixel body 301 of the optical element, the N-type semiconductor layer 40 and the P-type semiconductor layer 3011 are insulated from each other by the first wall layer 3021. This better prevents short circuits and leakage between the N-type semiconductor layer 40 and the P-type semiconductor layer 3011, and effectively ensures the reliability of the optoelectronic device.

[0069] As shown in Figure 3, in some specific embodiments, the pixel unit 30 is located between the N-type semiconductor layer 40 and the driving wafer 20, and the N-type semiconductor layer 40 extends to the outside of the outer edge wall 302 and contacts the cathode metal part 50 on the side.

[0070] Furthermore, the second surface 402 of the N-type semiconductor layer 40 can be in direct contact with the top surface of the cathode metal element 50.

[0071] The aforementioned N-type semiconductor layer 40 may extend to the outside of the pixel unit from only one side, or it may extend to the outside of the pixel unit from both sides.

[0072] The outer edge wall 302 is disposed between the N-type semiconductor layer 40 and the driving wafer 20. One end of the outer edge wall 302 is in contact with the N-type semiconductor layer 40, and the other end has a certain gap with the driving wafer 20. This gap is filled by the first insulating dielectric layer 60.

[0073] In some embodiments, the aforementioned gap is formed between the outer edge wall 302 and the second insulating dielectric layer 90, and this gap is filled by the first insulating dielectric layer 60. In some embodiments, the aforementioned cathode metal element 50 can be arranged in a ring shape to surround the periphery of the pixel unit. In this case, the aforementioned cathode metal element can also serve as an optical resonant cavity, that is, to prevent optical crosstalk between pixel units and improve pixel brightness. In other embodiments, the aforementioned cathode metal element 50 can also be arranged on one side, as long as the N-type semiconductor layer 40 is in contact with the side cathode metal element 50.

[0074] As shown in Figure 13, the area corresponding to each pixel unit on the driving wafer is a pixel area. A cathode wiring area 130 can be set around the pixel area. A cathode metal part 50 is set above the cathode wiring area 130 and is located between the N-type semiconductor layer 40 and the cathode wiring area 130 to achieve cathode connection.

[0075] The aforementioned cathode wiring area 130 can be considered as a cathode contact; for example, the cathode contact 80 in Figure 2 can also be considered as a cathode wiring area. The cathode wiring area 130 can be a continuous area or a discontinuous area.

[0076] In one embodiment, each pixel unit 30 is covered with a first insulating dielectric layer 60, and an anode metal element 70 is disposed on the first insulating dielectric layer 60. The P-type semiconductor layer 3011 of the pixel unit 30 is electrically connected to the corresponding anode contact 201 on the driving wafer 20 through the anode metal element 70, so as to conveniently realize the anode connection. The arrangement is simple and the connection is reliable.

[0077] The first insulating dielectric layer 60 can achieve isolation and insulation between adjacent pixel units 30 to avoid mutual interference between adjacent pixel units 30.

[0078] In one embodiment, as shown in Figures 2, 3, 4 and 6, the driving wafer 20 is further provided with a cathode contact 80 corresponding to the cathode metal element 50. The cathode contact 80 and the anode contact 201 are insulated from each other by a second insulating dielectric layer 90. One end of the cathode metal element 50 is connected to the N-type semiconductor layer 40, and the other end is connected to the corresponding cathode contact 80.

[0079] By setting cathode contacts 80 on the driving wafer 20, the cathode transmission distance can be effectively shortened, which is more conducive to cathode current transmission.

[0080] As shown in Figure 2, in some specific embodiments, the cathode contact 80 can be a region surrounding the pixel unit, and it can be a continuous region or a non-continuous region.

[0081] Furthermore, the material of the second insulating dielectric layer 90 can be one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0082] Furthermore, a second insulating dielectric layer 90 is deposited on the driving wafer 20, and the anode contact 201 can be embedded in the second insulating dielectric layer 90; the cathode contact 80 can also be embedded in the second insulating dielectric layer 90.

[0083] In one embodiment, the N-type semiconductor layer 40 has a first surface 401 and a second surface 402 facing each other. The light-emitting area of ​​the N-type semiconductor layer 40 is located on the first surface 401, and the pixel unit 30 is located between the second surface 402 and the driving wafer 20. As shown in FIG2, the contact surface between the cathode metal element 50 and the N-type semiconductor layer 40 is located on the second surface 402.

[0084] Alternatively, as shown in Figure 4, the contact surface between the cathode metal element 50 and the N-type semiconductor layer 40 covers part of the first surface 401 and does not block the light-emitting area of ​​the N-type semiconductor layer 40, so that the light-emitting area of ​​the N-type semiconductor layer 40 is always exposed.

[0085] In one embodiment, as shown in FIG11, there is a gap between the outer edge wall 302 of the pixel unit 30 and the adjacent cathode metal part 50.

[0086] Alternatively, in extreme cases, as shown in Figure 12, the outer edge wall 302 of the pixel unit 30 contacts the adjacent cathode metal part 50 to maximize the transmission of cathode current.

[0087] Furthermore, a first insulating dielectric layer 60 is filled between the cathode metal element 50 and the adjacent pixel unit 30.

[0088] In one embodiment, as shown in Figures 2-6, the outer wall 302 further includes a second wall layer 3022, which is attached to the outer wall of the first wall layer 3021 so that there is no gap between them.

[0089] Furthermore, the second wall layer 3022 is made of metal to enhance the cathode electrical connection or enhance reflection.

[0090] Furthermore, the second wall layer 3022 is either a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, to enhance optical or electrical functions.

[0091] By setting a reflective layer in the second wall layer 3022, the effect of side reflection can be achieved, which is more conducive to the realization of all-round reflection. This greatly improves the brightness of the pixel unit 30 and the collimation of light, thereby obtaining better performance and a smaller divergence angle.

[0092] By providing a conductive layer in the second wall layer 3022, it is easier to make electrical connections between the pixel unit 30 and other components.

[0093] The reflective layer can be deposited using high-reflectivity metals such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh), or platinum (Pt).

[0094] The conductive layer can be deposited using highly conductive metals such as aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0095] The second wall layer 3022 can also be a stack of transparent conductive layer and metal layer, such as silver or titanium tungsten film layer superimposed on zinc oxide.

[0096] In one embodiment, as shown in FIG3, a step portion 30211 is formed at one end of the first wall layer 3021 near the N-type semiconductor layer 40, and a second wall layer 3022 is located on the step portion 30211.

[0097] In another embodiment, as shown in FIG2, the end of the first wall layer 3021 near the N-type semiconductor layer 40 may also adopt a stepless portion 30211 structure.

[0098] In one embodiment, as shown in FIG2, the light-emitting region of the N-type semiconductor layer 40 is formed with a plurality of protrusions 4011, so that the surface of the light-emitting region is uneven, thereby reducing or destroying total internal reflection at the interface between the semiconductor material and the air, thereby improving the light extraction efficiency of the LED.

[0099] In one embodiment, as shown in stage b of FIG7, the angle θ between the pixel body 301 and the N-type semiconductor layer 40 is about 90°, specifically it can be 60° to 120°, preferably 75° to 105°.

[0100] In one embodiment, as shown in FIG3, the length L2 of the pixel body 301 is 0.5um to 50um.

[0101] In one embodiment, the thickness L1 of the first wall layer 3021 is 50 nm to 1500 nm. This thickness range allows for the maximization of the dielectric layer thickness required for omnidirectional reflective structures that meet different wavelength requirements while achieving ideal insulating coverage.

[0102] As shown in Figure 7, this embodiment also discloses a method for fabricating a high-brightness optoelectronic device, including,

[0103] 1) Prepare a driving wafer 20 such that the driving wafer 20 includes an anode contact 201;

[0104] And the compound semiconductor 110 is prepared, as shown in stage a of Figure 7. The compound semiconductor 110 includes a substrate 1101 and an N-type semiconductor layer 40, an active layer 3012 and a P-type semiconductor layer 3011 sequentially formed along a direction away from the substrate 1101.

[0105] 2) As shown in the bd stage of Figure 7, the compound semiconductor 110 is processed to obtain a pixel unit 30 corresponding to the anode contact 201. The pixel unit 30 includes a pixel body 301 and an outer edge wall 302. The outer edge wall 302 is disposed on the side wall of the pixel body 301. The outer edge wall 302 includes a first wall layer 3021, which is an insulator. The first wall layer 3021 is attached to the side wall of the pixel body 301. The pixel body 301 includes a P-type semiconductor layer 3011 and an active layer 3012. The active layer 3012 is located between the P-type semiconductor layer 3011 and the N-type semiconductor layer 40. The N-type semiconductor layer 40 is exposed outside the pixel unit 30.

[0106] 3) As shown in stage e of Figure 7, the compound semiconductor 110 with pixel unit 30 and the driving wafer 20 are connected, so that the pixel unit 30 is located between the N-type semiconductor layer 40 and the driving wafer 20, and the P-type semiconductor layer 3011 of each pixel unit 30 is electrically connected to the corresponding anode contact 201 on the driving wafer 20.

[0107] 4) Remove the substrate 1101 of the compound semiconductor 110;

[0108] Furthermore, removing the substrate 1101 allows the N-type semiconductor layer 40 to be directly exposed;

[0109] 5) As shown in stage g of Figure 7, the N-type semiconductor layer 40 is electrically connected to the cathode metal part 50, so that the cathode metal part 50 is located on the side of the pixel unit 30 to expose the light-emitting area of ​​the N-type semiconductor layer 40.

[0110] In one embodiment, as shown in stage f of FIG7, the light-emitting region of the N-type semiconductor layer 40 can be formed with multiple protrusions 4011 by surface roughening treatment to improve the light extraction efficiency of the light-emitting region. This roughening treatment can be performed after removing the substrate 1101 in step 4, or after completing step 5, depending on the actual situation.

[0111] Furthermore, as shown in stage a of Figure 7, when preparing the compound semiconductor 110, a hard mask 120 can also be prepared on the side of the P-type semiconductor layer 3011 away from the substrate 1101, so as to facilitate the realization of the P-type ohmic contact function and the subsequent pixel patterning etching mask function.

[0112] Among them, compound semiconductor 110 usually refers to a compound formed by two or more elements. For example, the compound semiconductor here is mainly a light-emitting diode epitaxial material, such as the InGaN ternary material system or the AlGaInP quaternary material system, etc., whose emission wavelength can cover the entire band from ultraviolet, visible light and infrared.

[0113] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are shown in Table 1 below. In some practical applications, the film layers of the compounds are more complex, or there is cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials, and active layer (MQW quantum well) sandwiched between the two:

[0114] Table 1. Film Material Table for Each Compound

[0115] In one embodiment, before connecting the compound semiconductor 110 with pixel units to the driving wafer 20, as shown in stage d of FIG7, a first insulating dielectric layer 60 is also wrapped around the outside of each pixel unit, and an anode metal element 70 is disposed on the first insulating dielectric layer 60. Then, the P-type semiconductor layer 3011 of the pixel unit 30 is electrically connected to the corresponding anode contact 201 on the driving wafer 20 through the anode metal element 70, thereby realizing anode connection. For example, one end of the anode metal element 70 can be in contact with the P-type semiconductor, and the other end can be in contact with the corresponding anode contact 201 on the driving wafer 20, thereby realizing electrical connection.

[0116] The anode metal part 70 can be provided on the first insulating dielectric layer 60 by using the damascus process, so that the anode metal part 70 is embedded on the first insulating dielectric layer 60.

[0117] The material of the anode metal part 70 may include one or more of TiN (titanium nitride), Al (aluminum), TaN (tantalum nitride) and Cu (copper).

[0118] In one embodiment, the first insulating dielectric layer 60 may be made of one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0119] During fabrication, a first insulating dielectric layer 60 can be formed by depositing the corresponding material on the entire surface outside the pixel unit.

[0120] In one embodiment, the cathode metal part 50 can be fabricated at the same time as the anode metal part 70, thereby thickening the cathode metal to carry a larger current.

[0121] The anode contact 201 on the drive wafer 20 can also be formed using the damascus process.

[0122] In one embodiment, a method for processing the compound semiconductor 110 to obtain the pixel unit 30 corresponding to the anode contact 201 includes the following steps:

[0123] Step S1) As shown in stage b of Figure 7, the compound semiconductor 110 is etched by the first etching method, and the etching is stopped at the N-type semiconductor layer 40 or the etching continues after the N-type semiconductor layer 40 is etched and is stopped at up to 50% of the thickness of the N-type semiconductor layer, thereby obtaining the pixel body 301 corresponding to the anode contact 201.

[0124] That is, if the etching stop position is located inside the N-type semiconductor layer 40, the etching depth of the N-type semiconductor layer 40 should be less than or equal to 50% of the thickness of the N-type semiconductor layer.

[0125] Furthermore, the first etching method mentioned above is either a dry etching method or a wet etching method.

[0126] Step S2) A first wall layer 3021 is deposited on the outside of the pixel body 301, and the first wall layer 3021 is etched using a dry etching method. After etching, only the first wall layer 3021 located on the side wall of the pixel body 301 is retained.

[0127] The first wall layer 3021 includes one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide, or niobium oxide.

[0128] In one embodiment, in step S2), the second wall layer 3022 also needs to be prepared. Specifically, the preparation can be carried out in two ways: one is a whole-body etching method, and the other is a layered etching method.

[0129] The overall etching method (see Figure 8) is as follows: In step S2), after depositing the first wall layer 3021 on the outside of the pixel body 301, the second wall layer 3022 needs to be deposited. After all the deposition is completed, the overall structure composed of the first wall layer 3021 and the second wall layer 3022 is etched using a dry etching method. After etching, only the first wall layer 3021 and the second wall layer 3022 located on the side wall of the pixel body 301 are retained.

[0130] In the pixel unit obtained by the above preparation method, a step portion 30211 is formed at the end of the first wall layer 3021 near the N-type semiconductor layer 40, and the second wall layer 3022 is located on the step portion 30211.

[0131] The layered etching method is as follows: In step S2), after depositing the first wall layer 3021 on the outside of the pixel body 301, the first wall layer 3021 is first etched using a dry etching method. After etching, only the first wall layer 3021 located on the side wall of the pixel body 301 is retained. Then, a second wall layer 3022 is deposited on the outside of the first wall layer 3021. After the deposition is completed, the second wall layer 3022 is etched using a dry etching method. After etching, only the second wall layer 3022 located on the side wall of the pixel body 301 is retained.

[0132] In the pixel unit obtained by the above preparation method, there is no step between the first wall layer 3021 and the second wall layer 3022.

[0133] The fabrication method of the outer edge wall 302 of the aforementioned pixel unit 30 does not require the use of a photolithography machine during fabrication. Instead, it adopts a dry etching method, which eliminates the need for more advanced photolithography machines and eliminates the need for exposure processes. This avoids the defects caused by patterning failure, large overlay offset, and high production cost in the prior art when using a photolithography machine for patterning etching. At the same time, it can effectively ensure the fabrication accuracy and achieve in-situ or self-alignment type accuracy. Submicron accuracy is achieved using micron-level equipment and processes.

[0134] The high-brightness optoelectronic device and its fabrication method described in the above embodiments directly connect the cathode metal part 50 to the side of the N-type semiconductor layer 40 to achieve cathode communication, thereby avoiding the cathode metal part 50 from blocking the light-emitting area of ​​the N-type semiconductor layer 40, greatly improving the light-emitting brightness and light-emitting efficiency of the pixel unit 30, and improving the reliability of use; in addition, the N-type semiconductor layer 40 and the P-type semiconductor layer 3011 are insulated from each other by the first wall layer 3021, which can better avoid short circuit leakage between the N-type semiconductor layer 40 and the P-type semiconductor layer 3011, and can also effectively ensure the reliability of use of the optoelectronic device.

[0135] Example 2

[0136] As shown in Figures 5 and 6, the main difference between this embodiment and Embodiment 1 is that a metal reinforcing member 100 is provided between the cathode metal member 50 and the N-type semiconductor layer 40 in this embodiment to enhance the cathode connection and strengthen current conduction.

[0137] If the second wall layer 3022 of the pixel unit 30 is made of conductive metal, then the material of the metal reinforcement 100 can be the same as that of the second wall layer 3022.

[0138] In one embodiment, as shown in FIG6, a cathode contact 80 corresponding to the cathode metal element 50 is also provided on the driving wafer 20. The cathode contact 80 and the anode contact 201 are insulated from each other by a second insulating dielectric layer 90. One end of the cathode metal element 50 is connected to the N-type semiconductor layer 40 through the metal reinforcement 100, and the other end is connected to the corresponding cathode contact 80.

[0139] In one embodiment, each pixel unit 30 is provided with metal reinforcement members 100 on both sides, as shown in FIG9, and there is a gap between the outer edge wall 302 of the pixel unit 30 and the adjacent metal reinforcement member 100.

[0140] Alternatively, in an extreme case, as shown in Figure 10, the outer edge wall 302 of the pixel unit 30 can contact the adjacent metal reinforcement 100 to achieve a gapless situation.

[0141] In one embodiment, during the fabrication of the metal reinforcement 100, the metal reinforcement 100 is deposited on the N-type semiconductor layer 40, such that the N-type semiconductor layer 40 is electrically connected to the cathode metal element 50 through the metal reinforcement 100. When the second wall layer 3022 is made of metal, the metal reinforcement 100 can be fabricated in the following manner:

[0142] When etching the second wall layer 3022 after deposition, as shown in Figure 9, in addition to retaining the second wall layer 3022 located on the sidewall of the pixel body 301, the second wall layer 3022 located on the N-type semiconductor surface on both sides of the pixel unit 30 is also retained.

[0143] (It can be partially or completely retained), with the second wall layer 3022 on both sides directly serving as the metal reinforcement 100. This method allows for full utilization of the material of the second wall layer 3022.

[0144] Example 3

[0145] As shown in Figure 14, in this embodiment, a color transfer layer 140 can also be deposited on the side of the N-type semiconductor layer 40 away from the driving wafer 20 to achieve the change of the light emission color of the pixel unit.

[0146] The color transfer layer 140 may include phosphors or quantum dots. When light passes through the color transfer layer 140, it excites the phosphors or quantum dots to achieve color conversion. For example, if the color transfer layer 140 is a mixture of quantum dots and photoresist (or silicone), then the color transfer layer 140 can change the wavelength of the light emitted by the pixel unit 30, thereby changing the color of the light emitted by the pixel unit 30, and thus converting the light emitted by the pixel unit 30 into light with a longer wavelength. Specifically, it can convert blue light emitted by the pixel unit 30 into green light or red light, or convert violet light emitted by the pixel unit 30 into blue light, green light, or red light, etc. The color transfer layer 140 may also be a mixture of phosphors and photoresist (or silicone), which will not be elaborated further here.

[0147] In the above structure, at least two pixel units 30 can share one N-type semiconductor layer 40. For example, the N-type semiconductor layer 40 can be arranged continuously on the entire surface to cover all pixel units 30 on the driving wafer, so that all pixel units share one N-type semiconductor layer 40.

[0148] The color transfer layer 140 can cover the entire surface of the N-type semiconductor layer 40 and be arranged continuously, which allows the color transfer layer 140 to cover at least two pixel units 30. This not only effectively ensures the color transfer effect, but also improves the fabrication efficiency of the color transfer layer.

[0149] In the above structure, at least two pixel units 30 can be located within the same annular cathode metal part 50.

[0150] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0151] It should be noted that the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A high-brightness optoelectronic device, characterized in that: include, A driving wafer, wherein the driving wafer includes an anode contact; A pixel unit, wherein the pixel unit is disposed on the driving wafer and corresponds to the anode contact; The pixel unit is located between the N-type semiconductor layer and the driving wafer. The pixel unit includes a pixel body, which includes a P-type semiconductor layer and an active layer. The active layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The P-type semiconductor layer is electrically connected to the corresponding anode contact on the driving wafer. The N-type semiconductor layer is electrically connected to the cathode metal element, which is located on the side of the pixel unit to expose the light-emitting area of ​​the N-type semiconductor layer.

2. The high-brightness optoelectronic device according to claim 1, characterized in that: The pixel unit further includes an outer edge wall, which is disposed on the side wall of the pixel body. The outer edge wall includes a first wall layer, which is an insulator. The first wall layer is attached to the side wall of the pixel body, and the P-type semiconductor layer and N-type semiconductor layer of each pixel unit are insulated from each other through the first wall layer.

3. The high-brightness optoelectronic device according to claim 1, characterized in that: Each pixel unit is covered with a first insulating dielectric layer, on which an anode metal element is disposed. The P-type semiconductor layer of the pixel unit is electrically connected to the corresponding anode contact on the driving wafer through the anode metal element.

4. The high-brightness optoelectronic device according to claim 3, characterized in that: The driving wafer is also provided with cathode contacts corresponding to the cathode metal element. The cathode contacts and anode contacts are insulated from each other by a second insulating dielectric layer. One end of the cathode metal element is connected to the N-type semiconductor layer, and the other end is connected to the corresponding cathode contact.

5. The high-brightness optoelectronic device according to claim 2, characterized in that: A metal reinforcement is provided between the cathode metal component and the N-type semiconductor layer.

6. The high-brightness optoelectronic device according to claim 5, characterized in that: Each pixel unit has metal reinforcements on both sides, and there is a gap between the outer edge wall of the pixel unit and the adjacent metal reinforcement, or the outer edge wall of the pixel unit is in contact with the adjacent metal reinforcement.

7. The optoelectronic device based on alignment bonding according to claim 1, characterized in that: The N-type semiconductor layer has a first surface and a second surface arranged opposite to each other. The light-emitting area of ​​the N-type semiconductor layer is located on the first surface. The pixel unit is located between the second surface and the driving wafer. The contact surface between the cathode metal element and the N-type semiconductor layer is located on the second surface. Alternatively, the contact surface between the cathode metal element and the N-type semiconductor layer covers part of the first surface and exposes the light-emitting area of ​​the N-type semiconductor layer.

8. The high-brightness optoelectronic device according to claim 2, characterized in that: There is a gap between the outer edge wall of the pixel unit and the adjacent cathode metal part, or the outer edge wall of the pixel unit is in contact with the adjacent cathode metal part.

9. The high-brightness optoelectronic device according to claim 2, characterized in that: The outer wall also includes a second wall layer, which is attached to the outer wall of the first wall layer.

10. The optoelectronic device based on alignment bonding according to claim 9, characterized in that: The second wall layer is either a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

11. The high-brightness optoelectronic device according to claim 1, characterized in that: The light-emitting region of the N-type semiconductor layer has multiple protrusions.

12. A method for fabricating a high-brightness optoelectronic device, characterized in that: include, Fabricate a driver wafer such that the driver wafer includes anode contacts; The invention also includes the preparation of a compound semiconductor comprising a substrate and an N-type semiconductor layer, an active layer and a P-type semiconductor layer sequentially formed along a direction away from the substrate. A pixel unit corresponding to the anode contact is obtained by processing a compound semiconductor. The pixel unit includes a pixel body, which includes a P-type semiconductor layer and an active layer. The active layer is located between the P-type semiconductor layer and the N-type semiconductor layer, and the N-type semiconductor layer is exposed to the outside of the pixel unit. A compound semiconductor having pixel units is connected to a driving wafer, such that the pixel units are located between an N-type semiconductor layer and the driving wafer, and that the P-type semiconductor layer of each pixel unit is electrically connected to a corresponding anode contact on the driving wafer. Remove the substrate from the compound semiconductor; The N-type semiconductor layer is electrically connected to the cathode metal element, such that the cathode metal element is located on the side of the pixel unit to expose the light-emitting area of ​​the N-type semiconductor layer.

13. The preparation method according to claim 12, characterized in that: The obtained pixel unit further includes an outer edge wall, which is disposed on the side wall of the pixel body. The outer edge wall includes a first wall layer, which is an insulator. The first wall layer is attached to the side wall of the pixel body, and the P-type semiconductor layer and N-type semiconductor layer of each pixel unit are insulated from each other through the first wall layer.

14. The preparation method according to claim 12, characterized in that: Before connecting the compound semiconductor with pixel units to the driving wafer, a first insulating dielectric layer is wrapped around the outside of each pixel unit, and an anode metal element is disposed on the first insulating dielectric layer. Then, the P-type semiconductor layer of the pixel unit is electrically connected to the corresponding anode contact on the driving wafer through the anode metal element.

15. The preparation method according to claim 13, characterized in that: A method for processing a compound semiconductor to obtain a pixel unit corresponding to the anode contact includes, Step S1) The compound semiconductor is etched by the first etching method, and the etching is stopped at the N-type semiconductor layer or the etching continues after the N-type semiconductor layer is etched and is stopped at a maximum of 50% of the thickness of the N-type semiconductor layer, thereby obtaining the pixel body corresponding to the anode contact. Step S2) Deposit a first wall layer on the outside of the pixel body and etch the first wall layer using a dry etching method. After etching, only the first wall layer located on the sidewall of the pixel body is retained.

16. The preparation method according to claim 15, characterized in that: In step S2), after depositing the first wall layer on the outside of the pixel body, a second wall layer needs to be deposited. After all the deposition is completed, the overall structure composed of the first wall layer and the second wall layer is etched using a dry etching method. After etching, only the first wall layer and the second wall layer located on the side wall of the pixel body are retained. Alternatively, after depositing a first wall layer on the outside of the pixel body, the first wall layer is first etched using a dry etching method, and only the first wall layer located on the sidewall of the pixel body is retained after etching. Then, a second wall layer is deposited on the outside of the first wall layer. After the deposition is completed, the second wall layer is etched using a dry etching method, and only the second wall layer located on the sidewall of the pixel body is retained after etching.

17. The preparation method according to claim 12, characterized in that: The driving wafer is provided with cathode contacts corresponding to the cathode metal element. The cathode contacts and anode contacts are insulated from each other by a second insulating dielectric layer. When the N-type semiconductor layer is electrically connected to the cathode metal element, one end of the cathode metal element is connected to the N-type semiconductor layer and the other end is connected to the corresponding cathode contact.

18. The preparation method according to claim 12, characterized in that: A metal reinforcement is deposited on the N-type semiconductor layer, so that the N-type semiconductor layer is electrically connected to the cathode metal through the metal reinforcement.

19. The preparation method according to claim 12, characterized in that: The light-emitting region of the N-type semiconductor layer needs to undergo surface roughening treatment to form multiple protrusions.

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