Array substrate, display panel, and display apparatus

Abstract

The present disclosure discloses an array substrate, a display panel, and a display apparatus. The array substrate comprises: a base substrate, the base substrate comprising a display area, and a non-display area located on at least one side of the display area; a common electrode line, located in the non-display area; at least one detection line, located in the non-display area, and comprising a first detection part located at a side of the common electrode line distant from the display area, and a second detection part, located at a side of the common electrode line close to the display area; at least one connecting line, located in the non-display area, the connecting line being connected to the first detection part and the second detection part of a same detection line, and the orthographic projection of the connecting line onto the base substrate intersecting with the orthographic projection of the common electrode line onto the base substrate; and at least one first electrostatic discharge structure, located in the non-display area, the first electrostatic discharge structure being connected to the first detection part.

Description

Array substrate, display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410670752.2, filed on May 28, 2024, entitled "Array Substrate, Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0004] Over the decades, the television industry has undergone a dramatic transformation, much like the mobile phone industry, evolving from bulky black-and-white TVs to color TVs, and now to large-screen smart displays. Technological innovation has been relentless. With product updates and the increasing demands of users for monitors, there's a need to constantly break with traditional technologies. Beyond advancements in low cost, high transmittance, and high contrast, the integration of sensors into display products—such as adding light and temperature sensors—aims to enhance the user experience. Summary of the Invention

[0005] The array substrate, display panel, and display device provided in this disclosure are specifically designed as follows:

[0006] On one hand, embodiments of this disclosure provide an array substrate, comprising:

[0007] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0008] The common electrode line is located in the non-display area;

[0009] At least one detection line is located in the non-display area, the detection line including a first detection part located on the side of the common electrode line away from the display area, and a second detection part located on the side of the common electrode line close to the display area;

[0010] At least one bonding line is located in the non-display area. The bonding line connects the first detection part and the second detection part of the same detection line. The orthographic projection of the bonding line on the substrate and the orthographic projection of the common electrode line on the substrate intersect each other.

[0011] At least one first electrostatic discharge structure is located in the non-display area, and the first electrostatic discharge structure is connected to the first detection unit.

[0012] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area having at least one bonding area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area;

[0013] The first detection unit is located in at least one of the third non-display areas, and the second detection unit is located in the first non-display area and / or the second non-display area.

[0014] In some embodiments, in the array substrate provided in the present disclosure, the at least one first electrostatic discharge structure includes a plurality of first sub-electrostatic discharge structures located in the third non-display area and close to the first non-display area;

[0015] The plurality of first sub-electrostatic discharge structures extend along a first direction and are arranged along the first direction, which is the arrangement direction of the first non-display area and the second non-display area.

[0016] In some embodiments, in the array substrate provided in the present disclosure, the third non-display area includes a gate driving circuit area, and the plurality of first sub-electrostatic discharge structures are located between the gate driving circuit area and the first non-display area.

[0017] In some embodiments, in the array substrate provided in the present disclosure, the at least one first electrostatic discharge structure includes a plurality of second sub-electrostatic discharge structures located in the third non-display area and close to the second non-display area;

[0018] A portion of the second sub-electrostatic discharge structure extends along the first direction, while the remaining second sub-electrostatic discharge structures extend along the second direction.

[0019] The first direction is the arrangement direction of the first non-display area and the second non-display area, and the second direction is the arrangement direction of the two third non-display areas.

[0020] In some embodiments, in the array substrate provided in the present disclosure, the third non-display area includes a gate driving circuit area;

[0021] Each of the second sub-electrostatic discharge structures between the gate driving circuit region and the display region is staggered in the second direction and overlaps in at most part in the first direction;

[0022] Each of the second sub-electrostatic discharge structures in the gate drive circuit region facing the second non-display area is arranged side by side along the second direction.

[0023] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transistors, the plurality of transistors being electrically connected to at least a portion of the detection lines;

[0024] The plurality of transistors are located in the second non-display area.

[0025] In some embodiments, the array substrate provided in this disclosure further includes multiple gate driving circuit lines and multiple second electrostatic discharge structures located in the non-display area, wherein the multiple second electrostatic discharge structures are connected to the multiple gate driving circuit lines, the at least one first electrostatic discharge structure, and the common electrode line.

[0026] In some embodiments, the array substrate provided in this disclosure further includes multiple data lines located in the display area, and multiple third electrostatic discharge structures and test lines located in the non-display area; wherein the multiple third electrostatic discharge structures are connected to the multiple data lines, and the multiple third electrostatic discharge structures are electrically connected to the test lines.

[0027] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transistors, the plurality of transistors being electrically connected to at least a portion of the detection lines;

[0028] The non-display area includes a first non-display area with at least one binding area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area;

[0029] Within the first non-display area, the at least one detection line is located between the plurality of third electrostatic discharge structures and the display area.

[0030] In some embodiments, in the array substrate provided in the present disclosure, within the second non-display area, the at least one detection line and the plurality of transistors are located between the plurality of third electrostatic discharge structures and the common electrode line.

[0031] In some embodiments, in the array substrate provided in the present disclosure, in the second non-display area, the orthogonal projection of the test line on the substrate intersects with the orthogonal projection of the at least one detection line on the substrate.

[0032] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line and the plurality of transistors are located between the plurality of third electrostatic discharge structures and the display area in the second non-display area.

[0033] In some embodiments, in the array substrate provided in the present disclosure, the test line is located on the side of the plurality of detection lines and the plurality of transistors away from the display area within the second non-display area.

[0034] In some embodiments, in the array substrate provided in the present disclosure, the detection line extends along a second direction in the first non-display area and / or the second non-display area, where the second direction is the arrangement direction of the two third non-display areas.

[0035] In some embodiments, in the array substrate provided in the present disclosure, at least a portion of the test line is located between the common electrode line and the display area on at least one side of the display area.

[0036] In some embodiments, in the array substrate provided in the present disclosure, at least a portion of the test line is located on the side of the common electrode line away from the display area on at least one side of the display area.

[0037] In some embodiments, the array substrate provided in this disclosure further includes a ground line located in the non-display area and a dummy line located on the side of the ground line closer to the display area;

[0038] The grounding wire includes at least one first tip, and the dummy wire includes a second tip positioned opposite the first tip.

[0039] In some embodiments, in the array substrate provided in the present disclosure, the dummy lines are continuously arranged, or the dummy lines include a plurality of independent dummy portions.

[0040] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area having at least one bonding area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; the dummy line is located in the second non-display area.

[0041] In some embodiments, in the array substrate provided in the present disclosure, the display area includes a plurality of sub-pixels arranged in an array, the spacing between the first tips in the second direction is approximately the same as the size of the sub-pixels in the second direction, the number of the first tips is the same as the number of the sub-pixels in the second direction, and the second direction is the arrangement direction of the two third non-display areas.

[0042] In some embodiments, in the array substrate provided in the present disclosure, the at least one detection line includes a temperature detection line, and the temperature detection line includes a plurality of integrally formed zigzag portions.

[0043] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transistors, the plurality of transistors being electrically connected to at least a portion of the detection lines;

[0044] The at least one detection line includes a first photosensitive detection line, a second photosensitive detection line, and at most a third photosensitive detection line;

[0045] The plurality of transistors are divided into a plurality of transistor groups. The gates of the plurality of transistors are connected to the first photosensitive detection line, the first terminals of the plurality of transistors are connected to the second photosensitive detection line, and different transistor groups are connected to different third photosensitive detection lines.

[0046] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0047] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate includes a black matrix, and at least a portion of the transistors' orthogonal projections on the substrate do not overlap with the orthogonal projections of the black matrix on the substrate.

[0048] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate further includes a color resist layer located on the side of the black matrix facing the array substrate, the color resist layer including a plurality of color resists of different colors, the plurality of color resists covering at least a portion of the transistor group.

[0049] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0050] Figure 1 is a schematic diagram of an array substrate structure provided in an embodiment of this disclosure;

[0051] Figure 2 is a magnified structural diagram of region Z1 in Figure 1;

[0052] Figure 3 is a schematic diagram of another enlarged structure of region Z1 in Figure 1;

[0053] Figure 4 is a magnified structural diagram of region Z2 in Figure 3;

[0054] Figure 5 is an enlarged structural diagram of region Z3 in Figure 1;

[0055] Figure 6 is an enlarged structural diagram of region Z4 in Figure 5;

[0056] Figure 7 is an enlarged structural diagram of region Z5 in Figure 2;

[0057] Figure 8 is an equivalent circuit diagram for detecting ambient light provided in an embodiment of this disclosure;

[0058] Figure 9 is an enlarged structural diagram of region Z6 in Figure 7;

[0059] Figure 10 is a schematic diagram of another enlarged structure of region Z1 in Figure 1;

[0060] Figure 11 is a schematic diagram of another enlarged structure of region Z1 in Figure 1;

[0061] Figure 12 is a schematic diagram of the wire width and wire spacing of a grounding wire provided in an embodiment of this disclosure;

[0062] Figure 13 is a schematic diagram of another type of wire width and wire spacing of the grounding wire provided in an embodiment of this disclosure;

[0063] Figure 14 is an enlarged structural diagram of region Z7 in Figure 1;

[0064] Figure 15 is a schematic diagram of the temperature detection principle provided in the embodiment of this disclosure;

[0065] Figure 16 is a schematic diagram of the electrostatic discharge structure provided in an embodiment of this disclosure;

[0066] Figure 17 is the equivalent circuit diagram of the electrostatic discharge structure shown in Figure 16;

[0067] Figure 18 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0068] Figure 19 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0070] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0071] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0072] In some embodiments, to ensure the anti-static (ESD) capability of mass-produced products, ESD testing is performed during product evaluation to determine the product's anti-static capability. The inventors discovered that static electricity tends to accumulate on the common electrode line (COM). However, because the bridging layer where the common electrode line intersects with the detection lines (e.g., light-sensing detection lines, temperature-sensing detection lines) is made of indium tin oxide (ITO), its conductivity is relatively poor. This causes static electricity to accumulate at the bridging location, breaking down the insulation layer and short-circuiting with the detection line. The static electricity then propagates to the detection line, further breaking down the insulation layer between the detection line and the scan signal output line (Gout), causing a short circuit between the detection line and the scan signal output line, resulting in abnormal image display.

[0073] To at least improve the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 is a schematic diagram of an array substrate structure provided by this disclosure embodiment; Figure 2 is an enlarged schematic diagram of region Z1 in Figure 1; Figure 3 is another enlarged schematic diagram of region Z1 in Figure 1; Figure 4 is an enlarged schematic diagram of region Z2 in Figure 3; Figure 5 is an enlarged schematic diagram of region Z3 in Figure 1; and Figure 6 is an enlarged schematic diagram of region Z4 in Figure 5. As can be seen from Figures 1 to 6, the array substrate provided by this disclosure embodiment includes:

[0074] The substrate 101 includes a display area AA and a non-display area located on at least one side of the display area AA. The non-display area may include a first non-display area BB1 and a second non-display area BB2 disposed on opposite sides of the display area AA, and two third non-display areas BB3 connecting the first non-display area BB1 and the second non-display area BB2. The first non-display area BB1 may be provided with at least one bonding area and at least one fan-out area FA, and at least one third non-display area BB3 may be provided with a gate drive circuit area GOA. In some embodiments, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

[0075] The common electrode line 102 is located in the non-display area (e.g., BB1, BB2, BB3). The common electrode line 102 can be set in the same layer and with the same material as the gate line. The material of the layer where the gate line is located can include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The layer where the gate line is located can be a single-layer structure or a multilayer structure. For example, the gate line is a single-layer structure composed of a molybdenum metal layer.

[0076] At least one detection line 103 is located in a non-display area (e.g., BB1, BB2, BB3). The detection line 103 includes a first detection section 1031 located on the side of the common electrode line 102 away from the display area AA, and a second detection section 1032 located on the side of the common electrode line 102 closer to the display area AA. Optionally, the first detection section 1031 and the second detection section 1032 are disposed in the same layer and with the same material as the gate line. The first detection section 1031 may be located in at least one third non-display area BB3, and the second detection section 1032 may be located in the first non-display area BB1 and / or the second non-display area BB2. This disclosure illustrates the example of the first detection section 1031 being located in the left and right third display areas BB3, and the second detection section 1032 being located in the first non-display area BB1 and the second non-display area BB2.

[0077] At least one bonding line 104 is located in the non-display area (e.g., BB1, BB2, BB3). The bonding line 104 connects the first detection part 1031 and the second detection part 1032 of the same detection line 103. The orthographic projection of the bonding line 104 on the substrate 101 intersects with the orthographic projection of the common electrode line 102 on the substrate 101. In some embodiments, the bonding line 104 can be disposed in the same layer and with the same material as the pixel electrode or common electrode of the display area AA. The material of the pixel electrode or common electrode can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO).

[0078] At least one first electrostatic discharge structure 105 is located in a non-display area (e.g., BB1, BB2, BB3). The first electrostatic discharge structure 105 is connected to the first detection unit 1031 to increase the electrostatic discharge path of the first detection unit 1031.

[0079] In the upper array substrate provided in this embodiment, by breaking the detection line 103 into a first detection section 1031 and a second detection section 1032, and connecting the first detection section 1031 and the second detection section 1032 through the connecting line 104, the electrostatic discharge defects caused by excessive static electricity accumulation on the long detection line 103 during the process can be improved. Furthermore, this disclosure adds an electrostatic discharge structure 105 connected to the detection line 103, thereby increasing the electrostatic discharge path of the detection line 103 and improving the anti-static capability. In addition, the common electrode line 102 is not cross-connected at the intersection with the detection line 103, which can optimize the conductivity of the common electrode line 102, reduce the risk of static electricity accumulation on the common electrode line 102, and thus improve the display defects caused by excessive static electricity on the common electrode line 102.

[0080] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG5 and FIG6, the first electrostatic discharge structure 105 may include a plurality of first sub-electrostatic discharge structures 1051 located in the third non-display area BB3 and close to the first non-display area BB1. Since there is sufficient space between the third non-display area BB3 and the first non-display area BB1, for example at the position corresponding to the virtual gate driving circuit (the virtual gate driving circuit is not electrically connected to the gate line of the display area), the present disclosure may provide a plurality of first sub-electrostatic discharge structures 1051 extending along the first direction Y and arranged along the first direction Y, where the first direction Y is the arrangement direction of the first non-display area BB1 and the second non-display area BB2. Optionally, the third non-display area BB3 includes the gate driving circuit area GOA, and the plurality of first sub-electrostatic discharge structures 1051 may be disposed between the gate driving circuit area GOA and the first non-display area BB1. Optionally, the areas of the first sub-electrostatic discharge structures 1051 and the virtual gate driving circuit and the common electrode line 102 at least partially overlap.

[0081] In some embodiments, as can be seen continuing to refer to Figures 5 and 6, within the third non-display area BB3, the number of detection lines 103 gradually increases from top to bottom (from the fan-out area to the display area), resulting in a sparser upper area and a denser lower area for the detection lines 103, affecting the uniformity of orientation (rubbing). To improve the uniformity of orientation, this disclosure provides a virtual line 106 of the same layer and material as the detection lines 103. Optionally, the virtual line 106 is located between a portion of the detection lines 103 and the first sub-electrostatic discharge structure 1051, and the extension line of the virtual line 106 can approximately coincide with the extension line of the detection line 103 below it. In addition, as can be seen in Figure 5, the first detection section 1031 is widened at the overlap with the overlap line 104 and near the overlap line 104 to ensure the stability of line switching.

[0082] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the error allowance, it is within the protection scope of this disclosure.

[0083] In some embodiments, as shown in Figures 2 to 4, the first electrostatic discharge structure 105 may further include a plurality of second sub-electrostatic discharge structures 1052 located in the third non-display area BB3 and close to the second non-display area BB2. Some of the second sub-electrostatic discharge structures 1052 extend along the first direction Y of the arrangement of the first non-display area BB1 and the second non-display area BB3, while the remaining second sub-electrostatic discharge structures 1052 extend along the second direction X of the arrangement of the two third non-display areas BB3, thereby fully utilizing the space of the third non-display area BB3 to achieve a narrow bezel effect. In some embodiments, the second sub-electrostatic discharge structures 1052 disposed between the gate driving circuit area GOA and the display area AA may be staggered in the second direction X and may partially overlap in the first direction Y; the second sub-electrostatic discharge structures 1052 on the side of the gate driving circuit area GOA facing the second non-display area BB2 may be arranged side-by-side along the second direction X.

[0084] In some embodiments, FIG7 is an enlarged structural schematic diagram of the Z5 region in FIG2. As can be seen from FIG2 and FIG7, the array substrate provided in the embodiments of this disclosure may further include a plurality of transistors 107, and the plurality of transistors 107 may be electrically connected to at least a portion of the detection lines 103; the transistors 107 may be located in the second non-display area BB2. In other embodiments, the transistors 107 may also be located in other non-display areas. This disclosure does not make specific limitations.

[0085] Figure 8 is an equivalent circuit diagram of ambient light detection provided in an embodiment of this disclosure. As shown in Figures 7 and 8, in some embodiments, multiple detection lines 103 may include a first light-sensing detection line LS1, a second light-sensing detection line LS2, and multiple third light-sensing detection lines LS3; multiple transistors 107 may be divided into multiple transistor groups (e.g., T11, T12, T13, T14), and each transistor group may include at least one transistor 107; the gates of all transistors 107 are connected to the first light-sensing detection line LS1, the first terminals of all transistors are connected to the second light-sensing detection line LS2, and different transistor groups (e.g., T11, T12, T13, T14) are connected to different third light-sensing detection lines LS3. In some embodiments, when it is necessary to detect ambient light brightness, voltage can be applied to the gate and first terminal of transistor 107 through the first light-sensing detection line LS1 and the second light-sensing detection line LS2, respectively, and the current value generated by ambient light irradiation can be detected through the third light-sensing detection line LS3, which is electrically connected to the second terminal of transistor 107. The greater the ambient light brightness, the greater the corresponding current value.

[0086] In some embodiments, FIG9 is an enlarged structural schematic diagram of region Z6 in FIG7. As can be seen from FIG9, transistor 107 in this disclosure can be composed of two small transistors to facilitate heat dissipation and improve the reliability of transistor 107. Referring again to FIG9, the gate G of transistor 107 in this disclosure can be integrally disposed with the first photosensitive detection line LS1. The first electrode S can be connected to the second photosensitive detection line LS2 through a hole through the first transfer electrode CE1. The second electrode D can be connected to the third photosensitive detection line LS3 through a hole through the second transfer electrode CE2. Optionally, the first transfer electrode CE1 and the second transfer electrode CE2 are disposed on the same layer and made of the same material as the pixel electrode or common electrode of the display area AA.

[0087] In some embodiments, as shown in FIG3, to improve orientation uniformity, a dummy transistor 108 may be provided, such that the dummy transistor 108 and transistor 107 are uniformly distributed between the second photosensitive detection line LS2 and the third photosensitive detection line LS3. Since the dummy transistor 108 in this disclosure is not used to detect ambient light intensity, it does not need to have conduction or cutoff characteristics. Based on this, at least one of the gate, first electrode, and second electrode of the dummy transistor 108 in this disclosure can be floating. Optionally, some dummy transistors 108 are disposed close to the common electrode line 102. In some embodiments, a transition electrode corresponding to the first electrode and second electrode of the dummy transistor 108 may still be provided, but the first electrode and second electrode of the dummy transistor 108 are not connected to the corresponding transition electrode by a hole.

[0088] In some embodiments, the array substrate provided in this disclosure, as shown in FIG2, 3, and 5, may further include multiple gate drive circuit lines 109 and multiple second electrostatic discharge structures 110 located in non-display areas (e.g., BB2, BB3). The second electrostatic discharge structures 110 are connected to the gate drive circuit lines 109, the first electrostatic discharge structure 105, and the common electrode line 102. In some embodiments, one end of the second electrostatic discharge structure 110 is connected to the gate drive circuit line 109, and the other end is connected to the common electrode line 102 through a fifth electrostatic discharge structure 110'. In this way, on the one hand, the static electricity on the gate drive circuit line 109 can be released to the common electrode line 102 through the second electrostatic discharge structure 110; on the other hand, the static electricity on the detection line 103 can be released to the common electrode line 102 in sequence through the first electrostatic discharge structure 105 and the second electrostatic discharge structure 110, thereby achieving electrostatic protection for the gate drive circuit line 109 and the detection line 103. Referring again to Figure 3, one end of the second electrostatic discharge structure 110 is electrically connected to the gate drive circuit signal line 109, and the other end can be electrically connected to the first electrostatic discharge structure 105 through the signal line on the same layer as the pixel electrode or common electrode. The other end of the first electrostatic discharge structure 105 is electrically connected to the detection line 103, and the signal line on the same layer as the pixel electrode or common electrode is connected to the common electrode line 102 through the fifth electrostatic discharge circuit 110'.

[0089] In some embodiments, the gate drive circuit signal line 109 is on the same layer and made of the same material as the gate line, and the gate drive circuit signal line 109 may include frame start signal lines STV1A and STV1B, total reset signal line STV0, clock signal lines CLK1 to CLK12 (specifically, the number of clock signal lines is not limited, and this case uses 12 as an example), noise reduction signal lines VDDO and VDDE, and a first low-level signal line, etc.; wherein, the frame start signal line can be one or more, which is not limited here. This case takes setting two frame start signal lines as an example. The frame start signal lines STV1A and STV1B are the trigger input signals for odd-numbered rows and even-numbered rows, respectively; the clock signal lines CLK1 to CLK12 are responsible for providing the output voltage of the gate of each row; the noise reduction signal lines VDDO and VDDE provide input signals for the noise reduction unit of the gate drive circuit, with a 50% duty cycle and alternating high and low levels; the first low-level signal line provides an internal low-level voltage for the gate drive circuit.

[0090] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 1 to 3 and 5, may further include multiple data lines 111 located in the display area AA, and multiple third electrostatic discharge structures 112 and test lines 113 located in the non-display area (e.g., BB1, BB2, BB3). The multiple third electrostatic discharge structures 112 are connected to the multiple data lines 111 and the test lines 113, so that static electricity on the data lines 111 is released to the test lines 113 via the third electrostatic discharge structures 112, thereby achieving electrostatic protection for the data lines 111. Optionally, the test lines 113 are connected to the common electrode line 102 via a fourth electrostatic discharge structure 116.

[0091] In some embodiments, as shown in FIG5, within the first non-display area BB1, the detection line 103 may be located between the third electrostatic discharge structure 112 and the display area AA. As shown in FIG3, within the second non-display area BB2, the detection line 103 and the transistor 107 (and the dummy transistor 108 are uniformly distributed between the second photosensitive detection line LS2 and the third photosensitive detection line LS3) may be located between the third electrostatic discharge structure 112 and the common electrode line 102. The orthographic projection of the test line 113 on the substrate 101 intersects with the orthographic projection of at least one detection line 103 on the substrate 101. To avoid short-circuiting between the test line 113 and the detection line 103, the test line 113 may be bridged by a third transition electrode CE3 of the same layer and material as the pixel electrode or the common electrode.

[0092] In some embodiments, as shown in Figures 2 and 7, within the second non-display area BB2, the detection line 103 and the transistor 107 may be located between the third electrostatic discharge structure 112 and the display area AA. The test line 113 is located on the side of the detection line 103 and the transistor 107 away from the display area AA to avoid the test line 113 intersecting with the detection line 103, thereby preventing the static electricity accumulated on the detection line 113 from undergoing electrostatic breakdown and being transferred to the detection line 103. Optionally, the test line 113 in this embodiment may be an ADD signal line used for array substrate testing during array test, which is not limited herein.

[0093] In some embodiments, FIG10 is a schematic diagram of another enlarged structure of the Z1 region in FIG1, and FIG11 is a schematic diagram of another enlarged structure of the Z1 region in FIG1. ​​As can be seen from FIG10 and FIG11, within the second non-display area BB2, the test line 113 can also extend only along the second direction X. In this case, the test line 113 only serves to connect multiple third electrostatic discharge structures 112. It can be seen that compared with FIG1 and FIG2, the test line 113 in FIG10 and FIG11 is shorter, which can reduce the amount of static electricity accumulation. Furthermore, since the test line 113 is not connected to the detection line 103, it can effectively prevent the static electricity accumulated on the detection line 113 from undergoing electrostatic breakdown and being transferred to the detection line 103.

[0094] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 2 and 3, at least a portion of the test line 113 may be located on the side of the common electrode line 102 away from the display area AA on at least one side. For example, in the third non-display area BB3, the test line 113 is located on the side of the common electrode line 102 away from the display area AA; in the first non-display area BB1 and the second non-display area BB2, the test line 113 extends from the outside (i.e., the side away from the display area AA) of the common electrode line 102 to the inside (i.e., the side closer to the display area AA) to connect with the third electrostatic discharge structure 112 within the common electrode line 102. In some embodiments, at least a portion of the test line 113 may also be located between the common electrode line 102 and the display area AA on at least one side of the display area AA to increase the distance between the test line 113 and the edge of the panel, reduce its electrostatic accumulation, and reduce the risk of electrostatic discharge. Referring again to Figure 2, optionally, at least a portion of the test line 113 is surrounded by the common electrode line 102, that is, at least a portion of the test line 113 is provided with the common electrode line 102 on both sides. The test lines 113 on both sides of the common electrode line 102 can be bridged by a fourth adapter electrode CE4, which can be in the same layer and material as the pixel electrode or the common electrode. Optionally, to reduce the amount of static electricity accumulated on the test lines 113 during the manufacturing process, the test lines 113 can be broken, and the broken test lines 113 can be connected by a fifth adapter electrode CE5. In addition, in some embodiments, the test lines 113 can be connected to the common electrode line 102 through a sixth electrostatic discharge structure 120, and the grounding line 114 can be connected to the common electrode line 102 through a seventh electrostatic discharge structure 121.

[0095] In some embodiments, the grounding wire 114 is the main signal line for electrostatic accumulation, as shown in Figures 12 and 13. This disclosure allows for increasing the line width 'a' of the grounding wire 114 (which can be disposed on the same layer and made of the same material as the gate line) at the corner between the first non-display area BB1 and the third non-display area BB3 from 30 μm to 31 μm to 45 μm (e.g., 35 μm), and increasing the line width 'd' within the third non-display area BB3 from 44 μm to 44.5 μm to 55 μm (e.g., 45 μm) to optimize grounding. The conductivity of line 114 is improved to reduce weak conductive points and avoid electrostatic discharge accumulation. At the same time, the distance b between the grounding line 114 and the test line 113 at the corner between the first non-display area BB1 and the third non-display area BB3 can be increased from 12μm to 15μm to 25μm (e.g., 20μm), and the spacing e within the third non-display area BB3 can be increased from 15μm to 20μm to 30μm (e.g., 25μm) to prevent discharge between the grounding line 114 and the test line 113 from causing burnout.

[0096] In some embodiments, FIG14 is an enlarged structural schematic diagram of the Z7 region in FIG1. ​​As can be seen from FIG14, the array substrate provided in the embodiments of this disclosure may further include a dummy line 115 located on the side of the ground line 114 near the display area AA. The dummy line 115 may be disposed on the same layer and with the same material as the gate line. The ground line 114 includes at least one first tip 1141, and the dummy line 115 includes a second tip 1151 opposite to the first tip 1141. Static electricity on the substrate (CF) side can be conducted to the silver paste dots through the back ITO, and then guided to the ground line 114 through the silver paste dots. When the static electricity accumulates and cannot be discharged into the panel through the lead, the in-plane will become the static electricity release location. To prevent the effective pattern from becoming a point of electrostatic discharge, this disclosure adds a dummy line 115 with a tip to the blank area of ​​the grounding wire 114 near the display area AA, so that the static electricity on the grounding wire 114 is released to the second tip 1151 through the first tip 1141. In this way, the dummy line 115 with the second tip 1151 acts as a sacrificial unit for electrostatic protection, thereby protecting the internal effective pattern.

[0097] In some embodiments, in the array substrate provided in the present disclosure, the dummy line 115 can be a continuously arranged trace or can include multiple dummy portions arranged in segments. Furthermore, since the blank area of ​​the second non-display area BB2 is sufficient, the present disclosure places the dummy line 115 within the second non-display area BB2. Of course, if the wiring space allows, the present disclosure can also place the dummy line 115 in other non-display areas, which is not limited here.

[0098] In some embodiments, in the array substrate provided in this disclosure, the display area AA includes a plurality of sub-pixels arranged in an array. The spacing of the first tips 1141 in the second direction X (equivalent to the spacing of the second tips 1151 in the second direction X) is approximately the same as the size of the sub-pixels in the second direction X (sub-pixel pitch). The number of first tips 1141 (equivalent to the number of second tips 1151) is the same as the number of sub-pixels in the second direction X. For example, the first tips 1141 are arranged in 3840 columns (same resolution), and the spacing is consistent with the sub-pixel pitch to minimize the risk of uneven alignment of the alignment layer. It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately the same" may be completely equivalent, or there may be some deviation (e.g., ±5% deviation). Therefore, the "approximately the same" relationship between related features is within the protection scope of this disclosure as long as the error is permissible.

[0099] In some embodiments, as shown in Figures 4, 6, and 15, the detection line 103 may include a temperature sensing line TS. The first end a of the temperature sensing line TS can be connected to a first level VCC, and the second end b is grounded. The resistance between the first end a of the temperature sensing line TS and the detection point Vout is Rin, and the resistance between the second end b of the temperature sensing line TS and the detection point Vout is R0. The resistance R of the temperature sensing line TS (equal to the sum of Rin and R0) changes with temperature (e.g., linearly). Therefore, changes in ambient temperature will cause changes in the resistance values ​​of Rin and R0 (e.g., linearly). The voltage value obtained by the microcontroller circuit (MCU) at the detection point Vout... The temperature changes with ambient temperature (e.g., linearly), allowing the microcontroller circuit (MCU) to determine the temperature by detecting the voltage value at the detection point Vout. In some embodiments, where wiring space permits, the length of the temperature sensing line TS can be maximized to increase its resistance, facilitating monitoring of the Vout voltage. Therefore, to increase the length of the temperature sensing line TS, it can be configured to include multiple integrally formed zigzag sections, the shape of which can approximate an "S" shape, etc. Optionally, the zigzag sections included in the temperature sensing line TS in this disclosure can be located within the second non-display area BB2. Where wiring space permits, the zigzag sections included in the temperature sensing line TS can also be located in other non-display areas; this disclosure does not impose specific limitations. Furthermore, in this disclosure, the light sensing line and the temperature sensing line can be configured simultaneously or separately; this is not limited here.

[0100] In some embodiments, for the sake of design simplification, the first electrostatic discharge structure 105, the second electrostatic discharge structure 110, the third electrostatic discharge structure 112, the fourth electrostatic discharge structure 116, the fifth electrostatic discharge structure 110', the sixth electrostatic discharge structure 120, and the seventh electrostatic discharge structure 121 of this disclosure are identical, as shown in Figures 16 and 17. The electrostatic discharge structure of this disclosure may include a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; wherein, the gate of the first transistor M1, the first terminal of the first transistor M1, and the second terminal of the second transistor M2 are connected; the second terminal of the first transistor M1, the gate of the second transistor M2, the first terminal of the second transistor M2, the gate of the third transistor M3, the first terminal of the third transistor M3, and the second terminal of the fourth transistor M4 are connected; the second terminal of the third transistor M3, the gate of the fourth transistor M4, and the first terminal of the fourth transistor M4 are connected. Optionally, one of the gates of the first transistor M1 and the fourth transistor M4 is used as the electrostatic input terminal esd_in and the other is used as the electrostatic output terminal esd_out. Figures 16 and 17 illustrate this with the gate of the first transistor M1 as the electrostatic input terminal esd_in and the gate of the fourth transistor M4 as the electrostatic output terminal esd_out.

[0101] In some embodiments, transistor 107, dummy transistor 108, first transistor M1, second transistor M2, third transistor M3, and fourth transistor M4 in this disclosure may be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), without limitation herein. In some embodiments, transistor 107, dummy transistor 108, first transistor M1, second transistor M2, third transistor M3, and fourth transistor M4 may be P-type transistors or N-type transistors. The first electrode may be the source and the second electrode may be the drain, or the first electrode may be the drain and the second electrode may be the source, without limitation herein. The active layers of the body transistor 107, the dummy transistor 108, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. To improve etching uniformity, as shown in Figure 16, a floating metal block 117 of the same layer and material as the first and second transistors can also be provided.

[0102] In some embodiments, as shown in Figures 1, 4, and 5, this disclosure may further include a short-circuit ring 118, a common electrode feedback line 119, a fan-out line FL, etc. Additionally, for metal lines with larger linewidths in non-display areas (e.g., common electrode line 102), to improve transmittance and ensure the curing effect of the sealant, a hollow structure can be provided in the area where the metal linewidth is larger. Referring again to Figures 4, 5, and 7, virtual signal lines DL can be provided between at least some of the detection lines 103 to prevent mutual interference between the detection lines 103. Other essential components of the array substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure.

[0103] Based on the same inventive concept, this disclosure provides a display panel. Figure 18 is a schematic diagram of the structure of the display panel provided in this disclosure. As shown in Figure 18, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle of solving the problem by this display panel is similar to the principle of solving the problem by the array substrate described above, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.

[0104] In some embodiments, in the display panel provided in this disclosure, as shown in FIG8, the opposing substrate 002 includes a black matrix 201, and at least some of the transistors 107's orthogonal projections on the substrate 101 and the black matrix 201's orthogonal projections on the substrate 101 do not overlap. This ensures that after the array substrate 001 and the opposing substrate 002 are aligned, ambient light illuminates the transistors 107 not covered by the black matrix 201. Furthermore, the transistors 107 covered by the black matrix 201 can serve as a reference. Since all transistors 107 have the same shape and size, and the first light-sensing detection line LS1 applies a uniform voltage to the gates of all transistors 107, and the second light-sensing detection line LS2 applies a uniform voltage to the first electrodes of all transistors 107, the influence of transistor structure, voltage, temperature, and other factors on the detection current is eliminated. Based on this, the current value of the transistors 107 not covered by the black matrix 201 minus the current value of the transistors 107 covered by the black matrix 201 is the current value generated by ambient light illumination, thereby realizing the detection of ambient light brightness.

[0105] In some embodiments, as shown in FIG8, the opposing substrate 002 further includes a color resist layer located on the side of the black matrix 201 facing the array substrate 001. The color resist layer 202 includes multiple color resists of different colors, such as a first color resist R, a second color resist G, and a third color resist B. These multiple color resists cover at least part of the transistor groups. For example, the first color resist R, the second color resist G, and the third color resist B cover transistor groups T11, T12, and T13, respectively, and the black matrix 201 covers transistor group T14. The carrier concentration in the channels of transistor groups T11, T12, and T13 is greatly affected by illumination. When a fixed voltage is applied, the current in the channels changes as the brightness of the light illuminating the channels changes. By combining the first color resist R, the second color resist G, and the third color resist B, the proportions of red, green, and blue light in ambient light can be detected, thereby taking into account both the brightness and color temperature of ambient light.

[0106] In some embodiments, the current values ​​of transistor groups T11, T12, T13, and T14 can be fed back to the system on chip (SOC) or the timer control register (TCON) for processing, and the brightness and / or color temperature of the backlight module can be adjusted according to the processing results.

[0107] In some embodiments of the present disclosure, as shown in FIG18, a liquid crystal layer 003 may be disposed between an array substrate 001 and a counter substrate 002 in a display panel. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 may be disposed on the side of the counter substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0108] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG19, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot LEDs.

[0109] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0110] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0111] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0112] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; The common electrode line is located in the non-display area; At least one detection line is located in the non-display area, the detection line including a first detection part located on the side of the common electrode line away from the display area, and a second detection part located on the side of the common electrode line close to the display area; At least one bonding line is located in the non-display area. The bonding line connects the first detection part and the second detection part of the same detection line. The orthographic projection of the bonding line on the substrate and the orthographic projection of the common electrode line on the substrate intersect each other. At least one first electrostatic discharge structure is located in the non-display area, and the first electrostatic discharge structure is connected to the first detection unit.

2. The array substrate of claim 1, wherein, The non-display area includes a first non-display area with at least one binding area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; The first detection unit is located in at least one of the third non-display areas, and the second detection unit is located in the first non-display area and / or the second non-display area.

3. The array substrate of claim 2, wherein, The at least one first electrostatic discharge structure includes a plurality of first sub-electrostatic discharge structures located in the third non-display area and close to the first non-display area; The plurality of first sub-electrostatic discharge structures extend along a first direction and are arranged along the first direction, which is the arrangement direction of the first non-display area and the second non-display area.

4. The array substrate of claim 3, wherein, The third non-display area includes a gate driving circuit area, and the plurality of first sub-electrostatic discharge structures are located between the gate driving circuit area and the first non-display area.

5. The array substrate according to any one of claims 2 to 4, wherein, The at least one first electrostatic discharge structure includes a plurality of second sub-electrostatic discharge structures located in the third non-display area and close to the second non-display area; A portion of the second sub-electrostatic discharge structure extends along the first direction, while the remaining second sub-electrostatic discharge structures extend along the second direction. The first direction is the arrangement direction of the first non-display area and the second non-display area, and the second direction is the arrangement direction of the two third non-display areas.

6. The array substrate of claim 5, wherein, The third non-display area includes a gate drive circuit area; Each of the second sub-electrostatic discharge structures between the gate driving circuit region and the display region is staggered in the second direction and overlaps in at most part in the first direction; Each of the second sub-electrostatic discharge structures in the gate drive circuit region facing the second non-display area is arranged side by side along the second direction.

7. The array substrate according to any one of claims 2 to 6, wherein, It also includes a plurality of transistors, said plurality of transistors being electrically connected to at least a portion of said detection line; The plurality of transistors are located in the second non-display area.

8. The array substrate according to any one of claims 1 to 7, wherein, It also includes multiple gate drive circuit lines and multiple second electrostatic discharge structures located in the non-display area, wherein the multiple second electrostatic discharge structures are connected to the multiple gate drive circuit lines, the at least one first electrostatic discharge structure, and the common electrode line.

9. The array substrate according to any one of claims 1 to 8, wherein, It also includes multiple data lines located in the display area, and multiple third electrostatic discharge structures and test lines located in the non-display area; wherein, the multiple third electrostatic discharge structures are connected to the multiple data lines, and the multiple third electrostatic discharge structures are electrically connected to the test lines.

10. The array substrate as claimed in claim 9, wherein, It also includes a plurality of transistors, said plurality of transistors being electrically connected to at least a portion of said detection line; The non-display area includes a first non-display area with at least one binding area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; Within the first non-display area, the at least one detection line is located between the plurality of third electrostatic discharge structures and the display area.

11. The array substrate as claimed in claim 10, wherein, Within the second non-display area, the at least one detection line and the plurality of transistors are located between the plurality of third electrostatic discharge structures and the common electrode line.

12. The array substrate as claimed in claim 11, wherein, Within the second non-display area, the orthographic projection of the test line on the substrate intersects with the orthographic projection of the at least one detection line on the substrate.

13. The array substrate as claimed in claim 10, wherein, Within the second non-display area, the at least one detection line and the plurality of transistors are located between the plurality of third electrostatic discharge structures and the display area.

14. The array substrate as claimed in claim 13, wherein, Within the second non-display area, the test lines are located on the side of the plurality of detection lines and the plurality of transistors away from the display area.

15. The array substrate as claimed in claim 11, 13, or 14, wherein, Within the first non-display area and / or the second non-display area, the detection line extends along a second direction, which is the arrangement direction of the two third non-display areas.

16. The array substrate according to any one of claims 9 to 15, wherein, At least a portion of the test line is located between the common electrode line and the display area on at least one side of the display area.

17. The array substrate according to any one of claims 9 to 15, wherein, At least a portion of the test line is located on the side of the common electrode line away from the display area on at least one side of the display area.

18. The array substrate according to any one of claims 1 to 17, wherein, It also includes a grounding wire located in the non-display area, and a dummy wire located on the side of the grounding wire closer to the display area; The grounding wire includes at least one first tip, and the dummy wire includes a second tip positioned opposite the first tip.

19. The array substrate as claimed in claim 18, wherein, The dummy lines are arranged continuously, or the dummy lines include multiple independent dummy parts.

20. The array substrate as claimed in claim 18 or 19, wherein, The non-display area includes a first non-display area with at least one binding area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; the dummy line is located in the second non-display area.

21. The array substrate as claimed in claim 20, wherein, The display area includes a plurality of sub-pixels arranged in an array. The spacing between the first tips in the second direction is approximately the same as the size of the sub-pixels in the second direction. The number of the first tips is the same as the number of the sub-pixels in the second direction. The second direction is the arrangement direction of the two third non-display areas.

22. The array substrate according to any one of claims 1 to 21, wherein, The at least one detection line includes a temperature-sensing detection line, which includes multiple integrally formed zigzag sections.

23. The array substrate according to any one of claims 1 to 22, wherein, It also includes a plurality of transistors, said plurality of transistors being electrically connected to at least a portion of said detection line; The at least one detection line includes a first photosensitive detection line, a second photosensitive detection line, and multiple third photosensitive detection lines; The plurality of transistors are divided into a plurality of transistor groups. The gates of the plurality of transistors are connected to the first photosensitive detection line, the first terminals of the plurality of transistors are connected to the second photosensitive detection line, and different transistor groups are connected to different third photosensitive detection lines.

24. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 23.

25. The display panel as claimed in claim 24, wherein, The opposing substrate includes a black matrix, and at least a portion of the transistors' orthogonal projections on the substrate do not overlap with the orthogonal projections of the black matrix on the substrate.

26. The display panel as claimed in claim 25, wherein, The opposing substrate further includes a color resist layer located on the side of the black matrix facing the array substrate, the color resist layer including multiple color resists of different colors, the multiple color resists covering at least a portion of the transistor group.

27. A display device, wherein, It includes a display panel as described in any one of claims 24 to 26, and a backlight module located on the light-incident side of the display panel.

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