Data processing device, electronic device, and data processing device manufacturing method

Abstract

A data processing device, an electronic device, and a data processing device manufacturing method. The data processing device comprises a logic processing layer, an in-memory computing layer, and a memory array layer. The logic processing layer, the in-memory computing layer and the memory array layer are at least partially stacked; the logic processing layer is configured to perform logic operation and / or control processing; the in-memory computing layer is configured to perform neural network operation on received data, and the memory array layer is configured to store the data of the in-memory computing layer; the memory array layer comprises a memory array, the memory array comprises a plurality of memory cells arranged in a plurality of rows and columns, and each of the plurality of memory cells comprises a transistor and a magnetic random access memory device electrically connected to the transistor. The data processing device can improve the data processing efficiency and the integration level.

Description

Data processing device, electronic device, and method for manufacturing data processing device

[0001] This application claims priority to Chinese Patent Application No. 202410683155.3, filed on May 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a data processing apparatus, an electronic device, and a method for manufacturing the data processing apparatus. Background Technology

[0003] Memristor-based in-memory computing systems can effectively perform matrix-vector multiplication in neural networks, but the input and output data need to be cached, and the efficiency of data transfer becomes a performance bottleneck. Cache bandwidth is limited by the bus interconnection under the two-dimensional integrated architecture, resulting in low transmission efficiency within a single operation and limiting parallel computing capabilities. Even with multi-level bus optimization, it is still constrained by the inefficiency of two-dimensional connections. Furthermore, traditional memristor chips are based on analog resistive switching characteristics. Although they have multiple resistive states that can be used for analog calculations, they are limited by non-ideal characteristics (such as conductance drift, high randomness, or limited erase / write cycles), making it difficult to achieve high-precision calculations. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a data processing apparatus, including: a logic processing layer, an in-memory computing layer, and a storage array layer, wherein the logic processing layer, the in-memory computing layer, and the storage array layer are at least partially stacked; the logic processing layer is configured to perform logical operations and / or control processing; the in-memory computing layer is configured to perform neural network operations on received data; the storage array layer is configured to store data for the in-memory computing layer; the storage array layer includes a storage array, the storage array including a plurality of storage cells arranged in multiple rows and columns, each of the plurality of storage cells including a transistor and a magnetic random access storage device electrically connected to the transistor.

[0005] For example, in a data processing apparatus provided in one embodiment of this disclosure, the magnetic random access storage device includes a first electrode layer, a free layer, a barrier layer, a pinning layer, and a second electrode layer stacked sequentially.

[0006] For example, in a data processing apparatus provided in one embodiment of this disclosure, the free layer includes an antiferromagnetic layer and a ferromagnetic layer stacked sequentially.

[0007] For example, in a data processing apparatus provided in one embodiment of this disclosure, the in-memory computing layer includes at least one in-memory computing array, each of the in-memory computing arrays including at least one memristor array, the memristor array including a plurality of memristors arranged in multiple rows and columns; the magnetic random access storage device includes a magnetic tunnel junction, the magnetic tunnel junction being placed at a offset position from the memristors.

[0008] For example, in a data processing apparatus provided in one embodiment of this disclosure, the transistor includes at least one of a carbon nanotube transistor, an indium oxide transistor, or a low-temperature polycrystalline silicon transistor.

[0009] For example, in a data processing apparatus provided in one embodiment of this disclosure, the magnetic random access memory device includes a spin-transfer torque magnetic random access memory device or a spin-orbit torque magnetic random access memory device.

[0010] At least one embodiment of this disclosure provides an electronic device, including a data processing device provided in any embodiment of this disclosure.

[0011] At least one embodiment of this disclosure provides a method for fabricating a data processing device, comprising: fabricating an in-memory computing layer and fabricating a memory array layer at least partially stacked with the in-memory computing layer using a semiconductor fabrication process, wherein the in-memory computing layer is configured to perform neural network operations on received data, and the memory array layer is configured to store data for the in-memory computing layer; the memory array layer is configured to store data for the in-memory computing layer, the memory array layer includes a memory array, the memory array includes a plurality of memory cells arranged in multiple rows and columns, each of the plurality of memory cells includes a transistor and a magnetic random access memory device electrically connected to the transistor.

[0012] For example, in a fabrication method provided in one embodiment of this disclosure, the fabrication of a magnetic random access memory device includes: fabricating a mask to define a patterned region of the magnetic random access memory device, wherein the mask includes a photoresist mask or a hard mask; and using the mask to fabricate a magnetic tunnel junction.

[0013] For example, in a fabrication method provided in one embodiment of this disclosure, the fabrication of a mask to define a patterned region of the magnetic random access memory device includes: defining the pattern of the magnetic tunnel junction region using a double-layer adhesive process.

[0014] For example, in a fabrication method provided in one embodiment of this disclosure, the fabrication of a magnetic tunnel junction using the mask includes: etching areas other than the patterned area of ​​the magnetic random access memory device using a dry etching process to preserve the patterned area of ​​the magnetic random access memory device.

[0015] For example, in a fabrication method provided in one embodiment of this disclosure, the in-memory computing layer includes at least one in-memory computing array, each of the in-memory computing arrays includes at least one memristor array, the memristor array includes multiple memristors arranged in multiple rows and columns; the fabrication of the magnetic random access memory device further includes: selecting a region on the surface of the memristor with a root mean square roughness of less than 1 nm or 0.2 nm to arrange a magnetic tunnel junction, and placing the magnetic tunnel junction at a position offset from the memristor.

[0016] For example, one embodiment of the present disclosure provides a fabrication method that further includes: providing a silicon substrate; fabricating a logic processing layer on the silicon substrate using a semiconductor fabrication process, wherein the logic processing layer is configured to perform logic operations and / or control processing, the in-memory computing layer is formed on the side of the logic processing layer away from the silicon substrate, and the memory array layer is formed on the side of the in-memory computing layer away from the silicon substrate. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0018] Figure 1 shows a schematic diagram of an MRAM memory cell;

[0019] Figure 2 shows a schematic diagram of the structure of an SOT-MRAM memory cell;

[0020] Figure 3 shows a schematic diagram of an STT-MRAM memory cell;

[0021] Figure 4 shows a schematic diagram of the working principle of an in-memory computing array;

[0022] Figure 5 shows a schematic diagram of the architecture of a data processing apparatus provided in at least one embodiment of the present disclosure;

[0023] Figure 6 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure;

[0024] Figure 7 shows a schematic diagram of a method for fabricating a magnetic random access storage device according to at least one embodiment of the present disclosure;

[0025] Figure 8 shows a schematic flowchart of a method for preparing a magnetoresistive random access device according to at least one embodiment of this disclosure; and

[0026] Figure 9 shows a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0029] Figure 1 shows a schematic diagram of an MRAM memory cell. Figure 1 shows an MRAM magnetic random access memory with a 2T1M (Two Transistor One Magnetic Tunnel Junction) structure, which includes two transistors (2T) and one MRAM memory device (1M).

[0030] As shown in Figure 1, an exemplary MRAM memory device includes a heavy metal layer (HM), a free layer (FL), a tunnel barrier layer (TBL, such as magnesium oxide MgO), and a pinned layer (PL) stacked sequentially.

[0031] The two transistors (2T) include a first transistor and a second transistor. The first transistor is connected to the read word line (RWL) and the bit line (BL) to the pinning layer (PL) of the MRAM memory device. The second transistor is connected to the write word line (WWL) and the bit line (BL) to the heavy metal layer (HM) of the MRAM memory device. The bit line (BL) is connected to both the pinning layer (PL) and the heavy metal layer (HM) of the MRAM memory device via the two transistors. The source line (SL) is connected to the heavy metal layer (HM) of the MRAM memory device. The first transistor is configured to control data reading from the MRAM memory cell via the read word line (RWL), and the second transistor is configured to control data writing to the MRAM memory cell via the write word line (WWL).

[0032] The 2T1M structure of MRAM memory cells improves the reliability and selectivity of data access and reduces crosstalk between adjacent cells through dual transistor control and the magnetoresistance effect of magnetic tunnel junction. It achieves non-volatile, high-speed, and high-density storage, and effectively performs data reading and writing by finely controlling current and magnetic field, with good anti-interference ability and data stability.

[0033] Figure 2 shows a schematic diagram of a SOT-MRAM memory cell. As shown in Figure 2, in a 2T1M memory cell based on SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory), the MRAM memory cell includes a heavy metal layer (HM), a free layer (FL), a barrier layer (TBL), and a pinning layer (PL) stacked sequentially. The bit line (BL) is connected to the heavy metal layer (HM) of the MRAM memory cell through a transistor, and the source line (SL) is connected to the heavy metal layer (HM) of the MRAM memory cell to provide read current or write current. The read word line (RWL) is connected to the gate of the transistor connected between the bit line and the pinning layer (PL) of the MRAM memory cell, and the write word line (WWL) is connected to the gate of the transistor connected between the bit line and the heavy metal layer (HM) of the MRAM memory cell.

[0034] During a write operation, the transistor, controlled by the enable signal on the write word line, connects the bit line to the heavy metal layer (HM) of the MRAM memory device. Current can be supplied through the bit line and source line to reverse the magnetization direction of the free layer. By adjusting the direction and magnitude of the current, the magnetization direction of the free layer can be switched. When the magnetization direction of the free layer is the same as that of the pinned layer, the bit being written is 0; when the magnetization direction of the free layer is opposite to that of the pinned layer, the bit being written is 1.

[0035] During a read operation, the transistor, controlled by the enable signal on the read word line, connects to the pinned layer (PL) of the MRAM memory device. Current is supplied via the bit lines and source lines to prevent the magnetization direction of the free layer from flipping. Data is then read by detecting the magnetization direction of the free layer. When the magnetization direction of the free layer aligns with that of the pinned layer, the stored bit is 0; when the magnetization direction of the free layer is opposite to that of the pinned layer, the stored bit is 1.

[0036] Figure 3 shows a schematic diagram of an STT-MRAM memory cell. As shown in Figure 3, in an STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) memory cell, the MRAM memory device includes a stacked free layer (FL), a barrier layer, and a pinned layer (PL). The bit line (BL) is connected to the free layer of the MRAM memory device to provide read or write current; the source line (SL) is connected to the pinned layer of the MRAM memory device through a transistor to provide read or write current; and the word line (WL) is connected to the gate of the transistor to select the cell to be read or written.

[0037] During a write operation, control signals on the word line can turn on transistors to provide corresponding current flowing through the MRAM memory device via the bit lines and source lines. The resulting current component passes through the barrier layer, causing the magnetization direction of the free layer to flip. Depending on the direction of the current, the magnetization direction of the free layer can be flipped from top to bottom or from bottom to top. Therefore, different data can be written by changing the direction of the current.

[0038] During a read operation, transistors are turned on via control signals on the word lines to provide corresponding currents flowing through the MRAM memory device via the bit lines and source lines, ensuring that the magnetization direction of the free layer does not reverse. The magnetization direction of the free layer is then determined by detecting voltage changes on the bit lines. If the magnetization direction of the free layer is the same as that of the pinned layer, the voltage on the bit line is lower; if the magnetization direction of the free layer is opposite to that of the pinned layer, the voltage on the bit line is higher. Therefore, the data stored in the MRAM memory device can be determined by reading the voltage on the bit lines.

[0039] Figure 4 illustrates a schematic diagram of the working principle of an in-memory computing array. As shown in Figure 4, the in-memory computing array (i.e., the memory computing array) includes memristor units arranged in rows and columns. The memristor units include memristors (such as resistive random access memory (RRAM), phase-change memory (PRAM), etc.). This in-memory computing array can perform matrix-vector multiplication operations according to Kirchhoff's laws. The data to be weighted matrix can be mapped to the resistance values ​​of each memristor and written into the in-memory computing array. The input vector is mapped to the input signal (voltage signal) of each row of the in-memory computing array, and the output signal (current signal) of each column is the product of the input voltage and the resistive random access conductance, which is the output vector.

[0040] ∑I=∑V*G,

[0041] Where I represents the output current of each column in the in-memory computing array, V represents the input voltage of each row in the in-memory computing array, and G represents the conductance of the memristor in the memristor cell. Therefore, the aforementioned in-memory computing array can be used for neural network computation.

[0042] Compared to the von Neumann architecture, in-memory computing offers advantages such as faster processing speed, lower power consumption, and higher integration density. In-memory computing integrates computational functions into storage units, reducing the frequent data transfer between data storage and computation modules and minimizing data transmission latency. Furthermore, by integrating computation and storage functions onto the same chip, it reduces the need for external connections and wiring, resulting in higher chip integration and enabling applications in smaller, thinner electronic devices. Neural networks are a key technology in fields such as deep learning, requiring massive computational resources and extremely high efficiency. In-memory computing not only meets the computational demands of neural networks but also achieves high-performance computing under low power consumption conditions.

[0043] However, the inventors of this disclosure have noted that in-memory computing chips face technical challenges related to cache capacity and chip area, cache bandwidth, and single-precision computing. For example, for a 32×32 in-memory computing array, a cache of at least 512 bits is required (i.e., for a 1k array, 0.5k data needs to be cached). However, when using 6T-SRAM to achieve the same capacity cache, the number of transistors required in the cache is three times that of a memristor array (using a 1T1R structure), resulting in a cache area that significantly exceeds that of the in-memory computing array, thus limiting the integration density.

[0044] Furthermore, in practical applications, considering the requirements of residual connections in neural networks, the cache capacity may need to be increased by another 2-3 times. In addition, in the two-dimensional integration method, the memristor array and the cache are interconnected through a bus, which leads to bandwidth limitations. For example, for a 128bit / 200MHz bus, only about three 32×32 arrays can be supported for parallel computing in one operation cycle, which restricts the overall computing efficiency of multi-memristor array chips.

[0045] Furthermore, the inventors of this disclosure have noted that while memristor chips, based on analog resistive switching characteristics, can achieve multiple resistive states to complete analog calculations, they are difficult to perform high-precision calculations due to non-ideal characteristics (such as conductance drift, randomness, or limitations on the number of erase / write cycles). MRAM, based on binary magnetic tunnel junctions, while possessing advantages such as stability and unlimited erase / write cycles, can only achieve two resistive states, making it suitable for high-precision calculations but not for high-performance matrix calculations. Therefore, how to construct a hybrid precision high-performance chip has become an urgent problem to be solved.

[0046] At least one embodiment of this disclosure provides a data processing apparatus and a method for preparing the data processing apparatus.

[0047] The data processing device includes a logic processing layer, an in-memory computing layer, and a memory array layer. The logic processing layer, in-memory computing layer, and memory array layer are at least partially stacked. The logic processing layer is configured to perform logic operations and / or control processing. The in-memory computing layer is configured to perform neural network operations on received data. The memory array layer is configured to store data for the in-memory computing layer. The memory array layer includes a memory array comprising multiple memory cells arranged in multiple rows and columns. Each memory cell includes a transistor and a magnetic random access memory device electrically connected to the transistor. This data processing device integrates in-memory computing and back-end compatible transistor technologies, and in at least one embodiment, it can also be used to implement mixed-precision computing, breaking through the von Neumann bottleneck, significantly improving data processing efficiency and integration, and achieving a chip design that combines high computing power and versatility. This data processing device can also be, for example, a chip, semiconductor device, or integrated circuit device employing three-dimensional integration technology; the embodiments disclosed herein are not limited in this regard.

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, this disclosure is not limited to these specific embodiments.

[0049] Figure 5 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure.

[0050] In some embodiments of this disclosure, as shown in FIG5, the data processing apparatus may include a logic processing layer, an in-memory computing layer, and a storage array layer. The logic processing layer, the in-memory computing layer, and the storage array layer are at least partially stacked. The logic processing layer is configured to perform logical operations and / or control processing, the in-memory computing layer is configured to perform neural network operations on the received data, and the storage array layer is configured to store data for the in-memory computing layer.

[0051] For example, the logic processing layer can perform operations such as combining, comparing, and filtering on data from the in-memory computing layer, the storage array layer, or other input sources to generate new logic signals or data streams to support the corresponding data processing tasks.

[0052] For example, data and / or control signals can be transmitted between the logic processing layer, the memory array layer, and the in-memory computing layer through interlayer metal interconnects.

[0053] For example, the in-memory computing layer can perform neural network operations such as matrix multiplication on data received from external input or provided by the memory array layer, through the in-memory computing array (e.g., memristors) included within the in-memory computing layer. It can also perform operations such as convolution, pooling, and activation functions as needed. For example, refer to the description of the working principle of the in-memory computing array in the foregoing embodiments; it will not be repeated here. Compared to the mode of retrieving data from the in-memory layer and then sending it to the processor for computation, the in-memory computing layer can significantly reduce data transfer overhead, thereby greatly improving computational efficiency, and is particularly suitable for large-scale parallel computing scenarios.

[0054] For example, the in-memory computing layer may include at least one in-memory computing array, which includes at least one memristor array. The memristor array may include multiple memristor cells arranged in multiple rows and columns, and each memristor cell includes a memristor and a switching element (e.g., a transistor).

[0055] For example, the material structure of at least one of the memristors may include: TiN / HfAlO x / TaO x / TiN or TiN / HfO2 / TaO x / TiN or TiN / HfO2 / TiN or TiN / HfZrO x / TaO x / TiN or TiN / HfAlZrO x / TaO x / TiN or TiN / SiO2 / TiN or TiN / HfO x / TaO x The embodiments of this disclosure do not limit the use of layered structures such as TiN. It should be noted that in the embodiments of this disclosure, X is not necessarily an integer, and the metal oxides can have different oxygen contents or oxygen ratios. For example, the oxygen content in each layer can be determined based on the amount of oxygen introduced during the manufacturing process. For example, the actual manufacturing process may include metal oxides with variable oxygen contents, such as a mixture of Ta2O5 and TaO, etc., and the embodiments of this disclosure do not limit this.

[0056] For example, the storage array layer can cache the data used by the in-memory computing layer.

[0057] For example, a memory array layer may include a memory array that may include multiple memory cells arranged in multiple rows and columns, each of the multiple memory cells may include a transistor and a magnetic random access memory (MRAM) device electrically connected to the transistor.

[0058] For example, a transistor can be configured to perform access control. By applying an appropriate control voltage signal to the gate of the transistor, the transistor can be precisely turned on or off, thereby performing operations on the connected MRAM memory device to read, write, or erase stored data.

[0059] For example, the transistor may include at least one of carbon nanotube (CNT) transistors, indium oxide transistors, or low-temperature polycrystalline silicon (LTPS) transistors, and the embodiments disclosed herein are not limited thereto.

[0060] For example, indium oxide transistors can include IGZO transistors, IGO transistors, or In2O3 transistors.

[0061] For example, each of the multiple storage units may include a 2T1M storage unit. The specific details of the 2T1M storage unit can be found in the description of the foregoing embodiments, and will not be repeated here.

[0062] For example, multiple 2T1M storage cells arranged in multiple rows and columns can form a storage array, thereby forming a storage array layer.

[0063] For example, magnetic random access memory devices may include spin-transfer torque magnetic random access memory devices (STT-MRAM) or spin-orbit torque magnetic random access memory devices (SOT-MRAM), and the embodiments disclosed herein are not limited thereto. For a description of spin-transfer torque magnetic random access memory devices and spin-orbit torque magnetic random access memory devices, please refer to the descriptions of STT-MRAM and SOT-MRAM in the foregoing embodiments, and will not be repeated here.

[0064] The storage array layer can quickly and reliably store neural network model parameters, training data, or intermediate calculation results in the in-memory computing layer under the premise of high density and low power consumption, providing corresponding data storage support for the in-memory computing layer.

[0065] In some embodiments of this disclosure, the magnetic random access storage device may include a first electrode layer, a free layer, a barrier layer (i.e., a tunneling layer), a pinning layer, and a second electrode layer stacked sequentially.

[0066] For example, the first electrode layer can be a metal with a strong spin-orbit coupling effect (such as Pt, W, or Ta, or an alloy material). The thickness of the first electrode layer can be, for example, 0–6 nm.

[0067] For example, a free layer may include an antiferromagnetic layer and a ferromagnetic layer stacked sequentially (i.e., an antiferromagnetic / ferromagnetic exchange-coupled layer).

[0068] For example, the antiferromagnetic layer in the free layer can also be used directly as the first electrode of the magnetic random access memory device.

[0069] For example, the material of the antiferromagnetic layer in the free layer may include collinear antiferromagnetic materials (e.g., Mn2Au), non-collinear antiferromagnetic materials (e.g., IrMn3, PtMn3, or Mn3Sn), or spin-splitting antiferromagnetic materials (e.g., RuO2, Mn5Si3), etc., and the embodiments of this disclosure are not limited thereto. The film thickness of the antiferromagnetic layer in the free layer may, for example, be 4-8 nm.

[0070] For example, the material of the ferromagnetic layer in the free layer may include CoFeB or Co materials, etc., and the embodiments of this disclosure are not limited thereto. The film thickness of the ferromagnetic layer in the free layer may be, for example, 0.8-1.4 nm, to obtain perpendicular magnetic anisotropy, that is, the easy magnetization direction is perpendicular or approximately perpendicular to the film surface.

[0071] For free layers, the antiferromagnetic layer exhibits zero magnetic moment due to the opposite alignment of adjacent magnetic moments. The magnetization direction of the antiferromagnetic layer is extremely stable and not easily altered by external influences. The magnetic moments within the ferromagnetic layer can align in the same direction, forming a net magnetic moment. The magnetization direction of the ferromagnetic layer can be modulated by external stimuli (such as electric current or magnetic field).

[0072] Because the antiferromagnetic layer is in close contact with the ferromagnetic layer, an exchange coupling occurs between them, which is a direct magnetic interaction between adjacent magnetic moments. This interaction can cause the magnetization direction of the ferromagnetic layer to be pinned to a specific direction by the antiferromagnetic moment, generating an exchange bias magnetic field inside even in the absence of an external magnetic field.

[0073] When there is no current or magnetic field, the magnetization direction of the free layer can be stabilized in a specific state due to the constraint of the pinned layer (with a fixed magnetization direction) and the influence of the exchange bias magnetic field provided by the antiferromagnetic layer / ferromagnetic layer. For example, it can store a binary bit ("0" or "1").

[0074] Because the exchange bias magnetic field is generated within the free layer, the symmetry of the spin-orbit torque (SOT) magnetization reversal is broken. When a current is applied in a specific direction, the spin-orbit torque (SOT) generated by the current can more effectively drive the vertical magnetization direction of the ferromagnetic layer to reverse along that specific direction, rather than the aimless reversal that might occur without bias. This allows the magnetization reversal process of the free layer to be directionally controlled by the current direction, without relying on an external magnetic field.

[0075] During data writing, a current in a specific direction is applied to the first electrode layer. As the current flows through the first electrode layer, the strong spin-orbit coupling effect in the metal electrode material generates the SOT effect. The SOT effect produces an effective torque within the ferromagnetic layer, acting on the magnetization vector and causing it to rotate. Due to the presence of the exchange bias magnetic field, the current only needs to overcome the coercivity of the ferromagnetic layer itself (i.e., the minimum energy required to maintain the magnetization state) to directionally flip the magnetization direction from one stable state to another, thus completing the data writing process.

[0076] When performing data reading operations, the magnetization state can be determined by measuring the change in tunneling resistance between the free layer and the pinned layer. When the magnetization directions of the two layers are parallel (in the same direction), the tunneling resistance is low, which can indicate that the stored binary bit is "0"; when the magnetization directions of the two layers are antiparallel (out of the same direction), the tunneling resistance is high, which can indicate that the stored binary bit is "1".

[0077] By introducing an antiferromagnetic / ferromagnetic exchange coupling layer, the free layer obtains a strong in-plane exchange bias magnetic field, which enables directional magnetization reversal to be achieved solely by current in the absence of an external magnetic field. This improves the operational efficiency of data storage, reduces power consumption, and enhances the adaptability of MRAM in specific application environments.

[0078] For example, the material of the barrier layer can be an insulating layer, such as MgO, and the film thickness of the barrier layer can be 1-2 nm.

[0079] For example, the pinning layer may include an artificial antiferromagnetic structure. The pinning layer may include a ferromagnetic layer, a non-magnetic metal layer, a ferromagnetic layer, and an antiferromagnetic layer stacked sequentially.

[0080] For example, the material of the ferromagnetic layer in the pinning layer may include CoFeB or Co materials, etc., and the embodiments of this disclosure are not limited thereto. The film thickness of the ferromagnetic layer in the pinning layer may be, for example, 0.8-1.4 nm.

[0081] For example, the material of the antiferromagnetic layer in the pinning layer may include IrMn3 or PtMn3, etc., and the embodiments of this disclosure are not limited thereto. The film thickness of the antiferromagnetic layer in the pinning layer may be, for example, 5-10 nm.

[0082] For example, the material of the non-magnetic metal layer in the pinning layer may include Ru or Ta, etc., and the embodiments of this disclosure are not limited thereto. The film thickness of the non-magnetic metal layer in the pinning layer may be, for example, 0.4-1.5 nm.

[0083] Furthermore, the easy magnetization axis of the free layer and the pinned layer can be perpendicular or approximately perpendicular to the film surface of the free layer and the pinned layer.

[0084] For example, the material of the second electrode can include metallic materials such as Pt, W, or Ta, or alloy materials. The film thickness of the second electrode can be, for example, 5-20 nm.

[0085] It should be noted that, considering mass production process errors, the actual film thickness may have an error of 5-10 nm. For example, the film thickness of the second electrode can also range from 1-30 nm.

[0086] In some embodiments of this disclosure, the magnetic random access storage device includes a magnetic tunnel junction (MTJ).

[0087] A magnetic tunnel junction can consist of a series of stacked ferromagnetic layers, an insulating layer, and another ferromagnetic layer. An insulating layer (e.g., a tunnel barrier layer) can be sandwiched between two ferromagnetic layers (e.g., one ferromagnetic layer with a fixed magnetization direction, and the other with a switchable magnetization direction). When the magnetization directions of the two ferromagnetic layers are parallel, electrons can efficiently tunnel through the insulating layer, resulting in a low-resistance state. When the magnetization directions of the two ferromagnetic layers are antiparallel, the tunneling effect weakens, resulting in a high-resistance state. This change in resistance can correspond to the storage of binary data "0" and "1".

[0088] Furthermore, the inventors of this disclosure have noted that the surface roughness of the in-memory computing layer can affect the performance of magnetic random access memory (MRAM) devices. A rough surface of the in-memory computing layer can lead to structural inhomogeneities in the magnetic tunnel junction (MTJ), affecting the precise control of electron tunneling efficiency, magnetic anisotropy, or spin-orbit torque effects, thereby impacting key performance indicators of MRAM devices such as stability, read / write speed, power consumption, and data retention capabilities.

[0089] Therefore, when selecting the location of the magnetic tunnel junction of MRAM, a location with a root mean square roughness (RMS) of less than or equal to 1 nanometer (or 0.2 nanometer) on the surface of the memory computing layer can be selected to ensure the high-performance operation of the MRAM magnetic tunnel junction.

[0090] For example, the memristors in the in-memory computing layer can be placed in offset positions from the magnetic tunnel junctions of the MRAM.

[0091] In at least one embodiment of this disclosure, staggering the magnetic tunnel junctions of the memristor and MRAM helps avoid mutual process interference, ensuring high-quality manufacturing of each device. It also ensures that the magnetic tunnel junction is positioned within a specific region that meets its surface roughness requirements, while the memristor can be integrated into a suitable region based on its surface quality requirements. Furthermore, since both the memristor and MRAM generate electric and magnetic fields during operation, although both are non-volatile, their electrical behavior may interfere with each other if they are too close, leading to read / write errors, signal crosstalk, or increased power consumption. Therefore, staggering the magnetic tunnel junctions of the memristor and MRAM avoids direct electrical coupling, maintaining the independence of their read / write operations and data integrity. Because the memristor and MRAM have different heat dissipation requirements, they may generate different heat distributions during data read / write operations. Staggering their positions also helps optimize thermal management, prevent the formation of localized hot spots, and maintain the stability and reliability of the data processing device. Furthermore, staggering the magnetic tunnel junctions of memristors and MRAMs allows for more flexible layout of the data processing device, enabling space to be allocated rationally according to the needs of each circuit layer and process limitations, which helps to improve the integration density of the data processing device.

[0092] Figure 6 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure. As shown in Figure 6, in some embodiments of the present disclosure, the data processing apparatus 100 may include a logic processing layer 101, an in-memory computing layer 102, and a memory array layer 103. The logic processing layer 101, the in-memory computing layer 102, and the memory array layer 103 are at least partially stacked.

[0093] For example, the logic processing layer 101 can be disposed on the silicon substrate, the in-memory computing layer 102 can be disposed on the side of the logic processing layer 101 away from the silicon substrate, and the memory array layer 103 can be disposed on the side of the in-memory computing layer 102 away from the silicon substrate.

[0094] For example, the data processing device 100 also includes an interlayer medium layer disposed between the logic processing layer 101, the in-memory computing layer 102 and the storage array layer 103. The interlayer medium layer includes a plurality of vias, and the logic processing layer 101, the in-memory computing layer 102 and the storage array layer 103 communicate through the plurality of vias.

[0095] For example, an interlayer medium 1 is provided between the logic processing layer 101 and the in-memory computing layer 102, and an interlayer medium 2 is provided between the in-memory computing layer 102 and the storage array layer 103.

[0096] For example, the logic processing layer 101 can be configured to perform logic operations and / or control processing, the in-memory computing layer 102 can be configured to perform neural network operations on the received data, and the memory array layer 103 can be configured to store data for the in-memory computing layer.

[0097] For example, the logic processing layer 101 can perform operations such as combining, comparing, and filtering on data from the in-memory computing layer 102, the storage array layer 103, or other input sources to generate new logic signals or data streams to support the corresponding data processing tasks.

[0098] For example, the in-memory computing layer 102 may include at least one in-memory computing array, each of which includes at least one memristor array, and the memristor array may include multiple memristors arranged in multiple rows and columns.

[0099] For example, the memory array layer 103 may include a memory array that may include multiple memory cells arranged in multiple rows and columns, each of the multiple memory cells may include a transistor and a magnetic random access memory device electrically connected to the transistor.

[0100] For example, transistors and magnetic random access memory devices can be arranged in a stacked manner in the memory array layer 103, or they can be arranged in a planar manner in the memory array layer 103.

[0101] The embodiments of this disclosure, through the stacked design of the logic processing layer 101, the in-memory computing layer 102, and the storage array layer 103, not only help to reduce the size of the data processing device and improve the integration, but also reduce the data transmission distance and latency between each circuit layer and improve the data processing speed.

[0102] At least one embodiment of this disclosure also provides a method for fabricating a data processing device. The method includes: fabricating an in-memory computing layer using a semiconductor fabrication process and fabricating a memory array layer at least partially stacked with the in-memory computing layer, wherein the memory array layer includes a memory array, the memory array including a plurality of memory cells arranged in multiple rows and columns, each of the plurality of memory cells including a transistor and a magnetic random access memory device electrically connected to the transistor.

[0103] For example, an in-memory computing layer is fabricated using semiconductor fabrication technology, and a memory array layer is fabricated using semiconductor fabrication technology, wherein the memory array layer and the in-memory computing layer are at least partially stacked.

[0104] For example, an in-memory computing array in an in-memory computing layer is fabricated using semiconductor fabrication technology. Each in-memory computing array includes at least one memristor array, and the memristor array includes multiple memristors arranged in multiple rows and columns.

[0105] For example, in the process of fabricating the memory array in the memory array layer using semiconductor fabrication technology, transistors can be fabricated first and then magnetic random access memory devices can be fabricated, or magnetic random access memory devices can be fabricated first and then transistors can be fabricated. The embodiments of this disclosure do not limit the order of fabrication of magnetic random access memory devices and transistors.

[0106] For fabricating transistors, a low-temperature back-end transistor fabrication process can be used, for example. Here, the fabrication temperature can be, for example, a low-temperature process of 300 degrees Celsius or less (or 400 degrees Celsius). The transistor can, for example, include at least one of carbon nanotube transistors, indium oxide transistors, or low-temperature polycrystalline silicon transistors.

[0107] In some embodiments of this disclosure, the method for fabricating the data processing device further includes providing a silicon substrate, fabricating a logic processing layer on the silicon substrate using a semiconductor fabrication process, forming an in-memory computing layer on the side of the logic processing layer away from the silicon substrate, and forming a memory array layer on the side of the in-memory computing layer away from the silicon substrate.

[0108] For example, the logic processing layer can be fabricated using CMOS logic circuit fabrication technology (or silicon-based CMOS technology) to manufacture CMOS transistors and other components to create the logic processing circuit.

[0109] In some embodiments of this disclosure, fabricating a magnetic random access memory (MRMH) device in a memory array layer may include fabricating a mask to define a patterned region of the MRMH device and using the mask to fabricate a magnetic tunnel junction.

[0110] For example, a mask may include a photoresist mask or a hard mask.

[0111] For example, the material of the mask can include metal or an insulating medium.

[0112] To prepare a hard mask, for example, a hard mask can be prepared using a double-layer photoresist through photolithography, deposition of metal or insulating medium, and a stripping process to define the patterned area of ​​the magnetic random access memory device.

[0113] For example, a two-layer adhesive process can be used to define the pattern of the magnetic tunnel junction region. Exemplarily, a base adhesive and a top adhesive can be sequentially coated on the substrate where the magnetic tunnel junction region is prepared. By controlling the exposure and development process, the base adhesive is patterned into a predetermined shape, wherein the top adhesive, after processing, can form a partially suspended "eaves" structure above the edge of the pattern defined by the base adhesive.

[0114] For example, based on this "eaves" double-layer adhesive structure, an insulating medium can be deposited, and then the photoresist can be dissolved and stripped away by soaking in a photoresist remover. The insulating medium attached above the photoresist can also be stripped away, thereby creating interconnects for a magnetic tunnel junction.

[0115] It should be noted that, in the embodiments of this disclosure, the undercoat refers to the photoresist first coated on the substrate of the magnetic tunnel junction region, and the topcoat refers to the photoresist coated on top of the undercoat.

[0116] For the preparation of photoresist masks, various micro- and nano-sized photoresist masks can be prepared by methods such as ultraviolet lithography, direct write lithography (DWL), electron beam lithography (EBL), and ion beam lithography (IBL).

[0117] For example, a double-layer photoresist mask can also be fabricated using a double-layer photoresist process, where a top resist is applied to the substrate in the magnetic tunnel junction region to form a double-layer photoresist mask with an upper suspended layer.

[0118] For fabricating magnetic tunnel junctions using masks, for example, a dry etching process can be used to etch areas outside the patterned regions of the magnetic random access memory (MRMemory) device to preserve the patterned regions of the MRMemory device.

[0119] For example, the dry etching process used in the embodiments of this disclosure may include: ion beam etching (IBE), atomic layer etching (ALE), reactive ion etching (RIE), or inductively coupled plasma etching (ICP), etc. The embodiments of this disclosure do not limit the specific dry etching process used.

[0120] It is important to note that during the fabrication of magnetic tunnel junctions using ion beam etching (IBE), if a perpendicular etching method is employed, meaning the ion beam is perpendicular (or nearly perpendicular) to the surface of the magnetic tunnel junction, numerous protruding "burrs" may appear at the top edge of the fabricated magnetic tunnel junction. These "burrs" can negatively impact subsequent processes and device performance. Therefore, a variable-angle etching method can be used. This involves etching the magnetic tunnel junction using the perpendicular angular component, followed by etching the sidewalls using other angular components (i.e., sidewall angular component etching). This reduces or even eliminates the "burr" phenomenon and also mitigates the secondary sputtering effect caused by ion beam etching, thereby improving the flatness, insulation, and magnetoresistance change rate of the magnetic tunnel junction and preventing device failure.

[0121] Figure 7 illustrates a schematic diagram of a method for fabricating a magnetic random access memory device according to at least one embodiment of this disclosure. As shown in Figure 7, the magnetic tunnel junction can first be etched using a vertical angular component, for example, a larger angle can be used for etching (e.g., the ion beam is at a 60-degree angle to the surface of the magnetic tunnel junction). This can quickly remove most of the material to be etched, but this step may still produce a certain amount of burrs.

[0122] Next, sidewall angular component etching is performed, for example, etching at a smaller angle (e.g., the ion beam is at a 30-degree angle to the magnetic tunnel junction surface). In this step, the ion beam bombardment of the sidewalls is more effective, which can specifically remove the burrs generated during the previous etching process, while further smoothing the sidewalls.

[0123] In addition, attention should be paid to the circulation and cooling issues during the etching process. For example, after etching at each of the different angles for a certain period of time (e.g., 1 minute), the etching can be paused and the sample allowed to cool for a period of time (e.g., 3 minutes). Cooling can help reduce the probability of secondary sputtering of material due to thermal effects during the etching process, and it is also beneficial to the stability of the sample structure and prevents morphology deterioration caused by overheating.

[0124] For example, the etching steps at the two angles shown in Figure 7 can be repeated several times to gradually optimize the surface quality and sidewall morphology of the magnetic tunnel junction until the desired etching effect is achieved.

[0125] In at least one embodiment of this disclosure, variable-angle etching technology can effectively reduce or even eliminate burrs at the top edge of the magnetic tunnel junction, improving the device's flatness, insulation, and magnetoresistance change rate, thereby enhancing the overall device performance and yield. By controlling the ion beam incident angle and etching steps, the etching characteristics of the ion beam at different angles and its effect on removing burrs are cleverly utilized, achieving precise control over the magnetic tunnel junction fabrication process.

[0126] In some embodiments of this disclosure, fabricating a magnetic random access memory device further includes: selecting a region on the surface of the internal computing layer with a root mean square roughness of less than 1 nm or 0.2 nm to arrange a magnetic tunnel junction, and placing the magnetic tunnel junction at a position offset from the memristor.

[0127] Here, when preparing the in-memory computing layer, a polishing operation (e.g., chemical mechanical polishing (CMP)) is required. Through the synergistic effect of chemical etching and mechanical polishing, the undulations of the in-memory computing layer are removed to ensure extremely low surface roughness (e.g., root mean square roughness below 1 nm, or even below 0.2 nm).

[0128] In the process of fabricating magnetic random access memory devices, the methods for arranging the specific locations of magnetic tunnel junctions and their beneficial effects can be referred to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0129] The following describes the fabrication method of a data processing device formed by stacking RRAM and SOT-MRAM as an example, including the following steps (1) to (5):

[0130] (1) Provide a silicon substrate.

[0131] (2) Fabricate logic circuit layers on silicon substrates.

[0132] (3) Prepare an in-memory computing layer on the logic circuit layer.

[0133] (4) Fabricate MRAM memory devices on the in-memory computing layer.

[0134] (5) Fabricate transistors for MRAM memory devices on the in-memory computing layer.

[0135] For example, CMOS transistors and other components can be fabricated on a silicon substrate using CMOS logic circuit fabrication technology (or silicon-based CMOS technology) to prepare logic processing circuits.

[0136] For example, the RRAM in-memory computing layer can be fabricated using a low-temperature (e.g., less than or equal to 400 degrees Celsius) back-end integration process. For instance, an exemplary method for fabricating a memory computing circuit layer may include the following steps:

[0137] (a) Deposit a stack of “lower electrode layer / resistive switching layer / thermal enhancement layer / upper electrode layer”.

[0138] (b) The stack is selectively etched using photolithography and dry etching processes to achieve the patterning of the resistive random access memory device.

[0139] (c) Deposit a passivation layer (such as a SiO2 thin film) using plasma-enhanced chemical vapor deposition.

[0140] (d) Use photolithography, dry etching or wet etching processes to etch the passivation layer and form interconnect connection point openings.

[0141] (e) A layer of tungsten (W) is deposited by electroplating, and then chemical mechanical polishing is used to grind the W clean except for the SiO2 pores (forming metal vias).

[0142] (f) Deposit metallic Al using physical vapor deposition.

[0143] (g) Using photolithography and dry etching processes, Al is selectively etched to form Al metal interconnects.

[0144] Figure 8 shows a schematic flowchart of a method for fabricating a magnetoresistive random access memory (MRAM) cell according to at least one embodiment of the present disclosure. As shown in Figure 8, the method for fabricating the MRAM memory device may include steps S210-S250.

[0145] (a) S210, to prepare SOT-MRAM stack.

[0146] For example, a multilayer thin film stack consisting of an insulating dielectric layer, a first electrode layer, a free layer, a barrier layer, a pinned layer, and a second electrode layer can be deposited sequentially using techniques such as magnetron sputtering or molecular beam epitaxy (MBE).

[0147] The material of the first electrode layer can include metals with strong spin-orbit coupling effects (such as Pt, W, Ta, or alloys), and the film thickness of the first electrode layer can be 0-6 nm; for example, the antiferromagnetic layer in the free layer can be used as the first electrode layer.

[0148] The free layer may comprise an exchange-coupled layer formed by sequentially stacked antiferromagnetic and ferromagnetic layers. The ferromagnetic layer material may be CoFeB or Co, and the film thickness of the ferromagnetic layer may be 0.8-1.4 nm. The material of the antiferromagnetic layer in the free layer may include collinear antiferromagnetic materials (e.g., Mn2Au), non-collinear antiferromagnetic materials (e.g., IrMn3, PtMn3, or Mn3Sn), or spin-splitting antiferromagnetic materials (e.g., RuO2, Mn5Si3), etc. The film thickness of the antiferromagnetic layer in the free layer may, for example, be 4-8 nm.

[0149] The barrier layer can be made of an insulating material, such as MgO. The thickness of the barrier layer can be 1-2 nm.

[0150] The pinning layer may include an artificial antiferromagnetic structure. The pinning layer may include a ferromagnetic layer, a non-magnetic metal layer, a ferromagnetic layer, and an antiferromagnetic layer stacked sequentially. The material of the ferromagnetic layer in the pinning layer may include CoFeB or Co, etc. The film thickness of the ferromagnetic layer in the pinning layer may be, for example, 0.8-1.4 nm. The material of the antiferromagnetic layer in the pinning layer may include IrMn3 or PtMn3, etc. The film thickness of the antiferromagnetic layer in the pinning layer may be, for example, 5-10 nm. The material of the non-magnetic metal layer in the pinning layer may include Ru or Ta, etc. The film thickness of the non-magnetic metal layer in the pinning layer may be, for example, 0.4-1.5 nm. The material of the second electrode may include metals such as Pt, W, or Ta, or alloys. The film thickness of the second electrode may be, for example, 5-20 nm.

[0151] (b) S220, to prepare SOT-MRAM magnetic tunnel junction.

[0152] For example, various micro- and nano-sized photoresist masks can be fabricated using processes such as ultraviolet lithography, laser direct writing, electron beam lithography, and ion beam lithography. Alternatively, a hard mask can be fabricated using a double-layer photoresist layer through photolithography, deposition, and lift-off processes to define the patterned regions of the MRAM. Another approach is to use a double-layer photoresist layer process to fabricate the photoresist mask, where the top resist forms a partially suspended magnetic tunnel junction structure on the bottom resist layer. Then, dry etching processes such as ion beam etching, atomic layer etching, reactive ion etching, or inductively coupled plasma etching are used to etch away the areas outside the MRAM pattern, preserving the MRAM patterned regions. It is important to note that if a photoresist mask is used to fabricate the magnetic tunnel junction, the photoresist mask must be removed at the end.

[0153] (c)S230, to prepare an insulating layer.

[0154] For example, methods such as magnetron sputtering, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition can be used to deposit an insulating layer (e.g., silicon oxide SiO2 or aluminum oxide Al2O3 thin film) on the entire surface of the device.

[0155] (d)S240, fabricating interconnect holes.

[0156] For example, photolithography can be used to define the opening area pattern of the second electrode and the first electrode, and then dry etching or wet etching can be used to etch the insulating layer to complete the opening, expose the connection hole of the two first electrodes and the first electrode, form the interconnect connection point, and finally remove the photoresist.

[0157] In some embodiments of this disclosure, it is also possible to choose to deposit an insulating layer directly without removing the photoresist mask during the fabrication of the SOT-MRAM magnetic tunnel junction, for example after photolithography and etching processes, and then peel off the photoresist mask and fabricate interconnects through a corresponding photoresist removal process.

[0158] (e)S250, fabrication of interconnect electrodes and wires.

[0159] For example, a conductive layer, such as tungsten (W), can be deposited using electroplating or chemical vapor deposition. Then, chemical mechanical polishing (CMP) is used for planarization, cleaning away the conductive layer (e.g., tungsten W) outside the opening, leaving only the conductive layer inside the opening to form a metal via. Next, physical vapor deposition (PVD) is used to deposit a conductive layer, such as aluminum (Al). Finally, dry etching processes such as photolithography or integrated circuit etching (ICP) are used to selectively etch the conductive layer (Al) to form conductive interconnects.

[0160] It is important to note that when fabricating interconnect electrodes and wires, a double-layer photoresist lithography process can be used to define the wire region pattern first, enabling conductive interconnection between the MRAM second and first electrodes and external devices or circuits. Because this photolithography uses a double-layer photoresist process, the top resist forms a double-layer photoresist structure with suspended edges on the bottom resist of the magnetic tunnel junction. Subsequently, a conductive layer (such as gold (Au), platinum (Pt), palladium (Pd), aluminum (Al), copper (Cu), tungsten (W), or titanium nitride (TiN)) is deposited using electron beam evaporation or magnetron sputtering. If the conductive layer has poor adhesion, an adhesion layer (such as titanium (Ti), chromium (Cr), or tantalum (Ta)) can be deposited first, followed by the conductive layer. The thickness of the deposited conductive layer can, for example, be less than half the thickness of the bottom resist. Then, the conductive layer regions supported by the photoresist can be removed in acetone or other resist-removing solutions, retaining the conductive layer pattern without photoresist. Furthermore, this step can be aided by prolonged immersion, ultrasonic treatment, or heating.

[0161] (f) Annealing operation.

[0162] For example, after the SOT-MRAM multilayer thin film deposition is completed, an annealing operation is required to crystallize the MgO barrier layer, improve the interface quality between the ferromagnetic layer and the barrier layer, and thus increase the magnetoresistance of the tunnel junction. This annealing operation can be performed, for example, in a high-temperature combined magnetic field environment. The annealing temperature can be set to, for example, 200-350 degrees Celsius, and the magnetic field direction can be set to the easy axis direction of the SOT-MRAM free layer, for example, perpendicular (or approximately perpendicular) to the thin film surface. The magnetic field strength can be set, for example, to 500-10000 Oersted.

[0163] For example, the transistor used for MRAM in step (5) above can be fabricated using a low-temperature (less than or equal to 400 degrees Celsius) back-end integration method. Here, the channel material of the transistor can include semiconductor channel materials such as carbon nanotubes, indium gallium zinc oxide, low-temperature polycrystalline silicon, and indium oxide (In2O3).

[0164] The following description uses the fabrication method of carbon nanotube transistors as an example to illustrate the method for fabricating downstream transistors. For example, the fabrication method of carbon nanotube transistors may include the following steps:

[0165] (a) A metal target Pd is deposited using photolithography and electron beam evaporation deposition, and then stripped to form a pattern, which serves as the back gate structure of a carbon nanotube transistor.

[0166] (b) An Al2O3 and HfO2 insulating layer is grown using atomic layer deposition technology as a gate oxide dielectric.

[0167] (c) Using photolithography and wet etching processes, selective etching of Al2O3 and HfO2 regions is used to achieve gate oxide openings.

[0168] (d) A layer of carbon nanotubes is deposited using a wet transfer process.

[0169] (e) Photolithography is used to deposit 80nm Pd by electron beam evaporation, and then the pattern is stripped to form the source and drain electrodes of the carbon nanotube transistor.

[0170] (f) Photolithography and oxygen plasma etching processes are used to selectively etch carbon nanotubes to isolate different devices.

[0171] (g) Atomic layer deposition was used to grow 45nm Al2O3 as a passivation layer.

[0172] (h) Using photolithography and wet etching processes, Al2O3 is selectively etched to form electrode contact holes.

[0173] (i) A metal interconnect pattern is formed by using a subsequent passivation process and a metal interconnect process.

[0174] Figure 9 shows a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure. As shown in Figure 9, the electronic device 300 includes a data processing device 400.

[0175] For example, the data processing device 400 can be any of the data processing device devices provided in the above embodiments. For example, the electronic device 300 may further include other devices, such as a central processing unit (CPU), a data bus, memory, etc. The electronic device 300 can be a signal processing device, a computing device, etc., and can be used as a controller, terminal device, or server device, etc.

[0176] In addition to the illustrative descriptions above, the following points also need to be noted in this disclosure:

[0177] (1) The accompanying drawings of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0178] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0179] (3) It should be understood that in the embodiments of this disclosure, the order of the above steps does not mean the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A data processing apparatus comprising: a logic processing layer, an in-memory computing layer, and a storage array layer, wherein the logic processing layer, the in-memory computing layer, and the storage array layer are at least partially stacked; the logic processing layer is configured to perform logical operations and / or control processing; the in-memory computing layer is configured to perform neural network operations on received data, and the storage array layer is configured to store data for the in-memory computing layer; the storage array layer comprises a storage array, the storage array comprises a plurality of storage units arranged in multiple rows and multiple columns, each of the plurality of storage units comprises a transistor and a magnetic random access memory device electrically connected to the transistor.

2. The data processing apparatus of claim 1, wherein, The magnetic random access memory device comprises a first electrode layer, a free layer, a barrier layer, a pinned layer, and a second electrode layer which are sequentially stacked.

3. The data processing apparatus of claim 2, wherein, The free layer comprises an antiferromagnetic layer and a ferromagnetic layer which are sequentially stacked.

4. The data processing apparatus according to any one of claims 1-3, wherein, The in-memory computing layer comprises at least one in-memory computing array, each of the in-memory computing array comprises at least one memristor array, the memristor array comprises a plurality of memristors arranged in multiple rows and multiple columns; The magnetic random access memory device comprises a magnetic tunnel junction, and the magnetic tunnel junction is placed away from the memristor.

5. The data processing apparatus according to any one of claims 1-4, wherein, The transistor comprises at least one of a carbon nanotube transistor, an indium-based oxide transistor, or a low-temperature polysilicon transistor.

6. The data processing apparatus according to any one of claims 1-5, wherein, The magnetic random access memory device comprises a spin transfer torque magnetic random access memory device or a spin orbit torque magnetic random access memory device.

7. An electronic device comprising the data processing device of any one of claims 1-6.

8. A method for manufacturing a data processing device, comprising: manufacturing an in-memory computing layer and a storage array layer which is at least partially stacked with the in-memory computing layer using a semiconductor manufacturing process, wherein the in-memory computing layer is configured to perform neural network operations on received data, and the storage array layer is configured to store data for the in-memory computing layer; the storage array layer comprises a storage array, the storage array comprises a plurality of storage units arranged in multiple rows and multiple columns, each of the plurality of storage units comprises a transistor and a magnetic random access memory device electrically connected to the transistor.

9. The production method according to claim 8, wherein The manufacturing of the magnetic random access memory device comprises: manufacturing a mask to define a patterned region of the magnetic random access memory device, wherein the mask comprises a photoresist mask or a hard mask; manufacturing a magnetic tunnel junction using the mask.

10. The production method according to claim 9, wherein The manufacturing of the mask to define the patterned region of the magnetic random access memory device comprises: defining a pattern of the magnetic tunnel junction region using a bilayer resist process.

11. The production method according to claim 9 or 10, wherein The manufacturing of the magnetic tunnel junction using the mask comprises: performing etching on other regions outside the patterned region of the magnetic random access memory device to retain the patterned region of the magnetic random access memory device through a dry etching process.

12. The method of making according to any one of claims 8-11, wherein, The in-memory computing layer comprises at least one in-memory computing array, each of the in-memory computing array comprises at least one memristor array, the memristor array comprises a plurality of memristors arranged in multiple rows and multiple columns; The manufacturing of the magnetic random access memory device further comprises: selecting a region of the memristor surface with a root mean square roughness less than 1 nm or 0.2 nm to arrange a magnetic tunnel junction, and placing the magnetic tunnel junction away from the memristor.

13. The method of any of claims 8-12, further comprising: providing a silicon substrate; fabricating a logic processing layer on the silicon substrate using semiconductor fabrication processes, wherein the logic processing layer is configured to perform logic operations and / or control processing, the in-memory computing layer is formed on a side of the logic processing layer distal to the silicon substrate, and the memory array layer is formed on a side of the in-memory computing layer distal to the silicon substrate.

Images