Track-and-hold circuit

Abstract

A track-and-hold circuit comprises an input buffer (1) that receives input signals (in+, in-), and emitter followers (2, 3) that switch a track mode and a hold mode in accordance with reference signals (TR, HO). The input buffer (1) is provided with a diode (DL) in which an anode is connected to the same power supply voltage as that of the emitter followers (2, 3) and a cathode is connected to a power supply terminal of the input buffer (1).

Description

Track-and-hold circuit

[0001] The present invention relates to a track-and-hold circuit used in a sampling phase comparator or the like.

[0002] In wireless communications, data transmission and reception requires modulation and demodulation using a frequency mixer, which requires a sine wave signal as a carrier. Large-capacity wireless transmission also requires a wide bandwidth, which effectively requires a higher carrier frequency. A phase-locked loop (PLL) with high frequency purity is often used to generate the sine wave signal used as the carrier, but in the high-frequency range, the frequency multiplication factor becomes large, which causes problems with phase noise performance.

[0003] In order to reduce the in-band phase noise of a PLL, a sampling PLL utilizing subsampling technology has been proposed (see Non-Patent Document 1). FIG. 8 shows the configuration of the PLL disclosed in Non-Patent Document 1. This PLL comprises a reference signal source 100, a sampling phase comparator 101, a low-pass filter (LPF) 102, a voltage-controlled oscillator (VCO) 103, and a frequency divider 104. The reference signal source 100 comprises a crystal oscillator 1000 and a buffer 1001. Unlike conventional PLLs, the PLL shown in FIG. 8 uses a sampling phase comparator 101 in the phase comparison (phase extraction) section, thereby reducing phase noise caused by the phase comparator.

[0004] A sampling circuit such as a track and hold amplifier circuit (THA) can be used as the sampling phase comparator 101. As shown in FIG. 9 , the THA is composed of an input buffer 200, a switch 201 operated by a clock signal CLK, and a hold capacitor 202. The input signal handled by a THA used as a general sampling circuit is a modulated signal, which is a non-periodic signal. On the other hand, the input signal handled by a THA used as a sampling phase comparator is a periodic signal.

[0005] 10 shows the configuration of a switched emitter follower (SEF), which is one of the configurations of a conventional THA (see Non-Patent Document 2). The SEF is composed of an input buffer 300 and emitter followers 301 and 302. The input buffer 300 is connected to a transistor Q １ , Q ２ , Q ９ and resistance R Ｌ１ , R Ｌ２ , R Ｅ１ , R Ｅ２ The emitter follower 301 is composed of a transistor Q ３ , Q ５ , Q ７ , Q １０ and hold capacitance C Ｈ１ The emitter follower 302 is composed of a transistor Q ４ , Q ６ , Q ８ , Q １１ and hold capacitance C Ｈ２ The operation of the SFE in track mode and hold mode will be explained below.

[0006] [In Track Mode] When the signal TR is at a high potential and the signal HO is at a low potential, the SEF shown in FIG. 10 operates in track mode. Ｌ１ and transistor Q １ and resistance R Ｅ１ and a path consisting of a resistor R Ｌ２ and transistor Q ２ and resistance R Ｅ２ The paths consisting of ＢＵＦ A current of / 2 flows through the transistor Q ３ , Q ５ and a path consisting of a transistor Q ４ , Q ６ The paths consisting of ＳＥＦ A current of 100 Ω flows through the transistor Q. ７ , Q ８ Therefore, the DC potential of the output terminals in_SEF+ and in_SEF− of the input buffer 300 (the input terminals of the emitter followers 301 and 302) in_SEF+ and in_SEF− in the track mode is VＣＣ＿ＢＵＦ -R Ｌ ×I ＢＵＦ / 2. ＣＣ＿ＢＵＦ is the power supply voltage of the input buffer 300, R Ｌ is the resistance R Ｌ１ , R Ｌ２ The value of the transistor Q acting as a switch ３ , Q ４ As mentioned above, ＳＥＦ Since a current of ３ , Q ４ Base-emitter voltage V ＢＥ This makes the transistor Q １ , Q ２ The signal input to the base of the emitter follower 301 propagates to the output terminals out_SEF+ and out_SEF− of the emitter followers 301 and 302 .

[0007] [Hold Mode] When the signal TR is at a low potential and the signal HO is at a high potential, the SEF shown in FIG. 10 operates in hold mode. Ｌ１ and transistor Q １ and resistance R Ｅ１ and a path consisting of a resistor R Ｌ２ and transistor Q ２ and resistance R Ｅ２ In the same way as in the track mode, the route consisting of ＢＵＦ On the other hand, in the hold mode, a current of 1 / 2 flows through the transistor Q ３ , Q ４ , Q ５ , Q ６ No current flows through the resistor R Ｌ１ and transistor Q ７ and a path consisting of a resistor R Ｌ２ and transistor Q ８ and each path consists of I ＳＥＦ Therefore, the DC potential of the terminals in_SEF+ and in_SEF- in the hold mode is V ＣＣ＿ＢＵＦ -R Ｌ × (I ＢＵＦ / 2+I ＳＥＦ) can be calculated. The DC potential change width of the terminals in_SEF+ and in_SEF- due to switching between the track mode and the hold mode is R Ｌ ×I ＳＥＦ The transistor Q acting as a switch ３ , Q ４ As mentioned above, no current flows through these transistors Q ３ , Q ４ Base-emitter voltage V ＢＥ Therefore, the transistor Q １ , Q ２ The signal input to the base of the emitter follower 301 is not transmitted to the output terminals out_SEF+ and out_SEF- of the emitter follower 302, and the input signal at the moment when the potentials of the signals TR and HO are switched is transmitted to the hold capacitance C Ｈ１ , C Ｈ２ is held by

[0008] In order for the SEF-based sampling phase comparator to operate at high speed, I ＳＥＦ In the circuit shown in FIG. 10, the DC potential V of the terminals in_SEF+ and in_SEF− in the track mode is ＣＣ＿ＢＵＦ -R Ｌ ×I ＢＵＦ / 2 to transistor Q １ , Q ２ Furthermore, the DC potential change width R of the terminals in_SEF+ and in_SEF- due to switching between the track mode and the hold mode is Ｌ ×I ＳＥＦ , transistor Q ３ , Q ４ In order to satisfy both conditions A and B, the power supply voltage V ＣＣ＿ＳＥＦ and the power supply voltage V of the input buffer 300 ＣＣ＿ＢＵＦ It was necessary to use different voltages for each. ＣＣ＿ＢＵＦ is the voltage V ＣＣ＿ＳＥＦ Such a power supply voltage V ＣＣ＿ＳＥＦ , V ＣＣ＿ＢＵＦDue to these conditions, additional external pads and multiple power supplies are required. This results in disadvantages such as an increase in circuit area due to the additional pads, and the increased number of power supply lines causes overlap with signal lines, resulting in poor high-frequency and noise characteristics. In other words, the circuit shown in Figure 10 has issues with reducing area, increasing frequency, and reducing noise.

[0009] As a simple method for solving this problem, as shown in FIG. ＣＣ＿ＳＥＦ and the power supply terminal of the input buffer 300 (resistor R Ｌ１ , R Ｌ２ resistor R Ｍ It is possible to insert a resistor R Ｍ By utilizing the voltage drop due to ＣＣ＿ＳＥＦ Specifically, the voltage V of the power supply terminal can be Ｍ But, V Ｍ =V ＣＣ＿ＢＵＦ =V ＣＣ＿ＳＥＦ -R Ｍ ×I ＢＵＦ Resistance R Ｍ As a result, the DC potential of the terminals in_SEF+ and in_SEF- is V ＣＣ＿ＳＥＦ -R Ｍ ×I ＢＵＦ -R Ｌ ×I ＢＵＦ / 2, and transistor Q １ , Q ２ The optimum bias point is obtained.

[0010] On the other hand, in the hold mode, the DC potential of the terminals in_SEF+ and in_SEF- is V ＣＣ＿ＳＥＦ -R Ｍ × (I ＢＵＦ +I ＳＥＦ )-R Ｌ × (I ＢＵＦ / 2+I ＳＥＦ The DC potential change width of the terminals in_SEF+ and in_SEF- due to switching between the track mode and the hold mode is (R Ｍ +R Ｌ ) × I ＳＥＦ , and compared with the circuit in FIG. Ｍ ×I ＳＥＦTherefore, the transistor Q ３ , Q ４ The base potential of the transistor Q ３ , Q ４ Since the breakdown voltage of the transistor Q ３ , Q ４ Therefore, the resistor R Ｍ It is not possible to solve the problem of the circuit of FIG.

[0011] It is also conceivable to solve the problems of the circuit in Figure 10 by providing a separate power supply circuit within the chip. However, when using high-speed HBTs (Heterojunction Bipolar Transistors) to handle high-frequency signals, it is difficult to realize the power supply circuit because pnp-type transistors cannot be used. Even if the power supply circuit were realized using an HBT process capable of manufacturing pnp-type transistors, problems would arise, such as the mask cost required to manufacture the pnp-type transistor, an increase in area, and considerations regarding the stability of the power supply circuit. For this reason, it is not realistic to solve the problems of the circuit in Figure 10 by using an on-chip power supply circuit.

[0012] X. Gao, et al., “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD / CP Noise is not Multiplied by N2”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 44, no. 12, pp. 3253-3263, Dec. 2009 S. Shahramian, et al., “Design Methodology for a 40-GSamples / s Track and Hold Amplifier in 0.18-μm SiGe BiCMOS Technology”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol.41, no.10, pp.2233-2240, Oct. 2006

[0013] SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a track-and-hold circuit capable of high frequency operation with a single power supply.

[0014] The track-and-hold circuit of the present invention comprises an input buffer configured to receive an input signal, and an emitter follower configured to switch, in response to a reference signal, between a track mode in which a signal that follows the output signal of the input buffer is output, and a hold mode in which the output signal of the input buffer is held and output at the timing of switching from the track mode to the hold mode, and the input buffer is characterized in that it comprises a diode having an anode connected to the same power supply voltage as the emitter follower and a cathode connected to the power supply terminal of the input buffer.

[0015] According to the present invention, by providing a diode whose anode is connected to the same power supply voltage as the emitter follower and whose cathode is connected to the power supply terminal of the input buffer, it is possible to achieve higher frequency operation with a single power supply than conventional track-and-hold circuits.When the present invention is used as a sampling phase comparator, it is possible to achieve higher frequency and lower phase noise in a PLL.

[0016] FIG. 1 is a circuit diagram showing the configuration of a track-and-hold circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing the relationship between diode current and forward drop voltage. FIG. 3 is a circuit diagram showing the configuration of a track-and-hold circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of a track-and-hold circuit according to a third embodiment of the present invention. FIG. 5 is a circuit diagram showing another configuration of a track-and-hold circuit according to the third embodiment of the present invention. FIG. 6 is a circuit diagram showing the configuration of a track-and-hold circuit according to a fourth embodiment of the present invention. FIG. 7 is a circuit diagram showing another configuration of a track-and-hold circuit according to the fourth embodiment of the present invention. FIG. 8 is a block diagram showing the configuration of a conventional PLL. FIG. 9 is a block diagram showing the configuration of a conventional track-and-hold circuit. FIG. 10 is a circuit diagram showing the configuration of a conventional switched emitter follower circuit. FIG. 11 is a circuit diagram showing another configuration of a conventional switched emitter follower circuit.

[0017] [First Embodiment] An embodiment of the present invention will now be described with reference to the drawings. Fig. 1 is a circuit diagram showing the configuration of a track-and-hold circuit (THA) according to a first embodiment of the present invention. The THA comprises an input buffer 1 and emitter followers 2 and 3.

[0018] The input buffer 1 is a transistor Q whose base is connected to the positive phase input terminal in+ of the THA and whose collector is connected to the negative phase output terminal of the input buffer 1 (the input terminal in_SEF- of the emitter follower 2). １ A transistor Q whose base is connected to the inverting input terminal in- of the THA and whose collector is connected to the positive output terminal of the input buffer 1 (the input terminal in_SEF+ of the emitter follower 3) ２ and the base is biased by V ＴＡＩＬ and a transistor Q whose emitter is connected to ground. ９ One end is the power supply terminal of the input buffer 1 (V Ｍ ), and the other end is connected to transistor Q １ The load resistor R connected to the collector of Ｌ１One end is connected to the power supply terminal of the input buffer 1, and the other end is connected to the transistor Q ２ The load resistor R connected to the collector of Ｌ２ and one end of the transistor Q １ The other end is connected to the emitter of transistor Q ９ Resistor R connected to the collector of Ｅ１ and one end of the transistor Q ２ The other end is connected to the emitter of transistor Q ９ Resistor R connected to the collector of Ｅ２ and the anode is connected to the power supply voltage V ＣＣ＿ＳＥＦ and a diode D whose cathode is connected to the power supply terminal of the input buffer 1. Ｌ It consists of:

[0019] The emitter follower 2 has a base connected to the input terminal in_SEF- of the emitter follower 2 and a collector connected to the power supply voltage V ＣＣ＿ＳＥＦ , and the emitter of the transistor Q is connected to the negative phase terminal out_SEF− of the THA. ３ A reference signal TR is input to the base of a transistor Q whose collector is connected to the inverted output terminal out_SEF-. ５ A reference signal HO complementary to the reference signal TR is input to the base of a transistor Q whose collector is connected to the input terminal in_SEF-. ７ and the base is biased by V ＴＡＩＬ and the collector of the transistor Q ５ , Q ７ and a transistor Q whose emitter is connected to ground. １０ and a hold capacitor C whose one end is connected to the inverted output terminal out_SEF- and whose other end is connected to ground. Ｈ１ It consists of:

[0020] The emitter follower 3 has a base connected to the input terminal in_SEF+ of the emitter follower 3 and a collector connected to the power supply voltage V ＣＣ＿ＳＥＦ , and the emitter of the transistor Q is connected to the positive output terminal out_SEF+ of the THA. ４ A reference signal TR is input to the base of a transistor Q whose collector is connected to the positive output terminal out_SEF+.６ A reference signal HO is input to the base of a transistor Q whose collector is connected to the input terminal in_SEF+. ８ and the base is biased by V ＴＡＩＬ and the collector of the transistor Q ６ , Q ８ and a transistor Q whose emitter is connected to ground. １１ and a hold capacitance C whose one end is connected to the positive phase output terminal out_SEF+ and whose other end is connected to ground. Ｈ２ It consists of:

[0021] In this embodiment, similar to the circuit of FIG. 10, when the signal TR is at a high potential and the signal HO is at a low potential, the circuit operates in the track mode. Ｌ１ and transistor Q １ and resistance R Ｅ１ and a path consisting of a resistor R Ｌ２ and transistor Q ２ and resistance R Ｅ２ The paths consisting of ＢＵＦ A current of / 2 flows through the transistor Q ３ , Q ５ and a path consisting of a transistor Q ４ , Q ６ The paths consisting of ＳＥＦ A current of flows.

[0022] When the signal TR is at a low potential and the signal HO is at a high potential, the circuit operates in a hold mode. Ｌ１ and transistor Q １ and resistance R Ｅ１ and a path consisting of a resistor R Ｌ２ and transistor Q ２ and resistance R Ｅ２ In the same way as in the track mode, the route consisting of ＢＵＦ A current of / 2 flows through the resistor R Ｌ１ and transistor Q ７ and a path consisting of a resistor R Ｌ２ and transistor Q ８ The paths consisting of ＳＥＦ A current of flows.

[0023] In this embodiment, the power supply voltage VＣＣ＿ＳＥＦ and the power supply terminal of input buffer 1 (resistance R Ｌ１ , R Ｌ２ Diode D Ｌ By inserting Ｆ The voltage at the power supply terminal V Ｍ But, V Ｍ =V ＣＣ＿ＢＵＦ =V ＣＣ＿ＳＥＦ -V Ｆ So that V Ｆ By designing the above, the DC potential of the terminals in_SEF+ and in_SEF- in track mode is V ＣＣ＿ＳＥＦ -V Ｆ -R Ｌ ×I ＢＵＦ / 2, and transistor Q １ , Q ２ The DC potential of the terminals in_SEF+ and in_SEF- in the hold mode is V ＣＣ＿ＳＥＦ -V Ｆ -R Ｌ × (I ＢＵＦ / 2+I ＳＥＦ ) Therefore, the DC potential change width of the terminals in_SEF+ and in_SEF- due to switching between the hold mode and the track mode is the same as that of the circuit in FIG. Ｌ ×I ＳＥＦ As mentioned above, R Ｌ is the load resistance R Ｌ１ , R Ｌ２ is the value.

[0024] In this way, in this embodiment, the transistor Q １ , Q ２ The optimum bias point of the transistor Q when switching between track mode and hold mode. ３ , Q ４ Therefore, it is possible to achieve both an appropriate ON / OFF ratio and to operate the device with a single power supply.

[0025] I ＳＥＦ In the situation where I is a large current, ＢＵＦ :I ＳＥＦ = 1:m (m>1), and the transistor Q ３ , Q ４The collector-base breakdown voltage is V ＣＢＯ (Collector-emitter breakdown voltage V ＣＥＯ (approximately equal to ), then equation (1) must be satisfied.

[0026]

[0027] R in formula (1) Ｍ is the diode D Ｌ 11 is used instead of the diode D. Ｌ The maximum allowable current that can guarantee the reliability of ＤＭＡＸ , the maximum allowable current density is J ＤＭＡＸ Then, diode D Ｌ The size of the pn junction area A Ｄ ) is (1 + m)I ＢＵＦ ≦A Ｄ J ＤＭＡＸ ≦I ＤＭＡＸ must be met.

[0028] As shown in FIG. Ｌ There is a dependency between the current and the forward voltage drop in the input buffer 1. Therefore, the voltage V Ｍ The voltage V Ｍ In order to reduce the change in Ｌ It is desirable to operate the device in a region where the slope of the current-forward voltage drop characteristic is steep by appropriately selecting the junction area and the number of parallel connections. For example, in region 200 in Figure 2, the forward voltage drop varies greatly with the current, while in region 201, the change in the forward voltage drop is small. Therefore, it is desirable to operate the device in region 201.

[0029] This embodiment is also advantageous in terms of impedance matching. In many cases, high frequency circuits are impedance matched at 50 Ω. When the input impedance of the emitter followers 2 and 3 is designed to be 50 Ω, the maximum power can be transmitted by matching the output impedance of the input buffer 1 to 50 Ω. The output impedance of the input buffer 1 is determined by the load resistance R Ｌ１ , R Ｌ２ The value of R ＬIn the conventional circuit, R Ｌ It was difficult to reduce R to 50Ω. Ｌ can be set to a sufficiently small value, and can even be set to 50 Ω.

[0030] 3 is a circuit diagram showing the configuration of a THA according to a second embodiment of the present invention. The THA of this embodiment is composed of an input buffer 1a and emitter followers 2 and 3. The input buffer 1a is connected to a transistor Q １ , Q ２ , Q ９ and resistance R Ｅ１ , R Ｅ２ One end is the power supply voltage V ＣＣ＿ＳＥＦ The load resistor R connected to Ｌ and the anode is resistor R Ｌ The cathode is connected to the other end of the transistor Q １ Diode D connected to the collector of Ｌ１ and the anode is resistor R Ｌ The cathode is connected to the other end of the transistor Q ２ Diode D connected to the collector of Ｌ２ The emitter followers 2 and 3 have the same configuration as in the first embodiment.

[0031] In this embodiment, the positions of the load resistor and the diode of the input buffer are interchanged in the configuration of the first embodiment. Ｌ１ , D Ｌ２ It is desirable to set the bias point of the transistor Q1 in a region where the slope of the current-forward voltage drop characteristic is small. However, this region is also important for the transistor Q2 when switching between the hold mode and the track mode. １ , Q ２ and the bias point of the transistor Q ３ , Q ４ This is limited to a range that does not significantly affect the breakdown voltage of the

[0032] 4 is a circuit diagram showing the configuration of a THA according to a third embodiment of the present invention. The THA of this embodiment is composed of an input buffer 1b and emitter followers 2 and 3. The input buffer 1b is different from the diode D of the first embodiment.Ｌ Instead, the base and collector are connected to the power supply voltage V ＣＣ＿ＳＥＦ The emitter is connected to the power supply terminal of the input buffer 1b (resistor R Ｌ１ , R Ｌ２ (connection point of １２ The transistor Q １２ Instead, the base and emitter are connected to the power supply voltage V ＣＣ＿ＳＥＦ and the collector of which is connected to the power supply terminal of the input buffer 1b.

[0033] Also, diode D Ｌ and transistor Q １２ Instead, the cathode is connected to the power supply voltage V ＣＣ＿ＳＥＦ , and the anode of which is connected to the power supply terminal of the input buffer 1b. In this case, the reverse breakdown voltage of the Zener diode is utilized. However, when implementing the configuration of this embodiment in an integrated circuit, it is desirable to use a configuration that uses a forward drop voltage from the viewpoints of integration, power supply voltage, and area saving. Therefore, the diode D Ｌ and transistor Q １２ A configuration using the following is desirable.

[0034] It is also possible to apply a diode-connected transistor to the second embodiment. The configuration in this case is shown in Figure 5. The input buffer 1c is the same as the input buffer 1a of the second embodiment except that the diode D Ｌ１ Instead, the base and collector are connected by a resistance R Ｌ The emitter of the transistor Q １ The collector of the transistor Q １３ Also, a diode D Ｌ２ Instead, the base and collector are connected by a resistance R Ｌ The emitter of the transistor Q ２ The collector of the transistor Q １４ We have set up a system.

[0035] [Fourth Embodiment] In the first to third embodiments, a differential THA configuration has been described, but a single-phase configuration is also possible. Figure 6 is a circuit diagram showing the configuration of a THA according to a fourth embodiment of the present invention. The THA of this embodiment is composed of an input buffer 11 and an emitter follower 12.

[0036] The input buffer 11 is a transistor Q whose base is connected to the input terminal in of the THA and whose collector is connected to the output terminal of the input buffer 11 (the input terminal in_SEF of the emitter follower 12). １ and one end of the transistor Q １ The load resistor R connected to the collector of Ｌ and one end of the transistor Q １ The other end of the resistor R is connected to the emitter of Ｅ and the anode is connected to the power supply voltage V ＣＣ＿ＳＥＦ and the cathode is connected to the resistor R Ｌ Diode D connected to the other end of Ｌ It consists of:

[0037] The emitter follower 12 has a base connected to the input terminal in_SEF of the emitter follower 12 and a collector connected to the power supply voltage V ＣＣ＿ＳＥＦ , and the emitter of the transistor Q is connected to the output terminal out_SEF of the THA. ３ A reference signal TR is input to the base of a transistor Q whose collector is connected to the output terminal out_SEF. ５ A reference signal HO is input to the base of a transistor Q whose collector is connected to the input terminal in_SEF. ７ and the base is biased by V ＴＡＩＬ and the collector of the transistor Q ５ , Q ７ and a transistor Q whose emitter is connected to ground. １０ and a hold capacitance C whose one end is connected to the output terminal out_SEF and whose other end is connected to ground. Ｈ It consists of:

[0038] The third embodiment can also be applied to this embodiment. The configuration in this case is shown in FIG. 7. The input buffer 11a has a diode DＬ Instead, the base and collector are connected to the power supply voltage V ＣＣ＿ＳＥＦ and the emitter is connected to resistor R Ｌ The other end of the transistor Q １５ The transistor Q １５ Instead, the cathode is connected to the power supply voltage V ＣＣ＿ＳＥＦ and the anode is connected to resistor R Ｌ Alternatively, a Zener diode may be used connected to the other end of the resistor.

[0039] [Fifth embodiment] In the first to fourth embodiments, the transistor Q １ ~Q １４ Although bipolar transistors are used as the gate electrodes, MOS transistors may also be used, or a combination of bipolar and MOS transistors may be used. When using MOS transistors, the bases, collectors, and emitters may be replaced with gates, drains, and sources, respectively, in the explanations of the first to fourth embodiments.

[0040] [Sixth Embodiment] The THA described in the first to fifth embodiments can be used as a sampling phase comparator for a PLL. When using the THA as a sampling phase comparator, signal TR and signal HO complementary to signal TR are input to the THA as reference signals (CLK in FIG. 9), and a signal from the frequency divider is input to the input terminal in of the THA (in+, in- in the case of a differential configuration).

[0041] When the THA is used as a sampling phase comparator, the frequency f of the signal input to the input terminal in (in+, in-) is ｏｓｃ is the frequency f of the reference signals TR and HO. ＲＥＦ It may be applied to a configuration equal to f or another configuration. ｏｓｃ >f ＲＥＦ When used as a sub-sampling phase comparator, ｏｓｃ <f ＲＥＦ It may also be used as an oversampling phase comparator.

[0042] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0043] (Supplementary Note 1) The track-and-hold circuit of the present invention comprises an input buffer configured to receive an input signal, and an emitter follower configured to switch, in response to a reference signal, between a track mode in which a signal that follows the output signal of the input buffer is output, and a hold mode in which the output signal of the input buffer is held and output at the timing of switching from the track mode to the hold mode, and the input buffer comprises a diode having an anode connected to the same power supply voltage as the emitter follower and a cathode connected to a power supply terminal of the input buffer.

[0044] (Supplementary Note 2) In the track-and-hold circuit according to Supplementary Note 1, the emitter followers include two emitter followers, a first emitter follower and a second emitter follower, and the input buffer includes a first transistor having a base or gate connected to the positive-phase input terminal of the track-and-hold circuit and a collector or drain connected to the input terminal of the first emitter follower, and a second transistor having a base or gate connected to the negative-phase input terminal of the track-and-hold circuit and a collector or drain connected to the input terminal of the second emitter follower. a third transistor having a base or gate connected to a bias voltage and an emitter or source connected to ground; a first resistor having one end connected to a power supply terminal of the input buffer and the other end connected to the collector or drain of the first transistor; a second resistor having one end connected to a power supply terminal of the input buffer and the other end connected to the collector or drain of the second transistor; a third resistor having one end connected to the emitter or source of the first transistor and the other end connected to the collector or drain of the third transistor; and a fourth resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the third transistor. The first emitter follower comprises a fourth transistor having a base or gate connected to the input terminal of the first emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to an inverting output terminal of the track-and-hold circuit; a fifth transistor connected to the input terminal of the first emitter follower; a sixth transistor having a base or gate to which a second reference signal complementary to the first reference signal is input and a collector or drain connected to the input terminal of the first emitter follower; a seventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the fifth and sixth transistors, and an emitter or source connected to ground; and a first capacitor having one end connected to the inverting output terminal and the other end connected to ground,The second emitter follower is composed of an eighth transistor having a base or gate connected to the input terminal of the second emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the positive phase output terminal of the track and hold circuit, a ninth transistor having a base or gate to which the first reference signal is input and a collector or drain connected to the positive phase output terminal, a tenth transistor having a base or gate to which the second reference signal is input and a collector or drain connected to the input terminal of the second emitter follower, an eleventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the ninth and tenth transistors, and an emitter or source connected to ground, and a second capacitor having one end connected to the positive phase output terminal and the other end connected to ground.

[0045] (Supplementary Note 3) In the track-and-hold circuit according to Supplementary Note 1, the input buffer comprises a first transistor having a base or gate connected to an input terminal of the track-and-hold circuit and a collector or drain connected to an input terminal of the emitter-follower, a first resistor having one end connected to a power supply terminal of the input buffer and the other end connected to the collector or drain of the first transistor, and a second resistor having one end connected to the emitter or source of the first transistor and the other end connected to ground; and the emitter-follower has a base or gate connected to the input terminal of the emitter-follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the input terminal of the track-and-hold circuit. a second transistor connected to the output terminal of the track-and-hold circuit; a third transistor having a base or gate to which a first reference signal is input and a collector or drain to which is connected the output terminal of the track-and-hold circuit; a fourth transistor having a base or gate to which a second reference signal complementary to the first reference signal is input and a collector or drain to which is connected the input terminal of the emitter follower; a fifth transistor having a base or gate connected to a bias voltage, a collector or drain connected to the emitters or sources of the third and fourth transistors, and an emitter or source connected to ground; and a capacitor having one end connected to the output terminal of the track-and-hold circuit and the other end connected to ground.

[0046] (Supplementary Note 4) A track-and-hold circuit of the present invention comprises an input buffer configured to receive an input signal, and first and second emitter followers configured to switch, in response to a reference signal, between a track mode in which a signal following the output signal of the input buffer is output, and a hold mode in which the output signal of the input buffer is held and output at the timing of switching from the track mode to the hold mode. The input buffer comprises a first transistor having a base or gate connected to a positive-phase input terminal of the track-and-hold circuit and a collector or drain connected to an input terminal of the first emitter follower, a second transistor having a base or gate connected to a negative-phase input terminal of the track-and-hold circuit and a collector or drain connected to an input terminal of the second emitter follower, a third transistor having a base or gate connected to a bias voltage and an emitter or source connected to ground, a first resistor having one end connected to a power supply voltage, and a resistor having one end connected to the emitter or source of the first transistor and the other end connected to the emitter or source of the third transistor. a second resistor connected to the collector or drain of the second transistor; a third resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the third transistor; a first diode having an anode connected to the other end of the first resistor and a cathode connected to the collector of the first transistor; and a second diode having an anode connected to the other end of the first resistor and a cathode connected to the collector of the second transistor. a fourth transistor having a first reference signal input to its base or gate and a collector or drain connected to the negative-phase output terminal of a track-and-hold circuit, and a fourth transistor having a first reference signal input to its base or gate and a collector or drain connected to the negative-phase output terminal of a track-and-hold circuit, and a sixth transistor having a second reference signal complementary to the first reference signal input to its base or gate and a collector or drain connected to the input terminal of the first emitter follower;the second emitter follower is comprised of an eighth transistor having a base or gate connected to the bias voltage, a collector or drain connected to the power supply voltage, and an emitter or source connected to the positive output terminal of the track and hold circuit; a seventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the fifth and sixth transistors, and an emitter or source connected to ground; and a first capacitor having one end connected to the negative output terminal and the other end connected to ground; a ninth transistor having a port to which the first reference signal is input and a collector or drain connected to the positive phase output terminal, a tenth transistor having a base or gate to which the second reference signal is input and a collector or drain connected to the input terminal of the second emitter follower, an eleventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the ninth and tenth transistors, and an emitter or source connected to ground, and a second capacitor having one end connected to the positive phase output terminal and the other end connected to ground.

[0047] The present invention can be applied to a sampling circuit.

[0048] 1, 1a to 1c, 11, 11a...input buffer, 2, 3, 12...emitter follower, Q １ ~Q １５ ...Transistor, D Ｌ , D Ｌ１ , D Ｌ２ ...Diode, R Ｌ , R Ｌ１ , R Ｌ２ , R Ｅ１ , R Ｅ２ ...Resistance, C Ｈ , C Ｈ１ , C Ｈ２ …capacity.

Claims

1. A track-and-hold circuit comprising: an input buffer configured to receive an input signal; and an emitter follower configured to switch, in response to a reference signal, between a track mode in which a signal that follows the output signal of said input buffer is output, and a hold mode in which the output signal of said input buffer is held and output at the timing of switching from said track mode to said hold mode, wherein said input buffer comprises a diode having an anode connected to the same power supply voltage as said emitter follower and a cathode connected to a power supply terminal of said input buffer.

2. The track and hold circuit of claim 1, wherein the emitter follower comprises two emitter followers, a first emitter follower and a second emitter follower, and the input buffer comprises: a first transistor having a base or gate connected to the positive phase input terminal of the track and hold circuit and a collector or drain connected to the input terminal of the first emitter follower; a second transistor having a base or gate connected to the negative phase input terminal of the track and hold circuit and a collector or drain connected to the input terminal of the second emitter follower; a third transistor having a base or gate connected to a bias voltage and an emitter or source connected to ground; a first resistor having one end connected to a power supply terminal of the input buffer and the other end connected to the collector or drain of the first transistor; and a second resistor having one end connected to a power supply terminal of the input buffer and the other end connected to the collector or drain of the second transistor. a third resistor having one end connected to the emitter or source of the first transistor and the other end connected to the collector or drain of the third transistor; and a fourth resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the third transistor, wherein the first emitter follower comprises: a fourth transistor having a base or gate connected to the input terminal of the first emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the inverting output terminal of a track and hold circuit; a fifth transistor having a base or gate to which a first reference signal is input and a collector or drain connected to the inverting output terminal; a sixth transistor having a base or gate to which a second reference signal complementary to the first reference signal is input and a collector or drain connected to the input terminal of the first emitter follower; a seventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the fifth and sixth transistors, and an emitter or source connected to ground;a first capacitor having one end connected to the negative phase output terminal and the other end connected to ground, wherein the second emitter follower comprises: an eighth transistor having a base or gate connected to the input terminal of the second emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the positive phase output terminal of the track and hold circuit; a ninth transistor having a base or gate to which the first reference signal is input and a collector or drain connected to the positive phase output terminal; a tenth transistor having a base or gate to which the second reference signal is input and a collector or drain connected to the input terminal of the second emitter follower; an eleventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the ninth and tenth transistors, and an emitter or source connected to ground; and a second capacitor having one end connected to the positive phase output terminal and the other end connected to ground.

3. In the track-and-hold circuit of claim 1, the input buffer comprises: a first transistor having a base or gate connected to the input terminal of the track-and-hold circuit and a collector or drain connected to the input terminal of the emitter follower; a first resistor having one end connected to the power supply terminal of the input buffer and the other end connected to the collector or drain of the first transistor; and a second resistor having one end connected to the emitter or source of the first transistor and the other end connected to ground; and the emitter follower comprises: a second transistor having a base or gate connected to the input terminal of the emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the output terminal of the track-and-hold circuit; a third transistor having a base or gate to which a first reference signal is input and a collector or drain connected to the output terminal of the track-and-hold circuit; a fourth transistor having a base or gate to which a second reference signal complementary to the first reference signal is input and a collector or drain connected to an input terminal of an emitter follower; a fifth transistor having a base or gate connected to a bias voltage, a collector or drain connected to the emitters or sources of the third and fourth transistors, and an emitter or source connected to ground; and a capacitor having one end connected to an output terminal of the track and hold circuit and the other end connected to ground.

4. An input buffer configured to receive an input signal; and first and second emitter followers configured to switch, in response to a reference signal, between a track mode in which a signal following the output signal of said input buffer is output, and a hold mode in which the output signal of said input buffer is held and output at the timing of switching from said track mode to said hold mode, wherein said input buffer comprises: a first transistor having a base or gate connected to a positive phase input terminal of a track-and-hold circuit and a collector or drain connected to an input terminal of said first emitter follower; a second transistor having a base or gate connected to a negative phase input terminal of the track-and-hold circuit and a collector or drain connected to an input terminal of said second emitter follower; a third transistor having a base or gate connected to a bias voltage and an emitter or source connected to ground; a first resistor having one end connected to a power supply voltage; and a second resistor having one end connected to the emitter or source of said first transistor and the other end connected to the collector or drain of said third transistor. a third resistor having one end connected to the emitter or source of the second transistor and the other end connected to the collector or drain of the third transistor; a first diode having an anode connected to the other end of the first resistor and a cathode connected to the collector of the first transistor; and a second diode having an anode connected to the other end of the first resistor and a cathode connected to the collector of the second transistor, wherein the first emitter follower comprises: a fourth transistor having a base or gate connected to the input terminal of the first emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the inverting output terminal of the track and hold circuit; a fifth transistor having a base or gate to which a first reference signal is input and a collector or drain connected to the inverting output terminal; a sixth transistor having a base or gate to which a second reference signal complementary to the first reference signal is input and a collector or drain connected to the input terminal of the first emitter follower;a seventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the fifth and sixth transistors, and an emitter or source connected to ground; and a first capacitor having one end connected to the negative phase output terminal and the other end connected to ground, wherein the second emitter follower is comprised of: an eighth transistor having a base or gate connected to the input terminal of the second emitter follower, a collector or drain connected to the power supply voltage, and an emitter or source connected to the positive phase output terminal of the track and hold circuit; a ninth transistor having a base or gate to which the first reference signal is input, and a collector or drain connected to the positive phase output terminal; and a tenth transistor having a base or gate to which the second reference signal is input, and a collector or drain connected to the input terminal of the second emitter follower. a second capacitor having one end connected to the positive output terminal and the other end connected to ground; an eleventh transistor having a base or gate connected to the bias voltage, a collector or drain connected to the emitters or sources of the ninth and tenth transistors, and an emitter or source connected to ground; and a second capacitor having one end connected to the positive output terminal and the other end connected to ground.

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