Quantum device

Abstract

According to the present invention, in a cross-sectional view in a second direction, an end portion of a lower surface of a first gate electrode is disposed further inward than an end portion of a semiconductor channel.

Description

quantum devices

[0001] The present invention relates to quantum devices.

[0002] The performance improvements of conventional (von Neumann) computers, driven by the miniaturization and integration of semiconductor elements, have reached their physical and economic limits in recent years, making it difficult to achieve dramatic performance improvements. Meanwhile, the need for high-load calculations, such as big data processing, media processing, deep learning, combinatorial optimization, quantum chemistry simulation, and Monte Carlo calculations, is growing year by year, creating high expectations for further improvements in computer performance. However, when performing such high-load calculations on conventional computers, obtaining satisfactory results takes an extremely long or even unrealistic amount of time. Therefore, to meet these computational needs, computers with a processing concept different from conventional ones are required.

[0003] For this reason, quantum computers have been attracting a great deal of attention in recent years. In quantum computers, the 0 or 1 state of one bit is expressed using different quantum states. And because quantum mechanics allows the superposition of different quantum states, it is also possible to express the state in which the 0 and 1 states are superimposed in one bit. Therefore, when a conventional computer is used to display an n-digit number in binary from 000...00 to 111...11 all at once, it takes 2 ｎ Previously, quantum computers required n bits, but quantum computers can simultaneously represent both 0 and 1 with one bit, so all of these can be represented with n bits. This allows the apparent amount of information to be calculated to be compressed, enabling calculations that are dramatically faster than conventional computers, and making the large-scale quantum chemistry simulations and Monte Carlo calculations mentioned above possible. The bits of quantum computers are called qubits to distinguish them from the bits of conventional computers.

[0004] Several methods have been proposed for realizing quantum computers. One of them is to use electron spin as a quantum bit. In this method, the up and down spin of electrons correspond to the states 0 and 1. Representative examples of this method are described in, for example, Non-Patent Documents 1-3.

[0005] For example, in the example of Non-Patent Document 2, the potential of a Si channel on a buried oxide film (BOX) is controlled by a gate electrode to form quantum wells (quantum dots), where electrons are stored. Then, for example, by applying a magnetic field perpendicular to the chip surface, electrons undergo Zeeman separation, and electrons with spin parallel to the magnetic field (here referred to as up spin) have lower energy than electrons with spin antiparallel to the magnetic field (here referred to as down spin). In other words, an energy difference occurs between the up spin and down spin states of electrons.

[0006] In this state, by irradiating the electrons for a certain period of time with electromagnetic waves whose frequency corresponds to the energy difference created by Zeeman splitting, it is possible to change the up-spin state to down-spin and vice versa (this phenomenon is known as Rabi oscillations).

[0007] In other words, it is possible to change the state of 0 to 1 and the state of 1 to 0, thereby operating the rotation gate of the quantum circuit. In addition, the height of the potential barrier between each electron can be lowered by adjusting the gate voltage, causing the spins of adjacent electrons to interfere (entangle). By doing so, it is possible, for example, to exchange (swap) the spin states of adjacent electrons. This makes it possible to operate the swap gate of the quantum circuit.

[0008] Furthermore, when the spins of adjacent electrons are interfered with, the energy difference created by Zeeman separation is affected by the orientation of the adjacent electrons. In other words, the value of the energy difference of electron A caused by Zeeman separation varies depending on whether electron B next to electron A has up or down spin. Therefore, the frequency of the electromagnetic wave that can cause electron A to undergo Rabi oscillation changes depending on whether electron B has up or down spin.

[0009] In other words, if the frequency of the irradiated electromagnetic waves is set to a constant value, a situation can be created in which electron A can be made to undergo Rabi oscillation if electron B has an up spin, but electron A cannot be made to undergo Rabi oscillation if electron B has a down spin. In other words, a so-called controlled NOT gate operation becomes possible, in which whether or not the quantum state of electron A can be changed is determined by the quantum state of electron B. This is a well-known method of quantum computation.

[0010] To read information (read the spin direction of an electron), an electron with a known spin (let's call it electron C) is placed in a quantum dot next to the quantum dot containing the electron to be read. If the electron to be read has the same spin direction as electron C, the electron to be read cannot tunnel to the dot containing electron C due to the Pauli blockade.

[0011] Therefore, in a dot where electron C exists, only one electron C remains. On the other hand, if the electron to be read is antiparallel to the spin of electron C, the electron to be read can tunnel to the dot where electron C exists. Therefore, in a dot where electron C exists, two electrons can exist: the electron to be read and electron C.

[0012] The difference in the number of charges in the dot where electron C exists can be read by placing a single-electron transistor next to the dot where electron C exists and monitoring the current flowing through that transistor. In this way, the spin direction of the electron to be read can be indirectly determined by monitoring the current value of the single-electron transistor.

[0013] For example, in Non-Patent Document 3, electrons A, B, and C are stored under gates SG1, SG2, and SG3, respectively. After performing the quantum operations and calculations described above on electrons A and B stored under SG1 and SG2, if the spin of electron B is in the same direction as the spin of electron C, electron B cannot move to the dot under SG3. On the other hand, if the spin of electron B is in the opposite direction to the spin of electron C, electron B can move to the dot under SG3. The spin direction of electron C is known.

[0014] The number of electrons present under SG3 can be determined by observing the current flowing through the single-electron transistor whose gate is the adjacent SGS. If the number of electrons present under SG3 is known in this way, the spin direction of electron B, which was under SG2, after the quantum operation can also be determined. Knowing the spin direction of electron B after the quantum operation means that the result of the quantum operation can be known.

[0015] In this way, quantum operations can be performed and the results can be read out. Note that in the device of Non-Patent Document 3, the channel portion through which electrons and holes can be conducted is formed of SOI, and the channel portion is defined using STI (Shallow Trench Isolation).

[0016] In other words, the outside of the channel is an insulating film, which prevents unintended leakage current between each terminal of the channel (source, drain, reservoir). It also prevents unintended leakage current between each device when many devices are integrated. So-called physical element isolation structures such as STI and LOCOS (Local Oxidation of Silicon) are essential structures for ensuring the reliability of many semiconductor devices, including quantum devices.

[0017] D. M. Zajac, A. J. Sigilito, M. Russ, F. Borjans, J. M. Taylor, G. Burkard, J. R. Petta1, “Resonantly driven CNOT gate for electron spins” Science359, 439-442 (2018) N. Lee, R. Tsuchiya, G. Shinkai, Y. Kanno, T. Mine, T. Takahama, R. Mizokuchi, T. Kodera, D. Hisamoto, and H. Mizuno, “Enhancing electrostatic coupling in silicon quantum dot array by dual gate oxide thickness for “large-scale integration” Appl. Phys. Lett. 116, 162106 (2020); doi: 10.1063 / 1.5141522Digh Hisamoto, Noriyuki Lee, Ryuta Tsuchiya, Toshiyuki Mine, Takeru Utsugi, Shinichi Saito, Hiroyuki Mizuno, "Electron Charge Sensor with Hole Current Operating at Cryogenic Temperature", Appl. Phys. Express 16 036504 (2023).

[0018] If we could form a quantum dot under each gate, control the number of electrons captured by them, and perform quantum operations and calculations as described in the background art, ideal quantum calculations could be achieved.

[0019] However, in reality, in addition to the intended quantum dots, multiple unintended extra quantum dots are often generated under each gate, and multiple electrons are captured by these quantum dots.

[0020] When quantum operations or calculations are performed on such a state, not only is the accuracy of the desired quantum operation significantly reduced, but it also becomes unclear which quantum dot's electrons the quantum operation acted on.

[0021] Furthermore, if an operation is performed to entangle electrons between different quantum dots, it becomes impossible to determine which quantum dot's electrons are entangled.

[0022] Furthermore, consider the case in Non-Patent Document 3 where an electron B under SG2 is moved to a quantum dot where an electron C under SG3 exists next to it, and the spin direction of electron B is determined. If there are multiple quantum dots under SG3 at this time, and an up-spin electron and a down-spin electron exist in separate quantum dots under SG3, electron B under SG2 can be conducted to any of the quantum dots under SG3 regardless of its spin direction. This makes it impossible to read out the calculation results.

[0023] When a channel is formed by a physical device isolation process (e.g., an STI process), the above-described unintentional extra quantum dots (hereinafter referred to as parasitic quantum dots) are generated at the boundary between the channel and the insulating film formed by the process, i.e., at the end or side wall of the channel.

[0024] On the other hand, physical element isolation structures are essential for many electronic devices, including quantum devices, and their integrated structures.

[0025] An object of the present invention is to suppress the generation of parasitic quantum dots in a quantum device having a channel formed by a physical element isolation structure.

[0026] A quantum device according to one aspect of the present invention comprises: a first layer having a semiconductor channel extending in a first direction defined by an element isolation structure; and a first gate electrode disposed on top of the first layer, extending in a second direction different from the first direction, and forming quantum dots in the semiconductor channel; wherein, in a cross-sectional view in the second direction, an end of the underside of the first gate electrode is disposed more inward than an end of the semiconductor channel.

[0027] According to one aspect of the present invention, it is possible to suppress the generation of parasitic quantum dots in a quantum device having a channel formed by a physical element isolation structure.

[0028] FIG. 1 is a diagram for explaining a quantum device according to a first embodiment. FIG. 2 is a diagram for explaining a quantum device according to a first embodiment. FIG. 3 is a diagram for explaining a quantum device according to a first embodiment. FIG. 4 is a diagram for explaining a quantum device according to a first embodiment. FIG. 5 is a diagram for explaining a quantum device according to a first embodiment. FIG. 6 is a diagram for explaining a quantum device according to a first embodiment. FIG. 7 is a diagram for explaining a quantum device according to a first embodiment. FIG. 8 is a diagram for explaining a quantum device according to a first embodiment. FIG. 9 is a diagram for explaining a quantum device according to a first embodiment. FIG. 10 is a diagram for explaining a quantum device according to a first embodiment. FIG. 1 is a diagram for explaining a quantum device of Example 1. FIG. 2 is a diagram for explaining a quantum device of Example 1. FIG. 3 is a diagram for explaining a quantum device of Example 1. FIG. 4 is a diagram for explaining a quantum device of Example 1. FIG. 5 is a diagram for explaining a quantum device of Example 1. FIG. 6 is a diagram for explaining a quantum device of Example 1. FIG. 7 is a diagram for explaining a quantum device of Example 1. FIG. 8 is a diagram for explaining a quantum device of Example 1. FIG. 9 is a diagram for explaining a quantum device of Example 2. FIG. 10 is a diagram for explaining a quantum device of Example 2. FIG. 11 is a diagram for explaining a quantum device of Example 2.FIG. 1 is a diagram illustrating a quantum device according to a second embodiment. FIG. 2 is a diagram illustrating a quantum device according to a second embodiment. FIG. 3 is a diagram illustrating a quantum device according to a second embodiment. FIG. 4 is a diagram illustrating a quantum device according to a second embodiment. FIG. 5 is a diagram illustrating a quantum device according to a second embodiment. FIG. 6 is a diagram illustrating a quantum device according to a third embodiment. FIG. 7 is a diagram illustrating a quantum device according to a third embodiment. FIG. 8 is a diagram illustrating a quantum device according to a third embodiment. FIG. 9 is a diagram illustrating a quantum device according to a third embodiment. FIG. 10 is a diagram illustrating a quantum device according to a third embodiment. FIG. 10 is a diagram for explaining a quantum device according to a third embodiment; FIG. 11 is a diagram for explaining a quantum device according to a third embodiment; FIG. 12 is a diagram for explaining a quantum device according to a first embodiment; FIG. 13 is a diagram for explaining a quantum device according to a second embodiment; FIG. 14 is a diagram for explaining a quantum device according to a third embodiment; FIG. 15 is a diagram for explaining a quantum device according to a first embodiment; and FIG. 16 is a diagram for explaining a quantum device according to a second embodiment.

[0029] In all drawings for explaining the present embodiment, components having the same function are assigned the same reference numerals, and repeated explanations thereof are omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The structures and materials described in the examples are examples for embodying the ideas of the present invention, and do not strictly specify the materials, dimensions, detailed structures, etc. Please note that the dimensions and scales of the drawings are not accurate, as priority has been given to ease of viewing.

[0030] 1 is a diagram for explaining a quantum device according to Example 1. In the present specification, a top view and a cross-sectional view may be shown together on one drawing, as in FIG.

[0031] Reference numerals 101, 103, and 105 denote diffusion layers, 107 denotes a channel, 108-117 denote gate electrodes, 120 denotes a Si oxide film, and 122 denotes Si (substrate portion). Portion 107 is Si that is not doped with any impurities. 101, 103, and 105 are doped with, for example, phosphorus in the case of N-type diffusion layers, and doped with, for example, boron in the case of P-type diffusion layers. In this specification, unless otherwise specified, the diffusion layers will be described as N-type diffusion layers. The device in FIG. 1 can be formed, for example, using an SOI (Silicon on Insulator) wafer and a conventional semiconductor process.

[0032] For details of the manufacturing method, please refer to, for example, Non-Patent Documents 2 and 3. Note that an insulating film (e.g., a Si oxide film, approximately 3-20 nm thick) exists between the channel and each gate electrode, and between each gate electrode. In the following description, 101 may be referred to as a reservoir, 103 as a source, and 105 as a drain.

[0033] FIG. 2 shows an example of a device having almost the same functions, which is fabricated using a normal Si wafer instead of an SOI wafer.

[0034] The difference from Figure 1 is that there is no Si oxide film 120 between the channel 107 and the Si substrate 122. In this case, the channel 107 and the Si substrate 122 are usually formed as a continuous member. Note that hereafter, an example using an SOI wafer will be basically explained. Furthermore, the device manufacturing method using an SOI wafer shown below can also be applied to an ordinary Si wafer to produce a device with almost the same functions.

[0035] FIG. 3 is a diagram illustrating the operation of the device shown in FIGS.

[0036] For example, by applying 0 V to 101, a positive voltage (for example, 2 V) to 108-114, a positive voltage (for example, 2 V) to 115-117, and a positive voltage (for example, 2 V) to 103, electrons can be transported from 101 to 103. Also, by applying a positive voltage (for example, 2 V) to 105 instead of 103, electrons can be transported from 101 to 105. Electrons are shown as 301 in the figure.

[0037] Furthermore, by applying a negative voltage (for example, −2 V) to the gate electrodes 108, 110, 112, and 114 and a positive voltage (for example, 2 V) to the gate electrodes 109, 111, and 113, a quantum well can be formed in which electrons are trapped under the gate electrodes 109, 111, and 113.

[0038] By further finely adjusting the voltages of these gate electrodes, it is possible to create a state in which one electron is trapped in each quantum well (under 109, 111, and 113), creating the state shown in Figure 4. To transport electrons one by one, for example, a pulsed positive voltage can be applied to gate electrode 108, and the application time of this pulsed positive voltage can be set to a time sufficient for just one electron to move from 101 to 109, thereby transporting just one electron from 101 to 109. Such single-electron transport and trapping methods have already been reported in many publications. For example, see Non-Patent Documents 1-3.

[0039] In the state shown in Figure 4, consider the case where a magnetic field B (>0) is applied perpendicular to the paper surface, from the Si substrate side of the device toward the gate electrode side. Also, define spin parallel to the magnetic field as up spin, and spin antiparallel to the magnetic field as down spin. The spin of the electrons below 113 is set to an up spin state.

[0040] Under these circumstances, by using a method that uses Rabi oscillations, it is possible to change the spin direction of each electron under 109 and 111 (corresponding to a rotation gate operation). In addition, by weakening the voltage applied to 110 and causing the electrons under 109 and 111 to interfere with each other, it is possible to swap the spins of the electrons (corresponding to a swap gate operation), or to perform a gate operation in which the rotation of one spin state depends on the spin state of the other (corresponding to a controlled NOT gate operation).

[0041] After performing such a calculation using gate operation, the strength of the negative voltage applied to 112 is slightly weakened, and the value of the positive voltage applied to 113 is slightly strengthened. By doing so, if the electrons under 111 are of up spin, the electrons under 111 cannot move to 113 due to the Pauli blockade, but if the electrons under 111 are of down spin, a state can be created in which the electrons under 111 can move to 113.

[0042] In other words, if the electron under 111 has down spin, that electron will move under 113 after a certain time has passed, and two electrons will remain under 113. On the other hand, if the electron under 111 has up spin, it cannot move under 113, and so only one electron will remain under 113 even after a certain time has passed. In other words, if we know the number of electrons that exist under 113 after a certain time has passed, we can know the spin state of the electron that existed under 111.

[0043] To read out the number of electrons, a readout method using a single-electron transistor in the quantum well formed under gate 116 is used. This method is as follows. For example, 0 V is applied to 103, 0.1 V to 105, a negative voltage is applied to 115 and 117, and a positive voltage is applied to 116. Then, by bringing the magnitude of the negative voltages to 115 and 117 closer to 0, electrons can tunnel from 103 to 105 (Figure 5). The value of the tunnel current at this time changes depending on the number of electrons present in 113. By reading this change, the number of electrons present in 113 can be determined.

[0044] The problems with the quantum devices described above will be explained in Fig. 6. For ease of understanding, the gates 109, 111, and 113 are shown with patterns in the drawings.

[0045] FIG. 6(a) is a top view of the device, and FIG. 6(b) shows a CC' cross section of the device and the potential distribution near the surface in the channel.

[0046] This potential distribution is the potential distribution obtained when a voltage greater than the voltage at which the channel 107 becomes a flat band is applied to the gate 113 in order to trap electrons below the gate 113, or when a voltage greater than the voltage applied to the Si substrate 122 is applied to the gate 113 (for example, when 0 V is applied to 122 and 2 V is applied to 113), or when a voltage greater than the voltage applied to the diffusion layers 101, 103, and 105 is applied to the gate 113 (for example, when 0 V is applied to 101, 103, and 105 and 2 V is applied to 113), or when a voltage is applied under other voltage conditions that causes electrons to be trapped below the gate 113.

[0047] This potential distribution is the potential distribution for electrons, and the lower the potential value, the more likely electrons are to exist in that location. As can be seen from the potential distribution in Figure 6, the potential at the end of the channel 107 is lower than in other areas and is recessed. This is because, when a voltage is applied to the gate 113, the electric field concentrates at the corners of the channel and the convex portions of the uneven portion of the channel sidewall. These areas then become parasitic quantum dots (indicated by x marks 200). Figure 7(a) shows this. When a voltage higher than that applied to the channel 107 is applied to the gate 113, the electric field lines concentrate at the corners of the channel end, as shown in the figure. Furthermore, as shown in Figure 7(b), if unevenness is created on the side of the channel due to the effects of channel processing, the electric field lines also concentrate at the protruding portions. In this way, the electric field concentrates in areas where the electric field lines concentrate, resulting in a lower potential than in other areas.

[0048] With this type of potential shape, two or more parasitic quantum dots are created by the potential depression at the channel edge, and electrons 301 are trapped in these areas, as shown in Figure 8(a). (For simplicity, only two electrons are shown in the figure, but in reality, many quantum dots are created in corners and in areas where the electric field is concentrated due to unevenness on the sidewall, making it impossible to know how many electrons are trapped in which locations.) On the other hand, Figure 8(b) shows a desirable, ideal potential shape and the electrons trapped there. With the device structure of Figure 8(a), it is impossible to create a potential shape like that shown in Figure 8(b). Figure 8(b) merely depicts a desirable potential shape.

[0049] The potential profile shown in Figure 8(b) has only one depression in the center of the channel. The ideal state is one in which the number, energy, spin direction, and other parameters of the electrons present there are properly controlled by the gate. For simplicity, only one electron is shown in Figure 8(b), but quantum computation is possible even if there are two or more electrons in the potential profile shown in Figure 8(b), as long as the number, energy, spin direction, and other parameters of the electrons present can be accurately grasped and controlled.

[0050] However, when multiple parasitic quantum dots are generated, as shown in Figures 6 and 8(a), electrons exist there whose number, energy state, and spin direction cannot be controlled, making it difficult to perform the intended quantum bit operations, calculations, and readout of the calculation results.

[0051] Figure 9 shows the structure of a quantum device that solves this problem (C-C' cross section). Figure 9(a) shows the structure formed using an SOI wafer, and Figure 9(b) shows the structure formed using a regular Si wafer.

[0052] Reference numeral 122 denotes Si, 120 denotes SiO2, 129 denotes a gate insulating film such as SiO2, 121 denotes an insulating film such as SiO2, and 113 denotes a gate electrode such as N-type polysilicon. Reference numerals 107 and 160 denote channel portions made of Si. Note that the Si of 160 and the Si of 122 in FIG. 9(b) are continuous members. A feature of the device in FIG. 9 is that the lower end of the gate 113 (the lower end of the T-shape) is located inside the end of the channel 107 or the channel 160. Note that the layout view from above is the same as that in FIG. 6(a).

[0053] To make it easier to understand, it can also be written as shown in Figure 72. In Figure 72, a dashed line 800 is drawn in addition to the diagram of Figure 6(a). Within the channel, the area outside this dashed line (the direction indicated by the black arrow) is the part where the channel is covered with insulating film 121. However, to avoid complicating the diagram, the top view will be explained below using Figure 6(a).

[0054] In this state, if a voltage higher than the voltage at which channel 107 becomes a flat band is applied to gate 113, or if a voltage higher than that applied to Si substrate 122 is applied to gate 113 (for example, 0 V is applied to 122 and 2 V is applied to 113), or if a voltage higher than that applied to diffusion layers 101, 103, and 105 is applied to gate 113 (for example, 0 V is applied to 101, 103, and 105 and 2 V is applied to 113), or if a voltage is applied under other voltage conditions that trap electrons under gate 113, an ideal potential shape (i.e., a potential shape in which only the center portion of the channel is depressed) as shown in the bottom of Fig. 9 is formed. This is because, as shown in Fig. 10, the electric field lines from the gate do not concentrate at the channel end, but rather the density of the electric field lines decreases as they approach the channel end.

[0055] Figure 11 shows the results of a simulation verifying the effect of this structure. The graph shows the results when the gate electrode width (Gw) is 30 nm and the channel width (Cw) is varied to (a) 25 nm, (b) 30 nm, and (c) 35 nm. The horizontal axis of the graph represents the distance from the center of the channel, and the vertical axis represents the potential value in the channel. The calculations were performed assuming a gate insulating film 129 thickness of 5 nm, a channel 107 thickness of 50 nm, a distance from channel 107 to 122 of 150 nm, a voltage applied to gate 113 of 1 V, and a voltage applied to substrate 122 of 0 V.

[0056] In the case of (a), where the edge of the lower part of the gate is located outside the edge of the channel, the potential distribution becomes lower toward the edge of the channel, making it easier for electrons to be captured at both ends of the channel. In other words, this is a potential distribution that creates parasitic quantum dots at both ends of the channel.

[0057] Next, in the case of the configuration (b), where the lower edge of the gate is located at the same position as the edge of the channel, the potential distribution has a depression near the center and is close to the ideal potential shape, but the potential near both ends of the channel is also slightly lower. In other words, even with the configuration (b), there is a certain effect in suppressing parasitic quantum dots, but there is still a possibility that parasitic quantum dots will form in the low-potential areas at both ends of the channel. Next, in the configuration (c), where the lower edge of the gate is located inside the edge of the channel, the potential is lowest near the center of the channel and there are no depressions in other parts. This is an ideal potential distribution that does not create parasitic quantum dots other than the intended quantum dots formed in the center of the channel.

[0058] That is, the results of this simulation also made it clear that the structure represented by Fig. 9 is a structure that can suppress parasitic quantum dots. The simulation results also showed that if the lower edge of the gate is even slightly inside the edge of the channel, it is effective in suppressing parasitic quantum dots, and in particular, if the lower edge of the gate is 5 nm or more inside the edge of the channel, an ideal potential distribution that reliably does not create parasitic quantum dots can be obtained.

[0059] An example of a manufacturing method for the quantum device is shown in Figure 12 and subsequent figures. To form a structure with a cross section like that shown in Figure 9 in a layout like the top view of Figure 6(a), it is generally necessary to have a manufacturing method that results in a CC' cross section like that shown in Figure 9 in a top view layout structure like that shown in Figure 12. Therefore, the process leading up to this structure will be explained by following the cross-sectional structures along A-A', CC', and DD' in the top view layout diagram of Figure 12. The completed structure is shown in Figures 13 and 14.

[0060] 13 shows the completed form when fabricated using an SOI wafer. 122 is Si, 120 is SiO2 (BOX), 403 is an insulating film such as SiO2, 404 and 406 are gate insulating films such as SiO2, 112, 113 and 114 are gates such as N-type polysilicon, and 107 is non-doped Si or lightly doped P-type Si.

[0061] On the other hand, Figure 14 shows the finished product when fabricated using a regular Si wafer. The difference from Figure 13 is that there is no SiO2 between the channel 107 and the substrate 122, and the channel and substrate are formed from a continuous material. The expected effects of the present invention can, of course, be obtained with both the device shown in Figure 13 and the device shown in Figure 14. The fabrication method for the desired structure will now be explained in Figure 15 and subsequent figures, tracing the cross-sectional structures along A-A', C-C', and D-D'. The fabrication method is basically shown using an SOI wafer as an example, but the desired structure can also be fabricated using a regular Si substrate using the same fabrication method. When using a Si substrate, simply consider 120 in the figure to be Si instead of SiO2.

[0062] 15, an SOI wafer is prepared in which 122 is a Si substrate, 120 is SiO2 (BOX), and 107 is Si (non-doped Si or lightly doped P-type Si). The thickness of 120 is, for example, 145 nm, and the thickness of 107 is, for example, 55 nm.

[0063] 16, an SiO2 film 401 is formed by, for example, thermal oxidation. The thickness of the SiO2 film 401 is, for example, 5 nm. Thereafter, an SiN film 402 is formed by the CVD method. The thickness is, for example, 50 nm.

[0064] 17, the SiN / SiO2 / Si laminated film is patterned using existing lithography and etching techniques as shown in the figure. In the cross sections DD' and CC', the width of the SiN / SiO2 / Si laminated film portion after patterning is, for example, 50 nm.

[0065] 18, an SiO2 film 403 is deposited by CVD to a thickness of, for example, 350 nm.

[0066] In FIG. 19, the SiO2 film 403 is polished and flattened by CMP until it reaches approximately the same height as the SiN film.

[0067] 20, the SiN film is etched and removed using hot phosphoric acid. After that, the SiO2 on the bottom surface of the Si is removed by dry etching. Note that this SiO2 etching can also be performed by wet etching using hydrofluoric acid.

[0068] 21, a gate insulating film 404 is deposited by, for example, CVD. 404 is, for example, an SiO2 film, and has a film thickness of, for example, 10 nm.

[0069] 22, a Si film 405 is deposited by CVD. 405 is, for example, Si doped with phosphorus, and the deposited film thickness is, for example, 50 nm. After the Si film is deposited, activation annealing is performed.

[0070] 23, the Si / SiO2 laminated film is patterned using existing lithography and etching techniques. In the AA' cross section, the width of the Si / SiO2 laminated film portion after patterning is, for example, 60 nm. The width between patterns is also, for example, 60 nm.

[0071] 24, a gate insulating film 406 is deposited by, for example, CVD. 406 is, for example, an SiO2 film, and has a thickness of, for example, 10 nm.

[0072] 25, a Si film 407 is deposited by CVD. 407 is, for example, Si doped with phosphorus, and the deposited film thickness is, for example, 120 nm. After the Si film is deposited, activation annealing is performed.

[0073] In Fig. 26, the Si film 407 is etched back by a thickness of 120 nm. The shape after that is as shown in Fig. 26, where the lower edge of the gate is located inside the edge of the channel in the D-D' cross section and the C-C' cross section, and the desired structure is obtained. In addition, the gates 112, 113, and 114 are each separated by an SiO2 film.

[0074] 27 and onwards provide a supplementary explanation of the above process when a normal Si substrate is used. As mentioned above, when a normal Si substrate is used instead of an SOI substrate, the part 120 in the previous manufacturing method can basically be regarded as Si.

[0075] 27, a Si substrate 122 is prepared. The substrate 122 is, for example, non-doped Si or lightly doped P-type Si.

[0076] 28, an SiO2 film 401 is formed by, for example, thermal oxidation. The thickness of the SiO2 film 401 is, for example, 5 nm. Thereafter, an SiN film 402 is formed by the CVD method. The thickness is, for example, 50 nm.

[0077] 29, the SiN / SiO2 / Si stacked structure is patterned using existing lithography and etching techniques as shown in the figure. In the cross sections DD' and CC', the width of the SiN / SiO2 / Si stacked structure portion after patterning is, for example, 50 nm.

[0078] 30, an SiO2 film 403 is deposited by CVD to a thickness of, for example, 350 nm.

[0079] 31, the SiO2 film 403 is polished and flattened by CMP until it is at approximately the same height as the SiN film. After that, the process is continued according to the manufacturing method shown in FIG. 20 onwards. This results in the final finished shape shown in FIG.

[0080] 32, the lower edge of the gate is located inside the edge of the channel in the DD' cross section and the CC' cross section, thus obtaining the desired structure. Also, the gates 112, 113, and 114 are separated from each other by SiO2 films.

[0081] FIG. 33 and subsequent figures show a manufacturing method that allows the lower edge of the gate to be positioned further inward from the channel edge than the manufacturing method shown above.

[0082] 33, after the structure shown in FIG. 24 has been formed, an insulating film 420 is formed. The insulating film 420 is, for example, an SiO2 film, and has a thickness of, for example, 5 nm.

[0083] 34, SiO2 is etched back by 5 nm, leaving SiO2 sidewalls with a thickness of 5 nm on the side walls of 406. Meanwhile, the film 420 that was present on the bottom surface of 406 is etched away.

[0084] 35, a Si film 407 is deposited by CVD. 407 is, for example, Si doped with phosphorus, and the deposited film thickness is, for example, 120 nm. After the Si film is deposited, activation annealing is performed.

[0085] In FIG. 36, the Si film 407 is etched back to a thickness of 120 nm. The shape after this is as shown in FIG. 36, where the lower end of the gate is located inside the channel edge in the D-D' cross section and the C-C' cross section, resulting in the desired structure. Gates 112, 113, and 114 are also separated from each other by SiO2 films. A feature of this structure is that, in the C-C' cross section, the lower end of the gate is located inside the channel edge by the thickness of 406 + 420.

[0086] On the other hand, since only film 406 exists between the channel surface and the lower surface of gate 113, the channel surface and the lower surface of gate 113 are separated by the film thickness of 406. In other words, the distance between the lower surface of the gate and the channel surface remains the same as film thickness 406, and the lower edge of the gate is located inward from the channel edge by a film thickness of 406 + 420. This is a difference from the structure in FIG.

[0087] 36, the distance between the lower surface of gate 113 and the channel surface is the same as that in FIG. 26 at film thickness 406, so the strength of the electric field effect exerted from gate 113 near the center of the channel is equivalent to that in the structure in FIG.

[0088] On the other hand, the structure in Fig. 36 has a greater distance between the lower edge of gate 113 and the edge of the channel than the structure in Fig. 26, so the electric field effect from gate 113 on the channel edge is even smaller than in the structure in Fig. 26, and as a result, the effect of suppressing the generation of parasitic quantum dots is further achieved. In other words, the structure in Fig. 36 has the characteristic of being able to achieve a greater effect of suppressing the generation of parasitic quantum dots at the channel edge while maintaining the ability to capture electrons near the center of the channel.

[0089] Although the above explanation has been given mainly on the case where electrons are captured by quantum dots, the present invention is also effective in the case where holes are captured instead of electrons. In this case, the diffusion layers 101, 103, and 105 are P-type.

[0090] 68, when a voltage smaller than that at which channel 107 becomes a flat band is applied to gate 113, or when a voltage smaller than that applied to Si substrate 122 is applied to gate 113 (for example, when 0 V is applied to 122 and −2 V is applied to 113), or when a voltage smaller than that applied to diffusion layers 101, 103, and 105 is applied to gate 113 (for example, when 0 V is applied to 101, 103, and 105 and −2 V is applied to 113), or when a voltage is applied under other voltage conditions that causes holes to be trapped below gate 113, an ideal potential shape (i.e., a convex potential shape in which holes are trapped only near the center of the channel and no parasitic quantum dots are generated at the channel ends) as shown in the bottom of Fig. 68 is formed. In the case of holes, since the polarity is opposite to that of electrons, a location with high potential is a stable location for holes.

[0091] The gate may also have a shape that tapers toward the bottom, as shown in FIG. 71(a). And, as shown in FIG. 71(b), the gate may have a pointed tip. In these cases, the bottom end of the gate is positioned further inside the channel, thereby further enhancing the effects of the present invention. The bottom of FIG. 71 shows the potential shape when a voltage that traps electrons in the channel is applied to gate 113, which is an ideal potential shape in which electrons are trapped only in the center of the channel. Of course, as mentioned above, when a voltage that traps holes in the channel is applied to gate 113, an ideal potential shape in which holes are trapped only in the center is also obtained.

[0092] In this example, another method and structure for suppressing parasitic quantum dots in the channel is disclosed, and the structure is shown in Figure 37.

[0093] FIG. 37(a) shows the top view layout of the device. The difference from the layout described so far (FIG. 6) is that new gates 601, 602, and 603 have been added. FIG. 37(b) shows a cross-sectional view taken along the line CC' in FIG. 37(a). The gates 601 and 602 are arranged on either side of the channel 107, with an insulating film (e.g., SiO2) sandwiched between them. Note that FIG. 37(b) shows the structure of this embodiment when fabricated using an SOI substrate. If the structure of this embodiment were fabricated using a normal Si substrate, it would look like FIG. 37(c). In this case, the channel portion 160 and the Si substrate 122 are formed from a continuous member.

[0094] In this structure, a voltage higher than the voltage at which the channel 107 or 160 becomes a flat band is applied to the gate 113, or a voltage higher than the voltage applied to the Si substrate 122 is applied to the gate 113 (for example, 0 V is applied to 122 and 2 V is applied to 113), or a voltage higher than the voltage applied to the diffusion layers 101, 103, and 105 is applied to the gate 113 (for example, 0 V is applied to 101, 103, and 105 and 2 V is applied to 113), or a voltage is applied to the gate 113 under other voltage conditions such that electrons are trapped under the gate 113, while a voltage lower than the voltage applied to the gate 113 is applied to the gates 601 and 602.

[0095] For example, suppose a large voltage (e.g., 2 V) is applied to gate 113, and a small voltage (−2 V) is applied to gates 601 and 602. Then, due to the influence of the electric field effect, electrons are less likely to exist near the ends and sidewalls of channel 107 close to gates 601 and 602, and electrons tend to exist only near the center of the channel, where the electric field effect from gates 601 and 602 is less likely to reach. In other words, as shown in Figures 37(b) and 37(c), an ideal potential is formed in which a depression exists only near the center of the channel, and the formation of parasitic quantum dots on the channel ends and sidewalls can be suppressed.

[0096] A manufacturing method for the device of Example 2 is shown in Figures 38 and onwards. In order to form a structure whose cross section is shown in Figures 37(b) and 37(c) in a layout like the top view of Figure 37(a), it is generally necessary to have a manufacturing method that results in a cross section like that shown in Figures 37(b) and 37(c) in a top view layout structure like that of Figure 38. Therefore, the process up to creating this structure will be explained by following the cross-sectional structures taken along lines A-A', C-C', and D-D' in the top view layout view of Figure 38. The completed form is shown in Figure 39.

[0097] 39 shows the completed form when fabricated using an SOI wafer. 122 is Si, 120 is SiO2 (BOX), 612 and 614 are gate insulating films, for example, SiO2, 112, 113 and 114 are gates, for example, N-type polysilicon, 107 is, for example, non-doped Si or lightly doped P-type Si, and 601 and 602 are gates, for example, N-type Si.

[0098] The manufacturing method for the desired structure will be explained below, following the cross-sectional structures of A-A', C-C', and D-D', starting with Figure 40. The manufacturing method will be basically shown using an SOI wafer as an example, but the desired structure can also be manufactured using a normal Si substrate using the same manufacturing method. When using a Si substrate, the only difference is that 120 in the diagram should be regarded as Si instead of SiO2.

[0099] 40, an SOI wafer is prepared in which 122 is a Si substrate, 120 is SiO2 (BOX), and 107 is Si (non-doped Si or lightly doped P-type Si). The thickness of 120 is, for example, 145 nm, and the thickness of 107 is, for example, 55 nm.

[0100] 41, an SiO2 film 401 is formed by, for example, thermal oxidation. The thickness of the SiO2 film 401 is, for example, 5 nm. Thereafter, an SiN film 402 is formed by the CVD method. The thickness is, for example, 50 nm.

[0101] 42, the SiN / SiO2 / Si laminated film is patterned using existing lithography and etching techniques as shown in the figure. In the DD' and CC' cross sections, the width of the SiN / SiO2 / Si laminated film portion after patterning is, for example, 50 nm.

[0102] In Fig. 43, an oxide film 610 is formed on the sidewall of the channel by thermal oxidation. The film thickness of 610 is, for example, 5 nm. Then, a Si film 611 is deposited by CVD. The film thickness of 611 is, for example, 350 nm. 611 is, for example, Si doped with phosphorus. After deposition, activation annealing is performed.

[0103] In FIG. 44, the Si film 611 is polished and flattened by CMP until it reaches approximately the same height as the SiN film.

[0104] In FIG. 45, the SiN film 402, part of the Si film 611, and the SiO2 film 401 are etched using dry etching, wet etching with hot phosphoric acid, wet etching with hydrofluoric acid, etc., to form the structure shown in FIG.

[0105] 46, a gate insulating film 612 is deposited by, for example, CVD. 612 is, for example, a SiO2 film, and has a thickness of, for example, 10 nm. Subsequently, a Si film 613 is deposited by CVD. 613 is, for example, Si doped with phosphorus, and has a deposited thickness of, for example, 50 nm. After the deposition of the Si film, activation annealing is performed.

[0106] 47, the Si / SiO2 laminated film is patterned using existing lithography and etching techniques. In the AA' cross section, the width of the Si / SiO2 laminated film portion after patterning is, for example, 60 nm. The width between patterns is also, for example, 60 nm.

[0107] 48, a gate insulating film 614 is deposited by, for example, CVD. 614 is, for example, an SiO2 film, and has a thickness of, for example, 10 nm.

[0108] 49, a Si film 615 is deposited by CVD. 615 is, for example, Si doped with phosphorus, and the deposited film thickness is, for example, 120 nm. After the Si film is deposited, activation annealing is performed.

[0109] In Fig. 50, the Si film 615 is etched back by a thickness of 120 nm. The resulting shape is as shown in Fig. 50, where the gates are positioned on the sides of the channel in the D-D' cross section and the C-C' cross section, thus obtaining the desired structure. The gates 112, 113, and 114 are each separated by an SiO2 film.

[0110] Contacts for supplying power to gates 601 and 602 may be made from the backside of the Si substrate (Fig. 51). 620 is a metal material for contacting 601, and 621 is an insulating film made of, for example, SiO2. This increases the degree of freedom in the positioning of the contacts and their wiring formed on the wafer surface side, allowing for a more flexible design, which in turn improves the reliability of the device.

[0111] Although the above explanation has been given mainly on the case where electrons are captured by quantum dots, the present invention is also effective in the case where holes are captured instead of electrons. In this case, the diffusion layers 101, 103, and 105 are P-type.

[0112] In the CC' cross-sectional structure of FIG. 69, a voltage smaller than the voltage at which channel 107 or 160 becomes a flat band is applied to gate 113, or a voltage smaller than the voltage applied to Si substrate 122 is applied to gate 113 (for example, 0 V is applied to 122 and -2 V is applied to 113), or a voltage smaller than the voltage applied to diffusion layers 101, 103, and 105 is applied to gate 113 (for example, 0 V is applied to 101, 103, and 105 and -2 V is applied to 113), or a voltage is applied under other voltage conditions such that holes are trapped under gate 113, while a voltage larger than the voltage applied to gate 113 is applied to gates 601 and 602.

[0113] For example, suppose a small voltage (e.g., −2 V) is applied to the gate 113, and a large voltage (2 V) is applied to the gates 601 and 602. Then, due to the influence of the electric field effect, holes are less likely to exist near the ends and sidewalls of the channel 107 close to the gates 601 and 602, and holes are more likely to exist only near the center of the channel, where the electric field effect from the gates 601 and 602 is less likely to reach.

[0114] 69(b) and 69(c), an ideal potential shape (i.e., a convex potential shape in which holes are captured only near the center of the channel and parasitic quantum dots are not generated at the channel edges) is formed. In the case of holes, the polarity is opposite to that of electrons, so a place with high potential is a stable place for holes.

[0115] In this embodiment, the gate is disposed adjacent to the entire sidewall of the channel, which is very effective in suppressing parasitic quantum dots on the entire sidewall of the channel.

[0116] In this example, another method and structure for suppressing parasitic quantum dots in the channel is disclosed. The structure is shown in Figure 52. Figure 52(a) shows the top view layout of the device.

[0117] The difference from the layouts explained so far (FIGS. 6 and 37) is that new gates 701, 702, and 703 have been added, and some of them are arranged above the channel. Figure 52(b) shows a cross-sectional view of the CC' cross section in Figure 52(a).

[0118] Gates 701 and 702 are arranged on either side of gate 113, with an insulating film 712 (e.g., SiO2) sandwiched therebetween. Portions of gates 701 and 702 are located above channel 107. Note that FIG. 52(b) shows the structure of this embodiment when fabricated using an SOI substrate. When the structure of this embodiment is fabricated using a normal Si substrate, it appears as shown in FIG. 52(c). In this case, channel portion 160 and Si substrate 122 are formed from a continuous member.

[0119] In this structure, a voltage higher than the voltage at which the channel 107 or 160 becomes a flat band is applied to the gate 113, or a voltage higher than the voltage applied to the Si substrate 122 is applied to the gate 113 (for example, 0 V is applied to 122 and 2 V is applied to 113), or a voltage higher than the voltage applied to the diffusion layers 101, 103, and 105 is applied to the gate 113 (for example, 0 V is applied to 101, 103, and 105 and 2 V is applied to 113), or a voltage is applied to the gate 113 under other voltage conditions such that electrons are trapped under the gate 113, while a voltage lower than the voltage applied to the gate 113 is applied to the gates 701 and 702. For example, suppose a large voltage (for example, 2 V) is applied to the gate 113 and a small voltage (−2 V) is applied to the gates 701 and 702.

[0120] As a result, due to the influence of this electric field effect, electrons are less likely to exist near the ends and sidewalls of the channel 107 close to the gates 701 and 702, and electrons are more likely to exist only near the center of the channel, where the electric field effect from the gates 701 and 702 is less likely to reach.

[0121] 52(b) and 52(c), an ideal potential is formed in which a depression exists only near the center of the channel, thereby suppressing the formation of parasitic quantum dots on the channel edges and sidewalls. Our investigations have shown that the effect of suppressing parasitic quantum dots can be obtained as long as the edges of gates 701 and 702 are located even slightly inside the channel edges, and that the effect of suppressing parasitic quantum dots can be obtained even more satisfactorily when the edges of gates 701 and 702 are located 5 nm or more inside the channel edges.

[0122] A manufacturing method for the device of Example 3 is shown in Figures 53 and onwards. In order to form a structure whose cross section is shown in Figures 52(b) and 52(c) in a layout like the top view of Figure 52(a), it is generally necessary to have a manufacturing method that results in a cross section like Figures 52(b) and 52(c) in a top view layout structure like Figure 53. Therefore, the process up to creating this structure will be explained by following the cross-sectional structures taken along lines A-A', C-C', and D-D' in the top view layout view of Figure 53. The completed form is shown in Figure 54.

[0123] 54 shows the completed form when fabricated using an SOI wafer. 122 is Si, 120 is SiO2 (BOX), 712, 714, and 716 are gate insulating films, for example, SiO2, 112, 113, and 114 are gates, for example, N-type polysilicon, 107 is, for example, non-doped Si or lightly doped P-type Si, and 701 and 702 are gates, for example, N-type Si.

[0124] The manufacturing method for the desired structure will be explained below, following the cross-sectional structures of A-A', C-C', and D-D', starting with Figure 55. The manufacturing method will be basically shown using an SOI wafer as an example, but the desired structure can also be manufactured using a normal Si substrate using the same manufacturing method. When using a Si substrate, the only difference is that 120 in the diagram should be regarded as Si instead of SiO2.

[0125] 55, an SOI wafer is prepared in which 122 is a Si substrate, 120 is SiO2 (BOX), and 107 is Si (non-doped Si or lightly doped P-type Si). The thickness of 120 is, for example, 145 nm, and the thickness of 107 is, for example, 55 nm.

[0126] 56, an SiO2 film 401 is formed by, for example, thermal oxidation. The thickness of the SiO2 film 401 is, for example, 5 nm. Thereafter, an SiN film 402 is formed by the CVD method. The thickness is, for example, 50 nm.

[0127] 57, the SiN / SiO2 / Si laminated film is patterned using existing lithography and etching techniques as shown in the figure. In the DD' and CC' cross sections, the width of the SiN / SiO2 / Si laminated film portion after patterning is, for example, 300 nm.

[0128] 58, an SiO2 film 711 is deposited by CVD. The thickness of 711 is, for example, 350 nm.

[0129] In FIG. 59, the SiO2 film 711 is polished and flattened by CMP until it reaches approximately the same height as the SiN film.

[0130] In Fig. 60, the 711 film is etched using hydrofluoric acid to lower the height of the 711 film. The SiN film is also etched and removed using hot phosphoric acid. The SiO2 on the bottom surface of the Si (107) is then removed by dry etching or wet etching using hydrofluoric acid. These processes result in the shape shown in Fig. 60.

[0131] In Fig. 61, a gate insulating film 712 is deposited by, for example, CVD. 712 is, for example, an SiO2 film, and has a thickness of, for example, 10 nm. Thereafter, a Si film 713 is deposited by CVD. 713 is, for example, Si doped with phosphorus, and has a deposited thickness of, for example, 30 nm. After the deposition of the Si film, activation annealing is performed.

[0132] In Fig. 62, the Si / SiO2 laminated film is processed using existing lithography and etching techniques to obtain the shape shown in Fig. 62. In the DD' cross section and CC' cross section, the width of the groove made of the Si / SiO2 film formed near the center of the channel is set to, for example, 70 nm.

[0133] 63, for example, SiO2 is deposited by CVD as the insulating film 714. The film thickness is, for example, 10 nm.

[0134] 64, a Si film 715 is deposited by CVD. 715 is, for example, Si doped with phosphorus, and the deposited film thickness is, for example, 50 nm. After the Si film is deposited, activation annealing is performed.

[0135] 65, the Si / SiO2 laminated film is patterned using existing lithography and etching techniques. In the AA' cross section, the width of the Si / SiO2 laminated film portion after patterning is, for example, 60 nm. The width between patterns is also, for example, 60 nm.

[0136] In Fig. 66, a gate insulating film 716 is deposited by, for example, CVD. 716 is, for example, an SiO2 film, and has a thickness of, for example, 10 nm. Thereafter, a Si film 717 is deposited by CVD. 717 is, for example, Si doped with phosphorus, and has a deposited film thickness of, for example, 120 nm. After the deposition of the Si film, activation annealing is performed.

[0137] In Fig. 67, the Si film 717 is etched back by a thickness of 120 nm. The shape after that is as shown in Fig. 67, where parts of the gates 701 and 702 are located above the channel in the D-D' cross section and the C-C' cross section, and the desired structure is obtained. The gates 112, 113, and 114 are separated from each other by SiO2 films.

[0138] Although the above explanation has been given mainly on the case where electrons are captured by quantum dots, the present invention is also effective in the case where holes are captured instead of electrons. In this case, the diffusion layers 101, 103, and 105 are P-type.

[0139] In the CC' cross-sectional structure of Figure 70, a voltage smaller than the voltage at which channel 107 or 160 becomes a flat band is applied to gate 113, or a voltage smaller than the voltage applied to Si substrate 122 is applied to gate 113 (for example, 0 V is applied to 122 and -2 V is applied to 113), or a voltage smaller than the voltage applied to diffusion layers 101, 103, and 105 is applied to gate 113 (for example, 0 V is applied to 101, 103, and 105 and -2 V is applied to 113), or a voltage is applied under other voltage conditions such that holes are trapped under gate 113, while a voltage larger than the voltage applied to gate 113 is applied to gates 701 and 702.

[0140] For example, suppose a small voltage (e.g., −2 V) is applied to gate 113, and a large voltage (2 V) is applied to gates 701 and 702. Then, due to the influence of the electric field effect, holes are less likely to exist near the ends and sidewalls of channel 107 close to gates 701 and 702, and holes are more likely to exist only near the center of the channel, where the electric field effect from gates 701 and 702 is less likely to reach. In other words, an ideal potential shape (i.e., a convex potential shape in which holes are captured only near the center of the channel and parasitic quantum dots are not generated at the channel ends) is formed, as shown in Figures 70(b) and 70(c). In the case of holes, since the polarity is opposite to that of electrons, a place with high potential is a stable place for holes.

[0141] This embodiment shows an example of the operation method of the quantum device shown in Examples 1 to 3. First, the operation of the device of Example 1 will be explained with reference to the top view of FIG.

[0142] For example, by applying 0 V to 101, a positive voltage (for example, 2 V) to 108-114, a positive voltage (for example, 2 V) to 115-117, and a positive voltage (for example, 2 V) to 103, electrons can be transported from 101 to 103. Furthermore, by applying a positive voltage (for example, 2 V) to 105 instead of 103, electrons can be transported from 101 to 105.

[0143] Furthermore, by applying a negative voltage (for example, -2 V) to the gate electrodes 108, 110, 112, and 114 and a positive voltage (for example, 2 V) to the gate electrodes 109, 111, and 113, it is possible to form quantum wells in which electrons are trapped under the gate electrodes 109, 111, and 113. Then, by further finely adjusting the voltages of these gate electrodes, it is possible to trap a desired number of electrons (even just one) in each quantum well (under 109, 111, and 113).

[0144] To transport electrons, for example, a pulsed positive voltage is applied to the gate electrode 108, and the application time of this pulsed positive voltage is set to a time sufficient for a desired number of electrons to move from 101 to 109, thereby enabling the desired number of electrons to be transported from 101 to 109. Of course, to move a desired number of electrons from 109 to 111, a pulsed positive voltage is applied to the gate 110, and the application time of this pulsed positive voltage is set to a time sufficient for a desired number of electrons to move from 109 to 111.

[0145] Such single electron transport and trapping methods have already been reported in many documents (see, for example, Non-Patent Documents 1-3).

[0146] Consider the case in FIG. 6(a) where a magnetic field B (>0) is applied in the direction perpendicular to the paper surface from the Si substrate side of the device toward the gate electrode side.

[0147] In the following description, when two or more electrons are captured under the gates 109, 111, and 113, the electron with the highest energy is the target of quantum manipulation.

[0148] The spin parallel to the applied magnetic field is defined as up spin, and the spin antiparallel to the applied magnetic field is defined as down spin. The spin of the electrons under 113 is kept in an up spin state.

[0149] Under these circumstances, by using a method that uses Rabi oscillations, it is possible to change the spin direction of each electron under 109 and 111 (corresponding to a rotation gate operation). In addition, by weakening the voltage applied to 110 and causing the electrons under 109 and 111 to interfere with each other, it is possible to swap the spins of the electrons (corresponding to a swap gate operation), or to perform a gate operation in which the rotation of one spin state depends on the spin state of the other (corresponding to a controlled NOT gate operation).

[0150] After performing such a calculation using gate operation, the strength of the negative voltage applied to 112 is slightly weakened, and the value of the positive voltage applied to 113 is slightly strengthened. By doing so, if the electrons under 111 are of up spin, the electrons under 111 cannot move to 113 due to the Pauli blockade, but if the electrons under 111 are of down spin, a state can be created in which the electrons under 111 can move to 113.

[0151] In other words, if the electron under 111 has down spin, that electron will move under 113 after a certain time has passed, and two electrons will remain under 113. On the other hand, if the electron under 111 has up spin, it cannot move under 113, and so only one electron will remain under 113 even after a certain time has passed. In other words, if we know the number of electrons that exist under 113 after a certain time has passed, we can know the spin state of the electron that existed under 111.

[0152] To read out the number of electrons, a readout method using a single-electron transistor in a quantum well formed under gate 116 is used. This method is as follows. For example, 0 V is applied to 103, 0.1 V to 105, a negative voltage is applied to 115 and 117, and a positive voltage is applied to 116. Then, by bringing the magnitude of the negative voltages to 115 and 117 closer to 0, electrons can tunnel from 103 to 105. The value of the tunnel current at this time changes depending on the number of electrons present in 113. By reading this change, the number of electrons present in 113 can be determined.

[0153] In order to suppress the possibility of parasitic quantum dots being generated at the bottom of the channel, a negative voltage (−2 V) may also be applied to the Si substrate 122 .

[0154] Although the above operation has been explained using electrons as an example, similar quantum operations can of course also be performed using holes. In that case, the diffusion layers 101, 103, and 105 are P-type. In the above-described operation, electrons are replaced with holes, and the positive and negative voltages applied to the gates and diffusion layers are reversed.

[0155] By operating the device of Example 1 as described above, highly accurate quantum manipulation becomes possible while suppressing parasitic quantum dots.

[0156] Next, the operation of the device of Example 2 will be described with reference to the top view of FIG. 37( a). The difference from the device of Example 1 is the presence of gates 601, 602, and 603. To prevent parasitic quantum dots of electrons from forming at the ends and sidewalls of the channel, a voltage smaller than the voltage applied to gates 109, 111, and 113 (for example, −2 V to gates 601, 602, and 603, and 2 V to gates 109, 111, and 113) is applied to gates 601, 602, and 603. In addition, to suppress the possibility of parasitic quantum dots being generated at the bottom of the channel, a negative voltage (−2 V) may also be applied to Si substrate 122.

[0157] Thereafter, by manipulating the gate voltage and magnetic field in the same manner as in the device operation of the first embodiment described above, highly accurate quantum manipulation becomes possible while suppressing the parasitic quantum dots.

[0158] Of course, similar quantum operations using holes are also possible. In that case, the diffusion layers 101, 103, and 105 are P-type. In the above-described operation, electrons are replaced with holes, and the positive and negative voltages applied to the gate and diffusion layers are reversed. By performing the above-described operation in the device of Example 2, highly accurate quantum operations are possible while suppressing parasitic quantum dots.

[0159] Next, the operation of the device of Example 3 will be described with reference to the top view of FIG.

[0160] The difference from the device of Example 1 is the presence of gates 701, 702, and 703. To prevent parasitic quantum dots of electrons from being formed at the ends and sidewalls of the channel, a voltage smaller than that applied to gates 109, 111, and 113 (for example, −2 V to gates 701, 702, and 703, and 2 V to gates 109, 111, and 113) is applied to gates 701, 702, and 703. A negative voltage (−2 V) may also be applied to Si substrate 122 to suppress the possibility of parasitic quantum dots being formed at the bottom of the channel.

[0161] Thereafter, by manipulating the gate voltage and magnetic field in the same manner as in the device operation of the first embodiment described above, highly accurate quantum manipulation becomes possible while suppressing the parasitic quantum dots.

[0162] Of course, a similar quantum operation can also be performed using holes. In that case, the diffusion layers 101, 103, and 105 are P-type. In the above-described operation, electrons are replaced with holes, and the positive and negative voltages applied to the gates and diffusion layers are reversed.

[0163] By operating the device of Example 3 as described above, highly accurate quantum manipulation becomes possible while suppressing parasitic quantum dots.

[0164] According to the above embodiment, potential wells due to electric field concentration at the semiconductor channel edge are unlikely to be formed, so that the generation of parasitic quantum dots is suppressed, and highly accurate quantum bit manipulation and calculation can be achieved.

[0165] 101 Diffusion layer 103 Diffusion layer 105 Diffusion layer 107 Channel 108 Gate 109 Gate 110 Gate 111 Gate 112 Gate 113 Gate 114 Gate 115 Gate 116 Gate 117 Gate 120 Silicon oxide film 122 Silicon substrate 160 Channel 300 Insulating film 301 Electron 401 Insulating film 402 Silicon nitride film 403 Insulating film 404 Insulating film 405 Gate material 406 Gate insulating film 407 Gate material 420 Insulating film 601 Gate 602 Gate 603 Gate 610 Insulating film 611 Gate material 612 Insulating film 613 Gate material 614 Insulating film 615 Gate material 620 Wiring 621 Insulating film 701 Gate 702 Gate 703 Gate 711 Insulating film 712 Insulating film 713 Gate material 714 Gate insulating film 715 Gate material 716 Insulating film 717 Gate material

Claims

1. A quantum device comprising: a first layer having a semiconductor channel extending in a first direction defined by an element isolation structure; and a first gate electrode disposed on top of the first layer, extending in a second direction different from the first direction, and forming quantum dots in the semiconductor channel, wherein, in a cross-sectional view in the second direction, an end of the underside of the first gate electrode is disposed more inward than an end of the semiconductor channel.

2. A quantum device according to claim 1, further comprising a second gate electrode extending in the second direction and adjusting the potential at the end of the semiconductor channel by applying a predetermined voltage thereto.

3. The quantum device according to claim 2, wherein the second gate electrode is disposed laterally of the first gate electrode in a second layer having the first gate electrode.

4. The quantum device according to claim 1, wherein electrons or holes are trapped in the quantum dots.

5. The quantum device according to claim 2, wherein electrons or holes are trapped in the quantum dots.

6. The quantum device according to claim 2, characterized in that a voltage is applied to the first gate electrode such that the electrons or holes are captured by the quantum dot, and when the electrons are to be confined in the quantum dot, a voltage smaller than the voltage applied to the first gate electrode is applied to the second gate, and when the holes are to be confined in the quantum dot, a voltage larger than the voltage applied to the first gate electrode is applied to the second gate, thereby adjusting the potential near the end of the channel.

7. The quantum device of claim 1, wherein when the quantum dot captures the electron, the potential near the center of the semiconductor channel is lowest when viewed in cross section in the second direction, and when the quantum dot captures the hole, the potential near the center of the semiconductor channel is highest when viewed in cross section in the second direction.

8. The quantum device according to claim 1, wherein, when viewed cross-sectionally in the second direction, the edge of the lower surface of the first gate electrode is 5 nm or more inward from the edge of the semiconductor channel.

9. The quantum device according to claim 1, wherein quantum manipulation or quantum operation is performed on the electrons or holes captured in the quantum dots.

10. A quantum device having a first layer having a semiconductor channel extending in a first direction, and a first gate electrode disposed on top of the first layer, extending in a second direction different from the first direction, and forming a quantum dot in the semiconductor channel, characterized in that it also has a second gate electrode extending in the second direction and adjusting the potential of an end of the semiconductor channel by applying a predetermined voltage thereto.

11. The quantum device of claim 10, wherein the second gate electrode is disposed in the first layer on a side of the semiconductor channel.

12. The quantum device according to claim 10, wherein electrons or holes are trapped in the quantum dots.

13. The quantum device described in claim 12, characterized in that a voltage is applied to the first gate electrode such that the electrons or holes are captured in the quantum dot, and when the electrons are to be confined in the quantum dot, a voltage smaller than the voltage applied to the first gate electrode is applied to the second gate, and when the holes are to be confined in the quantum dot, a voltage larger than the voltage applied to the first gate electrode is applied to the second gate, thereby adjusting the potential near the end of the channel.

14. The quantum device described in claim 12, characterized in that when the quantum dot captures the electron, the potential near the center of the semiconductor channel is lowest when viewed in cross section in the second direction, and when the quantum dot captures the hole, the potential near the center of the semiconductor channel is highest when viewed in cross section in the second direction.

15. The quantum device according to claim 12, wherein quantum manipulation or quantum operation is performed on the electrons or holes captured in the quantum dots.

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