Multi-level inverter and electric motor system

Abstract

This multi-level inverter comprises: a first terminal and a second terminal to which DC voltage is applied; a third terminal; a first switching element and a capacitor which are sequentially connected in series between the second terminal and the third terminal; a second switching element which is connected between the first terminal and a connecting point between the first switching element and the capacitor; a switching circuit; and a control circuit. The switching circuit is a circuit having: a plurality of switch units connected in series between the first terminal and the third terminal; and output terminals. The switching circuit generates potentials at a plurality of levels including the potential of the second terminal, and outputs the potentials at the plurality of levels from the output terminals. The control circuit controls switching of the first switching element, the second switching element, and the plurality of switch units.

Description

Multilevel inverter and electric motor system

[0001] The present disclosure relates to a multilevel inverter and an electric motor system.

[0002] Conventionally, multilevel inverters have been used as inverters that convert DC voltages into voltages of multiple levels and output the voltages (see, for example, Patent Documents 1 and 2 listed below). By using such multilevel inverters, it is possible to reduce voltage fluctuations, current ripples, and noise compared to two-level inverters.

[0003] JP 2008-161003 A JP 2002-58256 A

[0004] In conventional multilevel inverters, the voltage utilization factor, which is the effective value of the output voltage divided by the input voltage, is determined by the power supply voltage, modulation method, etc. The magnitude of this voltage utilization factor limits the performance of the electric motor that can be driven by the multilevel inverter. Therefore, it is desirable to improve the voltage utilization factor in multilevel inverters.

[0005] The present disclosure describes a multilevel inverter and motor system capable of achieving higher voltage utilization.

[0006] A multilevel inverter according to one aspect of the present disclosure includes first and second terminals to which a DC voltage is applied, a third terminal, a first switching element and a capacitor connected in series in order between the second and third terminals, a second switching element connected between the first terminal and a connection point between the first switching element and the capacitor, a switching circuit, and a control circuit that controls switching of the first switching element, the second switching element, and a plurality of switch units. The switching circuit is a circuit having a plurality of switch units connected in series between the first and third terminals and an output terminal. The switching circuit generates a plurality of levels of potential including the potential of the second terminal and outputs the a plurality of levels of potential from the output terminal. The control circuit controls switching of the first switching element, the second switching element, and the plurality of switch units.

[0007] The multilevel inverter and motor system of the present disclosure can achieve a higher voltage utilization rate.

[0008] FIG. 1 is a schematic diagram of a multilevel inverter 1 according to an embodiment of the present disclosure. FIG. 2 is a circuit diagram showing a configuration of a multilevel inverter circuit 2. FIG. 3 is a diagram showing example time waveforms of phase currents, phase voltages, and line voltages generated by the multilevel inverter circuit 2, and an example time waveform of a voltage across a capacitor CL. FIG. 4 is a waveform diagram illustrating the control state of a switching circuit SWu in a control circuit 3. FIG. 5 is a table illustrating the control state modes of the switching circuit SWu in the control circuit 3. FIG. 6 is a circuit diagram illustrating the control state modes of the switching circuit SWu. FIG. 7 is a circuit diagram illustrating the control state modes of the switching circuit SWu. FIG. 8 is a waveform diagram showing the time waveforms of drive pulses of transistors Q1 and Q2. FIG. 9 is a schematic diagram showing the configuration of an electric motor system 100 according to another embodiment of the present disclosure. FIG. 10 is a circuit diagram illustrating the configuration of a multilevel inverter circuit 2 according to another embodiment of the present disclosure. FIG. 11 is a circuit diagram illustrating the configuration of a multilevel inverter circuit 20 according to another embodiment of the present disclosure.

[0009] A multilevel inverter according to one aspect of the present disclosure includes first and second terminals to which a DC voltage is applied, a third terminal, a first switching element and a capacitor connected in series in order between the second and third terminals, a second switching element connected between the first terminal and a connection point between the first switching element and the capacitor, a switching circuit, and a control circuit. The switching circuit is a circuit having a plurality of switch units connected in series between the first and third terminals and an output terminal. The switching circuit generates multiple levels of potential including the potential of the second terminal and outputs the multiple levels of potential from the output terminal. The control circuit controls switching of the first switching element, the second switching element, and the plurality of switch units.

[0010] In this multilevel inverter, a control circuit controls the switching of the first switching element and the second switching element. In a conventional multilevel inverter, a DC voltage is applied between the first terminal and the third terminal, and the potential fluctuation of the second terminal is controlled. As a result, a voltage half the DC voltage is applied between the first terminal and the second terminal and between the second terminal and the third terminal. On the other hand, according to one aspect of the present disclosure, when a plurality of switch units are switched in a specific pattern in multilevel inverter control, which is control for outputting a plurality of voltage levels, the first switching element and the second switching element are complementarily switched, thereby making it possible to charge a capacitor to a voltage equal to the DC voltage. For example, when one of the plurality of switch units is turned off, the first switching element is turned off and the second switching element is turned on, thereby applying a DC voltage and charging the capacitor. This makes it possible to apply a voltage equal to the DC voltage between the first terminal and the second terminal and between the second terminal and the third terminal without affecting the conventional multilevel inverter control. As a result, it is possible to double the voltage output from the output terminal of the switching circuit compared to a conventional multilevel inverter, and therefore the multilevel inverter can output a voltage close to the input voltage, thereby achieving a higher voltage utilization rate.

[0011] In the above aspect, the control circuit may turn off the first switching element and turn on the second switching element when the switching states of the plurality of switch units in the switching circuit are in a first state. The control circuit may turn on the first switching element and turn off the second switching element when the switching states of the plurality of switch units in the switching circuit are in a second state. In this case, when the switching states of the plurality of switch units are in the first state, the capacitor is charged to a voltage equal to the DC voltage. This allows the capacitor to be charged to a voltage equal to the DC voltage without affecting multilevel inverter control, so that a voltage equal to the DC voltage can be applied between the first terminal and the second terminal and between the second terminal and the third terminal. As a result, the output voltage from the output terminals of the switching circuit can be doubled compared to conventional multilevel inverters.

[0012] In the above aspect, the first state may be a state in which a switch unit connected to the third terminal among the plurality of switch units is turned off. The second state may be a state in which a switch unit connected to the third terminal among the plurality of switch units is turned on. In this case, the capacitor can be charged to a voltage equal to the DC voltage without affecting multilevel inverter control, and therefore the same voltage as the DC voltage can be applied between the first terminal and the second terminal and between the second terminal and the third terminal. As a result, the output voltage from the output terminal of the switching circuit can be doubled compared to a conventional multilevel inverter.

[0013] In the above aspect, the plurality of switch units include a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit. In the switching circuit, the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are connected in series between a first terminal and a third terminal, in that order, and the output terminal is connected to a connection point between the second switch unit and the third switch unit. The switching circuit may include a first clamp diode connected to the second terminal and the connection point between the first switch unit and the second switch unit, and a second clamp diode connected to the second terminal and the connection point between the third switch unit and the fourth switch unit. With this configuration, the first switch unit and the third switch unit are switched complementarily, and the second switch unit and the fourth switch unit are switched complementarily, thereby allowing the switching circuit to output three levels of potential, including the potential of the second terminal. This allows the first and second switching elements to be complementarily switched in response to control to output three-level voltages, thereby charging the capacitor to the same voltage as the DC voltage. As a result, in a multilevel inverter that outputs three-level voltages, it is possible to output a voltage close to the input voltage, thereby achieving a higher voltage utilization rate.

[0014] In the above aspect, the control circuit may turn off the first switching element and turn on the second switching element when the fourth switch unit is off in the switching circuit. In the switching circuit, the control circuit may turn on the first switching element and turn off the second switching element when the fourth switch unit is on. In this case, when the fourth switch unit is switched in a specific pattern in multilevel inverter control, the first switching element and the second switching element are complementarily switched. This allows the capacitor to be charged to a voltage equal to the DC voltage without affecting multilevel inverter control, and therefore allows the same voltage as the DC voltage to be applied between the first terminal and the second terminal and between the second terminal and the third terminal. As a result, the output voltage from the output terminal of the switching circuit can be doubled compared to a conventional multilevel inverter.

[0015] In the above aspect, the capacitor may be a film capacitor, in which case the capacitor can be charged to a voltage equal to the DC voltage even when the switching speeds of the first switching element and the second switching element are increased.

[0016] Furthermore, an electric motor system according to one aspect of the embodiment may include the multilevel inverter according to the above aspect and an electric motor connected to an output terminal of the multilevel inverter. With this configuration, it is possible to apply a voltage close to the input voltage to the electric motor. As a result, it is possible to drive an electric motor with higher performance. Furthermore, it is possible to reduce the magnitude of the current flowing through the electric motor, thereby suppressing heat generation in the electric motor. This makes it possible to reduce the cooling area of ​​the electric motor. Furthermore, it is possible to double the voltage applied to the electric motor without providing a power converter including a large-capacity capacitor and inductor, or a transformer. As a result, it is possible to reduce the size and weight of the electric motor system. Furthermore, compared to a conventional multilevel inverter, when driving an electric motor with the same performance, it is possible to reduce the DC voltage applied to the multilevel inverter by half.

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and redundant description will be omitted.

[0018] FIG. 1 is a schematic diagram of a multilevel inverter 1 according to an embodiment of the present disclosure. The multilevel inverter 1 shown in the figure is a power conversion system that converts DC power into AC power. The multilevel inverter 1 is a power conversion system that drives an externally connected electric motor in a three-phase, three-wire system. The multilevel inverter 1 is, for example, a three-level NPC-type multilevel inverter. The multilevel inverter 1 may be capable of outputting three-level voltages. For example, the multilevel inverter 1 may be a three-level T-type type, a three-level ANPC type, or a drive system other than those described above. The multilevel inverter 1 includes a multilevel inverter circuit 2 and a control circuit 3 that controls the operation of the multilevel inverter circuit 2.

[0019] Here, a description will be given of the circuit configuration of the multilevel inverter circuit 2. FIG.

[0020] The multilevel inverter circuit 2 has a first terminal IN1 and a second terminal IN2 to which a DC voltage Vdc is applied from the outside, and a third terminal P3. For example, the DC voltage Vdc is applied to the first terminal IN1 and the second terminal IN2 so that the first terminal IN1 has a higher voltage than the second terminal IN2. The multilevel inverter circuit 2 has a capacitor CH connected between the first terminal IN1 and the second terminal IN2. The capacitor CH is charged by applying the DC voltage Vdc across the capacitor CH.

[0021] The multilevel inverter circuit 2 includes a transistor Q1 (first switching element) and a capacitor CL connected in series between a second terminal IN2 and a third terminal P3. Additionally, the multilevel inverter circuit 2 includes a transistor Q2 (second switching element) connected between the first terminal IN1 and a connection point P4 between the transistor Q1 and the capacitor CL. The multilevel inverter circuit 2 includes diodes D1 and D2 connected in parallel to the transistors Q1 and Q2, respectively.

[0022] The transistors Q1 and Q2 are, for example, N-type field effect transistors (FETs). The source terminal of the transistor Q1 is connected to the second terminal IN2. The drain terminal of the transistor Q1 is connected to the connection point P4. The source terminal of the transistor Q2 is connected to the connection point P4. The drain terminal of the transistor Q2 is connected to the first terminal IN1. A control voltage is applied to the gate terminals of the transistors Q1 and Q2 from the control circuit 3, and the transistors Q1 and Q2 are switched in response to the control voltage. The diodes D1 and D2 are configured such that the cathode terminals of the diodes D1 and D2 are connected to the drain terminals of the transistors Q1 and Q2, respectively, and the anode terminals of the diodes D1 and D2 are connected to the source terminals of the transistors Q1 and Q2, respectively. These diodes D1 and D2 are elements for forming a path for an output current that flows backward through the transistors Q1 and Q2. The transistors Q1 and Q2 are driven complementarily. For example, when transistor Q1 is on (conducting), transistor Q2 is off (non-conducting), and when transistor Q1 is off, transistor Q2 is on.

[0023] When switching the transistors Q1 and Q2 on and off, both transistors Q1 and Q2 are turned off for a moment to prevent the transistors Q1 and Q2 from being turned on at the same time. For example, before turning on one of the two transistors Q1 and Q2, the other of the two transistors Q1 and Q2 is turned off.

[0024] The multilevel inverter circuit 2 has three switching circuits SWu, SWv, and SWw connected in parallel to two capacitors CH and CL between the first terminal IN1 and the third terminal P3, and three output terminals OUTu, OUTv, and OUTw connected to the three switching circuits SWu, SWv, and SWw, respectively.

[0025] Next, the configuration of the switching circuits SWu, SWv, and SWw will be described.

[0026] The switching circuit SWu includes a first switch section SW1, a second switch section SW2, a third switch section SW3, a fourth switch section SW4, and two clamp diodes DH and DL between the first terminal IN1 and the third terminal P3. The first switch section SW1, the second switch section SW2, the third switch section SW3, and the fourth switch section SW4 are connected in series in this order between the first terminal IN1 and the third terminal P3. The first switch section SW1 includes a transistor QHU and a diode DHU connected in parallel with the transistor QHU. The second switch section SW2 includes a transistor QHD and a diode DHD connected in parallel with the transistor QHD. The third switch section SW3 includes a transistor QLU and a diode DLU connected in parallel with the transistor QLU. The fourth switch section SW4 includes a transistor QLD and a diode DLD connected in parallel to the transistor QLD. The first switch section SW1, the second switch section SW2, the third switch section SW3, and the fourth switch section SW4 each constitute an arm.

[0027] The transistors QHU, QHD, QLU, and QLD are, for example, N-type field effect transistors (FETs). The drain terminal of each of the transistors QHU, QHD, QLU, and QLD is connected to a first terminal IN1 (high voltage) and a source terminal is connected to a third terminal P3 (low voltage). A control voltage is applied to each of the gate terminals of the transistors QHU, QHD, QLU, and QLD from a control circuit 3, and the transistors QHU, QHD, QLU, and QLD are switched in response to the control voltage. The diodes DHU, DHD, DLU, and DLD are configured such that the cathode terminals of the transistors QHU, QHD, QLU, and QLD are connected to the drain terminals of the transistors QHU, QHD, QLU, and QLD, respectively, and the anode terminals of the transistors QHU, QHD, QLU, and QLD are connected to the source terminals of the transistors QHU, QHD, QLU, and QLD, respectively. The diodes DHU, DHD, DLU, and DLD are elements for forming a path for the output current that flows backward through the transistors QHU, QHD, QLU, and QLD.

[0028] Although FIG. 2 shows the transistor QHU and the diode DHU as separate elements, they may be provided as a single element. For example, if the transistor QHU is implemented as a MOSFET, the diode DHU may not be provided. In this case, the drain terminal of the transistor QHU is connected to the first terminal IN1, and the source terminal is connected to the third terminal P3. A body diode is provided between the source and drain terminals of the transistor QHU. The body diode provides a path for the output current flowing back through the MOSFET. In this way, the body diode in the transistor QHU, which is a MOSFET, replaces the function of the diode DHU in FIG. 6. Similarly, the transistor QHD and the diode DHD, the transistor QLU and the diode DLU, and the transistor QLD and the diode DLD may each be provided as a single element.

[0029] The clamp diode (first clamp diode) DH is configured such that its anode terminal is connected to the second terminal IN2 and its cathode terminal is connected to the connection point between the two transistors QHU and QHD. The clamp diode (second clamp diode) DL is configured such that its cathode terminal is connected to the second terminal IN2 and its anode terminal is connected to the connection point between the two transistors QLU and QLD. The clamp diode DH has the role of clamping the potential of the connection point between the two arms on the first terminal IN1 side, i.e., the potential of the connection point between the two transistors QHU and QHD, to the potential of the second terminal IN2 when this potential becomes lower than the potential of the second terminal IN2. The clamp diode DL has the role of clamping the potential of the connection point between the two arms on the third terminal P3 side, i.e., the potential of the connection point between the two transistors QLU and QLD, to the potential of the second terminal IN2 when the potential of the connection point becomes equal to or higher than the potential of the second terminal IN2.

[0030] The configurations of the other two switching circuits SWv and SWw are the same as that of the switching circuit SWu. The three output terminals OUTu, OUTv, and OUTw are connected to the connection point between the second switch section SW2 and the third switch section SW3 of the switching circuits SWu, SWv, and SWw, respectively, that is, the connection point between the two transistors QHD and QLU.

[0031] The control circuit 3 is an integrated circuit (IC) that controls the operation of the multilevel inverter circuit 2. Specifically, the control circuit 3 generates phase voltages in each of the three switching circuits SWu, SWv, and SWw, which fluctuate between three voltage levels including the potential of the second terminal IN2, and controls the operation of the multilevel inverter circuit 2 so that, as a result of generating the phase voltages, phase currents that periodically increase and decrease are output from the three output terminals OUTu, OUTv, and OUTw. FIG. 3 shows examples of time waveforms of the phase currents, phase voltages, and line voltages generated by the multilevel inverter circuit 2, as well as an example of a time waveform of the voltage across the capacitor CL. FIG. 3(a) shows the time waveforms of the phase currents Iu, Iv, and Iw output from the output terminals OUTu, OUTv, and OUTw, respectively. FIG. 3(b) shows the time waveform of the phase voltage Vu at the output terminal OUTu. FIG. 3(c) shows the time waveform of the line voltage Vuv between the output terminals OUTu and OUTv. FIG. 3(d) shows the DC voltage Vdc and the voltage V across the capacitor CL. ＣＬ3 shows a time waveform of the phase voltage Vu. FIG. 3 shows a case where a DC voltage Vdc is input to the multilevel inverter circuit 2 and a three-phase motor is connected to the output terminals OUTu, OUTv, and OUTw. In FIG. 3, a phase voltage Vu is generated so as to periodically fluctuate between three voltage levels: 0 V, which is the potential of the second terminal IN2, +Vdc, and −Vdc, and is output from the output terminal OUTu. As a result, phase voltages Vv and Vw with similar waveforms but shifted in phase from each other are generated at the output terminals OUTv and OUTw, and a voltage with a waveform that periodically fluctuates between five voltage levels is generated as the line voltage Vuv. As a result, when an electric motor such as a three-phase motor is connected as a load to the output terminals OUTu, OUTv, and OUTw, the multilevel inverter circuit 2 can output phase currents Iu, Iv, and Iw that are shifted in phase from each other from the output terminals OUTu, OUTv, and OUTw.

[0032] FIG. 4 is a waveform diagram illustrating the control state of the switching circuit SWu using the carrier level shift method in the control circuit 3. FIGS. 4(a), 4(b), and 4(c) each show the time change of the control signal. FIG. 4(d) shows the time change of the phase voltage Vu. FIG. 5 is a diagram illustrating the control state modes of the switching circuit SWu using the carrier level shift method in the control circuit 3. FIGS. 6 and 7 are circuit diagrams showing the switching circuit SWu in each operation mode. FIGS. 6(a) and 7(a) show the circuit for operation mode "1." FIGS. 6(b) and 7(b) show the circuit for operation mode "2" or "3." FIGS. 6(c) and 7(c) show the circuit for operation mode "4."

[0033] When controlling the switching circuit SWu, the control circuit 3 references two triangular carrier waves CA1 and CA2 whose signal levels are shifted up and down, and a modulating wave MS, which is a sine wave whose signal level periodically fluctuates across the two triangular waves (FIG. 4(a)). The control circuit 3 then compares the levels of the carrier CA1 and the modulating wave MS and generates a pulse modulated wave (FIG. 4(b)) that changes between "0" and "1" depending on the comparison result. The control circuit 3 then compares the levels of the carrier CA2 and the modulating wave MS and generates a pulse modulated wave (FIG. 4(c)) that changes between "0" and "1" depending on the comparison result. Furthermore, the control circuit 3 classifies the operation mode into three modes: an operating mode "1," an operating mode "2" or "3," and an operating mode "4" depending on the values ​​of the two pulse modulated waves. The control circuit 3 then controls the four transistors QHU, QHD, QLU, and QLD of the switching circuit SWu to switch in accordance with the three operating modes. In addition, the control circuit 3 controls the transistors Q1 and Q2 to switch in accordance with the operation modes "1", "2", or "3", as well as "4", of the switching circuits SWu, SWv, and SWw. When each of the switching circuits SWu, SWv, and SWw in the multilevel inverter 1 transitions from operation mode "1" to operation mode "4", it always passes through operation mode "2" or "3". When each of the switching circuits SWu, SWv, and SWw in the multilevel inverter 1 transitions from operation mode "4" to operation mode "1", it always passes through operation mode "2" or "3".

[0034] As shown in FIG. 5, in operation mode "1", the comparison result of carrier CA1 is "1" and the comparison result of carrier CA2 is "1". In operation mode "1", transistors QHU and QHD are turned on and transistors QLU and QLD are turned off. As a result, the output voltage of switching circuit SWu is set to +Vdc, which is the potential of first terminal IN1 (FIG. 6(a)). Also, in operation mode "1", transistor Q1 may be turned off and transistor Q2 may be turned on, thereby charging capacitor CL (FIG. 7(a)). In operation mode "1", transistor Q1 may be turned on and transistor Q2 may be turned off, thereby discharging capacitor CL.

[0035] In operation modes "2" and "3," the comparison result of carrier CA1 is "0" and the comparison result of carrier CA2 is "1." In operation modes "2" and "3," transistors QHD and QLU are turned on and transistors QHU and QLD are turned off. As a result, the output voltage of the switching circuit SWu is set to 0 V, which is the potential of the second terminal IN2 (FIG. 6B). Whether operation mode "2" or "3" is selected depends on the energization state of the motor to which the multilevel inverter circuit 2 outputs voltage. Operation mode "2" is an operation mode in which the output current of the switching circuit SWu is set to a "positive direction" that flows toward the motor. Operation mode "3" is an operation mode in which the output current of the switching circuit SWu is set to a "negative direction" that flows from the motor. In operation modes "2" and "3," transistor Q1 may be turned off and transistor Q2 may be turned on, thereby charging capacitor CL (FIG. 7B). In the case of operation mode "2" or "3", the transistor Q1 may be turned on and the transistor Q2 may be turned off, thereby discharging the capacitor CL.

[0036] In operation mode "4", the comparison result of carrier CA1 is "0" and the comparison result of carrier CA2 is "0". In operation mode "4", transistors QHU and QHD are turned off and transistors QLU and QLD are turned on. As a result, the output voltage of switching circuit SWu is set to -Vdc, which is the potential of third terminal P3 (FIG. 6(c)). In operation mode "4", transistor Q1 is turned on and transistor Q2 is turned off, thereby discharging capacitor CL (FIG. 7(c)).

[0037] The control circuit 3 turns off the transistor Q1 and turns on the transistor Q2 when the switching states of the multiple switch units SW1 to SW4 in all of the switching circuits SWu, SWv, and SWw are in a first state. The first state is a state in which the fourth switch unit SW4, which is connected to the third terminal P3 among the multiple switch units SW1 to SW4, is turned off. For example, the control circuit 3 turns off the transistor Q1 and turns on the transistor Q2 when all of the switching circuits SWu, SWv, and SWw are in operation mode "1," "2," or "3." As a result, by connecting the capacitor CL in parallel with the DC voltage Vdc, the voltage Vdc is applied to the capacitor CL, and the capacitor CL is charged (FIGS. 7A and 7B).

[0038] The control circuit 3 turns on the transistor Q1 and turns off the transistor Q2 when the switching states of the multiple switch units SW1 to SW4 in at least one of the switching circuits SWu, SWv, and SWw are in the second state. The second state is a state in which the fourth switch unit SW4 connected to the third terminal P3 among the multiple switch units SW1 to SW4 is on. For example, the control circuit 3 turns on the transistor Q1 and turns off the transistor Q2 when at least one of the switching circuits is in the operating mode "4." This connects the capacitor CL in series with the DC voltage Vdc between the first terminal IN1 and the third terminal P3, thereby discharging the capacitor CL (FIG. 7(c)). At this time, because the capacitor CL is in a charged state, the third terminal P3 is set to a voltage lower than the second terminal IN2 by the voltage Vdc, and the potential of the third terminal P3 is set to -Vdc.

[0039] FIG. 8 is a waveform diagram showing the time waveforms of the drive pulses of transistors Q1 and Q2. As shown in FIG. 8, when all of the switching circuits SWu, SWv, and SWw are in operation mode "1," "2," or "3," the control circuit 3 sets the drive pulse to "1" to turn off transistor Q1 and turn on transistor Q2. This causes the control circuit 3 to control the capacitor CL to charge. When at least one of the switching circuits is in operation mode "4," the control circuit 3 sets the drive pulse to "0" to turn on transistor Q1 and turn off transistor Q2. This causes the control circuit 3 to control the capacitor CL to discharge. Note that if the switching of transistors Q1 and Q2 is too late, the control circuit 3 may set the drive pulse to "1" when all of the switching circuits SWu, SWv, and SWw are in operation mode "1," "2," or "3."

[0040] In this way, the transistors Q1 and Q2 are switched in response to the switching of the operation modes in the switching circuits SWu, SWv, and SWw, thereby charging and discharging the capacitor CL.ＣＬ In the example shown in FIG. 3(d), the voltage V across the capacitor CL is maintained at Vdc. ＣＬ is maintained at about Vdc.

[0041] The configuration of an electric motor system according to another embodiment of the present disclosure will be described. Fig. 9 is a schematic diagram showing the configuration of an electric motor system 100. The electric motor system 100 includes the multilevel inverter 1 described above and a three-phase motor system 10, which is an electric motor connected to the output terminals OUTu, OUTv, and OUTw of the multilevel inverter circuit 2. The three-phase motor system 10 incorporates an inductor and a three-phase motor, and is configured so that the three-phase motor is connected to the output terminals OUTu, OUTv, and OUTw via the inductor. However, a generator may be used as the electric motor connected to the multilevel inverter 1, and the multilevel inverter 1 may be used for power regeneration of the electric motor system 100.

[0042] The effects of the multilevel inverter 1 and the electric motor system 100 according to the above-described embodiment will now be described. In conventional multilevel inverters, the voltage utilization factor, which is the effective value of the output voltage divided by the input voltage, is determined by the power supply voltage, modulation method, and the like. The magnitude of this voltage utilization factor limits the performance of the electric motor that can be driven by the multilevel inverter. Therefore, improving the voltage utilization factor is desirable in multilevel inverters. However, in conventional multilevel inverters, the voltage output from each output terminal is half the input voltage, so the maximum difference in output voltage between the output terminals is the same as the input voltage. Therefore, in conventional multilevel inverters, in order to improve the voltage utilization factor, it was necessary to devise a PWM modulation method focusing on space vector modulation, etc. Furthermore, in conventional multilevel inverters, a transformer or a DC / DC converter was required to increase the power supply voltage.

[0043] In a conventional multilevel inverter, a DC voltage is applied between the first terminal IN1 and the third terminal P3, and the voltage of the second terminal IN2 is controlled (intermediate potential fluctuation control is executed). As a result, a voltage that is half the DC voltage Vdc is applied between the first terminal IN1 and the second terminal IN2 and between the second terminal IN2 and the third terminal P3.

[0044] In contrast, in the multilevel inverter 1 according to the embodiment, the control circuit 3 controls the switching of the transistors Q1 and Q2. With this configuration, when the multiple switch units SW1 to SW4 are switched in a specific pattern in multilevel inverter control, which is control for outputting multiple-level voltages, the transistors Q1 and Q2 are complementarily switched, thereby charging the capacitor CL to a voltage equal to the DC voltage Vdc. For example, when the fourth switch unit SW4 is turned off, the transistor Q1 is turned off and the transistor Q2 is turned on, thereby charging the capacitor CL to a voltage equal to the DC voltage Vdc. This makes it possible to apply a voltage equal to the DC voltage Vdc between the first terminal IN1 and the second terminal IN2 and between the second terminal IN2 and the third terminal P3 without affecting conventional multilevel inverter control. As a result, it is possible to double the voltages output from the output terminals OUTu, OUTv, and OUTw of the switching circuits SWu, SWv, and SWw compared to conventional multilevel inverters. In other words, the multilevel inverter 1 can output a doubled voltage without connecting multiple power sources or using a transformer. Therefore, the multilevel inverter 1 can output a voltage close to the input voltage, thereby achieving a higher voltage utilization rate.

[0045] Furthermore, since the current value flowing through the multilevel inverter 1 is halved, losses in the multilevel inverter 1 can be reduced. Furthermore, since the withstand voltage required for each element in the multilevel inverter 1 is increased and the current capacity required for each element is halved, the capabilities of the high-voltage elements in the multilevel inverter 1 can be more effectively utilized. Furthermore, even when a half-times voltage is applied to the multilevel inverter 1 as a DC voltage, the same voltage as that of the conventional multilevel inverter 1 can be output from the output terminals OUTu, OUTv, and OUTw of the switching circuits SWu, SWv, and SWw without affecting conventional multilevel inverter control. Therefore, compared to the conventional multilevel inverter, it is possible to drive an electric motor with the same torque at half the DC voltage. Furthermore, by complementary switching of the transistors Q1 and Q2, the capacitor CL can be connected in parallel to the DC voltage Vdc and charged, eliminating the need to control the potential fluctuation of the second terminal IN2. This makes it possible to increase the voltage utilization rate.

[0046] Furthermore, according to this embodiment, the control circuit 3 turns off the transistor Q1 and turns on the transistor Q2 when the switching states of the switch units SW1 to SW4 in all of the switching circuits SWu, SWv, and SWw are in a first state. The control circuit 3 turns on the transistor Q1 and turns off the transistor Q2 when the switching states of the switch units SW1 to SW4 in at least one of the switching circuits SWu, SWv, and SWw are in a second state. In this case, when the switch units SW1 to SW4 are switched in a specific pattern during multilevel inverter control, the transistors Q1 and Q2 are switched complementarily. This makes it possible to charge the capacitor CL to a voltage equal to the DC voltage Vdc without affecting the multilevel inverter control, and therefore makes it possible to apply a voltage equal to the DC voltage Vdc between the first terminal IN1 and the second terminal IN2 and between the second terminal IN2 and the third terminal P3. As a result, compared to the conventional multilevel inverter 1, it is possible to double the output voltages from the output terminals OUTu, OUTv, and OUTw of the switching circuits SWu, SWv, and SWw.

[0047] According to this embodiment, the first state is a state in which the fourth switch SW4, which is connected to the third terminal P3 among the multiple switch units SW1 to SW4, is turned off. The second state is a state in which the fourth switch SW4, which is connected to the third terminal P3 among the multiple switch units SW1 to SW4, is turned on. In this state, the capacitor CL can be charged to a voltage equal to the DC voltage Vdc without affecting multilevel inverter control, and therefore the same voltage as the DC voltage Vdc can be applied between the first terminal IN1 and the second terminal IN2 and between the second terminal IN2 and the third terminal P3. As a result, the output voltages from the output terminals OUTu, OUTv, and OUTw of the switching circuits SWu, SWv, and SWw can be doubled compared to conventional multilevel inverters.

[0048] According to this embodiment, the plurality of switch sections SW1 to SW4 include a first switch section SW1, a second switch section SW2, a third switch section SW3, and a fourth switch section SW4. In the switching circuits SWu, SWv, and SWw, the first switch section SW1, the second switch section SW2, the third switch section SW3, and the fourth switch section SW4 are connected in series in this order between the first terminal IN1 and the third terminal P3, and the output terminals OUTu, OUTv, and OUTw are connected to a connection point between the second switch section SW2 and the third switch section SW3. Each of the switching circuits SWu, SWv, and SWw includes a clamp diode DH connected between the second terminal IN2 and a connection point between the first switch unit SW1 and the second switch unit SW2, and a clamp diode DL connected between the second terminal IN2 and a connection point between the third switch unit SW3 and the fourth switch unit SW4. With this configuration, the first switch unit SW1 and the third switch unit SW3 are complementarily switched, and the second switch unit SW2 and the fourth switch unit SW4 are complementarily switched, thereby outputting three-level potentials, including the potential of the second terminal IN2, from the switching circuits SWu, SWv, and SWw. This allows the transistors Q1 and Q2 to be complementarily switched in response to control to output three-level voltages, thereby charging the capacitor CL to a voltage equal to the DC voltage Vdc. As a result, the multilevel inverter 1 that outputs three-level voltages can output voltages close to the input voltage, thereby achieving a higher voltage utilization rate.

[0049] Furthermore, according to this embodiment, the control circuit 3 turns off the transistor Q1 and turns on the transistor Q2 when the switching states of the switch units SW1 to SW4 in all of the switching circuits SWu, SWv, and SWw are in the first state. In at least one of the switching circuits SWu, SWv, and SWw, the control circuit 3 turns on the transistor Q1 and turns off the transistor Q2 when the switching states of the switch units SW1 to SW4 are in the second state. In this case, when the switching states of the switch units SW1 to SW4 are in the first state, the capacitor CL is charged to a voltage equal to the DC voltage Vdc. This allows the capacitor CL to be charged to a voltage equal to the DC voltage Vdc without affecting multilevel inverter control, so that a voltage equal to the DC voltage Vdc can be applied between the first terminal IN1 and the second terminal IN2 and between the second terminal IN2 and the third terminal P3. As a result, compared to the conventional multilevel inverter 1, the output voltages from the output terminals OUTu, OUTv, and OUTw of the switching circuits SWu, SWv, and SWw can be doubled.

[0050] Furthermore, according to this embodiment, the capacitor CL is a film capacitor, which allows the capacitor CL to be charged to the same voltage as the DC voltage Vdc even when the switching speed of the transistors Q1 and Q2 is increased.

[0051] Furthermore, an electric motor system 100 according to one aspect of the embodiment includes the multilevel inverter 1 according to the above aspect and a three-phase motor system 10 connected to output terminals OUTu, OUTv, and OUTw of the multilevel inverter 1. With this configuration, a voltage close to the input voltage can be applied to the three-phase motor system 10. As a result, a higher-performance three-phase motor system 10 can be driven. Furthermore, the magnitude of the current flowing through the three-phase motor system 10 can be reduced, thereby suppressing heat generation in the three-phase motor system 10. This allows a smaller cooling area for the three-phase motor system 10. Furthermore, the voltage applied to the three-phase motor system 10 can be doubled without the need for a power converter including a large-capacity capacitor and inductor, or a transformer. As a result, the electric motor system 100 can be made smaller and lighter. Furthermore, when driving an electric motor having the same performance as a conventional electric motor, the DC voltage applied to the multilevel inverter 1 can be halved, thereby reducing the DC voltage.

[0052] Although various embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments and may be modified or applied to other applications without departing from the spirit and scope of the claims. The circuit configuration of the multilevel inverter circuit 2 of the above embodiments is not limited to the above. It is sufficient that each switching circuit SWu, SWv, and SWw can output three-level voltages and that the capacitor CL can be charged. For example, in the multilevel inverter circuit 2, it is sufficient that a DC voltage Vdc is applied between the first terminal IN1 and the second terminal IN2. In the example shown in FIG. 10, the capacitor CH does not need to be connected between the first terminal IN1 and the second terminal IN2. In this case, the number of capacitors in the multilevel inverter circuit 2 is reduced, thereby enabling the multilevel inverter to be made smaller and lighter.

[0053] Furthermore, for example, the circuit configuration around the first terminal IN1, the second terminal IN2, and the third terminal P3 is not limited to the above. As shown in FIG. 11 , the multilevel inverter 1 may have a multilevel inverter circuit 20 instead of the multilevel inverter circuit 2. Unlike the multilevel inverter circuit 2, the multilevel inverter circuit 20 applies a DC voltage Vdc between the first terminal IN1 and the second terminal IN2 so that the second terminal IN2 has a higher voltage than the first terminal IN1. The source terminal of the transistor Q1 is connected to the connection point P4. The drain terminal of the transistor Q1 is connected to the second terminal IN2. The source terminal of the transistor Q2 is connected to the first terminal IN. The drain terminal of the transistor Q2 is connected to the connection point P4. The drain terminals of the transistors QHU, QHD, QLU, and QLD are connected to the third terminal P3 (high voltage) side. The source terminals of the transistors QHU, QHD, QLU, and QLD are connected to the first terminal IN1 (low voltage) side. The transistors QHU, QHD, QLU, and QLD are connected in series in this order between the third terminal P3 and the first terminal IN1. The connection order of the transistors QHU, QHD, QLU, and QLD is reversed from that of the above embodiment. The first state is a state in which the first switch SW1, of the multiple switch units SW1 to SW4, connected to the third terminal P3, is turned off. The second state is a state in which the first switch SW1, of the multiple switch units SW1 to SW4, connected to the third terminal P3, is turned on.

[0054] In the above embodiment, the transistors Q1 and Q2 are driven complementarily, but this is not limiting. For example, a dead time may be provided in the switching of each transistor to prevent both transistors Q1 and Q2 from being turned on and to prevent a short circuit. In this case, a transition time may be provided when switching between the on state and the off state of the transistors Q1 and Q2. This prevents both transistors Q1 and Q2 from being turned on. As a result, it is possible to prevent the power supply from being short-circuited.

[0055] Furthermore, for example, the transistors Q1 and Q2 may be alternately turned on and off. As an example, when the transistors Q1 and Q2 are turned off, a first control in which the transistor Q1 is turned on and then turned off and a second control in which the transistor Q2 is turned on and then turned off may be alternately executed.

[0056] In the above embodiment, one circuit element including the capacitors CH and CL that apply a DC voltage to the switching circuits SWu, SWv, and SWw and the transistors Q1 and Q2 is provided, but this is not limited to this. For example, the above circuit element may be provided for each of the switching circuits SWu, SWv, and SWw. This reduces the current flowing through the multilevel inverter circuit 2, thereby improving the design flexibility of the multilevel inverter circuit 2. Furthermore, since the loop inductance in the multilevel inverter circuit 2 is reduced, surge voltages can be suppressed. This reduces failures of each circuit element.

[0057] 10 and 11, the plurality of switch units SW1 to SW4 are insulated gate bipolar transistors (IGBTs), but are not limited to this. The plurality of switch units SW1 to SW4 may be SiC-MOSFETs, GaN (gallium nitride)-HEMTs, GaO (gallium oxide)-MOSFETs, or other transistors other than those described above.

[0058] In the above embodiment, the multilevel inverter 1 is a 3LV-NPC multilevel inverter, but is not limited to this. For example, the multilevel inverter 1 may be a 3LV-ANPC (active neutral point clamp) multilevel inverter, and may have two switches instead of the clamp diodes DL and DH. In this case, by actively controlling the two switches, when the potential of the connection point between the two transistors QHU and QHD becomes equal to or lower than the potential of the second terminal IN2, the potential of the connection point between the two transistors QHU and QHD is clamped to the potential of the second terminal IN2.

[0059] The multilevel inverter of the present disclosure is [1] "a multilevel inverter including: a first terminal and a second terminal to which a DC voltage is applied; a third terminal; a first switching element and a capacitor connected in series in this order between the second terminal and the third terminal; a second switching element connected between the first terminal and a connection point between the first switching element and the capacitor; a switching circuit having a plurality of switch units connected in series between the first terminal and the third terminal, and an output terminal, the switching circuit generating a plurality of levels of potential including the potential of the second terminal and outputting the plurality of levels of potential from the output terminal; and a control circuit controlling switching of the first switching element, the second switching element, and the plurality of switch units."

[0060] The multilevel inverter of the present disclosure may be [2] "the multilevel inverter according to the above [1], wherein, when the switching states of the plurality of switch units in the switching circuit are in a first state, the control circuit turns off the first switching element and turns on the second switching element, and when the switching states of the plurality of switch units in the switching circuit are in a second state, the control circuit turns on the first switching element and turns off the second switching element."

[0061] The multilevel inverter of the present disclosure may be [3] "the multilevel inverter according to the above [2], in which the first state is a state in which a switch unit connected to a third terminal among the plurality of switch units is turned off, and the second state is a state in which a switch unit connected to a third terminal among the plurality of switch units is turned on."

[0062] The multilevel inverter of the present disclosure may be [4] "the multilevel inverter according to any one of the above [1] to [3], wherein the plurality of switch units include a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, and in the switching circuit, the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit are connected in series between a first terminal and a third terminal in this order, an output terminal is connected to a connection point between the second switch unit and the third switch unit, and the multilevel inverter includes a first clamp diode connected between the second terminal and the connection point between the first switch unit and the second switch unit, and a second clamp diode connected between the second terminal and the connection point between the third switch unit and the fourth switch unit."

[0063] The multilevel inverter of the present disclosure may be [5] "the multilevel inverter described in the above [4], wherein, when the fourth switch unit is off in the switching circuit, the control circuit turns off the first switching element and turns on the second switching element, and when the fourth switch unit is on in the switching circuit, the control circuit turns on the first switching element and turns off the second switching element."

[0064] The multilevel inverter of the present disclosure may be [6] "the multilevel inverter according to any one of the above [1] to [5], in which the capacitor is a film capacitor."

[0065] The electric motor system of the present disclosure is [7] "an electric motor system including a multilevel inverter according to any one of [1] to [6] above and an electric motor connected to an output terminal of the multilevel inverter."

[0066] 1 Multilevel inverter 3 Control circuit CL Capacitor IN1 First terminal IN2 Second terminal P3 Third terminal P4 Connection point Q1 Transistor (first switching element) Q2 Transistor (second switching element) SWu, SWv, SWw Switching circuit SW1 First switch section SW2 Second switch section SW3 Third switch section SW4 Fourth switch section DH Clamp diode (first clamp diode) DL Clamp diode (second clamp diode) OUTu, OUTv, OUTw Output terminal Vdc DC voltage 100 Motor system 10 Three-phase motor system (motor)

Claims

1. A multilevel inverter comprising: first and second terminals to which a DC voltage is applied; a third terminal; a first switching element and a capacitor connected in series in this order between the second and third terminals; a second switching element connected between the first terminal and a connection point between the first switching element and the capacitor; a switching circuit having a plurality of switch units connected in series between the first and third terminals and an output terminal, the switching circuit generating a plurality of levels of potential including the potential of the second terminal and outputting the plurality of levels of potential from the output terminal; and a control circuit controlling switching of the first switching element, the second switching element, and the plurality of switch units.

2. The multilevel inverter according to claim 1, wherein the control circuit turns off the first switching element and turns on the second switching element when the switching states of the plurality of switch units in the switching circuit are in a first state, and turns on the first switching element and turns off the second switching element when the switching states of the plurality of switch units in the switching circuit are in a second state.

3. The multilevel inverter according to claim 2, wherein the first state is a state in which a switch unit among the plurality of switch units connected to the third terminal is turned off, and the second state is a state in which a switch unit among the plurality of switch units connected to the third terminal is turned on.

4. The multilevel inverter according to claim 1 or 2, wherein the plurality of switch units include a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit, and wherein the switching circuit includes: the first switch unit, the second switch unit, the third switch unit, and the fourth switch unit connected in series in this order between the first terminal and the third terminal; the output terminal connected to a connection point between the second switch unit and the third switch unit; a first clamp diode connected between the second terminal and the connection point between the first switch unit and the second switch unit; and a second clamp diode connected between the second terminal and the connection point between the third switch unit and the fourth switch unit.

5. The multilevel inverter according to claim 4, wherein the control circuit, when the fourth switch unit in the switching circuit is off, turns off the first switching element and turns on the second switching element, and when the fourth switch unit in the switching circuit is on, turns on the first switching element and turns off the second switching element.

6. The multilevel inverter according to claim 1 or 2, wherein the capacitor is a film capacitor.

7. A motor system comprising: the multilevel inverter according to claim 1 or 2; and an electric motor connected to the output terminals of the multilevel inverter.

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