Semiconductor device and preparation method therefor, and three-dimensional dynamic random access memory

Abstract

A semiconductor device and a preparation method therefor, and a three-dimensional dynamic random access memory. The semiconductor device comprises: a substrate; a stacked structure arranged on the substrate, wherein the stacked structure comprises a support structure, and memory cells stacked in a first direction, each of the memory cells comprises a cylindrical first electrode extending in a second direction, the first electrode comprises a first end and a second end in the second direction, the first end is blind, the second end has an opening, the second end is connected to the support structure, the support structure comprises a first portion surrounding part of an outer surface of the first electrode, the first direction intersects the substrate, and the second direction is parallel to the substrate; and a first dielectric layer and a second electrode layer, wherein the first dielectric layer covers at least part of an inner surface of the first electrode, at least part of an outer surface between the first end and the second end, and at least part of the surface of the support structure, and the second electrode layer covers the first dielectric layer.

Description

Semiconductor device and method of manufacturing the same, three-dimensional dynamic random access memory

[0001] The present disclosure is based on and claims priority to Chinese Patent Application No. 202410740576.5, filed on June 7, 2024, entitled “Semiconductor device and method of manufacturing the same, three-dimensional dynamic random access memory”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor device and method of manufacturing the same, three-dimensional dynamic random access memory. BACKGROUND

[0003] Development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of semiconductor device structures, technical barriers encountered by existing structures become more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0004] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes multiple transistors stacked on a substrate, which meets the above-mentioned requirements.

[0005] SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a semiconductor device is provided, comprising:

[0007] a substrate;

[0008] a stack structure disposed on the substrate, the stack structure comprising: a support structure and a memory cell stacked along a first direction;

[0009] the memory cell comprising a cylindrical first electrode extending along a second direction, the first electrode comprising a first end and a second end along the second direction, the first end being a blind opening, the second end having an opening, the second end being connected to the support structure, the support structure comprising a first portion surrounding a part of an outer surface of the first electrode, the first direction intersecting the substrate, the second direction being parallel to the substrate;

[0010] the stack structure further comprising: a first dielectric layer and a second electrode layer, the first dielectric layer covering at least part of an inner surface of the first electrode, at least part of an outer surface between the first end and the second end, and at least part of a surface of the support structure;

[0011] the second electrode layer covering the first dielectric layer.

[0012] In some embodiments, the support structure comprises a second portion connected to the second end, the second portion having an opening, the opening of the second portion at least partially coinciding with the opening of the second end.

[0013] In some embodiments, the opening of the second portion coincides with the opening of the second end.

[0014] In some embodiments, the semiconductor device comprises a plurality of stack structures arranged along a third direction, the third direction being parallel to the substrate and intersecting the second direction.

[0015] In some embodiments, the support structure of an adjacent stack structure is provided with a connecting portion between the support structures.

[0016] In some embodiments, the first dielectric layer covers at least part of a surface of the connecting portion.

[0017] In some embodiments, the support structure comprises a third end and a fourth end in the first direction, the third end being away from the substrate, the fourth end being close to the substrate, the connecting portion comprising an upper connecting portion and a lower connecting portion, the upper connecting portion connecting adjacent third ends, the lower connecting portion connecting adjacent fourth ends.

[0018] In some embodiments, the upper connecting portion is farther away from the substrate than the first electrode in the first direction, the lower connecting portion is closer to the substrate than the first electrode in the first direction.

[0019] In some embodiments, the first dielectric layer covering at least part of an outer surface between the first end and the second end surrounds the first electrode with the second direction as an axis.

[0020] In some embodiments, the first dielectric layer covering at least part of an outer surface between the first end and the second end is covered with a second electrode.

[0021] In some embodiments, the semiconductor device further comprises a conductive filling layer, the conductive filling layer covering the second electrode.

[0022] In some embodiments, the semiconductor device further comprises a conductive filling layer, the conductive filling layer covering the second electrode, the conductive filling layer being partially provided between adjacent stack structures.

[0023] According to a second aspect of embodiments of the present disclosure, a three-dimensional dynamic random access memory is provided, comprising:

[0024] Any of the aforementioned semiconductor devices, sub-word line drivers, and sensitive amplifiers.

[0025] According to a third aspect of embodiments of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising:

[0026] providing a substrate;

[0027] forming a first electrode stacked along a first direction on a substrate, the first electrode being a cylinder extending along a second direction, the first electrode including a first end and a second end along the second direction, the first end being blind, and the second end having an opening;

[0028] forming a support structure connected to the second end at the second end, the support structure including a first portion surrounding a part of an outer surface of the first electrode;

[0029] forming a first dielectric layer on at least a part of an inner surface of the first electrode, at least a part of an outer surface between the first end and the second end, and at least a part of a surface of the support structure;

[0030] forming a second electrode layer on the first dielectric layer;

[0031] the first direction intersects the substrate, and the second direction is parallel to the substrate.

[0032] In some embodiments, forming the first electrode stacked along the first direction includes forming a plurality of first electrodes stacked along a third direction spaced apart, the third direction being parallel to the substrate and intersecting the second direction;

[0033] forming the support structure includes forming a connecting portion between the support structures corresponding to adjacent first electrodes stacked, the support structure including a third end and a fourth end along the first direction, the third end being away from the substrate, and the fourth end being close to the substrate, the connecting portion including an upper connecting portion connecting adjacent third ends and a lower connecting portion connecting adjacent fourth ends;

[0034] forming the first dielectric layer includes forming the first dielectric layer on at least a part of a surface of the connecting portion;

[0035] forming the second electrode includes forming the second electrode on a surface of the first dielectric layer on at least a part of a surface of the connecting portion.

[0036] In some embodiments, the support structure is formed with a second portion connected to the second end, the second portion having an opening, and the opening of the second portion is aligned with the opening of the second end.

[0037] In the embodiments of the present disclosure, due to the technical features of the support structure, the support of the support structure makes it possible to make a longer cylindrical first electrode, thereby obtaining a capacitor with a larger capacity, and further saving the chip space occupied by the capacitor and improving the integration. BRIEF DESCRIPTION OF DRAWINGS

[0038] FIG. 1 is a schematic diagram of a semiconductor device according to an example embodiment;

[0039] FIGS. 2-4 are schematic diagrams of a structure at a step in the manufacture of a semiconductor device according to an example embodiment;

[0040] Figures 5, 10, 13, 15, 17, 19, 21 are schematic cross-sectional views of a portion of a structure Aa at a step in semiconductor device fabrication, according to an example embodiment;

[0041] Figures 6, 8, 11, 14, 16, 18, 20, 22 are schematic cross-sectional views of a portion of a structure Bb at a step in semiconductor device fabrication, according to an example embodiment;

[0042] Figures 7, 9, 12, 23, 24 are schematic cross-sectional views of a portion of a structure Cc at a step in semiconductor device fabrication, according to an example embodiment. DETAILED DESCRIPTION

[0043] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the example embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.

[0045] It can be understood that the meanings of "on", "over" and "above" in the present disclosure should be interpreted in the broadest way, so that "on" not only means "on" something with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0046] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0047] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope less than the scope of the underlying or overlying structure. Furthermore, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers.

[0048] It should be noted that the technical solutions disclosed in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0049] According to a first aspect of the embodiments of the present disclosure, as shown in FIGS. 1 and 17, a semiconductor device 10 is provided, comprising:

[0050] a substrate 100;

[0051] a stack structure 1000 is disposed on the substrate, the stack structure comprising: support structures 400, 401 and memory cells 1100 stacked along a first direction;

[0052] The memory cell comprises a cylindrical first electrode 300 extending along a second direction, the first electrode comprising a first end 310 and a second end 320 along the second direction, the first end being blind, and the second end having an opening, the second end being connected to the support structure, the support structure comprising a first portion 410 surrounding part of the outer surface of the first electrode, the first direction D1 intersecting the substrate, and the second direction D2 being parallel to the substrate;

[0053] The stack structure further comprises: a first dielectric layer C3 and a second electrode layer C4, the first dielectric layer covering at least part of the inner surface of the first electrode, at least part of the outer surface between the first end and the second end, and at least part of the surface of the support structure;

[0054] The second electrode layer covers the first dielectric layer.

[0055] In some embodiments, the support structure comprises: a second portion 420 connected to the second end, the second portion having an opening, and the opening of the second portion at least partially coincides with the opening of the second end, preferably, the opening of the second portion coincides with the opening of the second end.

[0056] In some embodiments, the semiconductor device comprises a plurality of stack structures arranged along a third direction D3, the third direction being parallel to the substrate and intersecting the second direction;

[0057] Among them, the support structures 400, 401 of adjacent stack structures are provided with a connecting portion 500.

[0058] In some embodiments, the first dielectric layer covers at least part of the surface of the connecting portion.

[0059] In some embodiments, the support structure comprises a third end 430 and a fourth end 440 in the first direction, the third end being away from the substrate, and the fourth end being close to the substrate, the connecting portion comprising an upper connecting portion 501 and a lower connecting portion 502, the upper connecting portion connecting adjacent third ends, and the lower connecting portion connecting adjacent fourth ends.

[0060] In some embodiments, the upper connection portion is farther from the substrate than the first electrode in the first direction, and the lower connection portion is closer to the substrate than the first electrode in the first direction.

[0061] In some embodiments, the first dielectric layer covering at least part of the outer surface between the first end and the second end surrounds the first electrode as a ring in the second direction.

[0062] In some embodiments, the first dielectric layer covering at least part of the outer surface between the first end and the second end is covered with a second electrode.

[0063] In some embodiments, the semiconductor device further comprises a conductive fill layer C5 covering the second electrode.

[0064] In some embodiments, the semiconductor device further comprises a conductive fill layer covering the second electrode, the conductive fill layer being partially disposed between adjacent stack structures.

[0065] In some embodiments, the memory cell further comprises an access transistor comprising a source 700, a drain 900, a gate 600, and an active layer 800 connected to the source and the drain, the drain being connected to the first end of the first electrode, and the gates of the access transistors of the memory cells in different layers of the stack structure being connected to form a word line extending in the first direction.

[0066] In some embodiments, the semiconductor device further comprises a bit line 200 and a lead-out structure 210. The bit line extends in a third direction, and there are a plurality of bit lines arranged in a stack in the first direction, corresponding to the memory cells in the stack structure, and connected to the sources of the access transistors.

[0067] In some embodiments, the semiconductor device comprises a plurality of stack structures arranged in the third direction. The sources of the access transistors of the memory cells in corresponding layers of different stack structures are connected to the same bit line.

[0068] According to a second aspect of embodiments of the present disclosure, as shown in FIG. 1, a three-dimensional dynamic random access memory 20 is provided, comprising any of the aforementioned semiconductor devices, a sub-word line driver SWD, and a sensitive amplifier SA. The sub-word line driver is connected to the word line, and the sensitive amplifier is connected to the bit line through the lead-out structure.

[0069] In some embodiments, one of the sub-word line driver and the sensitive amplifier is disposed on the substrate of the semiconductor device and connected to the semiconductor device through a wire.

[0070] In some embodiments, the sub-word line driver and the sensitive amplifier are both disposed on the substrate of the semiconductor device and connected to the semiconductor device through a wire.

[0071] In some embodiments, the three-dimensional dynamic random access memory further comprises another substrate, one of the sub-word line driver and the sensitive amplifier is disposed on the another substrate, the another substrate is bonded to the semiconductor device. The one of the sub-word line driver and the sensitive amplifier is connected to the semiconductor device by the bonding and the wire.

[0072] In some embodiments, the three-dimensional dynamic random access memory further comprises another substrate, one of the sub-word line driver and the sensitive amplifier is disposed on the another substrate, the another substrate is bonded to the semiconductor device. The one of the sub-word line driver and the sensitive amplifier is connected to the semiconductor device by the bonding and the wire.

[0073] According to a third aspect of the embodiments of the present disclosure, as shown in FIGS. 2-24, a method for manufacturing a semiconductor device is provided, comprising:

[0074] A substrate is provided, which can be made of single crystal silicon, germanium-silicon, silicon carbide, or other semiconductor materials, and can include other previously prepared structures, such as transistors disposed in the substrate.

[0075] A first electrode is formed on the substrate in a first direction, the first electrode is in a cylindrical shape extending in a second direction, the first electrode includes a first end and a second end in the second direction, the first end is blind, and the second end has an opening.

[0076] Specifically, an initial stack structure is formed on the substrate, the initial stack structure is formed by alternately preparing a material layer M1 and a material layer M2.

[0077] In some embodiments, the initial stack structure can be alternately prepared by depositing silicon nitride and silicon oxide, or by epitaxially growing single crystal silicon and single crystal germanium-silicon, or by alternately preparing silicon oxide and single crystal silicon, or by alternately preparing silicon oxide and polycrystalline silicon, or by etching two different thin film materials with a high etching selectivity. The material layer M1 and the material layer M2 respectively represent the two different materials selected.

[0078] In some embodiments, a barrier layer M3 is formed on the initial stack structure, which can serve as an etching stop layer, or a stop layer in a chemical mechanical polishing process, or to protect the initial stack structure from collapsing in an etching process. Optionally, the material of the barrier layer M3 is titanium nitride.

[0079] As shown in FIG. 3, FIGS. 5-7, a plurality of spaced-apart trenches T1 are formed in the initial stack structure by a patterning process, the trenches have a first predetermined width, and the distance between the trenches has a second predetermined width. Optionally, the first predetermined width is related to the distance between the stack structures to be prepared, and the second predetermined width is related to the width of the first electrode to be prepared.

[0080] In some embodiments, the patterning process comprises forming a photoresist on the barrier layer M3, exposing the photoresist to form a spaced groove pattern, etching the barrier layer and the initial stack structure through the patterned photoresist to form the groove.

[0081] In some embodiments, the patterning process further comprises forming a hard mask on the barrier layer M3, forming a photoresist on the hard mask, exposing the photoresist to form a spaced groove pattern, etching the hard mask through the patterned photoresist to transfer the groove pattern to the hard mask, stripping the photoresist, and etching the barrier layer and the initial stack structure through the patterned hard mask.

[0082] In some embodiments, as the semiconductor manufacturing process develops, the integration level increases and the size shrinks. A single patterning process cannot form the desired first and second preset widths, and multiple patterning processes are needed to form the desired first and second preset widths. For example, a twice exposure and etching process (LELE), or a self-aligned double patterning process (SADP), or a self-aligned quadruple patterning process (SAQP), etc.

[0083] In some embodiments, the method of etching the groove can be a dry etching process.

[0084] In some embodiments, to ensure complete etching, the depth of the groove is generally greater than the initial stack structure.

[0085] As shown in FIG. 4, FIGS. 8-9, first fill the groove T1 with a protective layer, preferably, fill the protective layer P1, the protective layer P2, and the protective layer P3 in sequence, and then make the groove T2.

[0086] In some embodiments, the protective layer is prepared by physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0087] In some embodiments, the protective layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or metal oxide such as tantalum oxide, hafnium oxide, aluminum oxide, polysilicon, and combinations thereof.

[0088] In some embodiments, preferably, the protective layer P1 is silicon oxide, the protective layer P2 is silicon nitride, and the protective layer P3 is polysilicon.

[0089] The process of making the groove T2 can be similar to the process of making the groove T1, which is not repeated here.

[0090] Further, as shown in FIGS. 10-12, the material layer M2 is etched through the groove T2, and then the electrode layer C1 and the filling layer C2 are deposited.

[0091] In particular, the etching removal of the material layer M2 through the trench T2 can be a lateral etching removal of the material layer M2 by an isotropic etching method. Preferably, the isotropic etching method includes a liquid phase etching. Optionally, the etching rate of the etching liquid of the liquid phase etching process to the material layer M2 is greater than the etching rate of the etching liquid to the material layer M1.

[0092] Further, after the removal of the material layer M2, an electrode layer C1 is deposited in the space left by the removal of the material layer M2. The electrode layer C1 will form a first electrode after the subsequent process is completed.

[0093] In some embodiments, the electrode layer C1 can include a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and a combination thereof; such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or a combination thereof, or a polysilicon, a gallium indium tin oxide, a tin indium oxide, or a combination thereof. Preferably, the electrode layer C1 is titanium nitride.

[0094] In some embodiments, the fabrication process of the electrode layer C1 can be selected from a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD), a vacuum evaporation, a furnace tube deposition, or the like.

[0095] Further, after the formation of the electrode layer C1, a filling layer C2 is deposited. The filling layer C2.

[0096] In some embodiments, the filling layer C2 can include a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and a combination thereof; such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or a combination thereof, or a polysilicon, a gallium indium tin oxide, a tin indium oxide, or a combination thereof. Preferably, the filling layer C2 is a polysilicon.

[0097] In some embodiments, the fabrication process of the filling layer C2 can be selected from a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD), a vacuum evaporation, a furnace tube deposition, or the like.

[0098] Further, a portion of the filling layer C2 and a portion of the electrode layer C1 are removed by an etching process.

[0099] In some embodiments, since the partial electrode layer C1 and the partial filling layer C2 are formed in the initial stack structure after etching, the blocking layer M3 is shielded. The etching process directly removes the other part of the filling layer C2 and the electrode layer C1 by using an isotropic etching process.

[0100] In some embodiments, the anisotropic etching process includes a dry etching process, a plasma etching process, etc.

[0101] In some embodiments, the filling layer C2 is a polysilicon material and the electrode layer C1 is a titanium nitride material, different dry etching processes are required for etching, so the filling layer C2 is etched first, and then the electrode layer C1 is etched.

[0102] In some embodiments, in order to ensure that the filling layer C2 and the electrode layer C1 are etched off, some materials are etched excessively, and finally the remaining filling layer is farther away from the trench T2 than the blocking layer M3, as shown in FIG. 10, the remaining electrode layer C1 is farther away from the trench T2 than the filling layer C2.

[0103] In some embodiments, as shown in FIG. 12, the electrode layer C1 forms a cylindrical structure in the space left after removing the material layer M2, and an opening is formed at one end close to the trench T2, and a blind end is formed at one end away from the trench T2.

[0104] A support structure connected to the second end is formed at the second end, and the support structure includes a first part surrounding the outer surface of the first electrode part;

[0105] As shown in FIGS. 13-18, a groove with a preset depth is etched in the material layer M1 through the trench T2, and the preset depth is related to the size of the support structure formed in the subsequent process. If a larger support structure is needed, a deeper preset depth is set, and if only a narrower support structure is needed, a shallower preset depth is set. It can be understood that in the subsequent manufacturing process, the support structure will occupy the outer surface of the first electrode, and the deeper the preset depth, the larger the outer surface of the first electrode occupied, and the corresponding storage capacity of the capacitor will be correspondingly affected and become smaller.

[0106] Specifically, etching the material layer M1 through the trench T2 can be by an isotropic etching method, which removes the material layer M1 by lateral etching. Preferably, the isotropic etching method includes a liquid phase etching process. Optionally, the etching rate of the etching liquid of the liquid phase etching process on the material layer M1 is greater than the etching rate of the etching liquid on the electrode layer C1 and the filling layer C2.

[0107] In some embodiments, the material layer M1 and the protection layer P1 are made of the same material or similar material, and the etching liquid has the same or similar etching rate on the material layer M1 and the protection layer P1. When the material layer M1 is etched, part of the protection layer P1 is removed. As shown in FIG. 14, compared with FIG. 11, the material layer M1 is further etched after being etched at the Bb cross section, and a shallow groove is formed at the position blocked by the barrier layer M3 and the position blocked by the substrate. The shallow groove at the barrier layer M3 is formed in the barrier layer M3, so the relative position is higher than the groove at the preset depth close to the barrier layer M3 in FIG. 13. The shallow groove at the substrate is formed in the substrate, so it is lower than the groove at the preset depth close to the substrate in FIG. 13.

[0108] Further, the support layer S1 is formed in the groove at the preset depth. Optionally, the support layer S1 material is formed in the groove at the preset depth and the trench T2 and the surface of the barrier layer M3 by a deposition process, and then the excess support layer S1 material is removed by etching. The etching process is controlled to form the support layer S1 in the groove at the preset depth, and the remaining support layer S1 at least exposes the end surface of the filling layer C2.

[0109] Optionally, the deposition process for forming the support layer S1 can be selected from physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, pulsed laser deposition (PLD) method, chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.

[0110] Optionally, the material of the support layer S1 is selected from silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, silicon carbon oxide, silicon carbide, etc. Preferably, the support layer S1 is selected from silicon carbon nitride.

[0111] Optionally, the etching process for removing the excess support layer S1 material can be selected from anisotropic etching process or isotropic etching process. Preferably, the isotropic etching process. The specific isotropic etching method includes liquid etching. Optionally, the etching rate of the etching liquid of the liquid etching process on the support layer S1 is greater than the etching rate of the etching liquid on the barrier layer M3, the electrode layer C1 and the filling layer C2.

[0112] In some embodiments, the remaining support layer S1 exposes the end surface of the filling layer C2 and the end surface at the edge of the electrode layer C1 opposite to the trench T2.

[0113] In some embodiments, the electrode layer C1 is farther away from the trench T2 than the filling layer C2, and the support layer S1 blocks the edge of the electrode layer C1 opposite to the trench T2, i.e., the second end of the first electrode formed subsequently.

[0114] In some embodiments, as shown in FIG. 16, after the material layer M1 is etched at the Bb cross section, the protection layer P1 is further etched, and a shallow groove is formed at the position blocked by the barrier layer M3 and the position blocked by the substrate. When the support layer S1 material is formed, the support layer S1 material is deposited in the shallow groove. After the excess support layer S1 material is removed by etching, the support layer S1 is formed in the shallow groove. Since the shallow groove at the barrier layer M3 is formed in the barrier layer M3, the relative position of the support layer S1 in the shallow groove at the barrier layer M3 is higher than the uppermost end of the support layer S1 in FIG. 15, i.e., the third end of the support structure formed in the subsequent process. Since the shallow groove at the substrate is formed in the substrate, the support layer S1 in the shallow groove at the substrate is lower than the lowermost end of the support layer S1 in FIG. 15, i.e., the fourth end of the support structure formed in the subsequent process.

[0115] Further, as shown in FIGS. 17-18, the filling layer C2, part of the material layer M1, the protection layer P1, the protection layer P2, and the protection layer P3 are removed to expose the inner surface and part of the outer surface of the electrode layer C1. Optionally, an isotropic etching process is used to remove the layers, and a liquid phase etching process is preferred. It can be understood that the removal of the filling layer C2, part of the material layer M1, the protection layer P1, the protection layer P2, and the protection layer P3 can be completed in one etching process, or can be completed by different etching processes. Optionally, the etching rate of the etching liquid of the liquid phase etching process on the support layer S1, the barrier layer M3, and the electrode layer C1 is less than the etching rate of the etching liquid on the filling layer C2, part of the material layer M1, the protection layer P1, the protection layer P2, and the protection layer P3.

[0116] In some embodiments, as shown in FIG. 17, the remaining support layer S1, i.e., the support structure in the semiconductor device, has a first part 410 surrounding part of the outer surface of the electrode layer C1 (i.e., the first electrode in the semiconductor device) and a second part 420 connected to the second end of the first electrode, which can be seen in the partial enlarged view.

[0117] In some embodiments, in the previous step, as shown in FIG. 15, the etching of the support layer S1 material is sufficient to completely expose the end surface of the filling layer C2, and the second part of the support structure formed in this step is self-aligned with the second end of the first electrode. After the filling layer C2 is removed in the second end of the first electrode, the remaining space forms an opening of the second end, and after the filling layer C2 is removed in the second part of the support structure, the remaining space forms an opening of the second part. The opening of the second end and the opening of the second part coincide.

[0118] In some embodiments, the preceding steps, as in Figure 15, if the etching of the support layer S1 material is not sufficient, will result in the filling layer C2 being exposed only partially at the end surface, with the remaining support layer S1 blocking part of the filling layer C2. At this step, the space remaining after the removal of the filling layer C2 in the second end of the first electrode forms the opening of the second end, and the space remaining after the removal of the filling layer C2 in the second part of the support structure forms the opening of the second part. The opening of the second part of the support structure and the opening of the second end of the first electrode only partially coincide.

[0119] In some embodiments, the preceding steps, as in Figure 15, if the etching of the support layer S1 material is sufficient, the remaining support layer S1 completely exposes the end surface of the filling layer C2 and the end surface at the edge of the electrode layer C1 opposite the trench T2, at this step, a first part is formed around the outer surface of the electrode layer C1 (i.e. the first electrode in the semiconductor device), and the support structure formed does not contain a second part connected to the second end of the first electrode.

[0120] In some embodiments, the preceding steps, as in Figure 15, if the etching of the support layer S1 material is sufficient, the remaining support layer S1 completely exposes the end surface of the filling layer C2 and the end surface at the edge of the electrode layer C1 opposite the trench T2, at this step, a first part is formed around the outer surface of the electrode layer C1 (i.e. the first electrode in the semiconductor device), and the support structure formed does not contain a second part connected to the second end of the first electrode.

[0121] In some embodiments, as shown in Figure 18, the support layer S1 remaining in the shallow trench forms a connecting part in the semiconductor device, the support layer S1 in the shallow trench at the blocking layer M3 forms an upper connecting part, and the support layer S1 in the shallow trench at the substrate forms a lower connecting part. It can be understood that because the relative position of the support layer S1 remaining in the shallow trench at the blocking layer M3 is higher than the uppermost end of the support layer S1 remaining in Figure 17, the upper connecting part obtained is higher than the third end of the support structure; similarly, because the relative position of the support layer S1 remaining in the shallow trench at the substrate is lower than the lowermost end of the support layer S1 remaining in Figure 17, the lower connecting part obtained is lower than the fourth end of the support structure.

[0122] In some embodiments, between the upper connecting part and the lower connecting part as in Figure 18, if the etching in the aforementioned process steps is not sufficient or part of the support layer S1 is intentionally retained, a connecting part is formed connecting adjacent support structures.

[0123] Further, as shown in FIGS. 19-23, a first dielectric layer C3 is formed on at least a portion of the inner surface of the first electrode, at least a portion of the outer surface between the first end and the second end, and at least a portion of the surface of the support structure, and a second electrode layer C4 is formed on the first dielectric layer. As a result of the foregoing steps, the inner surface and a portion of the outer surface of the electrode layer C1 are exposed by removing the filling layer C2, the material layer M1, the protective layer P1, the protective layer P2, and the protective layer P3. At this step, the first dielectric layer C3 is formed on the exposed surface of the electrode layer C1 by a single deposition process. The first dielectric layer C3 is formed on the inner surface of the first electrode, the exposed surface of the support structure connected to the first electrode, the exposed outer surface between the first end and the second end of the first electrode, the upper surface of the barrier layer M3, and the inner surface of the trench T2.

[0124] In some embodiments, as shown in FIG. 20, the first dielectric layer C3 is formed on the exposed surface of the upper connection portion and the barrier layer connected to the upper connection portion, and the first dielectric layer C3 is formed on the exposed inner surface of the trench T1 and the exposed surface of the lower connection portion connected to the substrate.

[0125] In some embodiments, the deposition process includes a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD), vacuum evaporation, or the like.

[0126] In some embodiments, the material of the first dielectric layer C3 is selected from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, or includes at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, for example.

[0127] After the first dielectric layer C3 is formed, the second electrode layer C4 is formed. The second electrode layer C4 is formed on the surface of the first dielectric layer C3 formed on the inner surface of the first electrode, the exposed surface of the support structure connected to the first electrode, the exposed outer surface between the first end and the second end of the first electrode, the upper surface of the barrier layer M3, and the inner surface of the trench T2. The first electrode, the second electrode layer overlapping the first electrode, and the first dielectric layer between the first electrode and the second electrode layer together constitute a storage capacitor. The storage capacitor of the stack structure shares the second electrode layer.

[0128] In some embodiments, as shown in FIG. 22, the second electrode layer C4 is formed on the surface of the first dielectric layer C3 formed on the upper connecting portion and the exposed surface of the barrier layer connected with the upper connecting portion, and on the surface of the first dielectric layer C3 formed on the exposed inner surface of the trench T1 and the exposed surface of the lower connecting portion connected with the substrate.

[0129] In some embodiments, the process method for forming the second electrode layer C4 includes a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD), vacuum evaporation, and the like.

[0130] In some embodiments, the material of the second electrode layer C4 is selected from a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and a combination thereof; such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or a combination thereof, or a polysilicon, a gallium indium tin oxide, a tin indium oxide, and the like non-metallic material or a combination thereof.

[0131] Further, a conductive filling layer C5 is formed on the surface of the second electrode layer C4, as shown in FIG. 24, the conductive filling layer C5 fills the voids of the stacked structure and the trenches between the stacked structures.

[0132] In some embodiments, the conductive filling layer C5 is formed in the trench T1 and the trench T2, and covers the second electrode layer C4 on the upper connecting portion and the barrier layer connected with the upper connecting portion, and covers the second electrode layer C4 on the lower connecting portion connected with the substrate.

[0133] Optionally, the process method for forming the second electrode layer C4 can be selected from a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, a chemical vapor deposition (CVD), vacuum evaporation, and the like.

[0134] Optionally, the material of the conductive filling layer C5 is selected from a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, and a combination thereof; such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or a combination thereof, or a polysilicon, a gallium indium tin oxide, a tin indium oxide, and the like non-metallic material or a combination thereof. Preferably, the conductive filling layer C5 is a polysilicon.

[0135] In some embodiments, the memory cell further comprises an access transistor, the access transistor comprising a source, a drain, a gate, and an active layer connected with the source and the drain, the drain is connected with the first end of the first electrode, and the gates of the corresponding access transistors in the memory cells of different layers of the stack structure are connected to form a word line extending along the first direction. Optionally, the access transistor can be formed before the first electrode. Specifically, as shown in FIG. 17, the material layer M2 connected with the first electrode can be replaced by the drain of the previously formed access transistor. The corresponding material layer M1 can be replaced by the material layer between the access transistors. Optionally, the access transistor can be formed after the first electrode. As shown in FIG. 17, the material layer M2 connected with the first electrode is etched, and the drain connected with the first electrode is made at the corresponding position. Optionally, the access transistor can be formed after the preparation of the capacitor structure and before the deposition of the conductive filling layer C5.

[0136] In some embodiments, due to the support of the support structure, a relatively longer cylindrical first electrode can be designed, and both the exposed inner surface and the outer surface of the first electrode can be used for depositing the first medium layer and the second electrode layer, thereby obtaining a larger effective area of the capacitor electrode and a larger capacitor capacity. Moreover, in the manufacturing method of the support structure, no additional patterning process is needed, and the preparation of the support structure can be completed only by deposition and etching processes, thereby saving the manufacturing cost and being more conducive to mass production.

[0137] In some embodiments, the access transistor is prepared before the first electrode, and the material layer between the access transistors can support the first end of the first electrode. In combination with the support structure of the second end of the first electrode, the first electrode can be well protected from being damaged in subsequent processes, thereby improving the product yield. Moreover, in the manufacturing method of the support structure, no additional patterning process is needed, and the preparation of the support structure can be completed only by deposition and etching processes, thereby saving the manufacturing cost and being more conducive to mass production.

[0138] In some embodiments, the semiconductor device comprises a plurality of stack structures, each of which has a corresponding support structure, and the support structures and the connecting portions between adjacent support structures form a network, thereby playing a better stabilizing role and being more conducive to supporting the first electrode. The first electrode can be well protected from being damaged in subsequent processes, thereby improving the product yield. Moreover, in the manufacturing method of the support structure, no additional patterning process is needed, and the preparation of the support structure can be completed only by deposition and etching processes, thereby saving the manufacturing cost and being more conducive to mass production.

[0139] The various semiconductor devices shown in the specific embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be implemented by a memory, such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0140] The above merely provides the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device (10) characterized by, The semiconductor device comprises: a substrate (100); a stack structure (1000) disposed on the substrate, the stack structure comprising: a support structure (400) and a memory cell (1100) disposed in a stack along a first direction (D1); the memory cell comprising a cylindrical first electrode (300) extending along a second direction (D2), the first electrode comprising a first end (310) and a second end (320) along the second direction, the first end being blind, the second end having an opening, the second end being connected to the support structure, the support structure comprising a first portion surrounding at least part of an outer surface of the first electrode, the first direction intersecting the substrate, the second direction being parallel to the substrate; the stack structure further comprising: a first dielectric layer (C3) and a second electrode layer (C4), the first dielectric layer covering at least part of an inner surface of the first electrode, at least part of an outer surface between the first end and the second end, and at least part of a surface of the support structure; the second electrode layer covering the first dielectric layer.

2. The semiconductor device of claim 1, wherein the support structure comprising a second portion (420) connected to the second end, the second portion having an opening, the opening of the second portion at least partially coinciding with the opening of the second end.

3. The semiconductor device of claim 2, wherein, the opening of the second portion coincides with the opening of the second end.

4. The semiconductor device of claim 1, wherein the semiconductor device comprising a plurality of the stack structures arranged along a third direction (D3), the third direction being parallel to the substrate and intersecting the second direction; wherein the support structures of adjacent stack structures are provided with a connecting portion (500).

5. The semiconductor device of claim 4, wherein, the first dielectric layer covers at least part of a surface of the connecting portion.

6. The semiconductor device of claim 4, wherein, the support structure comprises a third end (430) and a fourth end (440) in the first direction, the third end being away from the substrate, the fourth end being close to the substrate, the connecting portion comprising an upper connecting portion (501) and a lower connecting portion (502), the upper connecting portion connecting adjacent third ends, the lower connecting portion connecting adjacent fourth ends.

7. The semiconductor device of claim 6, wherein, the upper connecting portion is farther away from the substrate than the first electrode in the first direction, the lower connecting portion is closer to the substrate than the first electrode in the first direction.

8. The semiconductor device of claim 1, wherein the first dielectric layer covering at least part of an outer surface between the first end and the second end surrounds the first electrode with the second direction as an axis.

9. The semiconductor device of claim 8, wherein, the second electrode is covered on the first dielectric layer covering at least part of an outer surface between the first end and the second end.

10. The semiconductor device of claim 1, wherein the semiconductor device further comprises a conductive filling layer (C5) covering the second electrode.

11. The semiconductor device of claim 4, wherein, the semiconductor device further comprises a conductive filling layer covering the second electrode, the conductive filling layer being partially disposed between adjacent stack structures.

12. A three-dimensional dynamic random access memory (20), characterized by The semiconductor device comprises: the semiconductor device, the sub-word line driver (SWD) and the sensitive amplifier (SA) of any one of claims 1-11.

13. A method of fabricating a semiconductor device, comprising: The semiconductor device comprises: providing a substrate; forming a first electrode on the substrate, the first electrode being stacked along a first direction, the first electrode being cylindrical along a second direction, the first electrode including a first end and a second end along the second direction, the first end being blind, the second end having an opening; forming a support structure connected to the second end at the second end, the support structure including a first portion surrounding a portion of an outer surface of the first electrode; forming a first dielectric layer on at least a portion of an inner surface of the first electrode, at least a portion of an outer surface between the first end and the second end, and at least a portion of a surface of the support structure; forming a second electrode layer on the first dielectric layer; the first direction intersecting the substrate, the second direction being parallel to the substrate.

14. The method of claim 13, wherein forming the first electrode includes forming a plurality of the first electrode stacked along a third direction, the third direction being parallel to the substrate and intersecting the second direction; forming the support structure includes forming a connecting portion between the support structures corresponding to adjacent ones of the first electrode stacked, the support structure including a third end and a fourth end along the first direction, the third end being distal from the substrate, the fourth end being proximal to the substrate, the connecting portion including an upper connecting portion connecting adjacent ones of the third end and a lower connecting portion connecting adjacent ones of the fourth end; forming the first dielectric layer includes forming the first dielectric layer on at least a portion of a surface of the connecting portion; forming the second electrode includes forming the second electrode on the first dielectric layer on at least a portion of a surface of the connecting portion.

15. The method of claim 13, wherein the support structure is formed with a second portion connected to the second end, the second portion having an opening, the opening of the second portion being aligned with the opening of the second end. ​

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