Single-event gate rupture-resistant sic mosfet and manufacturing method therefor

Abstract

The present invention provides a single-event gate rupture-resistant SiC MOSFET and a manufacturing method therefor. The SiC MOSFET, from bottom to top, sequentially comprises: a drain metallization layer, an N+ substrate layer, an N-drift region, a current spreading region, P-well regions, second N+ source regions, second P-base regions, a first P-base region, a first N+ source region, gate oxide layers, polysilicon gates, isolation oxide layers, and a source metallization layer. The first N+ source region, the second N+ source regions, and the P-well regions are in contact with the source metallization layer; each second N+ source region surrounds the bottom, two corners, and one sidewall of a corresponding trench gate oxide layer; and each second N+ source region is shielded by a corresponding P-well region and second P-base region, and is isolated from the current spreading region and the N-drift region. The present invention effectively suppresses a strong electric field in gate oxide caused by high-energy charged particle radiation, thereby greatly improving the single-event gate rupture resistance of the trench-type SiC MOSFET.

Description

SiC MOSFET with anti-single event gate rupture and preparation method

[0001] The present application claims priority to the Chinese patent application No. 202410738115.4, filed on June 7, 2024, and entitled "SiC MOSFET with anti-single event gate rupture and preparation method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the technical field of power semiconductors, and particularly relates to a SiC MOSFET with anti-single event gate rupture and a preparation method. BACKGROUND

[0003] The trench type SiC MOSFET has the advantages of high breakdown voltage, fast switching speed, low on-resistance, etc., and its performance is superior to that of the planar type SiC MOSFET, which meets the urgent needs of new space power systems for high-voltage power devices.

[0004] Space is full of a large number of high-energy charged particles. When these high-energy charged particles enter the interior of a power semiconductor device, they may cause permanent damage to the device. According to a large number of ground accelerator simulation tests, the trench type SiC MOSFET is generally not resistant to high-energy charged particle radiation, and single event gate rupture (SEGR) occurs at about 10% of the rated voltage, causing permanent damage to the device. If the conventional trench type SiC MOSFET without radiation hardening is directly applied in a space power system, it will seriously threaten the on-orbit life of the spacecraft.

[0005] The trench type SiC MOSFET is very sensitive and vulnerable to single event gate rupture, because when high-energy charged particles enter the interior of the device, they will collide and ionize to produce a large number of electron-hole pairs. The holes accumulate rapidly at the gate oxide interface under the action of a strong electric field, generating a transient strong electric field. Once the transient strong electric field exceeds the critical breakdown field value, the gate oxide will break down, and a leakage current channel will be formed.

[0006] Due to the geometric asymmetry of the trench corner, when high-energy charged particles are incident, the maximum electric field of the trench corner gate oxide will be greater than that of the trench bottom. How to suppress or alleviate the transient strong electric field of the gate oxide caused by hole accumulation at the trench corner and the trench bottom is the key to the anti-single event gate rupture hardening design of the trench type SiC MOSFET.

[0007] As shown in Figure 1 is a schematic diagram of a conventional trench SiC MOSFET structure, which can be used as a comparative device of the present application, which includes: a source metallization layer 101, an isolation oxygen 102, a gate oxide 103, a polysilicon gate 104, an N+ source region 105, a P-base region 106, a P-well region 107, an N-drift region 108, an N+ substrate region 109, and a drain metallization layer 110.

[0008] SUMMARY

[0009] The technical problem solved by the present application is to overcome the shortcomings of the prior art, and provide an anti-single event gate punchthrough SiC MOSFET and a preparation method, so as to solve the problem of single event gate punchthrough caused by high-energy charged particle radiation in space applications.

[0010] The technical scheme provided by the present application is as follows:

[0011] In a first aspect, an anti-single event gate punchthrough SiC MOSFET and a preparation method are provided, comprising:

[0012] An N+ substrate layer;

[0013] A drain metallization layer located on the lower surface of the N+ substrate layer;

[0014] An N-drift region located on the upper surface of the N+ substrate layer;

[0015] A current spreading region located on the upper surface of the partial N-drift region;

[0016] A first P-base region located on the upper surface of the current spreading region;

[0017] A first N+ source region located on the upper surface of the first P-base region;

[0018] The gate trench contacts the first N+ source region, the first P-base region, and the current spreading region on one side, and the gate oxide is located on the bottom and the sidewall of the gate trench;

[0019] A polysilicon gate located on the upper surface of the gate oxide, and the top of the polysilicon gate is flush with the top of the N+ source region;

[0020] An isolation oxygen located on the upper surface of the polysilicon gate and the partial first N+ source region;

[0021] A P-well region located on the upper surface of the partial N-drift region and contacting the current spreading region;

[0022] A second N+ source region located on the upper surface of the partial P-well region, surrounding the bottom, two corners, and one sidewall of the trench gate oxide;

[0023] The second P-base region is located on the upper surface of the partial second N+ source region and the partial P-well region, and is in contact with the gate oxide sidewall and the current spreading region.

[0024] The source metal layer is located on the upper surface of the isolation oxide, the first N+ source region, the partial second N+ source region and the partial P-well region.

[0025] The second N+ source region is shielded by the P-well region and the second P-base region, and is isolated from the current spreading region and the N-drift region.

[0026] Preferably, the first N+ source region is made of N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1×10 19 ~ 1×10 20 cm -3 , the thickness is 0.1 μm ~ 0.5 μm, and the width is 1 μm ~ 5 μm.

[0027] Preferably, the second N+ source region is made of N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1×10 19 ~ 1×10 20 cm -3 , the thickness is 1.0 μm ~ 4.0 μm, and the width is 0.8 μm ~ 3.0 μm.

[0028] Preferably, the first P-base region is made of P-type SiC, the doping element is aluminum or boron, the doping concentration is 1×10 17 ~ 1×10 18 cm -3 , the thickness is 0.1 μm ~ 0.6 μm, and the width is 1.0 μm ~ 5.0 μm.

[0029] Preferably, the second P-base region is made of P-type SiC, the doping element is aluminum or boron, the doping concentration is 1×10 17 ~ 1×10 18 cm -3 , the thickness is 0.1 μm ~ 0.6 μm, and the width is 0.4 μm ~ 1.5 μm.

[0030] Preferably, the P-well region is made of P-type SiC, the doping element is aluminum or boron, the doping concentration is 1×10 18 ~ 5×10 19 cm -3 , the thickness is 1.5 μm ~ 5.0 μm, and the width is 1.0 μm ~ 6.0 μm.

[0031] Preferably, the current spreading region is made of N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1×10 16~5x10 17 cm -3 , thickness 1.0 μm ~ 4.0 μm, width 0.8 μm ~ 3.0 μm.

[0032] Preferably, the gate oxide is SiO2, HfO2 or Al2O3, with a thickness of 40 nm ~ 150 nm.

[0033] Preferably, the isolation oxide is SiO2, HfO2 or Al2O3, with a thickness of 0.1 μm ~ 2.0 μm.

[0034] Preferably, the polysilicon gate is N-type polysilicon, with a doping element of phosphorus and a doping concentration of 1 x 10 19 ~ 1 x 10 20 cm -3 , thickness 1.0 μm ~ 3.0 μm, width 0.5 μm ~ 1.5 μm.

[0035] Preferably, the N-drift region is N-type SiC, with a doping element of nitrogen or phosphorus and a doping concentration of 1 x 10 13 ~ 5 x 10 16 cm -3 , thickness 5 μm ~ 50 μm.

[0036] Preferably, the N+ substrate layer is N-type SiC, with a doping element of nitrogen or phosphorus and a doping concentration of 5 x 10 18 ~ 1 x 10 20 cm -3 , thickness 50 μm ~ 400 μm.

[0037] In a second aspect, a method for manufacturing a SiC MOSFET resistant to single event gate punch-through and a method for manufacturing the same are provided, and the method includes but is not limited to the following steps:

[0038] ① Growing an N-drift region on a heavily doped SiC N+ substrate layer by epitaxy;

[0039] ② Growing an N-type epitaxial layer with high concentration on the N-drift region by epitaxy;

[0040] ③ Making a mask to shield part of the upper surface of the N-type epitaxial layer, and forming a partial P-well region by ion implantation;

[0041] ④ On the basis of the previous step, growing an N-type epitaxial layer with the same concentration by epitaxy;

[0042] ⑤ Making different masks, and forming a partial P-well region and a second N+ source region on the newly grown epitaxial layer by multiple photolithography and control of ion implantation energy;

[0043] ⑥On the basis of the previous step, a layer of N-type epitaxial layer with the same concentration is grown again, and multiple sets of different masks are made, and then multiple photoetchings and ion implantation with different energies are used to form part of the P-well region, the second N+ source region and the second P-base region on the newly grown epitaxial layer;

[0044] ⑦On the basis of the previous step, a layer of N-type epitaxial layer with the same concentration is grown again, and ion implantation is used to form the remaining P-well region, the second N+ source region, and the first N+ source region and the first P-base region in the middle part of the epitaxial layer on the newly grown epitaxial layer;

[0045] ⑧A trench is etched on the epitaxial layer grown in the previous step ⑦ by dry etching, one side of the gate trench is in contact with the first N+ source region, the first P-base region, the current spreading region, the second P-base region and the second N+ source region, the other side of the trench is only in contact with the second N+ source region, and the bottom of the trench is in contact with the second N+ source region;

[0046] ⑨A uniform and dense gate oxide layer is grown on the bottom and sidewall of the trench, a conductive medium polysilicon gate is deposited and photoetched and etched to form a gate electrode, and a thick oxide layer is deposited on the top surface of the trench to form an isolation oxide;

[0047] ⑩The back surface is thinned and metal sputtering is performed to form a drain metallization layer on the surface of the SiC N+ substrate layer, and the front surface is deposited with metal to form a source metallization layer on the upper surface of the device structure.

[0048] In summary, the present application at least includes the following beneficial technical effects:

[0049] When the trench type SiC MOSFET is in a blocking state, a large number of holes generated by high-energy charged particle collision ionization move towards the gate and the source under the action of a strong electric field. The high-doped concentration N-type second N+ source region is connected to the source, and a large number of electrons therein can recombine with the holes moving towards the gate oxide, and at the same time, the second N+ source region absorbs the holes, which move quickly to the source, reducing the hole density accumulated at the gate oxide interface. In addition, the high-doped concentration P-well region is also connected to the source, which surrounds and shields the second N+ source region, and the P-well region can quickly absorb the holes, which move to the source, reducing the number of holes moving to the second N+ source region. Under the joint action of the second N+ source region and the P-well region, the number of holes accumulated at the gate oxide interface is greatly reduced, and the instantaneous electric field strength is effectively reduced.

[0050] When the trench SiC MOSFET is in a forward conduction state, the first N+ source region injects electrons into the current spreading region through the first P-base region; in addition, the second N+ source region injects electrons into the current spreading region through the second P-base region. The cooperation of the second N+ source region and the second P-base region increases the effective channel area without increasing the chip area, and the on-current is doubled, so that the on-resistance of the trench SiC MOSFET is further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0051] Fig. 1 is a schematic diagram of a conventional trench SiC MOSFET structure;

[0052] Fig. 2 is a schematic diagram of a trench SiC MOSFET structure with single-particle gate punch resistance of the present application;

[0053] Fig. 3 is a flowchart of a preparation method of a trench SiC MOSFET structure with single-particle gate punch resistance of the present application;

[0054] Fig. 4 is a schematic diagram of the movement trajectory of electron-hole pairs of a conventional trench SiC MOSFET structure under high-energy charged particle radiation;

[0055] Fig. 5 is a schematic diagram of the movement trajectory of electron-hole pairs of a trench SiC MOSFET structure with single-particle gate punch resistance of the present application under high-energy charged particle radiation;

[0056] Fig. 6 is a comparison chart of the breakdown characteristics of a trench SiC MOSFET structure with single-particle gate punch resistance of the present application and a conventional trench SiC MOSFET structure;

[0057] Fig. 7 is a TCAD simulation chart of the change of the electric field intensity at the gate oxide position of a trench SiC MOSFET structure with single-particle gate punch resistance of the present application and a conventional trench SiC MOSFET structure under high-energy charged particle incident at the most sensitive position, with a linear energy transfer value of 0.52 pC / μm. DETAILED DESCRIPTION

[0058] To make the purpose, technical solutions and advantages of the present application clearer, the disclosed embodiments of the present application will be further described in detail below with reference to the drawings.

[0059] The embodiment of the application discloses a schematic diagram of a SiC MOSFET and a preparation method of the SiC MOSFET, as shown in FIG. 2, comprising a plurality of parallel cells, each cell comprising: a source metal layer 201, an isolation oxygen 202, a gate oxide 203, a polysilicon gate 204, a first N+ source region 205, a first P-base region 206, a second N+ source region 207, a P-well region 208, a second P-base region 209, a current spreading region 210, an N-drift region 211, an N+ substrate layer 212 and a drain metal layer 213.

[0060] The drain metal layer 213 is located on the lower surface of the N+ substrate layer 212; the N-drift region 211 is located on the upper surface of the N+ substrate layer 212; the current spreading region 210 is located on the upper surface of the middle part of the N-drift region 211; the first P-base region 206 is located on the upper surface of the current spreading region 210; the first N+ source region 205 is located on the upper surface of the first P-base region 206, and the width of the first N+ source region 205 is the same as the width of the first P-base region 206;

[0061] The P-well region 208 is located on the upper surface of part of the N-drift region 211 and contacts the current spreading region 210, and the P-well region 208 comprises two parts, and the two parts of the P-well region 208 are located on the two sides of the current spreading region 210, respectively, a first protrusion is arranged on the side of each part of the P-well region 208 close to the current spreading region 210, a second protrusion is arranged on the side of each part of the P-well region 208 away from the current spreading region 210, and the height of the second protrusion is greater than that of the first protrusion, so as to form a groove between the first protrusion and the second protrusion; the second N+ source region 207 is located in the groove on the surface of part of the P-well region 208; a gate trench is arranged in the second N+ source region 207, and the gate trench is located in the middle part of the second N+ source region 207, so that the second N+ source region 207 forms a third protrusion and a fourth protrusion on the two sides of the gate trench, the third protrusion is located on the side of the gate trench close to the current spreading region 210, the fourth protrusion is located on the side of the gate trench away from the current spreading region 210, the end of the third protrusion away from the N-drift region 211 is flush with the first protrusion, and the end of the fourth protrusion away from the N-drift region 211 is flush with the second protrusion, so that one side of the gate trench contacts the second P-base region 209, the current spreading region 210, the first N+ source region 205 and the first P-base region 206, and the other side and the bottom of the gate trench contact the second N+ source region 207; the gate oxide 203 is located on the bottom and the sidewall of the gate trench; the polysilicon gate 204 is located on the upper surface of the gate oxide 203, and the top of the polysilicon gate 204 is flush with the top of the N+ source region 205; the second N+ source region 207 surrounds the bottom, two corners and one sidewall of the trench gate oxide 203;

[0062] The second P-base region 209 is located on the upper surface of the second N+ source region 207 and the P-well region 208 on the side of the trench gate oxide 203 close to the current spreading region 210, that is, the second P-base region 209 is located on the side of the first and third protrusions away from the N-drift region 211, and the width of the second P-base region 209 is equal to the width of the first and third protrusions; the side of the second P-base region 209 away from the N-drift region 211 is in turn the current spreading region 210, the first P-base region 206 and the first N+ source region 205, and the end of the second P-base region 209, the current spreading region 210, the first P-base region 206 and the first N+ source region 205 is flush; the second P-base region 209 is in contact with the gate oxide 203 sidewall and the current spreading region 210;

[0063] The isolation oxygen 202 is located on the top of the polysilicon gate 204 and the gate oxide 203 outside the polysilicon gate 204, and the width direction of the isolation oxygen 202 is along the direction from the polysilicon gate 204 to the current spreading region 210, and the width of the isolation oxygen 202 is greater than the total width of the gate oxide 203, so that the two ends of the isolation oxygen 202 exceed the gate oxide 203 and cover part of the upper surface of the first N+ source region 205; the source metal layer 201 is located on the upper surface of the isolation oxygen 202, the first N+ source region 205, the second N+ source region 207 and the P-well region 208.

[0064] The first N+ source region 205, the second N+ source region 207 and the P-well region 208 are in contact with the source metal layer 201; the second N+ source region 207 surrounds the bottom, two corners and one sidewall of the trench gate oxide 203; the second N+ source region 207 is shielded by the P-well region 208 and the second P-base region 209, and is isolated from the current spreading region 210 and the N-drift region 211.

[0065] The material of the first N+ source region 205 is N-type SiC, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1×10 19 ~1×10 20 cm -3 , the thickness is 0.1 μm~0.5 μm, and the width is 1 μm~5 μm.

[0066] The material of the second N+ source region 207 is N-type SiC, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1×10 19 ~1×10 20 cm -3 , the thickness is 1.0 μm~4.0 μm, and the width is 0.8 μm~3.0 μm.

[0067] The material of the first P-base region 206 is P-type SiC, the doping element is aluminum element or boron element, and the doping concentration is 1×1017 ~1x10 18 cm -3 , thickness 0.1 μm ~ 0.6 μm, width 1 μm ~ 5 μm.

[0068] The material of the second P-base region 209 is P-type SiC, the doping element is aluminum element or boron element, and the doping concentration is 1x10 17 ~1x10 18 cm -3 , thickness 0.1 μm ~ 0.6 μm, width 0.4 μm ~ 1.5 μm.

[0069] The material of the P-well region 208 is P-type SiC, the doping element is aluminum element or boron element, and the doping concentration is 1x10 18 ~5x10 19 cm -3 , thickness 1.5 μm ~ 5 μm, width 1 μm ~ 6 μm.

[0070] The material of the current spreading region 210 is N-type SiC, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1x10 16 ~5x10 17 cm -3 , thickness 1.0 μm ~ 4.0 μm, width 0.8 μm ~ 3.0 μm.

[0071] The material of the gate oxide 203 is SiO2, HfO2 or Al2O3, and the thickness is 40 nm ~ 150 nm.

[0072] The material of the isolation oxide 202 is SiO2, HfO2 or Al2O3, and the thickness is 0.1 μm ~ 2 μm.

[0073] The material of the polysilicon gate 204 is N-type polysilicon, the doping element is phosphorus element, and the doping concentration is 1x10 19 ~1x10 20 cm -3 , thickness 1 μm ~ 3 μm, width 0.5 μm ~ 1.5 μm.

[0074] The material of the N-drift region 211 is N-type SiC, the doping element is nitrogen element or phosphorus element, and the doping concentration is 1x10 13 ~5x10 16 cm -3 , thickness 5 μm ~ 50 μm.

[0075] The material of the N+ substrate layer 212 is N-type SiC, the doping element is nitrogen element or phosphorus element, and the doping concentration is 5x10 18 ~1x10 20 cm -3, thickness is 50 μm ~ 400 μm.

[0076] Figure 3 is a preparation method flow chart of the present application, i.e. a SiC MOSFET and a preparation method of anti-single particle gate punch, the specific preparation process includes:

[0077] Step 1, epitaxially growing a layer of N-drift region 211 on the heavily doped SiC N+ substrate layer 212, the doping concentration is 1 × 10 13 ~ 5 × 10 16 cm -3 , thickness is 5 μm ~ 50 μm;

[0078] Step 2, epitaxially growing a layer of high-concentration N-type epitaxial layer on the N-drift region 211, the doping concentration is 1 × 10 16 ~ 5 × 10 17 cm -3 , thickness is 0.5 μm ~ 1.0 μm;

[0079] Step 3, making a mask to shield part of the upper surface of the N-type epitaxial layer, and performing aluminum or boron ion implantation to form a partial P-well region 208, the doping concentration is 1 × 10 18 ~ 5 × 10 19 cm -3 ;

[0080] Step 4, on the basis of step 3, epitaxially growing a layer of N-type epitaxial layer with the same concentration, the doping concentration is consistent with the epitaxial layer grown in step 3, the doping concentration is 1 × 10 16 ~ 5 × 10 17 cm -3 , thickness is 0.5 μm ~ 1.5 μm;

[0081] Step 5, making different masks, using multiple lithography and controlling ion implantation energy to form a partial P-well region 208 and a second N+ source region 207 on the newly grown epitaxial layer;

[0082] Step 6, on the basis of step 5, epitaxially growing a layer of N-type epitaxial layer with the same concentration, the doping concentration is 1 × 10 16 ~ 5 × 10 17 cm -3, the thickness is 0.1-0.6 μm, a plurality of different mask plates are made, and the part P-well area 208, the second N+ source area 207 and the second P-base area 209 are sequentially formed on the newly grown epitaxial layer by using multiple photoetching and controlling ion implantation energy, wherein the width of the second P-base area 209 is 0.4-1.5 μm, and the boundary of the second P-base area 209 close to the current spreading area 210 side is aligned with the P-well area 208 below;

[0083] Step 7, based on step 6, an N-type epitaxial layer with the same concentration is further grown, the doping concentration is still 1×10 16 ~ 5×10 17 cm -3 , the thickness is 0.5-3.0 μm, the remaining P-well area 208, the second N+ source area 207, the first N+ source area 205 and the first P-base area 206 in the middle part of the epitaxial layer surface are formed on the newly grown epitaxial layer by using multiple photoetching and controlling ion implantation energy, and the first N+ source area is above the first P-base area;

[0084] Step 8, a groove is etched on the surface of the epitaxial layer grown in step 7 by dry etching, one side of the gate groove is in contact with the first N+ source area 205, the first P-base area 206, the current spreading area 210, the second P-base area 209 and the second N+ source area 207, the other side of the groove is only in contact with the second N+ source area 207, and the bottom of the groove is in contact with the second N+ source area 207;

[0085] Step 9, a uniform and dense gate oxide layer (i.e. gate oxide 203) is grown on the bottom and sidewall of the groove, a conductive medium polysilicon gate 204 is deposited and photoetched and etched to form a gate electrode, and a thick oxide layer is deposited on the upper surface of the groove to form an isolation oxide 202;

[0086] Step 10, back thinning and metal sputtering treatment are performed to form a drain metallization layer 213 on the surface of the SiC N+ substrate layer 212, and front deposition of metal is performed to form a source metallization layer 201 on the upper surface of the device structure.

[0087] The working principle of the trench type SiC MOSFET with anti-single-particle gate punch reinforcement according to the application is as follows:

[0088] When the trench SiC MOSFET of the present application is in the on state, a certain positive voltage needs to be applied to the polysilicon gate 204 (i.e. gate), at this time, the device channel is opened, forming two conduction paths: one is in turn drain metallization layer 213, N+ substrate layer 212, N- drift region 211, current spreading region 210, first P-base region 206, first N+ source region 205, source metallization layer 201; the other is in turn drain metallization layer 213, N+ substrate layer 212, N- drift region 211, current spreading region 210, second P-base region 209, second N+ source region 207, source metallization layer 201. The cooperation of the second N+ source region 207 and the second P-base region 209 increases the effective channel area without increasing the chip area, and the on current is doubled, so that the on resistance of the trench SiC MOSFET of the present application is further reduced.

[0089] When the trench SiC MOSFET of the present application is in the off state, zero voltage or negative voltage needs to be applied to the gate, at this time the channel is closed and there is no conduction path. When high-energy charged particles enter the device at this time, a large number of holes generated by collision ionization of high-energy charged particles move to the gate and source (i.e. source metallization layer 201) under the action of strong electric field. The high-doped N-type second N+ source region 207 is connected to the source, a large number of electrons therein can recombine with the holes moving to the gate oxide 203, and at the same time the second N+ source region 207 absorbs the holes. Since the second N+ source region 207 has high doping concentration, the holes move quickly to the source, reducing the hole density accumulated at the gate oxide 203 interface. In addition, the high-doped P-well region 208 is also connected to the source, which surrounds and shields the second N+ source region 207. The P-well region 208 can quickly absorb holes, and the holes move to the source, reducing the number of holes moving to the second N+ source region 207. Under the joint action of the second N+ source region 207 and the P-well region 208, the number of holes accumulated at the gate oxide 203 interface is greatly reduced, and the instantaneous electric field strength is effectively reduced. Figures 4 and 5 are schematic diagrams of the movement trajectories of electron-hole pairs when high-energy charged particles are radiated in the conventional trench SiC MOSFET and the anti-single event gate punch-through hardened structure proposed by the present application, respectively.

[0090] In order to further illustrate the performance of the anti-single event gate punch-through hardened trench SiC MOSFET of the present application, in this embodiment, the simulation tool TCAD is used to simulate the device and compare the performance of the present application with that of the conventional trench SiC MOSFET.

[0091] Figure 6 shows that by comparing the breakdown characteristics of the structures in Figures 1 and 2, it can be seen that the breakdown voltage of the trench SiC MOSFET reinforced with single-particle gate breakdown resistance of the present invention and the traditional trench SiC MOSFET are both around 650V, which is equivalent to a device with a rated voltage of 600V.

[0092] Figure 7 shows a linear energy conversion (LET) value of 0.52 pC / μm, equivalent to 78.7 MeV / (mg / cm²). 2 The simulation graph shows the change of the gate oxide electric field intensity over time when Ta ions are incident at the most sensitive location of a trench SiC MOSFET. For a conventional trench SiC MOSFET, with a drain bias voltage V... DS At a voltage of 100V, the maximum electric field of the gate oxide reaches 10MeV / cm, far exceeding the critical breakdown electric field value of the gate oxide (6MeV / cm). However, the trench-type SiC MOSFET with single-particle gate breakdown hardening of this invention, at a drain bias voltage of V... DS At 600V, the maximum electric field strength remains below 3MeV / cm, not exceeding the critical breakdown electric field of the gate oxide. It can be seen that this invention effectively improves the threshold voltage for single-particle gate breakdown.

[0093] The contents not described in detail in this application specification are common knowledge to those skilled in the art.

[0094] The present application has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. A single event latch-up immune SiC MOSFET, characterized in that, Each cell includes: a drain metallization layer (213), an N+ substrate layer (212) and an N- drift region (211) arranged in sequence; a current spreading region (210) located in the middle of the N- drift region (211) away from the surface of the N+ substrate layer (212); a first P-base region (206) located on the surface of the current spreading region (210) away from the N- drift region (211); a first N+ source region (205) located on the surface of the first P-base region (206) away from the current spreading region (210); a P-well region (208) located on the surface of the N- drift region (211) away from the N+ substrate layer (212), the P-well region (208) includes two parts, and the two parts of the P-well region (208) are located on the two sides of the current spreading region (210) and are in contact with the current spreading region (210); each part of the P-well region (208) is provided with a first protrusion on the side close to the current spreading region (210) and a second protrusion on the side away from the current spreading region (210), and the height of the second protrusion is greater than that of the first protrusion to form a groove between the first protrusion and the second protrusion; a second N+ source region (207) located in the groove on the surface of the P-well region (208); the second N+ source region (207) is provided with a gate trench, so that the second N+ source region (207) forms a third protrusion and a fourth protrusion on the two sides of the gate trench, the third protrusion is located on the side of the gate trench close to the current spreading region (210), and the fourth protrusion is located on the side of the gate trench away from the current spreading region (210); a gate oxide (203) located on the bottom and the sidewall of the gate trench, one sidewall of the gate trench is in contact with the current spreading region (210), the first N+ source region (205) and the first P-base region (206), and the other sidewall and the bottom of the gate trench are in contact with the second N+ source region (207); a polysilicon gate (204) located on the surface of the gate oxide (203) away from the second N+ source region (207), and the surface of the polysilicon gate (204) away from the N- drift region (211) is flush with the first N+ source region (205); an isolation oxide (202) located on the surface of the polysilicon gate (204) and the gate oxide (203) away from the N- drift region (211); a source metallization layer (201) located on the surface of the isolation oxide (202), the first N+ source region (205), part of the second N+ source region (207) and part of the P-well region (208).

2. The single event latch-up immune SiC MOSFET of claim 1, wherein, Each cell further includes: a second P-base region (209) located on the surface of the first protrusion and the third protrusion away from the N- drift region (211), the second P-base region (209) is in contact with the sidewall of the gate oxide (203) and the current spreading region (210); the side of the second P-base region (209) away from the first protrusion is in sequence of the current spreading region (210), the first P-base region (206) and the first N+ source region (205). The second N+ source region (207) is shielded by the P-well region (208) and the second P-base region (209) and is isolated from the current spreading region (210) and the N-drift region (211).

3. The single event latch-up immune SiC MOSFET of claim 1, wherein: The material of the first N+ source region (205) is N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1×10 19 ~1×10 20 cm -3 , the thickness is 0.1 μm~0.5 μm, and the width is 1 μm~5 μm; The material of the second N+ source region (207) is N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1 x 1018~1 x 1020cm-3, the thickness is 1.0 μm~4.0 μm, and the width is 0.8 μm~3.0 μm. 19 cm 20 cm -3 ​ 4. The single event latch-up immune SiC MOSFET of claim 1, wherein: The material of the first P-base region (206) is P-type SiC, the doping element is aluminum element or boron element, the doping concentration is 1×1018~1×1020cm-3, the thickness is 0.1μm~0.6μm, and the width is 1μm~5μm. 17 cm 18 -3, the thickness is 0.1μm~0.6μm, and the width is 1μm~5μm. -3 cm -3 -3, the thickness is 0.1μm~0.6μm, and the width is 1μm~5μm. The material of the second P-base region (209) is P-type SiC, the doping element is aluminum element or boron element, the doping concentration is 1 x 1018~1 x 1020cm-3, the thickness is 0.1 μm~0.6 μm, and the width is 0.4 μm~1.5 μm. 17 ~1 x 1020cm-3 18 cm -3 , the thickness is 0.1 μm~0.6 μm, and the width is 0.4 μm~1.5 μm.

5. The single event latch-up immune SiC MOSFET of claim 1, wherein: The material of the P-well region (208) is P-type SiC, the doping element is aluminum element or boron element, the doping concentration is 1x10 18 ~5x10 19 cm -3 , the thickness is 1.5 μm~5.0 μm, and the width is 1.0 μm~6.0 μm.

6. The single event latch-up immune SiC MOSFET of claim 1, wherein: The material of the current spreading region (210) is N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1×10 16 ~5×10 17 cm -3 , the thickness is 1.0 μm~4.0 μm, and the width is 0.8 μm~3.0 μm.

7. The single event latch-up immune SiC MOSFET of claim 1, wherein: The material of the polysilicon gate (204) is N-type polysilicon, the doping element is phosphorus element, the doping concentration is 1×10 19 ~1×10 20 cm -3 , the thickness is 1.0 μm~3.0 μm, and the width is 0.5 μm~1.5 μm.

8. The single event latch-up immune SiC MOSFET of claim 1, wherein: The gate oxide (203) is made of SiO2, HfO2 or Al2O3 and has a thickness of 40-150 nm; the isolation oxide is made of SiO2, HfO2 or Al2O3 and has a thickness of 0.1-2.0 μm.

9. The single event latch-up immune SiC MOSFET of claim 1, wherein: The material of the N-drift region (211) is N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 1×10 13 ~5×10 16 cm -3 , and the thickness is 5μm~50μm. The material of the N+ substrate layer (212) is N-type SiC, the doping element is nitrogen or phosphorus, the doping concentration is 5×10 18 ~1×10 20 cm -3 , and the thickness is 50μm~400μm.

10. The method of claim 1-9, wherein the SiC MOSFET is prepared by the steps of: The method comprises the following steps: ​ S1: epitaxially growing an N-drift region (211) on a heavily doped SiC N+ substrate layer (212); S2: a high-concentration N-type epitaxial layer is epitaxially grown on the surface of the N- drift region (211) away from the N+ substrate layer (212), with a doping concentration of 1×10 16 ~5×10 17 cm -3 -1.0 μm in thickness; S3: making a mask to shield part of the surface of the N-type epitaxial layer, implanting aluminum or boron ions to form part of the P-well region (208), and forming the current spreading region (210) at the position shielded by the mask; S4: on the basis of step S3, epitaxially growing an N-type epitaxial layer again, the thickness and doping concentration of which are the same as those of the epitaxial layer grown last time; S5: making different masks and forming part of the P-well region (208) and part of the second N+ source region (207) on the newly grown epitaxial layer by using multiple photolithography and ion implantation energy control; S6: On the basis of step S5, a N-type epitaxial layer is again epitaxially grown, with a doping concentration of 1×1018~5×1018cm-3 and a thickness of 0.1μm~0.6μm, and then a part of P-well region (208), second N+ source region (207) and second P-base region (209) are formed in sequence on the N-type epitaxial layer newly grown in this step by using multiple photoetching and controlling ion implantation energy. 16 ~5×1018 17 cm-3 -3 , and a thickness of 0.1μm~0.6μm, and then a part of P-well region (208), second N+ source region (207) and second P-base region (209) are formed in sequence on the N-type epitaxial layer newly grown in this step by using multiple photoetching and controlling ion implantation energy. S7: Based on step S6, grow another N-type epitaxial layer with the same doping concentration of 1×10⁻⁶. 16 ~5×10 17 cm -3 The thickness is 0.5μm to 3.0μm. Then, by using multiple photolithography and controlling the ion implantation energy, the remaining P-well region (208) and the second N+ source region (207) are formed sequentially on the newly grown epitaxial layer, and the first N+ source region (205) and the first P-base region (206) are formed in the middle part of the epitaxial layer surface. S8: etching a gate trench on the surface of the second N+ source region (207) by dry etching, one side of the gate trench being in contact with the first N+ source region (205), the first P-base region (206), the current spreading region (210), the second P-base region (209) and the second N+ source region (207), and the other side and the bottom of the gate trench being in contact with the second N+ source region (207) only; S9: growing a uniform and dense gate oxide (203) on the bottom and the sidewall of the gate trench, depositing a conductive medium polysilicon gate (204) and performing photolithography and etching to form a gate electrode, and depositing a thick oxide layer on the surface of the trench to form an isolation oxide (202); S10: performing back thinning and metal sputtering treatment to form a drain metallization layer (213) on the surface of the SiC N+ substrate layer (212), and performing front deposition of metal to form a source metallization layer (201) on the upper surface of the device structure.

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